1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 STMMAC Ethtool support
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/mii.h>
15 #include <linux/phylink.h>
16 #include <linux/net_tstamp.h>
17 #include <asm/io.h>
18
19 #include "stmmac.h"
20 #include "dwmac_dma.h"
21 #include "dwxgmac2.h"
22
23 #define REG_SPACE_SIZE 0x1060
24 #define GMAC4_REG_SPACE_SIZE 0x116C
25 #define MAC100_ETHTOOL_NAME "st_mac100"
26 #define GMAC_ETHTOOL_NAME "st_gmac"
27 #define XGMAC_ETHTOOL_NAME "st_xgmac"
28
29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
30 *
31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
32 * same time due to the conflicting macro names.
33 */
34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100
35
36 #define ETHTOOL_DMA_OFFSET 55
37
38 struct stmmac_stats {
39 char stat_string[ETH_GSTRING_LEN];
40 int sizeof_stat;
41 int stat_offset;
42 };
43
44 #define STMMAC_STAT(m) \
45 { #m, sizeof_field(struct stmmac_extra_stats, m), \
46 offsetof(struct stmmac_priv, xstats.m)}
47
48 static const struct stmmac_stats stmmac_gstrings_stats[] = {
49 /* Transmit errors */
50 STMMAC_STAT(tx_underflow),
51 STMMAC_STAT(tx_carrier),
52 STMMAC_STAT(tx_losscarrier),
53 STMMAC_STAT(vlan_tag),
54 STMMAC_STAT(tx_deferred),
55 STMMAC_STAT(tx_vlan),
56 STMMAC_STAT(tx_jabber),
57 STMMAC_STAT(tx_frame_flushed),
58 STMMAC_STAT(tx_payload_error),
59 STMMAC_STAT(tx_ip_header_error),
60 /* Receive errors */
61 STMMAC_STAT(rx_desc),
62 STMMAC_STAT(sa_filter_fail),
63 STMMAC_STAT(overflow_error),
64 STMMAC_STAT(ipc_csum_error),
65 STMMAC_STAT(rx_collision),
66 STMMAC_STAT(rx_crc_errors),
67 STMMAC_STAT(dribbling_bit),
68 STMMAC_STAT(rx_length),
69 STMMAC_STAT(rx_mii),
70 STMMAC_STAT(rx_multicast),
71 STMMAC_STAT(rx_gmac_overflow),
72 STMMAC_STAT(rx_watchdog),
73 STMMAC_STAT(da_rx_filter_fail),
74 STMMAC_STAT(sa_rx_filter_fail),
75 STMMAC_STAT(rx_missed_cntr),
76 STMMAC_STAT(rx_overflow_cntr),
77 STMMAC_STAT(rx_vlan),
78 STMMAC_STAT(rx_split_hdr_pkt_n),
79 /* Tx/Rx IRQ error info */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Tx/Rx IRQ Events */
90 STMMAC_STAT(rx_early_irq),
91 STMMAC_STAT(threshold),
92 STMMAC_STAT(tx_pkt_n),
93 STMMAC_STAT(rx_pkt_n),
94 STMMAC_STAT(normal_irq_n),
95 STMMAC_STAT(rx_normal_irq_n),
96 STMMAC_STAT(napi_poll),
97 STMMAC_STAT(tx_normal_irq_n),
98 STMMAC_STAT(tx_clean),
99 STMMAC_STAT(tx_set_ic_bit),
100 STMMAC_STAT(irq_receive_pmt_irq_n),
101 /* MMC info */
102 STMMAC_STAT(mmc_tx_irq_n),
103 STMMAC_STAT(mmc_rx_irq_n),
104 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
105 /* EEE */
106 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
107 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
108 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
109 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
110 STMMAC_STAT(phy_eee_wakeup_error_n),
111 /* Extended RDES status */
112 STMMAC_STAT(ip_hdr_err),
113 STMMAC_STAT(ip_payload_err),
114 STMMAC_STAT(ip_csum_bypassed),
115 STMMAC_STAT(ipv4_pkt_rcvd),
116 STMMAC_STAT(ipv6_pkt_rcvd),
117 STMMAC_STAT(no_ptp_rx_msg_type_ext),
118 STMMAC_STAT(ptp_rx_msg_type_sync),
119 STMMAC_STAT(ptp_rx_msg_type_follow_up),
120 STMMAC_STAT(ptp_rx_msg_type_delay_req),
121 STMMAC_STAT(ptp_rx_msg_type_delay_resp),
122 STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
123 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
124 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
125 STMMAC_STAT(ptp_rx_msg_type_announce),
126 STMMAC_STAT(ptp_rx_msg_type_management),
127 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
128 STMMAC_STAT(ptp_frame_type),
129 STMMAC_STAT(ptp_ver),
130 STMMAC_STAT(timestamp_dropped),
131 STMMAC_STAT(av_pkt_rcvd),
132 STMMAC_STAT(av_tagged_pkt_rcvd),
133 STMMAC_STAT(vlan_tag_priority_val),
134 STMMAC_STAT(l3_filter_match),
135 STMMAC_STAT(l4_filter_match),
136 STMMAC_STAT(l3_l4_filter_no_match),
137 /* PCS */
138 STMMAC_STAT(irq_pcs_ane_n),
139 STMMAC_STAT(irq_pcs_link_n),
140 STMMAC_STAT(irq_rgmii_n),
141 /* DEBUG */
142 STMMAC_STAT(mtl_tx_status_fifo_full),
143 STMMAC_STAT(mtl_tx_fifo_not_empty),
144 STMMAC_STAT(mmtl_fifo_ctrl),
145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
148 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
149 STMMAC_STAT(mac_tx_in_pause),
150 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
151 STMMAC_STAT(mac_tx_frame_ctrl_idle),
152 STMMAC_STAT(mac_tx_frame_ctrl_wait),
153 STMMAC_STAT(mac_tx_frame_ctrl_pause),
154 STMMAC_STAT(mac_gmii_tx_proto_engine),
155 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
156 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
157 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
158 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
162 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
163 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
164 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
165 STMMAC_STAT(mac_gmii_rx_proto_engine),
166 /* TSO */
167 STMMAC_STAT(tx_tso_frames),
168 STMMAC_STAT(tx_tso_nfrags),
169 };
170 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
171
172 /* HW MAC Management counters (if supported) */
173 #define STMMAC_MMC_STAT(m) \
174 { #m, sizeof_field(struct stmmac_counters, m), \
175 offsetof(struct stmmac_priv, mmc.m)}
176
177 static const struct stmmac_stats stmmac_mmc[] = {
178 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
179 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
180 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
181 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
182 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
183 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
184 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
185 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
186 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
187 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
188 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
189 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
190 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
191 STMMAC_MMC_STAT(mmc_tx_underflow_error),
192 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
193 STMMAC_MMC_STAT(mmc_tx_multicol_g),
194 STMMAC_MMC_STAT(mmc_tx_deferred),
195 STMMAC_MMC_STAT(mmc_tx_latecol),
196 STMMAC_MMC_STAT(mmc_tx_exesscol),
197 STMMAC_MMC_STAT(mmc_tx_carrier_error),
198 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
199 STMMAC_MMC_STAT(mmc_tx_framecount_g),
200 STMMAC_MMC_STAT(mmc_tx_excessdef),
201 STMMAC_MMC_STAT(mmc_tx_pause_frame),
202 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
203 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
204 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
205 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
206 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
207 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
208 STMMAC_MMC_STAT(mmc_rx_crc_error),
209 STMMAC_MMC_STAT(mmc_rx_align_error),
210 STMMAC_MMC_STAT(mmc_rx_run_error),
211 STMMAC_MMC_STAT(mmc_rx_jabber_error),
212 STMMAC_MMC_STAT(mmc_rx_undersize_g),
213 STMMAC_MMC_STAT(mmc_rx_oversize_g),
214 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
215 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
216 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
217 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
218 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
219 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
220 STMMAC_MMC_STAT(mmc_rx_unicast_g),
221 STMMAC_MMC_STAT(mmc_rx_length_error),
222 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
223 STMMAC_MMC_STAT(mmc_rx_pause_frames),
224 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
225 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
226 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
227 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
228 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
229 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
230 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
231 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
232 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
233 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
234 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
235 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
236 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
237 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
238 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
239 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
240 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
241 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
242 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
243 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
244 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
245 STMMAC_MMC_STAT(mmc_rx_udp_gd),
246 STMMAC_MMC_STAT(mmc_rx_udp_err),
247 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
248 STMMAC_MMC_STAT(mmc_rx_tcp_err),
249 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
250 STMMAC_MMC_STAT(mmc_rx_icmp_err),
251 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
252 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
253 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
254 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
255 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
256 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
257 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
258 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
259 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
260 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
261 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
262 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
263 };
264 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
265
stmmac_ethtool_getdrvinfo(struct net_device * dev,struct ethtool_drvinfo * info)266 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
267 struct ethtool_drvinfo *info)
268 {
269 struct stmmac_priv *priv = netdev_priv(dev);
270
271 if (priv->plat->has_gmac || priv->plat->has_gmac4)
272 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
273 else if (priv->plat->has_xgmac)
274 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
275 else
276 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
277 sizeof(info->driver));
278
279 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
280 }
281
stmmac_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)282 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
283 struct ethtool_link_ksettings *cmd)
284 {
285 struct stmmac_priv *priv = netdev_priv(dev);
286
287 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
288 priv->hw->pcs & STMMAC_PCS_SGMII) {
289 struct rgmii_adv adv;
290 u32 supported, advertising, lp_advertising;
291
292 if (!priv->xstats.pcs_link) {
293 cmd->base.speed = SPEED_UNKNOWN;
294 cmd->base.duplex = DUPLEX_UNKNOWN;
295 return 0;
296 }
297 cmd->base.duplex = priv->xstats.pcs_duplex;
298
299 cmd->base.speed = priv->xstats.pcs_speed;
300
301 /* Get and convert ADV/LP_ADV from the HW AN registers */
302 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
303 return -EOPNOTSUPP; /* should never happen indeed */
304
305 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
306
307 ethtool_convert_link_mode_to_legacy_u32(
308 &supported, cmd->link_modes.supported);
309 ethtool_convert_link_mode_to_legacy_u32(
310 &advertising, cmd->link_modes.advertising);
311 ethtool_convert_link_mode_to_legacy_u32(
312 &lp_advertising, cmd->link_modes.lp_advertising);
313
314 if (adv.pause & STMMAC_PCS_PAUSE)
315 advertising |= ADVERTISED_Pause;
316 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
317 advertising |= ADVERTISED_Asym_Pause;
318 if (adv.lp_pause & STMMAC_PCS_PAUSE)
319 lp_advertising |= ADVERTISED_Pause;
320 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
321 lp_advertising |= ADVERTISED_Asym_Pause;
322
323 /* Reg49[3] always set because ANE is always supported */
324 cmd->base.autoneg = ADVERTISED_Autoneg;
325 supported |= SUPPORTED_Autoneg;
326 advertising |= ADVERTISED_Autoneg;
327 lp_advertising |= ADVERTISED_Autoneg;
328
329 if (adv.duplex) {
330 supported |= (SUPPORTED_1000baseT_Full |
331 SUPPORTED_100baseT_Full |
332 SUPPORTED_10baseT_Full);
333 advertising |= (ADVERTISED_1000baseT_Full |
334 ADVERTISED_100baseT_Full |
335 ADVERTISED_10baseT_Full);
336 } else {
337 supported |= (SUPPORTED_1000baseT_Half |
338 SUPPORTED_100baseT_Half |
339 SUPPORTED_10baseT_Half);
340 advertising |= (ADVERTISED_1000baseT_Half |
341 ADVERTISED_100baseT_Half |
342 ADVERTISED_10baseT_Half);
343 }
344 if (adv.lp_duplex)
345 lp_advertising |= (ADVERTISED_1000baseT_Full |
346 ADVERTISED_100baseT_Full |
347 ADVERTISED_10baseT_Full);
348 else
349 lp_advertising |= (ADVERTISED_1000baseT_Half |
350 ADVERTISED_100baseT_Half |
351 ADVERTISED_10baseT_Half);
352 cmd->base.port = PORT_OTHER;
353
354 ethtool_convert_legacy_u32_to_link_mode(
355 cmd->link_modes.supported, supported);
356 ethtool_convert_legacy_u32_to_link_mode(
357 cmd->link_modes.advertising, advertising);
358 ethtool_convert_legacy_u32_to_link_mode(
359 cmd->link_modes.lp_advertising, lp_advertising);
360
361 return 0;
362 }
363
364 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
365 }
366
367 static int
stmmac_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)368 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
369 const struct ethtool_link_ksettings *cmd)
370 {
371 struct stmmac_priv *priv = netdev_priv(dev);
372
373 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
374 priv->hw->pcs & STMMAC_PCS_SGMII) {
375 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause;
376
377 /* Only support ANE */
378 if (cmd->base.autoneg != AUTONEG_ENABLE)
379 return -EINVAL;
380
381 mask &= (ADVERTISED_1000baseT_Half |
382 ADVERTISED_1000baseT_Full |
383 ADVERTISED_100baseT_Half |
384 ADVERTISED_100baseT_Full |
385 ADVERTISED_10baseT_Half |
386 ADVERTISED_10baseT_Full);
387
388 mutex_lock(&priv->lock);
389 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
390 mutex_unlock(&priv->lock);
391
392 return 0;
393 }
394
395 if (priv->plat->tx_queues_to_use > 1 && cmd->base.duplex == DUPLEX_HALF) {
396 netdev_warn(priv->dev, "Half-Duplex can only work with single queue\n");
397 return -EINVAL;
398 }
399
400 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
401 }
402
stmmac_ethtool_getmsglevel(struct net_device * dev)403 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
404 {
405 struct stmmac_priv *priv = netdev_priv(dev);
406 return priv->msg_enable;
407 }
408
stmmac_ethtool_setmsglevel(struct net_device * dev,u32 level)409 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
410 {
411 struct stmmac_priv *priv = netdev_priv(dev);
412 priv->msg_enable = level;
413
414 }
415
stmmac_check_if_running(struct net_device * dev)416 static int stmmac_check_if_running(struct net_device *dev)
417 {
418 if (!netif_running(dev))
419 return -EBUSY;
420 return 0;
421 }
422
stmmac_ethtool_get_regs_len(struct net_device * dev)423 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
424 {
425 struct stmmac_priv *priv = netdev_priv(dev);
426
427 if (priv->plat->has_xgmac)
428 return XGMAC_REGSIZE * 4;
429 else if (priv->plat->has_gmac4)
430 return GMAC4_REG_SPACE_SIZE;
431 return REG_SPACE_SIZE;
432 }
433
stmmac_ethtool_gregs(struct net_device * dev,struct ethtool_regs * regs,void * space)434 static void stmmac_ethtool_gregs(struct net_device *dev,
435 struct ethtool_regs *regs, void *space)
436 {
437 struct stmmac_priv *priv = netdev_priv(dev);
438 u32 *reg_space = (u32 *) space;
439
440 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
441 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
442
443 /* Copy DMA registers to where ethtool expects them */
444 if (priv->plat->has_gmac4) {
445 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
446 memcpy(®_space[ETHTOOL_DMA_OFFSET],
447 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
448 NUM_DWMAC4_DMA_REGS * 4);
449 } else if (!priv->plat->has_xgmac) {
450 memcpy(®_space[ETHTOOL_DMA_OFFSET],
451 ®_space[DMA_BUS_MODE / 4],
452 NUM_DWMAC1000_DMA_REGS * 4);
453 }
454 }
455
stmmac_nway_reset(struct net_device * dev)456 static int stmmac_nway_reset(struct net_device *dev)
457 {
458 struct stmmac_priv *priv = netdev_priv(dev);
459
460 return phylink_ethtool_nway_reset(priv->phylink);
461 }
462
stmmac_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)463 static void stmmac_get_ringparam(struct net_device *netdev,
464 struct ethtool_ringparam *ring)
465 {
466 struct stmmac_priv *priv = netdev_priv(netdev);
467
468 ring->rx_max_pending = DMA_MAX_RX_SIZE;
469 ring->tx_max_pending = DMA_MAX_TX_SIZE;
470 ring->rx_pending = priv->dma_rx_size;
471 ring->tx_pending = priv->dma_tx_size;
472 }
473
stmmac_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)474 static int stmmac_set_ringparam(struct net_device *netdev,
475 struct ethtool_ringparam *ring)
476 {
477 if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
478 ring->rx_pending < DMA_MIN_RX_SIZE ||
479 ring->rx_pending > DMA_MAX_RX_SIZE ||
480 !is_power_of_2(ring->rx_pending) ||
481 ring->tx_pending < DMA_MIN_TX_SIZE ||
482 ring->tx_pending > DMA_MAX_TX_SIZE ||
483 !is_power_of_2(ring->tx_pending))
484 return -EINVAL;
485
486 return stmmac_reinit_ringparam(netdev, ring->rx_pending,
487 ring->tx_pending);
488 }
489
490 static void
stmmac_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)491 stmmac_get_pauseparam(struct net_device *netdev,
492 struct ethtool_pauseparam *pause)
493 {
494 struct stmmac_priv *priv = netdev_priv(netdev);
495 struct rgmii_adv adv_lp;
496
497 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
498 pause->autoneg = 1;
499 if (!adv_lp.pause)
500 return;
501 } else {
502 phylink_ethtool_get_pauseparam(priv->phylink, pause);
503 }
504 }
505
506 static int
stmmac_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)507 stmmac_set_pauseparam(struct net_device *netdev,
508 struct ethtool_pauseparam *pause)
509 {
510 struct stmmac_priv *priv = netdev_priv(netdev);
511 struct rgmii_adv adv_lp;
512
513 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
514 pause->autoneg = 1;
515 if (!adv_lp.pause)
516 return -EOPNOTSUPP;
517 return 0;
518 } else {
519 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
520 }
521 }
522
stmmac_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * dummy,u64 * data)523 static void stmmac_get_ethtool_stats(struct net_device *dev,
524 struct ethtool_stats *dummy, u64 *data)
525 {
526 struct stmmac_priv *priv = netdev_priv(dev);
527 u32 rx_queues_count = priv->plat->rx_queues_to_use;
528 u32 tx_queues_count = priv->plat->tx_queues_to_use;
529 unsigned long count;
530 int i, j = 0, ret;
531
532 if (priv->dma_cap.asp) {
533 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
534 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
535 &count, NULL))
536 data[j++] = count;
537 }
538 }
539
540 /* Update the DMA HW counters for dwmac10/100 */
541 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats,
542 priv->ioaddr);
543 if (ret) {
544 /* If supported, for new GMAC chips expose the MMC counters */
545 if (priv->dma_cap.rmon) {
546 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
547
548 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
549 char *p;
550 p = (char *)priv + stmmac_mmc[i].stat_offset;
551
552 data[j++] = (stmmac_mmc[i].sizeof_stat ==
553 sizeof(u64)) ? (*(u64 *)p) :
554 (*(u32 *)p);
555 }
556 }
557 if (priv->eee_enabled) {
558 int val = phylink_get_eee_err(priv->phylink);
559 if (val)
560 priv->xstats.phy_eee_wakeup_error_n = val;
561 }
562
563 if (priv->synopsys_id >= DWMAC_CORE_3_50)
564 stmmac_mac_debug(priv, priv->ioaddr,
565 (void *)&priv->xstats,
566 rx_queues_count, tx_queues_count);
567 }
568 for (i = 0; i < STMMAC_STATS_LEN; i++) {
569 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
570 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
571 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
572 }
573 }
574
stmmac_get_sset_count(struct net_device * netdev,int sset)575 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
576 {
577 struct stmmac_priv *priv = netdev_priv(netdev);
578 int i, len, safety_len = 0;
579
580 switch (sset) {
581 case ETH_SS_STATS:
582 len = STMMAC_STATS_LEN;
583
584 if (priv->dma_cap.rmon)
585 len += STMMAC_MMC_STATS_LEN;
586 if (priv->dma_cap.asp) {
587 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
588 if (!stmmac_safety_feat_dump(priv,
589 &priv->sstats, i,
590 NULL, NULL))
591 safety_len++;
592 }
593
594 len += safety_len;
595 }
596
597 return len;
598 case ETH_SS_TEST:
599 return stmmac_selftest_get_count(priv);
600 default:
601 return -EOPNOTSUPP;
602 }
603 }
604
stmmac_get_strings(struct net_device * dev,u32 stringset,u8 * data)605 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
606 {
607 int i;
608 u8 *p = data;
609 struct stmmac_priv *priv = netdev_priv(dev);
610
611 switch (stringset) {
612 case ETH_SS_STATS:
613 if (priv->dma_cap.asp) {
614 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
615 const char *desc;
616 if (!stmmac_safety_feat_dump(priv,
617 &priv->sstats, i,
618 NULL, &desc)) {
619 memcpy(p, desc, ETH_GSTRING_LEN);
620 p += ETH_GSTRING_LEN;
621 }
622 }
623 }
624 if (priv->dma_cap.rmon)
625 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
626 memcpy(p, stmmac_mmc[i].stat_string,
627 ETH_GSTRING_LEN);
628 p += ETH_GSTRING_LEN;
629 }
630 for (i = 0; i < STMMAC_STATS_LEN; i++) {
631 memcpy(p, stmmac_gstrings_stats[i].stat_string,
632 ETH_GSTRING_LEN);
633 p += ETH_GSTRING_LEN;
634 }
635 break;
636 case ETH_SS_TEST:
637 stmmac_selftest_get_strings(priv, p);
638 break;
639 default:
640 WARN_ON(1);
641 break;
642 }
643 }
644
645 /* Currently only support WOL through Magic packet. */
stmmac_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)646 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
647 {
648 struct stmmac_priv *priv = netdev_priv(dev);
649
650 if (!priv->plat->pmt)
651 return phylink_ethtool_get_wol(priv->phylink, wol);
652
653 mutex_lock(&priv->lock);
654 if (device_can_wakeup(priv->device)) {
655 wol->supported = WAKE_MAGIC | WAKE_UCAST;
656 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame)
657 wol->supported &= ~WAKE_MAGIC;
658 wol->wolopts = priv->wolopts;
659 }
660 mutex_unlock(&priv->lock);
661 }
662
stmmac_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)663 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
664 {
665 struct stmmac_priv *priv = netdev_priv(dev);
666 u32 support = WAKE_MAGIC | WAKE_UCAST;
667
668 if (!device_can_wakeup(priv->device))
669 return -EOPNOTSUPP;
670
671 if (!priv->plat->pmt) {
672 int ret = phylink_ethtool_set_wol(priv->phylink, wol);
673
674 if (!ret)
675 device_set_wakeup_enable(priv->device, !!wol->wolopts);
676 return ret;
677 }
678
679 /* By default almost all GMAC devices support the WoL via
680 * magic frame but we can disable it if the HW capability
681 * register shows no support for pmt_magic_frame. */
682 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
683 wol->wolopts &= ~WAKE_MAGIC;
684
685 if (wol->wolopts & ~support)
686 return -EINVAL;
687
688 if (wol->wolopts) {
689 pr_info("stmmac: wakeup enable\n");
690 device_set_wakeup_enable(priv->device, 1);
691 enable_irq_wake(priv->wol_irq);
692 } else {
693 device_set_wakeup_enable(priv->device, 0);
694 disable_irq_wake(priv->wol_irq);
695 }
696
697 mutex_lock(&priv->lock);
698 priv->wolopts = wol->wolopts;
699 mutex_unlock(&priv->lock);
700
701 return 0;
702 }
703
stmmac_ethtool_op_get_eee(struct net_device * dev,struct ethtool_eee * edata)704 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
705 struct ethtool_eee *edata)
706 {
707 struct stmmac_priv *priv = netdev_priv(dev);
708
709 if (!priv->dma_cap.eee)
710 return -EOPNOTSUPP;
711
712 edata->eee_enabled = priv->eee_enabled;
713 edata->eee_active = priv->eee_active;
714 edata->tx_lpi_timer = priv->tx_lpi_timer;
715 edata->tx_lpi_enabled = priv->tx_lpi_enabled;
716
717 return phylink_ethtool_get_eee(priv->phylink, edata);
718 }
719
stmmac_ethtool_op_set_eee(struct net_device * dev,struct ethtool_eee * edata)720 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
721 struct ethtool_eee *edata)
722 {
723 struct stmmac_priv *priv = netdev_priv(dev);
724 int ret;
725
726 if (!priv->dma_cap.eee)
727 return -EOPNOTSUPP;
728
729 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled)
730 netdev_warn(priv->dev,
731 "Setting EEE tx-lpi is not supported\n");
732
733 if (!edata->eee_enabled)
734 stmmac_disable_eee_mode(priv);
735
736 ret = phylink_ethtool_set_eee(priv->phylink, edata);
737 if (ret)
738 return ret;
739
740 if (edata->eee_enabled &&
741 priv->tx_lpi_timer != edata->tx_lpi_timer) {
742 priv->tx_lpi_timer = edata->tx_lpi_timer;
743 stmmac_eee_init(priv);
744 }
745
746 return 0;
747 }
748
stmmac_usec2riwt(u32 usec,struct stmmac_priv * priv)749 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
750 {
751 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
752
753 if (!clk) {
754 clk = priv->plat->clk_ref_rate;
755 if (!clk)
756 return 0;
757 }
758
759 return (usec * (clk / 1000000)) / 256;
760 }
761
stmmac_riwt2usec(u32 riwt,struct stmmac_priv * priv)762 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
763 {
764 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
765
766 if (!clk) {
767 clk = priv->plat->clk_ref_rate;
768 if (!clk)
769 return 0;
770 }
771
772 return (riwt * 256) / (clk / 1000000);
773 }
774
stmmac_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)775 static int stmmac_get_coalesce(struct net_device *dev,
776 struct ethtool_coalesce *ec)
777 {
778 struct stmmac_priv *priv = netdev_priv(dev);
779
780 ec->tx_coalesce_usecs = priv->tx_coal_timer;
781 ec->tx_max_coalesced_frames = priv->tx_coal_frames;
782
783 if (priv->use_riwt) {
784 ec->rx_max_coalesced_frames = priv->rx_coal_frames;
785 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv);
786 }
787
788 return 0;
789 }
790
stmmac_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)791 static int stmmac_set_coalesce(struct net_device *dev,
792 struct ethtool_coalesce *ec)
793 {
794 struct stmmac_priv *priv = netdev_priv(dev);
795 u32 rx_cnt = priv->plat->rx_queues_to_use;
796 unsigned int rx_riwt;
797
798 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) {
799 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
800
801 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
802 return -EINVAL;
803
804 priv->rx_riwt = rx_riwt;
805 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
806 }
807
808 if ((ec->tx_coalesce_usecs == 0) &&
809 (ec->tx_max_coalesced_frames == 0))
810 return -EINVAL;
811
812 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
813 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
814 return -EINVAL;
815
816 /* Only copy relevant parameters, ignore all others. */
817 priv->tx_coal_frames = ec->tx_max_coalesced_frames;
818 priv->tx_coal_timer = ec->tx_coalesce_usecs;
819 priv->rx_coal_frames = ec->rx_max_coalesced_frames;
820 return 0;
821 }
822
stmmac_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)823 static int stmmac_get_rxnfc(struct net_device *dev,
824 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
825 {
826 struct stmmac_priv *priv = netdev_priv(dev);
827
828 switch (rxnfc->cmd) {
829 case ETHTOOL_GRXRINGS:
830 rxnfc->data = priv->plat->rx_queues_to_use;
831 break;
832 default:
833 return -EOPNOTSUPP;
834 }
835
836 return 0;
837 }
838
stmmac_get_rxfh_key_size(struct net_device * dev)839 static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
840 {
841 struct stmmac_priv *priv = netdev_priv(dev);
842
843 return sizeof(priv->rss.key);
844 }
845
stmmac_get_rxfh_indir_size(struct net_device * dev)846 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
847 {
848 struct stmmac_priv *priv = netdev_priv(dev);
849
850 return ARRAY_SIZE(priv->rss.table);
851 }
852
stmmac_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)853 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
854 u8 *hfunc)
855 {
856 struct stmmac_priv *priv = netdev_priv(dev);
857 int i;
858
859 if (indir) {
860 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
861 indir[i] = priv->rss.table[i];
862 }
863
864 if (key)
865 memcpy(key, priv->rss.key, sizeof(priv->rss.key));
866 if (hfunc)
867 *hfunc = ETH_RSS_HASH_TOP;
868
869 return 0;
870 }
871
stmmac_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)872 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,
873 const u8 *key, const u8 hfunc)
874 {
875 struct stmmac_priv *priv = netdev_priv(dev);
876 int i;
877
878 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP))
879 return -EOPNOTSUPP;
880
881 if (indir) {
882 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
883 priv->rss.table[i] = indir[i];
884 }
885
886 if (key)
887 memcpy(priv->rss.key, key, sizeof(priv->rss.key));
888
889 return stmmac_rss_configure(priv, priv->hw, &priv->rss,
890 priv->plat->rx_queues_to_use);
891 }
892
stmmac_get_channels(struct net_device * dev,struct ethtool_channels * chan)893 static void stmmac_get_channels(struct net_device *dev,
894 struct ethtool_channels *chan)
895 {
896 struct stmmac_priv *priv = netdev_priv(dev);
897
898 chan->rx_count = priv->plat->rx_queues_to_use;
899 chan->tx_count = priv->plat->tx_queues_to_use;
900 chan->max_rx = priv->dma_cap.number_rx_queues;
901 chan->max_tx = priv->dma_cap.number_tx_queues;
902 }
903
stmmac_set_channels(struct net_device * dev,struct ethtool_channels * chan)904 static int stmmac_set_channels(struct net_device *dev,
905 struct ethtool_channels *chan)
906 {
907 struct stmmac_priv *priv = netdev_priv(dev);
908
909 if (chan->rx_count > priv->dma_cap.number_rx_queues ||
910 chan->tx_count > priv->dma_cap.number_tx_queues ||
911 !chan->rx_count || !chan->tx_count)
912 return -EINVAL;
913
914 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
915 }
916
stmmac_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)917 static int stmmac_get_ts_info(struct net_device *dev,
918 struct ethtool_ts_info *info)
919 {
920 struct stmmac_priv *priv = netdev_priv(dev);
921
922 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
923
924 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
925 SOF_TIMESTAMPING_TX_HARDWARE |
926 SOF_TIMESTAMPING_RX_SOFTWARE |
927 SOF_TIMESTAMPING_RX_HARDWARE |
928 SOF_TIMESTAMPING_SOFTWARE |
929 SOF_TIMESTAMPING_RAW_HARDWARE;
930
931 if (priv->ptp_clock)
932 info->phc_index = ptp_clock_index(priv->ptp_clock);
933
934 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
935
936 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
937 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
938 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
939 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
940 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
941 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
942 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
943 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
944 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
945 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
946 (1 << HWTSTAMP_FILTER_ALL));
947 return 0;
948 } else
949 return ethtool_op_get_ts_info(dev, info);
950 }
951
stmmac_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)952 static int stmmac_get_tunable(struct net_device *dev,
953 const struct ethtool_tunable *tuna, void *data)
954 {
955 struct stmmac_priv *priv = netdev_priv(dev);
956 int ret = 0;
957
958 switch (tuna->id) {
959 case ETHTOOL_RX_COPYBREAK:
960 *(u32 *)data = priv->rx_copybreak;
961 break;
962 default:
963 ret = -EINVAL;
964 break;
965 }
966
967 return ret;
968 }
969
stmmac_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)970 static int stmmac_set_tunable(struct net_device *dev,
971 const struct ethtool_tunable *tuna,
972 const void *data)
973 {
974 struct stmmac_priv *priv = netdev_priv(dev);
975 int ret = 0;
976
977 switch (tuna->id) {
978 case ETHTOOL_RX_COPYBREAK:
979 priv->rx_copybreak = *(u32 *)data;
980 break;
981 default:
982 ret = -EINVAL;
983 break;
984 }
985
986 return ret;
987 }
988
989 static const struct ethtool_ops stmmac_ethtool_ops = {
990 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
991 ETHTOOL_COALESCE_MAX_FRAMES,
992 .begin = stmmac_check_if_running,
993 .get_drvinfo = stmmac_ethtool_getdrvinfo,
994 .get_msglevel = stmmac_ethtool_getmsglevel,
995 .set_msglevel = stmmac_ethtool_setmsglevel,
996 .get_regs = stmmac_ethtool_gregs,
997 .get_regs_len = stmmac_ethtool_get_regs_len,
998 .get_link = ethtool_op_get_link,
999 .nway_reset = stmmac_nway_reset,
1000 .get_ringparam = stmmac_get_ringparam,
1001 .set_ringparam = stmmac_set_ringparam,
1002 .get_pauseparam = stmmac_get_pauseparam,
1003 .set_pauseparam = stmmac_set_pauseparam,
1004 .self_test = stmmac_selftest_run,
1005 .get_ethtool_stats = stmmac_get_ethtool_stats,
1006 .get_strings = stmmac_get_strings,
1007 .get_wol = stmmac_get_wol,
1008 .set_wol = stmmac_set_wol,
1009 .get_eee = stmmac_ethtool_op_get_eee,
1010 .set_eee = stmmac_ethtool_op_set_eee,
1011 .get_sset_count = stmmac_get_sset_count,
1012 .get_rxnfc = stmmac_get_rxnfc,
1013 .get_rxfh_key_size = stmmac_get_rxfh_key_size,
1014 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1015 .get_rxfh = stmmac_get_rxfh,
1016 .set_rxfh = stmmac_set_rxfh,
1017 .get_ts_info = stmmac_get_ts_info,
1018 .get_coalesce = stmmac_get_coalesce,
1019 .set_coalesce = stmmac_set_coalesce,
1020 .get_channels = stmmac_get_channels,
1021 .set_channels = stmmac_set_channels,
1022 .get_tunable = stmmac_get_tunable,
1023 .set_tunable = stmmac_set_tunable,
1024 .get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1025 .set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1026 };
1027
stmmac_set_ethtool_ops(struct net_device * netdev)1028 void stmmac_set_ethtool_ops(struct net_device *netdev)
1029 {
1030 netdev->ethtool_ops = &stmmac_ethtool_ops;
1031 }
1032