1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/phy/phy.h>
15 #include <linux/of_net.h>
16 #include <linux/gpio.h>
17 #include <linux/module.h>
18 #include <linux/nvmem-consumer.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/regmap.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/soc/rockchip/rk_vendor_storage.h>
28 #include "stmmac_platform.h"
29 #include "dwmac-rk-tool.h"
30
31 #define MAX_ETH 2
32
33 struct rk_priv_data;
34 struct rk_gmac_ops {
35 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
36 int tx_delay, int rx_delay);
37 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
38 void (*set_to_sgmii)(struct rk_priv_data *bsp_priv);
39 void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
40 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
41 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
42 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
43 bool enable);
44 void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
45 };
46
47 struct rk_priv_data {
48 struct platform_device *pdev;
49 phy_interface_t phy_iface;
50 int bus_id;
51 struct regulator *regulator;
52 bool suspended;
53 const struct rk_gmac_ops *ops;
54
55 bool clk_enabled;
56 bool clock_input;
57 bool integrated_phy;
58
59 struct clk *clk_mac;
60 struct clk *gmac_clkin;
61 struct clk *mac_clk_rx;
62 struct clk *mac_clk_tx;
63 struct clk *clk_mac_ref;
64 struct clk *clk_mac_refout;
65 struct clk *clk_mac_speed;
66 struct clk *aclk_mac;
67 struct clk *pclk_mac;
68 struct clk *clk_phy;
69 struct clk *pclk_xpcs;
70 struct clk *clk_xpcs_eee;
71
72 struct reset_control *phy_reset;
73
74 int tx_delay;
75 int rx_delay;
76
77 struct regmap *grf;
78 struct regmap *php_grf;
79 struct regmap *xpcs;
80
81 unsigned char otp_data;
82 unsigned int bgs_increment;
83 };
84
85 /* XPCS */
86 #define XPCS_APB_INCREMENT (0x4)
87 #define XPCS_APB_MASK GENMASK_ULL(20, 0)
88
89 #define SR_MII_BASE (0x1F0000)
90 #define SR_MII1_BASE (0x1A0000)
91
92 #define VR_MII_DIG_CTRL1 (0x8000)
93 #define VR_MII_AN_CTRL (0x8001)
94 #define VR_MII_AN_INTR_STS (0x8002)
95 #define VR_MII_LINK_TIMER_CTRL (0x800A)
96
97 #define SR_MII_CTRL_AN_ENABLE \
98 (BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000)
99 #define MII_MAC_AUTO_SW (0x0200)
100 #define PCS_MODE_OFFSET (0x1)
101 #define MII_AN_INTR_EN (0x1)
102 #define PCS_SGMII_MODE (0x2 << PCS_MODE_OFFSET)
103 #define PCS_QSGMII_MODE (0X3 << PCS_MODE_OFFSET)
104 #define VR_MII_CTRL_SGMII_AN_EN (PCS_SGMII_MODE | MII_AN_INTR_EN)
105 #define VR_MII_CTRL_QSGMII_AN_EN (PCS_QSGMII_MODE | MII_AN_INTR_EN)
106
107 #define SR_MII_OFFSET(_x) ({ \
108 typeof(_x) (x) = (_x); \
109 (((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \
110 }) \
111
xpcs_read(void * priv,int reg)112 static int xpcs_read(void *priv, int reg)
113 {
114 struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
115 int ret, val;
116
117 ret = regmap_read(bsp_priv->xpcs,
118 (u32)(reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK,
119 &val);
120 if (ret)
121 return ret;
122
123 return val;
124 }
125
xpcs_write(void * priv,int reg,u16 value)126 static int xpcs_write(void *priv, int reg, u16 value)
127 {
128 struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
129
130 return regmap_write(bsp_priv->xpcs,
131 (reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, value);
132 }
133
xpcs_poll_reset(struct rk_priv_data * bsp_priv,int dev)134 static int xpcs_poll_reset(struct rk_priv_data *bsp_priv, int dev)
135 {
136 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
137 unsigned int retries = 12;
138 int ret;
139
140 do {
141 msleep(50);
142 ret = xpcs_read(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1);
143 if (ret < 0)
144 return ret;
145 } while (ret & MDIO_CTRL1_RESET && --retries);
146
147 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
148 }
149
xpcs_soft_reset(struct rk_priv_data * bsp_priv,int dev)150 static int xpcs_soft_reset(struct rk_priv_data *bsp_priv, int dev)
151 {
152 int ret;
153
154 ret = xpcs_write(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1,
155 MDIO_CTRL1_RESET);
156 if (ret < 0)
157 return ret;
158
159 return xpcs_poll_reset(bsp_priv, dev);
160 }
161
xpcs_setup(struct rk_priv_data * bsp_priv,int mode)162 static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode)
163 {
164 int ret, i, id = bsp_priv->bus_id;
165 u32 val;
166
167 if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
168 return 0;
169
170 ret = xpcs_soft_reset(bsp_priv, id);
171 if (ret) {
172 dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
173 return ret;
174 }
175
176 xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0);
177 xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1);
178
179 if (mode == PHY_INTERFACE_MODE_SGMII)
180 xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
181 VR_MII_CTRL_SGMII_AN_EN);
182 else
183 xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
184 VR_MII_CTRL_QSGMII_AN_EN);
185
186 if (mode == PHY_INTERFACE_MODE_QSGMII) {
187 for (i = 0; i < 4; i++) {
188 val = xpcs_read(bsp_priv,
189 SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1);
190 xpcs_write(bsp_priv,
191 SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1,
192 val | MII_MAC_AUTO_SW);
193 xpcs_write(bsp_priv, SR_MII_OFFSET(i) + MII_BMCR,
194 SR_MII_CTRL_AN_ENABLE);
195 }
196 } else {
197 val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
198 xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
199 val | MII_MAC_AUTO_SW);
200 xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
201 SR_MII_CTRL_AN_ENABLE);
202 }
203
204 return ret;
205 }
206
207 #define HIWORD_UPDATE(val, mask, shift) \
208 ((val) << (shift) | (mask) << ((shift) + 16))
209
210 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
211 #define GRF_CLR_BIT(nr) (BIT(nr+16))
212
213 #define DELAY_ENABLE(soc, tx, rx) \
214 ((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
215 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
216
217 #define DELAY_ENABLE_BY_ID(soc, tx, rx, id) \
218 ((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE(id) : soc##_GMAC_TXCLK_DLY_DISABLE(id)) | \
219 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE(id) : soc##_GMAC_RXCLK_DLY_DISABLE(id)))
220
221 #define DELAY_VALUE(soc, tx, rx) \
222 ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
223 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
224
225 #define GMAC_RGMII_CLK_DIV_BY_ID(soc, id, div) \
226 (soc##_GMAC##id##_CLK_RGMII_DIV##div)
227
228 #define GMAC_RMII_CLK_DIV_BY_ID(soc, id, div) \
229 (soc##_GMAC##id##_CLK_RMII_DIV##div)
230
231 /* Integrated EPHY */
232
233 #define RK_GRF_MACPHY_CON0 0xb00
234 #define RK_GRF_MACPHY_CON1 0xb04
235 #define RK_GRF_MACPHY_CON2 0xb08
236 #define RK_GRF_MACPHY_CON3 0xb0c
237
238 #define RK_MACPHY_ENABLE GRF_BIT(0)
239 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
240 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
241 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
242 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
243 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
244
rk_gmac_integrated_ephy_powerup(struct rk_priv_data * priv)245 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
246 {
247 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
248 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
249
250 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
251 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
252
253 if (priv->phy_reset) {
254 /* PHY needs to be disabled before trying to reset it */
255 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
256 if (priv->phy_reset)
257 reset_control_assert(priv->phy_reset);
258 usleep_range(10, 20);
259 if (priv->phy_reset)
260 reset_control_deassert(priv->phy_reset);
261 usleep_range(10, 20);
262 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
263 msleep(30);
264 }
265 }
266
rk_gmac_integrated_ephy_powerdown(struct rk_priv_data * priv)267 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
268 {
269 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
270 if (priv->phy_reset)
271 reset_control_assert(priv->phy_reset);
272 }
273
274 /* Integrated FEPHY */
275 #define RK_FEPHY_SHUTDOWN GRF_BIT(1)
276 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
277 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
278 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
279 #define RK_FEPHY_PHY_ID GRF_BIT(11)
280
281 #define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0)
282
283 #define RK_FEPHY_BGS_MAX 7
284
rk_gmac_integrated_fephy_power(struct rk_priv_data * priv,unsigned int ctrl_offset,unsigned int bgs_offset,bool up)285 static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
286 unsigned int ctrl_offset,
287 unsigned int bgs_offset,
288 bool up)
289 {
290 struct device *dev = &priv->pdev->dev;
291
292 if (IS_ERR(priv->grf) || !priv->phy_reset) {
293 dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
294 __func__);
295 return;
296 }
297
298 if (up) {
299 unsigned int bgs = priv->otp_data;
300
301 reset_control_assert(priv->phy_reset);
302 udelay(20);
303 regmap_write(priv->grf, ctrl_offset,
304 RK_FEPHY_POWERUP |
305 RK_FEPHY_INTERNAL_RMII_SEL |
306 RK_FEPHY_24M_CLK_SEL |
307 RK_FEPHY_PHY_ID);
308
309 if (bgs > (RK_FEPHY_BGS_MAX - priv->bgs_increment) &&
310 bgs <= RK_FEPHY_BGS_MAX) {
311 bgs = HIWORD_UPDATE(RK_FEPHY_BGS_MAX, 0xf, 0);
312 } else {
313 bgs += priv->bgs_increment;
314 bgs &= 0xf;
315 bgs = HIWORD_UPDATE(bgs, 0xf, 0);
316 }
317
318 regmap_write(priv->grf, bgs_offset, bgs);
319 usleep_range(10 * 1000, 12 * 1000);
320 reset_control_deassert(priv->phy_reset);
321 usleep_range(50 * 1000, 60 * 1000);
322 } else {
323 regmap_write(priv->grf, ctrl_offset,
324 RK_FEPHY_SHUTDOWN);
325 }
326 }
327
328 #define PX30_GRF_GMAC_CON1 0x0904
329
330 /* PX30_GRF_GMAC_CON1 */
331 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
332 GRF_BIT(6))
333 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
334 #define PX30_GMAC_SPEED_100M GRF_BIT(2)
335
px30_set_to_rmii(struct rk_priv_data * bsp_priv)336 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
337 {
338 struct device *dev = &bsp_priv->pdev->dev;
339
340 if (IS_ERR(bsp_priv->grf)) {
341 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
342 return;
343 }
344
345 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
346 PX30_GMAC_PHY_INTF_SEL_RMII);
347 }
348
px30_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)349 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
350 {
351 struct device *dev = &bsp_priv->pdev->dev;
352 int ret;
353
354 if (IS_ERR(bsp_priv->clk_mac_speed)) {
355 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
356 return;
357 }
358
359 if (speed == 10) {
360 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
361 PX30_GMAC_SPEED_10M);
362
363 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
364 if (ret)
365 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
366 __func__, ret);
367 } else if (speed == 100) {
368 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
369 PX30_GMAC_SPEED_100M);
370
371 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
372 if (ret)
373 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
374 __func__, ret);
375
376 } else {
377 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
378 }
379 }
380
381 static const struct rk_gmac_ops px30_ops = {
382 .set_to_rmii = px30_set_to_rmii,
383 .set_rmii_speed = px30_set_rmii_speed,
384 };
385
386 #define RK1808_GRF_GMAC_CON0 0X0900
387 #define RK1808_GRF_GMAC_CON1 0X0904
388
389 /* RK1808_GRF_GMAC_CON0 */
390 #define RK1808_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
391 #define RK1808_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
392
393 /* RK1808_GRF_GMAC_CON1 */
394 #define RK1808_GMAC_PHY_INTF_SEL_RGMII \
395 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
396 #define RK1808_GMAC_PHY_INTF_SEL_RMII \
397 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
398 #define RK1808_GMAC_FLOW_CTRL GRF_BIT(3)
399 #define RK1808_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
400 #define RK1808_GMAC_SPEED_10M GRF_CLR_BIT(2)
401 #define RK1808_GMAC_SPEED_100M GRF_BIT(2)
402 #define RK1808_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
403 #define RK1808_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
404 #define RK1808_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
405 #define RK1808_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
406
rk1808_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)407 static void rk1808_set_to_rgmii(struct rk_priv_data *bsp_priv,
408 int tx_delay, int rx_delay)
409 {
410 struct device *dev = &bsp_priv->pdev->dev;
411
412 if (IS_ERR(bsp_priv->grf)) {
413 dev_err(dev, "Missing rockchip,grf property\n");
414 return;
415 }
416
417 regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
418 RK1808_GMAC_PHY_INTF_SEL_RGMII |
419 DELAY_ENABLE(RK1808, tx_delay, rx_delay));
420
421 regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
422 DELAY_VALUE(RK1808, tx_delay, rx_delay));
423 }
424
rk1808_set_to_rmii(struct rk_priv_data * bsp_priv)425 static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
426 {
427 struct device *dev = &bsp_priv->pdev->dev;
428
429 if (IS_ERR(bsp_priv->grf)) {
430 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
431 return;
432 }
433
434 regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
435 RK1808_GMAC_PHY_INTF_SEL_RMII);
436 }
437
rk1808_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)438 static void rk1808_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
439 {
440 struct device *dev = &bsp_priv->pdev->dev;
441 int ret;
442
443 if (IS_ERR(bsp_priv->grf)) {
444 dev_err(dev, "Missing rockchip,grf property\n");
445 return;
446 }
447
448 if (speed == 10) {
449 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
450 if (ret)
451 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
452 __func__, ret);
453 } else if (speed == 100) {
454 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
455 if (ret)
456 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
457 __func__, ret);
458 } else if (speed == 1000) {
459 ret = clk_set_rate(bsp_priv->clk_mac_speed, 125000000);
460 if (ret)
461 dev_err(dev, "%s: set clk_mac_speed rate 125000000 failed: %d\n",
462 __func__, ret);
463 } else {
464 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
465 }
466 }
467
rk1808_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)468 static void rk1808_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
469 {
470 struct device *dev = &bsp_priv->pdev->dev;
471 int ret;
472
473 if (IS_ERR(bsp_priv->clk_mac_speed)) {
474 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
475 return;
476 }
477
478 if (speed == 10) {
479 regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
480 RK1808_GMAC_SPEED_10M);
481
482 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
483 if (ret)
484 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
485 __func__, ret);
486 } else if (speed == 100) {
487 regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
488 RK1808_GMAC_SPEED_100M);
489
490 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
491 if (ret)
492 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
493 __func__, ret);
494
495 } else {
496 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
497 }
498 }
499
500 static const struct rk_gmac_ops rk1808_ops = {
501 .set_to_rgmii = rk1808_set_to_rgmii,
502 .set_to_rmii = rk1808_set_to_rmii,
503 .set_rgmii_speed = rk1808_set_rgmii_speed,
504 .set_rmii_speed = rk1808_set_rmii_speed,
505 };
506
507 #define RK3128_GRF_MAC_CON0 0x0168
508 #define RK3128_GRF_MAC_CON1 0x016c
509
510 /* RK3128_GRF_MAC_CON0 */
511 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
512 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
513 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
514 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
515 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
516 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
517
518 /* RK3128_GRF_MAC_CON1 */
519 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \
520 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
521 #define RK3128_GMAC_PHY_INTF_SEL_RMII \
522 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
523 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
524 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
525 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
526 #define RK3128_GMAC_SPEED_100M GRF_BIT(10)
527 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
528 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
529 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
530 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
531 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
532 #define RK3128_GMAC_RMII_MODE GRF_BIT(14)
533 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
534
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)535 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
536 int tx_delay, int rx_delay)
537 {
538 struct device *dev = &bsp_priv->pdev->dev;
539
540 if (IS_ERR(bsp_priv->grf)) {
541 dev_err(dev, "Missing rockchip,grf property\n");
542 return;
543 }
544
545 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
546 RK3128_GMAC_PHY_INTF_SEL_RGMII |
547 RK3128_GMAC_RMII_MODE_CLR);
548 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
549 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
550 DELAY_VALUE(RK3128, tx_delay, rx_delay));
551 }
552
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)553 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
554 {
555 struct device *dev = &bsp_priv->pdev->dev;
556
557 if (IS_ERR(bsp_priv->grf)) {
558 dev_err(dev, "Missing rockchip,grf property\n");
559 return;
560 }
561
562 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
563 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
564 }
565
rk3128_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)566 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
567 {
568 struct device *dev = &bsp_priv->pdev->dev;
569
570 if (IS_ERR(bsp_priv->grf)) {
571 dev_err(dev, "Missing rockchip,grf property\n");
572 return;
573 }
574
575 if (speed == 10)
576 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
577 RK3128_GMAC_CLK_2_5M);
578 else if (speed == 100)
579 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
580 RK3128_GMAC_CLK_25M);
581 else if (speed == 1000)
582 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
583 RK3128_GMAC_CLK_125M);
584 else
585 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
586 }
587
rk3128_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)588 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
589 {
590 struct device *dev = &bsp_priv->pdev->dev;
591
592 if (IS_ERR(bsp_priv->grf)) {
593 dev_err(dev, "Missing rockchip,grf property\n");
594 return;
595 }
596
597 if (speed == 10) {
598 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
599 RK3128_GMAC_RMII_CLK_2_5M |
600 RK3128_GMAC_SPEED_10M);
601 } else if (speed == 100) {
602 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
603 RK3128_GMAC_RMII_CLK_25M |
604 RK3128_GMAC_SPEED_100M);
605 } else {
606 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
607 }
608 }
609
610 static const struct rk_gmac_ops rk3128_ops = {
611 .set_to_rgmii = rk3128_set_to_rgmii,
612 .set_to_rmii = rk3128_set_to_rmii,
613 .set_rgmii_speed = rk3128_set_rgmii_speed,
614 .set_rmii_speed = rk3128_set_rmii_speed,
615 };
616
617 #define RK3228_GRF_MAC_CON0 0x0900
618 #define RK3228_GRF_MAC_CON1 0x0904
619
620 #define RK3228_GRF_CON_MUX 0x50
621
622 /* RK3228_GRF_MAC_CON0 */
623 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
624 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
625
626 /* RK3228_GRF_MAC_CON1 */
627 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
628 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
629 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
630 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
631 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
632 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
633 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
634 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
635 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
636 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
637 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
638 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
639 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
640 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
641 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
642 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
643 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
644 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
645 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
646
647 /* RK3228_GRF_COM_MUX */
648 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
649
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)650 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
651 int tx_delay, int rx_delay)
652 {
653 struct device *dev = &bsp_priv->pdev->dev;
654
655 if (IS_ERR(bsp_priv->grf)) {
656 dev_err(dev, "Missing rockchip,grf property\n");
657 return;
658 }
659
660 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
661 RK3228_GMAC_PHY_INTF_SEL_RGMII |
662 RK3228_GMAC_RMII_MODE_CLR |
663 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
664
665 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
666 DELAY_VALUE(RK3128, tx_delay, rx_delay));
667 }
668
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)669 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
670 {
671 struct device *dev = &bsp_priv->pdev->dev;
672
673 if (IS_ERR(bsp_priv->grf)) {
674 dev_err(dev, "Missing rockchip,grf property\n");
675 return;
676 }
677
678 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
679 RK3228_GMAC_PHY_INTF_SEL_RMII |
680 RK3228_GMAC_RMII_MODE);
681
682 /* set MAC to RMII mode */
683 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
684 }
685
rk3228_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)686 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
687 {
688 struct device *dev = &bsp_priv->pdev->dev;
689
690 if (IS_ERR(bsp_priv->grf)) {
691 dev_err(dev, "Missing rockchip,grf property\n");
692 return;
693 }
694
695 if (speed == 10)
696 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
697 RK3228_GMAC_CLK_2_5M);
698 else if (speed == 100)
699 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
700 RK3228_GMAC_CLK_25M);
701 else if (speed == 1000)
702 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
703 RK3228_GMAC_CLK_125M);
704 else
705 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
706 }
707
rk3228_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)708 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
709 {
710 struct device *dev = &bsp_priv->pdev->dev;
711
712 if (IS_ERR(bsp_priv->grf)) {
713 dev_err(dev, "Missing rockchip,grf property\n");
714 return;
715 }
716
717 if (speed == 10)
718 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
719 RK3228_GMAC_RMII_CLK_2_5M |
720 RK3228_GMAC_SPEED_10M);
721 else if (speed == 100)
722 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
723 RK3228_GMAC_RMII_CLK_25M |
724 RK3228_GMAC_SPEED_100M);
725 else
726 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
727 }
728
rk3228_integrated_phy_power(struct rk_priv_data * priv,bool up)729 static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
730 {
731 if (up) {
732 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
733 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
734
735 rk_gmac_integrated_ephy_powerup(priv);
736 } else {
737 rk_gmac_integrated_ephy_powerdown(priv);
738 }
739 }
740
741 static const struct rk_gmac_ops rk3228_ops = {
742 .set_to_rgmii = rk3228_set_to_rgmii,
743 .set_to_rmii = rk3228_set_to_rmii,
744 .set_rgmii_speed = rk3228_set_rgmii_speed,
745 .set_rmii_speed = rk3228_set_rmii_speed,
746 .integrated_phy_power = rk3228_integrated_phy_power,
747 };
748
749 #define RK3288_GRF_SOC_CON1 0x0248
750 #define RK3288_GRF_SOC_CON3 0x0250
751
752 /*RK3288_GRF_SOC_CON1*/
753 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
754 GRF_CLR_BIT(8))
755 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
756 GRF_BIT(8))
757 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
758 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
759 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
760 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
761 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
762 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
763 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
764 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
765 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
766 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
767 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
768
769 /*RK3288_GRF_SOC_CON3*/
770 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
771 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
772 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
773 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
774 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
775 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
776
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)777 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
778 int tx_delay, int rx_delay)
779 {
780 struct device *dev = &bsp_priv->pdev->dev;
781
782 if (IS_ERR(bsp_priv->grf)) {
783 dev_err(dev, "Missing rockchip,grf property\n");
784 return;
785 }
786
787 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
788 RK3288_GMAC_PHY_INTF_SEL_RGMII |
789 RK3288_GMAC_RMII_MODE_CLR);
790 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
791 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
792 DELAY_VALUE(RK3288, tx_delay, rx_delay));
793 }
794
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)795 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
796 {
797 struct device *dev = &bsp_priv->pdev->dev;
798
799 if (IS_ERR(bsp_priv->grf)) {
800 dev_err(dev, "Missing rockchip,grf property\n");
801 return;
802 }
803
804 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
805 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
806 }
807
rk3288_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)808 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
809 {
810 struct device *dev = &bsp_priv->pdev->dev;
811
812 if (IS_ERR(bsp_priv->grf)) {
813 dev_err(dev, "Missing rockchip,grf property\n");
814 return;
815 }
816
817 if (speed == 10)
818 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
819 RK3288_GMAC_CLK_2_5M);
820 else if (speed == 100)
821 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
822 RK3288_GMAC_CLK_25M);
823 else if (speed == 1000)
824 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
825 RK3288_GMAC_CLK_125M);
826 else
827 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
828 }
829
rk3288_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)830 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
831 {
832 struct device *dev = &bsp_priv->pdev->dev;
833
834 if (IS_ERR(bsp_priv->grf)) {
835 dev_err(dev, "Missing rockchip,grf property\n");
836 return;
837 }
838
839 if (speed == 10) {
840 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
841 RK3288_GMAC_RMII_CLK_2_5M |
842 RK3288_GMAC_SPEED_10M);
843 } else if (speed == 100) {
844 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
845 RK3288_GMAC_RMII_CLK_25M |
846 RK3288_GMAC_SPEED_100M);
847 } else {
848 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
849 }
850 }
851
852 static const struct rk_gmac_ops rk3288_ops = {
853 .set_to_rgmii = rk3288_set_to_rgmii,
854 .set_to_rmii = rk3288_set_to_rmii,
855 .set_rgmii_speed = rk3288_set_rgmii_speed,
856 .set_rmii_speed = rk3288_set_rmii_speed,
857 };
858
859 #define RK3308_GRF_MAC_CON0 0x04a0
860
861 /* Rk3308_GRF_MAC_CON1 */
862 #define RK3308_MAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
863 GRF_BIT(4))
864 #define RK3308_MAC_SPEED_10M GRF_CLR_BIT(0)
865 #define Rk3308_MAC_SPEED_100M GRF_BIT(0)
866
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)867 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
868 {
869 struct device *dev = &bsp_priv->pdev->dev;
870
871 if (IS_ERR(bsp_priv->grf)) {
872 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
873 return;
874 }
875
876 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
877 RK3308_MAC_PHY_INTF_SEL_RMII);
878 }
879
rk3308_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)880 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
881 {
882 struct device *dev = &bsp_priv->pdev->dev;
883 int ret;
884
885 if (IS_ERR(bsp_priv->clk_mac_speed)) {
886 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
887 return;
888 }
889
890 if (speed == 10) {
891 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
892 RK3308_MAC_SPEED_10M);
893
894 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
895 if (ret)
896 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
897 __func__, ret);
898 } else if (speed == 100) {
899 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
900 Rk3308_MAC_SPEED_100M);
901
902 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
903 if (ret)
904 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
905 __func__, ret);
906
907 } else {
908 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
909 }
910 }
911
912 static const struct rk_gmac_ops rk3308_ops = {
913 .set_to_rmii = rk3308_set_to_rmii,
914 .set_rmii_speed = rk3308_set_rmii_speed,
915 };
916
917 #define RK3328_GRF_MAC_CON0 0x0900
918 #define RK3328_GRF_MAC_CON1 0x0904
919 #define RK3328_GRF_MAC_CON2 0x0908
920 #define RK3328_GRF_MACPHY_CON1 0xb04
921
922 /* RK3328_GRF_MAC_CON0 */
923 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
924 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
925
926 /* RK3328_GRF_MAC_CON1 */
927 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \
928 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
929 #define RK3328_GMAC_PHY_INTF_SEL_RMII \
930 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
931 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
932 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
933 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
934 #define RK3328_GMAC_SPEED_100M GRF_BIT(2)
935 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
936 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
937 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
938 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
939 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
940 #define RK3328_GMAC_RMII_MODE GRF_BIT(9)
941 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
942 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
943 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
944 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
945 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
946
947 /* RK3328_GRF_MACPHY_CON1 */
948 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
949
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)950 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
951 int tx_delay, int rx_delay)
952 {
953 struct device *dev = &bsp_priv->pdev->dev;
954
955 if (IS_ERR(bsp_priv->grf)) {
956 dev_err(dev, "Missing rockchip,grf property\n");
957 return;
958 }
959
960 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
961 RK3328_GMAC_PHY_INTF_SEL_RGMII |
962 RK3328_GMAC_RMII_MODE_CLR |
963 DELAY_ENABLE(RK3328, tx_delay, rx_delay));
964
965 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
966 DELAY_VALUE(RK3328, tx_delay, rx_delay));
967 }
968
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)969 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
970 {
971 struct device *dev = &bsp_priv->pdev->dev;
972 unsigned int reg;
973
974 if (IS_ERR(bsp_priv->grf)) {
975 dev_err(dev, "Missing rockchip,grf property\n");
976 return;
977 }
978
979 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
980 RK3328_GRF_MAC_CON1;
981
982 regmap_write(bsp_priv->grf, reg,
983 RK3328_GMAC_PHY_INTF_SEL_RMII |
984 RK3328_GMAC_RMII_MODE);
985 }
986
rk3328_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)987 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
988 {
989 struct device *dev = &bsp_priv->pdev->dev;
990
991 if (IS_ERR(bsp_priv->grf)) {
992 dev_err(dev, "Missing rockchip,grf property\n");
993 return;
994 }
995
996 if (speed == 10)
997 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
998 RK3328_GMAC_CLK_2_5M);
999 else if (speed == 100)
1000 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
1001 RK3328_GMAC_CLK_25M);
1002 else if (speed == 1000)
1003 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
1004 RK3328_GMAC_CLK_125M);
1005 else
1006 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
1007 }
1008
rk3328_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1009 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1010 {
1011 struct device *dev = &bsp_priv->pdev->dev;
1012 unsigned int reg;
1013
1014 if (IS_ERR(bsp_priv->grf)) {
1015 dev_err(dev, "Missing rockchip,grf property\n");
1016 return;
1017 }
1018
1019 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
1020 RK3328_GRF_MAC_CON1;
1021
1022 if (speed == 10)
1023 regmap_write(bsp_priv->grf, reg,
1024 RK3328_GMAC_RMII_CLK_2_5M |
1025 RK3328_GMAC_SPEED_10M);
1026 else if (speed == 100)
1027 regmap_write(bsp_priv->grf, reg,
1028 RK3328_GMAC_RMII_CLK_25M |
1029 RK3328_GMAC_SPEED_100M);
1030 else
1031 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1032 }
1033
rk3328_integrated_phy_power(struct rk_priv_data * priv,bool up)1034 static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
1035 {
1036 if (up) {
1037 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
1038 RK3328_MACPHY_RMII_MODE);
1039
1040 rk_gmac_integrated_ephy_powerup(priv);
1041 } else {
1042 rk_gmac_integrated_ephy_powerdown(priv);
1043 }
1044 }
1045
1046 static const struct rk_gmac_ops rk3328_ops = {
1047 .set_to_rgmii = rk3328_set_to_rgmii,
1048 .set_to_rmii = rk3328_set_to_rmii,
1049 .set_rgmii_speed = rk3328_set_rgmii_speed,
1050 .set_rmii_speed = rk3328_set_rmii_speed,
1051 .integrated_phy_power = rk3328_integrated_phy_power,
1052 };
1053
1054 #define RK3366_GRF_SOC_CON6 0x0418
1055 #define RK3366_GRF_SOC_CON7 0x041c
1056
1057 /* RK3366_GRF_SOC_CON6 */
1058 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
1059 GRF_CLR_BIT(11))
1060 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
1061 GRF_BIT(11))
1062 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
1063 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
1064 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
1065 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
1066 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
1067 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
1068 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
1069 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
1070 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
1071 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
1072 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
1073
1074 /* RK3366_GRF_SOC_CON7 */
1075 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1076 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1077 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1078 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1079 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1080 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1081
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1082 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
1083 int tx_delay, int rx_delay)
1084 {
1085 struct device *dev = &bsp_priv->pdev->dev;
1086
1087 if (IS_ERR(bsp_priv->grf)) {
1088 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1089 return;
1090 }
1091
1092 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1093 RK3366_GMAC_PHY_INTF_SEL_RGMII |
1094 RK3366_GMAC_RMII_MODE_CLR);
1095 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
1096 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
1097 DELAY_VALUE(RK3366, tx_delay, rx_delay));
1098 }
1099
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)1100 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
1101 {
1102 struct device *dev = &bsp_priv->pdev->dev;
1103
1104 if (IS_ERR(bsp_priv->grf)) {
1105 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1106 return;
1107 }
1108
1109 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1110 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
1111 }
1112
rk3366_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1113 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1114 {
1115 struct device *dev = &bsp_priv->pdev->dev;
1116
1117 if (IS_ERR(bsp_priv->grf)) {
1118 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1119 return;
1120 }
1121
1122 if (speed == 10)
1123 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1124 RK3366_GMAC_CLK_2_5M);
1125 else if (speed == 100)
1126 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1127 RK3366_GMAC_CLK_25M);
1128 else if (speed == 1000)
1129 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1130 RK3366_GMAC_CLK_125M);
1131 else
1132 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
1133 }
1134
rk3366_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1135 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1136 {
1137 struct device *dev = &bsp_priv->pdev->dev;
1138
1139 if (IS_ERR(bsp_priv->grf)) {
1140 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1141 return;
1142 }
1143
1144 if (speed == 10) {
1145 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1146 RK3366_GMAC_RMII_CLK_2_5M |
1147 RK3366_GMAC_SPEED_10M);
1148 } else if (speed == 100) {
1149 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
1150 RK3366_GMAC_RMII_CLK_25M |
1151 RK3366_GMAC_SPEED_100M);
1152 } else {
1153 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1154 }
1155 }
1156
1157 static const struct rk_gmac_ops rk3366_ops = {
1158 .set_to_rgmii = rk3366_set_to_rgmii,
1159 .set_to_rmii = rk3366_set_to_rmii,
1160 .set_rgmii_speed = rk3366_set_rgmii_speed,
1161 .set_rmii_speed = rk3366_set_rmii_speed,
1162 };
1163
1164 #define RK3368_GRF_SOC_CON15 0x043c
1165 #define RK3368_GRF_SOC_CON16 0x0440
1166
1167 /* RK3368_GRF_SOC_CON15 */
1168 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
1169 GRF_CLR_BIT(11))
1170 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
1171 GRF_BIT(11))
1172 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
1173 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
1174 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
1175 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
1176 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
1177 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
1178 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
1179 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
1180 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
1181 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
1182 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
1183
1184 /* RK3368_GRF_SOC_CON16 */
1185 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1186 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1187 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1188 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1189 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1190 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1191
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1192 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
1193 int tx_delay, int rx_delay)
1194 {
1195 struct device *dev = &bsp_priv->pdev->dev;
1196
1197 if (IS_ERR(bsp_priv->grf)) {
1198 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1199 return;
1200 }
1201
1202 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1203 RK3368_GMAC_PHY_INTF_SEL_RGMII |
1204 RK3368_GMAC_RMII_MODE_CLR);
1205 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
1206 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
1207 DELAY_VALUE(RK3368, tx_delay, rx_delay));
1208 }
1209
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)1210 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
1211 {
1212 struct device *dev = &bsp_priv->pdev->dev;
1213
1214 if (IS_ERR(bsp_priv->grf)) {
1215 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1216 return;
1217 }
1218
1219 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1220 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
1221 }
1222
rk3368_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1223 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1224 {
1225 struct device *dev = &bsp_priv->pdev->dev;
1226
1227 if (IS_ERR(bsp_priv->grf)) {
1228 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1229 return;
1230 }
1231
1232 if (speed == 10)
1233 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1234 RK3368_GMAC_CLK_2_5M);
1235 else if (speed == 100)
1236 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1237 RK3368_GMAC_CLK_25M);
1238 else if (speed == 1000)
1239 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1240 RK3368_GMAC_CLK_125M);
1241 else
1242 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
1243 }
1244
rk3368_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1245 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1246 {
1247 struct device *dev = &bsp_priv->pdev->dev;
1248
1249 if (IS_ERR(bsp_priv->grf)) {
1250 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1251 return;
1252 }
1253
1254 if (speed == 10) {
1255 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1256 RK3368_GMAC_RMII_CLK_2_5M |
1257 RK3368_GMAC_SPEED_10M);
1258 } else if (speed == 100) {
1259 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
1260 RK3368_GMAC_RMII_CLK_25M |
1261 RK3368_GMAC_SPEED_100M);
1262 } else {
1263 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1264 }
1265 }
1266
1267 static const struct rk_gmac_ops rk3368_ops = {
1268 .set_to_rgmii = rk3368_set_to_rgmii,
1269 .set_to_rmii = rk3368_set_to_rmii,
1270 .set_rgmii_speed = rk3368_set_rgmii_speed,
1271 .set_rmii_speed = rk3368_set_rmii_speed,
1272 };
1273
1274 #define RK3399_GRF_SOC_CON5 0xc214
1275 #define RK3399_GRF_SOC_CON6 0xc218
1276
1277 /* RK3399_GRF_SOC_CON5 */
1278 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
1279 GRF_CLR_BIT(11))
1280 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
1281 GRF_BIT(11))
1282 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
1283 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
1284 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
1285 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
1286 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
1287 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
1288 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
1289 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
1290 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
1291 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
1292 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
1293
1294 /* RK3399_GRF_SOC_CON6 */
1295 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1296 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1297 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1298 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1299 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1300 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1301
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1302 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
1303 int tx_delay, int rx_delay)
1304 {
1305 struct device *dev = &bsp_priv->pdev->dev;
1306
1307 if (IS_ERR(bsp_priv->grf)) {
1308 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1309 return;
1310 }
1311
1312 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1313 RK3399_GMAC_PHY_INTF_SEL_RGMII |
1314 RK3399_GMAC_RMII_MODE_CLR);
1315 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
1316 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
1317 DELAY_VALUE(RK3399, tx_delay, rx_delay));
1318 }
1319
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)1320 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
1321 {
1322 struct device *dev = &bsp_priv->pdev->dev;
1323
1324 if (IS_ERR(bsp_priv->grf)) {
1325 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1326 return;
1327 }
1328
1329 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1330 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
1331 }
1332
rk3399_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1333 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1334 {
1335 struct device *dev = &bsp_priv->pdev->dev;
1336
1337 if (IS_ERR(bsp_priv->grf)) {
1338 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1339 return;
1340 }
1341
1342 if (speed == 10)
1343 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1344 RK3399_GMAC_CLK_2_5M);
1345 else if (speed == 100)
1346 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1347 RK3399_GMAC_CLK_25M);
1348 else if (speed == 1000)
1349 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1350 RK3399_GMAC_CLK_125M);
1351 else
1352 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
1353 }
1354
rk3399_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1355 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1356 {
1357 struct device *dev = &bsp_priv->pdev->dev;
1358
1359 if (IS_ERR(bsp_priv->grf)) {
1360 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1361 return;
1362 }
1363
1364 if (speed == 10) {
1365 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1366 RK3399_GMAC_RMII_CLK_2_5M |
1367 RK3399_GMAC_SPEED_10M);
1368 } else if (speed == 100) {
1369 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1370 RK3399_GMAC_RMII_CLK_25M |
1371 RK3399_GMAC_SPEED_100M);
1372 } else {
1373 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1374 }
1375 }
1376
1377 static const struct rk_gmac_ops rk3399_ops = {
1378 .set_to_rgmii = rk3399_set_to_rgmii,
1379 .set_to_rmii = rk3399_set_to_rmii,
1380 .set_rgmii_speed = rk3399_set_rgmii_speed,
1381 .set_rmii_speed = rk3399_set_rmii_speed,
1382 };
1383
1384 #define RK3528_VO_GRF_GMAC_CON 0X60018
1385 #define RK3528_VPU_GRF_GMAC_CON5 0X40018
1386 #define RK3528_VPU_GRF_GMAC_CON6 0X4001c
1387
1388 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1389 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1390 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
1391 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
1392
1393 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
1394 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
1395
1396 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
1397 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
1398 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
1399
1400 #define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12)
1401 #define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12)
1402
1403 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
1404 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
1405 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
1406 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
1407
1408 #define RK3528_GMAC1_CLK_RGMII_DIV1 \
1409 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
1410 #define RK3528_GMAC1_CLK_RGMII_DIV5 \
1411 (GRF_BIT(11) | GRF_BIT(10))
1412 #define RK3528_GMAC1_CLK_RGMII_DIV50 \
1413 (GRF_BIT(11) | GRF_CLR_BIT(10))
1414
1415 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
1416 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
1417 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
1418 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
1419
1420 #define RK3528_VO_GRF_MACPHY_CON0 0X6001c
1421 #define RK3528_VO_GRF_MACPHY_CON1 0X60020
1422
rk3528_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1423 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
1424 int tx_delay, int rx_delay)
1425 {
1426 struct device *dev = &bsp_priv->pdev->dev;
1427
1428 if (IS_ERR(bsp_priv->grf)) {
1429 dev_err(dev, "Missing rockchip,grf property\n");
1430 return;
1431 }
1432
1433 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1434 RK3528_GMAC1_PHY_INTF_SEL_RGMII);
1435
1436 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1437 DELAY_ENABLE(RK3528, tx_delay, rx_delay));
1438
1439 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
1440 DELAY_VALUE(RK3528, tx_delay, rx_delay));
1441 }
1442
rk3528_set_to_rmii(struct rk_priv_data * bsp_priv)1443 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
1444 {
1445 struct device *dev = &bsp_priv->pdev->dev;
1446 unsigned int id = bsp_priv->bus_id;
1447
1448 if (IS_ERR(bsp_priv->grf)) {
1449 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1450 return;
1451 }
1452
1453 if (id == 1)
1454 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1455 RK3528_GMAC1_PHY_INTF_SEL_RMII);
1456 else
1457 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
1458 RK3528_GMAC0_PHY_INTF_SEL_RMII |
1459 RK3528_GMAC0_CLK_RMII_DIV2);
1460 }
1461
rk3528_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1462 static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1463 {
1464 struct device *dev = &bsp_priv->pdev->dev;
1465 unsigned int val = 0;
1466
1467 switch (speed) {
1468 case 10:
1469 val = RK3528_GMAC1_CLK_RGMII_DIV50;
1470 break;
1471 case 100:
1472 val = RK3528_GMAC1_CLK_RGMII_DIV5;
1473 break;
1474 case 1000:
1475 val = RK3528_GMAC1_CLK_RGMII_DIV1;
1476 break;
1477 default:
1478 goto err;
1479 }
1480
1481 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1482 return;
1483 err:
1484 dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
1485 }
1486
rk3528_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1487 static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1488 {
1489 struct device *dev = &bsp_priv->pdev->dev;
1490 unsigned int val, offset, id = bsp_priv->bus_id;
1491
1492 switch (speed) {
1493 case 10:
1494 val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
1495 RK3528_GMAC0_CLK_RMII_DIV20;
1496 break;
1497 case 100:
1498 val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
1499 RK3528_GMAC0_CLK_RMII_DIV2;
1500 break;
1501 default:
1502 goto err;
1503 }
1504
1505 offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
1506 regmap_write(bsp_priv->grf, offset, val);
1507
1508 return;
1509 err:
1510 dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
1511 }
1512
rk3528_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1513 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1514 bool input, bool enable)
1515 {
1516 unsigned int value, id = bsp_priv->bus_id;
1517
1518 if (id == 1) {
1519 value = input ? RK3528_GMAC1_CLK_SELET_IO :
1520 RK3528_GMAC1_CLK_SELET_CRU;
1521 value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1522 RK3528_GMAC1_CLK_RMII_GATE;
1523 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
1524 } else {
1525 value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1526 RK3528_GMAC0_CLK_RMII_GATE;
1527 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
1528 }
1529 }
1530
rk3528_integrated_sphy_power(struct rk_priv_data * priv,bool up)1531 static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
1532 {
1533 rk_gmac_integrated_fephy_power(priv, RK3528_VO_GRF_MACPHY_CON0,
1534 RK3528_VO_GRF_MACPHY_CON1, up);
1535 }
1536
1537 static const struct rk_gmac_ops rk3528_ops = {
1538 .set_to_rgmii = rk3528_set_to_rgmii,
1539 .set_to_rmii = rk3528_set_to_rmii,
1540 .set_rgmii_speed = rk3528_set_rgmii_speed,
1541 .set_rmii_speed = rk3528_set_rmii_speed,
1542 .set_clock_selection = rk3528_set_clock_selection,
1543 .integrated_phy_power = rk3528_integrated_sphy_power,
1544 };
1545
1546 /* sys_grf */
1547 #define RK3562_GRF_SYS_SOC_CON0 0X0400
1548 #define RK3562_GRF_SYS_SOC_CON1 0X0404
1549
1550 #define RK3562_GMAC0_CLK_RMII_MODE GRF_BIT(5)
1551 #define RK3562_GMAC0_CLK_RGMII_MODE GRF_CLR_BIT(5)
1552
1553 #define RK3562_GMAC0_CLK_RMII_GATE GRF_BIT(6)
1554 #define RK3562_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(6)
1555
1556 #define RK3562_GMAC0_CLK_RMII_DIV2 GRF_BIT(7)
1557 #define RK3562_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(7)
1558
1559 #define RK3562_GMAC0_CLK_RGMII_DIV1 \
1560 (GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
1561 #define RK3562_GMAC0_CLK_RGMII_DIV5 \
1562 (GRF_BIT(7) | GRF_BIT(8))
1563 #define RK3562_GMAC0_CLK_RGMII_DIV50 \
1564 (GRF_CLR_BIT(7) | GRF_BIT(8))
1565
1566 #define RK3562_GMAC0_CLK_RMII_DIV2 GRF_BIT(7)
1567 #define RK3562_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(7)
1568
1569 #define RK3562_GMAC0_CLK_SELET_CRU GRF_CLR_BIT(9)
1570 #define RK3562_GMAC0_CLK_SELET_IO GRF_BIT(9)
1571
1572 #define RK3562_GMAC1_CLK_RMII_GATE GRF_BIT(12)
1573 #define RK3562_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(12)
1574
1575 #define RK3562_GMAC1_CLK_RMII_DIV2 GRF_BIT(13)
1576 #define RK3562_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(13)
1577
1578 #define RK3562_GMAC1_RMII_SPEED100 GRF_BIT(11)
1579 #define RK3562_GMAC1_RMII_SPEED10 GRF_CLR_BIT(11)
1580
1581 #define RK3562_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(15)
1582 #define RK3562_GMAC1_CLK_SELET_IO GRF_BIT(15)
1583
1584 /* ioc_grf */
1585 #define RK3562_GRF_IOC_GMAC_IOFUNC0_CON0 0X10400
1586 #define RK3562_GRF_IOC_GMAC_IOFUNC0_CON1 0X10404
1587 #define RK3562_GRF_IOC_GMAC_IOFUNC1_CON0 0X00400
1588 #define RK3562_GRF_IOC_GMAC_IOFUNC1_CON1 0X00404
1589
1590 #define RK3562_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1591 #define RK3562_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1592 #define RK3562_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1593 #define RK3562_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1594
1595 #define RK3562_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
1596 #define RK3562_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
1597
1598 #define RK3562_GMAC0_IO_EXTCLK_SELET_CRU GRF_CLR_BIT(2)
1599 #define RK3562_GMAC0_IO_EXTCLK_SELET_IO GRF_BIT(2)
1600
1601 #define RK3562_GMAC1_IO_EXTCLK_SELET_CRU GRF_CLR_BIT(3)
1602 #define RK3562_GMAC1_IO_EXTCLK_SELET_IO GRF_BIT(3)
1603
rk3562_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1604 static void rk3562_set_to_rgmii(struct rk_priv_data *bsp_priv,
1605 int tx_delay, int rx_delay)
1606 {
1607 struct device *dev = &bsp_priv->pdev->dev;
1608
1609 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1610 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1611 return;
1612 }
1613
1614 if (bsp_priv->bus_id > 0)
1615 return;
1616
1617 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1618 RK3562_GMAC0_CLK_RGMII_MODE);
1619
1620 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1,
1621 DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1622 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON0,
1623 DELAY_VALUE(RK3562, tx_delay, rx_delay));
1624
1625 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1,
1626 DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1627 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON0,
1628 DELAY_VALUE(RK3562, tx_delay, rx_delay));
1629 }
1630
rk3562_set_to_rmii(struct rk_priv_data * bsp_priv)1631 static void rk3562_set_to_rmii(struct rk_priv_data *bsp_priv)
1632 {
1633 struct device *dev = &bsp_priv->pdev->dev;
1634
1635 if (IS_ERR(bsp_priv->grf)) {
1636 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1637 return;
1638 }
1639
1640 if (!bsp_priv->bus_id)
1641 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1642 RK3562_GMAC0_CLK_RMII_MODE);
1643 }
1644
rk3562_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1645 static void rk3562_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1646 {
1647 struct device *dev = &bsp_priv->pdev->dev;
1648 unsigned int val = 0, offset, id = bsp_priv->bus_id;
1649
1650 switch (speed) {
1651 case 10:
1652 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1653 if (id > 0) {
1654 val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 20);
1655 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1656 RK3562_GMAC1_RMII_SPEED10);
1657 } else {
1658 val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 20);
1659 }
1660 } else {
1661 val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 50);
1662 }
1663 break;
1664 case 100:
1665 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1666 if (id > 0) {
1667 val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 2);
1668 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1669 RK3562_GMAC1_RMII_SPEED100);
1670 } else {
1671 val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 2);
1672 }
1673 } else {
1674 val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 5);
1675 }
1676 break;
1677 case 1000:
1678 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1679 val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 1);
1680 else
1681 goto err;
1682 break;
1683 default:
1684 goto err;
1685 }
1686
1687 offset = (bsp_priv->bus_id > 0) ? RK3562_GRF_SYS_SOC_CON1 :
1688 RK3562_GRF_SYS_SOC_CON0;
1689 regmap_write(bsp_priv->grf, offset, val);
1690
1691 return;
1692 err:
1693 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1694 }
1695
rk3562_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1696 static void rk3562_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1697 bool enable)
1698 {
1699 struct device *dev = &bsp_priv->pdev->dev;
1700 unsigned int value;
1701
1702 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1703 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1704 return;
1705 }
1706
1707 if (!bsp_priv->bus_id) {
1708 value = input ? RK3562_GMAC0_CLK_SELET_IO :
1709 RK3562_GMAC0_CLK_SELET_CRU;
1710 value |= enable ? RK3562_GMAC0_CLK_RMII_NOGATE :
1711 RK3562_GMAC0_CLK_RMII_GATE;
1712 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, value);
1713
1714 value = input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1715 RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1716 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, value);
1717 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1718 } else {
1719 value = input ? RK3562_GMAC1_CLK_SELET_IO :
1720 RK3562_GMAC1_CLK_SELET_CRU;
1721 value |= enable ? RK3562_GMAC1_CLK_RMII_NOGATE :
1722 RK3562_GMAC1_CLK_RMII_GATE;
1723 regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON1, value);
1724
1725 value = input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1726 RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1727 regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1728 }
1729 }
1730
1731 static const struct rk_gmac_ops rk3562_ops = {
1732 .set_to_rgmii = rk3562_set_to_rgmii,
1733 .set_to_rmii = rk3562_set_to_rmii,
1734 .set_rgmii_speed = rk3562_set_gmac_speed,
1735 .set_rmii_speed = rk3562_set_gmac_speed,
1736 .set_clock_selection = rk3562_set_clock_selection,
1737 };
1738
1739 #define RK3568_GRF_GMAC0_CON0 0X0380
1740 #define RK3568_GRF_GMAC0_CON1 0X0384
1741 #define RK3568_GRF_GMAC1_CON0 0X0388
1742 #define RK3568_GRF_GMAC1_CON1 0X038c
1743
1744 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1745 #define RK3568_GMAC_GMII_MODE GRF_BIT(7)
1746 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \
1747 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1748 #define RK3568_GMAC_PHY_INTF_SEL_RMII \
1749 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1750 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
1751 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1752 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1753 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1754 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1755 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1756
1757 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1758 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1759 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1760
1761 #define RK3568_PIPE_GRF_XPCS_CON0 0X0040
1762
1763 #define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL GRF_BIT(0)
1764 #define RK3568_PIPE_GRF_XPCS_SGMII_MAC_SEL GRF_BIT(1)
1765 #define RK3568_PIPE_GRF_XPCS_PHY_READY GRF_BIT(2)
1766
rk3568_set_to_sgmii(struct rk_priv_data * bsp_priv)1767 static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv)
1768 {
1769 struct device *dev = &bsp_priv->pdev->dev;
1770 u32 offset_con1;
1771
1772 if (IS_ERR(bsp_priv->grf)) {
1773 dev_err(dev, "%s: Missing rockchip,grfs property\n", __func__);
1774 return;
1775 }
1776
1777 offset_con1 = bsp_priv->bus_id == 1 ? RK3568_GRF_GMAC1_CON1 :
1778 RK3568_GRF_GMAC0_CON1;
1779 regmap_write(bsp_priv->grf, offset_con1, RK3568_GMAC_GMII_MODE);
1780
1781 xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_SGMII);
1782 }
1783
rk3568_set_to_qsgmii(struct rk_priv_data * bsp_priv)1784 static void rk3568_set_to_qsgmii(struct rk_priv_data *bsp_priv)
1785 {
1786 struct device *dev = &bsp_priv->pdev->dev;
1787 u32 offset_con1;
1788
1789 if (IS_ERR(bsp_priv->grf)) {
1790 dev_err(dev, "%s: Missing rockchip,grfs property\n", __func__);
1791 return;
1792 }
1793
1794 offset_con1 = bsp_priv->bus_id == 1 ? RK3568_GRF_GMAC1_CON1 :
1795 RK3568_GRF_GMAC0_CON1;
1796 regmap_write(bsp_priv->grf, offset_con1, RK3568_GMAC_GMII_MODE);
1797
1798 xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_QSGMII);
1799 }
1800
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1801 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1802 int tx_delay, int rx_delay)
1803 {
1804 struct device *dev = &bsp_priv->pdev->dev;
1805 u32 offset_con0, offset_con1;
1806
1807 if (IS_ERR(bsp_priv->grf)) {
1808 dev_err(dev, "Missing rockchip,grf property\n");
1809 return;
1810 }
1811
1812 offset_con0 = (bsp_priv->bus_id == 1) ? RK3568_GRF_GMAC1_CON0 :
1813 RK3568_GRF_GMAC0_CON0;
1814 offset_con1 = (bsp_priv->bus_id == 1) ? RK3568_GRF_GMAC1_CON1 :
1815 RK3568_GRF_GMAC0_CON1;
1816
1817 regmap_write(bsp_priv->grf, offset_con1,
1818 RK3568_GMAC_PHY_INTF_SEL_RGMII |
1819 DELAY_ENABLE(RK3568, tx_delay, rx_delay));
1820
1821 regmap_write(bsp_priv->grf, offset_con0,
1822 DELAY_VALUE(RK3568, tx_delay, rx_delay));
1823 }
1824
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1825 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1826 {
1827 struct device *dev = &bsp_priv->pdev->dev;
1828 u32 offset_con1;
1829
1830 if (IS_ERR(bsp_priv->grf)) {
1831 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1832 return;
1833 }
1834
1835 offset_con1 = (bsp_priv->bus_id == 1) ? RK3568_GRF_GMAC1_CON1 :
1836 RK3568_GRF_GMAC0_CON1;
1837
1838 regmap_write(bsp_priv->grf, offset_con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1839 }
1840
rk3568_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1841 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1842 {
1843 struct device *dev = &bsp_priv->pdev->dev;
1844 unsigned long rate;
1845 int ret;
1846
1847 switch (speed) {
1848 case 10:
1849 rate = 2500000;
1850 break;
1851 case 100:
1852 rate = 25000000;
1853 break;
1854 case 1000:
1855 rate = 125000000;
1856 break;
1857 default:
1858 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1859 return;
1860 }
1861
1862 ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1863 if (ret)
1864 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1865 __func__, rate, ret);
1866 }
1867
1868 static const struct rk_gmac_ops rk3568_ops = {
1869 .set_to_rgmii = rk3568_set_to_rgmii,
1870 .set_to_rmii = rk3568_set_to_rmii,
1871 .set_to_sgmii = rk3568_set_to_sgmii,
1872 .set_to_qsgmii = rk3568_set_to_qsgmii,
1873 .set_rgmii_speed = rk3568_set_gmac_speed,
1874 .set_rmii_speed = rk3568_set_gmac_speed,
1875 };
1876
1877 /* sys_grf */
1878 #define RK3588_GRF_GMAC_CON7 0X031c
1879 #define RK3588_GRF_GMAC_CON8 0X0320
1880 #define RK3588_GRF_GMAC_CON9 0X0324
1881
1882 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
1883 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
1884 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
1885 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
1886
1887 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
1888 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
1889
1890 /* php_grf */
1891 #define RK3588_GRF_GMAC_CON0 0X0008
1892 #define RK3588_GRF_CLK_CON1 0X0070
1893
1894 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
1895 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1896 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
1897 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1898
1899 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
1900 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
1901
1902 #define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
1903 #define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
1904
1905 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
1906 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
1907
1908 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \
1909 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1910 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \
1911 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1912 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \
1913 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1914
1915 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
1916 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
1917
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1918 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1919 int tx_delay, int rx_delay)
1920 {
1921 struct device *dev = &bsp_priv->pdev->dev;
1922 u32 offset_con, id = bsp_priv->bus_id;
1923
1924 if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1925 dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1926 return;
1927 }
1928
1929 offset_con = bsp_priv->bus_id == 1 ? RK3588_GRF_GMAC_CON9 :
1930 RK3588_GRF_GMAC_CON8;
1931
1932 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1933 RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1934
1935 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1936 RK3588_GMAC_CLK_RGMII_MODE(id));
1937
1938 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1939 DELAY_ENABLE_BY_ID(RK3588, tx_delay, rx_delay, id));
1940
1941 regmap_write(bsp_priv->grf, offset_con,
1942 DELAY_VALUE(RK3588, tx_delay, rx_delay));
1943 }
1944
rk3588_set_to_rmii(struct rk_priv_data * bsp_priv)1945 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1946 {
1947 struct device *dev = &bsp_priv->pdev->dev;
1948
1949 if (IS_ERR(bsp_priv->php_grf)) {
1950 dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1951 return;
1952 }
1953
1954 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1955 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->bus_id));
1956
1957 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1958 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->bus_id));
1959 }
1960
rk3588_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1961 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1962 {
1963 struct device *dev = &bsp_priv->pdev->dev;
1964 unsigned int val = 0, id = bsp_priv->bus_id;
1965
1966 switch (speed) {
1967 case 10:
1968 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1969 val = RK3588_GMA_CLK_RMII_DIV20(id);
1970 else
1971 val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1972 break;
1973 case 100:
1974 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1975 val = RK3588_GMA_CLK_RMII_DIV2(id);
1976 else
1977 val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1978 break;
1979 case 1000:
1980 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1981 val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1982 else
1983 goto err;
1984 break;
1985 default:
1986 goto err;
1987 }
1988
1989 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1990
1991 return;
1992 err:
1993 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1994 }
1995
rk3588_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1996 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1997 bool enable)
1998 {
1999 unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->bus_id) :
2000 RK3588_GMAC_CLK_SELET_CRU(bsp_priv->bus_id);
2001
2002 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->bus_id) :
2003 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->bus_id);
2004
2005 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
2006 }
2007
2008 static const struct rk_gmac_ops rk3588_ops = {
2009 .set_to_rgmii = rk3588_set_to_rgmii,
2010 .set_to_rmii = rk3588_set_to_rmii,
2011 .set_rgmii_speed = rk3588_set_gmac_speed,
2012 .set_rmii_speed = rk3588_set_gmac_speed,
2013 .set_clock_selection = rk3588_set_clock_selection,
2014 };
2015
2016 #define RV1106_VOGRF_GMAC_CLK_CON 0X60004
2017
2018 #define RV1106_VOGRF_MACPHY_RMII_MODE GRF_BIT(0)
2019 #define RV1106_VOGRF_GMAC_CLK_RMII_DIV2 GRF_BIT(2)
2020 #define RV1106_VOGRF_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(2)
2021
2022 #define RV1106_VOGRF_MACPHY_CON0 0X60028
2023 #define RV1106_VOGRF_MACPHY_CON1 0X6002C
2024
rv1106_set_to_rmii(struct rk_priv_data * bsp_priv)2025 static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
2026 {
2027 struct device *dev = &bsp_priv->pdev->dev;
2028
2029 if (IS_ERR(bsp_priv->grf)) {
2030 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2031 return;
2032 }
2033
2034 regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
2035 RV1106_VOGRF_MACPHY_RMII_MODE |
2036 RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
2037 }
2038
rv1106_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)2039 static void rv1106_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2040 {
2041 struct device *dev = &bsp_priv->pdev->dev;
2042 unsigned int val = 0;
2043
2044 if (IS_ERR(bsp_priv->grf)) {
2045 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2046 return;
2047 }
2048
2049 if (speed == 10) {
2050 val = RV1106_VOGRF_GMAC_CLK_RMII_DIV20;
2051 } else if (speed == 100) {
2052 val = RV1106_VOGRF_GMAC_CLK_RMII_DIV2;
2053 } else {
2054 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
2055 return;
2056 }
2057
2058 regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val);
2059 }
2060
rv1106_integrated_sphy_power(struct rk_priv_data * priv,bool up)2061 static void rv1106_integrated_sphy_power(struct rk_priv_data *priv, bool up)
2062 {
2063 rk_gmac_integrated_fephy_power(priv, RV1106_VOGRF_MACPHY_CON0,
2064 RV1106_VOGRF_MACPHY_CON1, up);
2065 }
2066
2067 static const struct rk_gmac_ops rv1106_ops = {
2068 .set_to_rmii = rv1106_set_to_rmii,
2069 .set_rmii_speed = rv1106_set_rmii_speed,
2070 .integrated_phy_power = rv1106_integrated_sphy_power,
2071 };
2072
2073 #define RV1108_GRF_GMAC_CON0 0X0900
2074
2075 /* RV1108_GRF_GMAC_CON0 */
2076 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
2077 GRF_BIT(6))
2078 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
2079 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
2080 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
2081 #define RV1108_GMAC_SPEED_100M GRF_BIT(2)
2082 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
2083 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
2084
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)2085 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
2086 {
2087 struct device *dev = &bsp_priv->pdev->dev;
2088
2089 if (IS_ERR(bsp_priv->grf)) {
2090 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2091 return;
2092 }
2093
2094 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
2095 RV1108_GMAC_PHY_INTF_SEL_RMII);
2096 }
2097
rv1108_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)2098 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2099 {
2100 struct device *dev = &bsp_priv->pdev->dev;
2101
2102 if (IS_ERR(bsp_priv->grf)) {
2103 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2104 return;
2105 }
2106
2107 if (speed == 10) {
2108 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
2109 RV1108_GMAC_RMII_CLK_2_5M |
2110 RV1108_GMAC_SPEED_10M);
2111 } else if (speed == 100) {
2112 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
2113 RV1108_GMAC_RMII_CLK_25M |
2114 RV1108_GMAC_SPEED_100M);
2115 } else {
2116 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
2117 }
2118 }
2119
2120 static const struct rk_gmac_ops rv1108_ops = {
2121 .set_to_rmii = rv1108_set_to_rmii,
2122 .set_rmii_speed = rv1108_set_rmii_speed,
2123 };
2124
2125 #define RV1126_GRF_GMAC_CON0 0X0070
2126 #define RV1126_GRF_GMAC_CON1 0X0074
2127 #define RV1126_GRF_GMAC_CON2 0X0078
2128
2129 /* RV1126_GRF_GMAC_CON0 */
2130 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \
2131 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
2132 #define RV1126_GMAC_PHY_INTF_SEL_RMII \
2133 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
2134 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
2135 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
2136 #define RV1126_M0_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
2137 #define RV1126_M0_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
2138 #define RV1126_M0_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
2139 #define RV1126_M0_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
2140 #define RV1126_M1_GMAC_RXCLK_DLY_ENABLE GRF_BIT(3)
2141 #define RV1126_M1_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
2142 #define RV1126_M1_GMAC_TXCLK_DLY_ENABLE GRF_BIT(2)
2143 #define RV1126_M1_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
2144
2145 /* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
2146 #define RV1126_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
2147 #define RV1126_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
2148
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)2149 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
2150 int tx_delay, int rx_delay)
2151 {
2152 struct device *dev = &bsp_priv->pdev->dev;
2153
2154 if (IS_ERR(bsp_priv->grf)) {
2155 dev_err(dev, "Missing rockchip,grf property\n");
2156 return;
2157 }
2158
2159 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
2160 RV1126_GMAC_PHY_INTF_SEL_RGMII |
2161 DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) |
2162 DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
2163
2164 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
2165 DELAY_VALUE(RV1126, tx_delay, rx_delay));
2166
2167 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
2168 DELAY_VALUE(RV1126, tx_delay, rx_delay));
2169 }
2170
rv1126_set_to_rmii(struct rk_priv_data * bsp_priv)2171 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
2172 {
2173 struct device *dev = &bsp_priv->pdev->dev;
2174
2175 if (IS_ERR(bsp_priv->grf)) {
2176 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2177 return;
2178 }
2179
2180 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
2181 RV1126_GMAC_PHY_INTF_SEL_RMII);
2182 }
2183
rv1126_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)2184 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
2185 {
2186 struct device *dev = &bsp_priv->pdev->dev;
2187 unsigned long rate;
2188 int ret;
2189
2190 switch (speed) {
2191 case 10:
2192 rate = 2500000;
2193 break;
2194 case 100:
2195 rate = 25000000;
2196 break;
2197 case 1000:
2198 rate = 125000000;
2199 break;
2200 default:
2201 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
2202 return;
2203 }
2204
2205 ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
2206 if (ret)
2207 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
2208 __func__, rate, ret);
2209 }
2210
rv1126_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)2211 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2212 {
2213 struct device *dev = &bsp_priv->pdev->dev;
2214 unsigned long rate;
2215 int ret;
2216
2217 switch (speed) {
2218 case 10:
2219 rate = 2500000;
2220 break;
2221 case 100:
2222 rate = 25000000;
2223 break;
2224 default:
2225 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
2226 return;
2227 }
2228
2229 ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
2230 if (ret)
2231 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
2232 __func__, rate, ret);
2233 }
2234
2235 static const struct rk_gmac_ops rv1126_ops = {
2236 .set_to_rgmii = rv1126_set_to_rgmii,
2237 .set_to_rmii = rv1126_set_to_rmii,
2238 .set_rgmii_speed = rv1126_set_rgmii_speed,
2239 .set_rmii_speed = rv1126_set_rmii_speed,
2240 };
2241
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)2242 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
2243 {
2244 struct rk_priv_data *bsp_priv = plat->bsp_priv;
2245 struct device *dev = &bsp_priv->pdev->dev;
2246 int ret;
2247
2248 bsp_priv->clk_enabled = false;
2249
2250 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
2251 if (IS_ERR(bsp_priv->mac_clk_rx))
2252 dev_err(dev, "cannot get clock %s\n",
2253 "mac_clk_rx");
2254
2255 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
2256 if (IS_ERR(bsp_priv->mac_clk_tx))
2257 dev_err(dev, "cannot get clock %s\n",
2258 "mac_clk_tx");
2259
2260 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
2261 if (IS_ERR(bsp_priv->aclk_mac))
2262 dev_err(dev, "cannot get clock %s\n",
2263 "aclk_mac");
2264
2265 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
2266 if (IS_ERR(bsp_priv->pclk_mac))
2267 dev_err(dev, "cannot get clock %s\n",
2268 "pclk_mac");
2269
2270 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
2271 if (IS_ERR(bsp_priv->clk_mac))
2272 dev_err(dev, "cannot get clock %s\n",
2273 "stmmaceth");
2274
2275 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
2276 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
2277 if (IS_ERR(bsp_priv->clk_mac_ref))
2278 dev_err(dev, "cannot get clock %s\n",
2279 "clk_mac_ref");
2280
2281 if (!bsp_priv->clock_input) {
2282 bsp_priv->clk_mac_refout =
2283 devm_clk_get(dev, "clk_mac_refout");
2284 if (IS_ERR(bsp_priv->clk_mac_refout))
2285 dev_err(dev, "cannot get clock %s\n",
2286 "clk_mac_refout");
2287 }
2288 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_SGMII ||
2289 bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
2290 bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
2291 if (IS_ERR(bsp_priv->pclk_xpcs))
2292 dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
2293 bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
2294 if (IS_ERR(bsp_priv->clk_xpcs_eee))
2295 dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
2296 }
2297
2298 bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
2299 if (IS_ERR(bsp_priv->clk_mac_speed))
2300 dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
2301
2302 if (bsp_priv->clock_input) {
2303 dev_info(dev, "clock input from PHY\n");
2304 } else {
2305 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
2306 clk_set_rate(bsp_priv->clk_mac, 50000000);
2307 }
2308
2309 if (plat->phy_node) {
2310 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
2311 /* If it is not integrated_phy, clk_phy is optional */
2312 if (bsp_priv->integrated_phy) {
2313 if (IS_ERR(bsp_priv->clk_phy)) {
2314 ret = PTR_ERR(bsp_priv->clk_phy);
2315 dev_err(dev, "Cannot get PHY clock: %d\n", ret);
2316 return -EINVAL;
2317 }
2318 clk_set_rate(bsp_priv->clk_phy, 50000000);
2319 }
2320 }
2321
2322 return 0;
2323 }
2324
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)2325 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
2326 {
2327 int phy_iface = bsp_priv->phy_iface;
2328
2329 if (enable) {
2330 if (!bsp_priv->clk_enabled) {
2331 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
2332 if (!IS_ERR(bsp_priv->mac_clk_rx))
2333 clk_prepare_enable(
2334 bsp_priv->mac_clk_rx);
2335
2336 if (!IS_ERR(bsp_priv->clk_mac_ref))
2337 clk_prepare_enable(
2338 bsp_priv->clk_mac_ref);
2339
2340 if (!IS_ERR(bsp_priv->clk_mac_refout))
2341 clk_prepare_enable(
2342 bsp_priv->clk_mac_refout);
2343 }
2344
2345 if (!IS_ERR(bsp_priv->clk_phy))
2346 clk_prepare_enable(bsp_priv->clk_phy);
2347
2348 if (!IS_ERR(bsp_priv->aclk_mac))
2349 clk_prepare_enable(bsp_priv->aclk_mac);
2350
2351 if (!IS_ERR(bsp_priv->pclk_mac))
2352 clk_prepare_enable(bsp_priv->pclk_mac);
2353
2354 if (!IS_ERR(bsp_priv->mac_clk_tx))
2355 clk_prepare_enable(bsp_priv->mac_clk_tx);
2356
2357 if (!IS_ERR(bsp_priv->clk_mac_speed))
2358 clk_prepare_enable(bsp_priv->clk_mac_speed);
2359
2360 if (!IS_ERR(bsp_priv->pclk_xpcs))
2361 clk_prepare_enable(bsp_priv->pclk_xpcs);
2362
2363 if (!IS_ERR(bsp_priv->clk_xpcs_eee))
2364 clk_prepare_enable(bsp_priv->clk_xpcs_eee);
2365
2366 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
2367 bsp_priv->ops->set_clock_selection(bsp_priv,
2368 bsp_priv->clock_input, true);
2369
2370 /**
2371 * if (!IS_ERR(bsp_priv->clk_mac))
2372 * clk_prepare_enable(bsp_priv->clk_mac);
2373 */
2374 usleep_range(100, 200);
2375 bsp_priv->clk_enabled = true;
2376 }
2377 } else {
2378 if (bsp_priv->clk_enabled) {
2379 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
2380 bsp_priv->ops->set_clock_selection(bsp_priv,
2381 bsp_priv->clock_input, false);
2382
2383 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
2384 clk_disable_unprepare(bsp_priv->mac_clk_rx);
2385
2386 clk_disable_unprepare(bsp_priv->clk_mac_ref);
2387
2388 clk_disable_unprepare(bsp_priv->clk_mac_refout);
2389 }
2390
2391 clk_disable_unprepare(bsp_priv->clk_phy);
2392
2393 clk_disable_unprepare(bsp_priv->aclk_mac);
2394
2395 clk_disable_unprepare(bsp_priv->pclk_mac);
2396
2397 clk_disable_unprepare(bsp_priv->mac_clk_tx);
2398
2399 clk_disable_unprepare(bsp_priv->clk_mac_speed);
2400
2401 clk_disable_unprepare(bsp_priv->pclk_xpcs);
2402
2403 clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
2404
2405 /**
2406 * if (!IS_ERR(bsp_priv->clk_mac))
2407 * clk_disable_unprepare(bsp_priv->clk_mac);
2408 */
2409 bsp_priv->clk_enabled = false;
2410 }
2411 }
2412
2413 return 0;
2414 }
2415
rk_gmac_phy_power_on(struct rk_priv_data * bsp_priv,bool enable)2416 static int rk_gmac_phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
2417 {
2418 struct regulator *ldo = bsp_priv->regulator;
2419 int ret;
2420 struct device *dev = &bsp_priv->pdev->dev;
2421
2422 if (!ldo)
2423 return 0;
2424
2425 if (enable) {
2426 ret = regulator_enable(ldo);
2427 if (ret)
2428 dev_err(dev, "fail to enable phy-supply\n");
2429 } else {
2430 ret = regulator_disable(ldo);
2431 if (ret)
2432 dev_err(dev, "fail to disable phy-supply\n");
2433 }
2434
2435 return 0;
2436 }
2437
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)2438 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
2439 struct plat_stmmacenet_data *plat,
2440 const struct rk_gmac_ops *ops)
2441 {
2442 struct rk_priv_data *bsp_priv;
2443 struct device *dev = &pdev->dev;
2444 int ret;
2445 const char *strings = NULL;
2446 int value;
2447
2448 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
2449 if (!bsp_priv)
2450 return ERR_PTR(-ENOMEM);
2451
2452 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
2453 bsp_priv->ops = ops;
2454 bsp_priv->bus_id = plat->bus_id;
2455
2456 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
2457 if (IS_ERR(bsp_priv->regulator)) {
2458 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
2459 dev_err(dev, "phy regulator is not available yet, deferred probing\n");
2460 return ERR_PTR(-EPROBE_DEFER);
2461 }
2462 dev_err(dev, "no regulator found\n");
2463 bsp_priv->regulator = NULL;
2464 }
2465
2466 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
2467 if (ret) {
2468 dev_err(dev, "Can not read property: clock_in_out.\n");
2469 bsp_priv->clock_input = true;
2470 } else {
2471 dev_info(dev, "clock input or output? (%s).\n",
2472 strings);
2473 if (!strcmp(strings, "input"))
2474 bsp_priv->clock_input = true;
2475 else
2476 bsp_priv->clock_input = false;
2477 }
2478
2479 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
2480 if (ret) {
2481 bsp_priv->tx_delay = -1;
2482 dev_err(dev, "Can not read property: tx_delay.");
2483 dev_err(dev, "set tx_delay to 0x%x\n",
2484 bsp_priv->tx_delay);
2485 } else {
2486 dev_info(dev, "TX delay(0x%x).\n", value);
2487 bsp_priv->tx_delay = value;
2488 }
2489
2490 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
2491 if (ret) {
2492 bsp_priv->rx_delay = -1;
2493 dev_err(dev, "Can not read property: rx_delay.");
2494 dev_err(dev, "set rx_delay to 0x%x\n",
2495 bsp_priv->rx_delay);
2496 } else {
2497 dev_info(dev, "RX delay(0x%x).\n", value);
2498 bsp_priv->rx_delay = value;
2499 }
2500
2501 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2502 "rockchip,grf");
2503 bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2504 "rockchip,php_grf");
2505 bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
2506 "rockchip,xpcs");
2507 if (!IS_ERR(bsp_priv->xpcs)) {
2508 struct phy *comphy;
2509
2510 comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
2511 if (IS_ERR(comphy))
2512 dev_err(dev, "devm_of_phy_get error\n");
2513 ret = phy_init(comphy);
2514 if (ret)
2515 dev_err(dev, "phy_init error\n");
2516 }
2517
2518 if (plat->phy_node) {
2519 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
2520 "phy-is-integrated");
2521 if (bsp_priv->integrated_phy) {
2522 unsigned char *efuse_buf;
2523 struct nvmem_cell *cell;
2524 size_t len;
2525
2526 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
2527 if (IS_ERR(bsp_priv->phy_reset)) {
2528 dev_err(&pdev->dev, "No PHY reset control found.\n");
2529 bsp_priv->phy_reset = NULL;
2530 }
2531
2532 if (of_property_read_u32(plat->phy_node, "bgs,increment",
2533 &bsp_priv->bgs_increment)) {
2534 bsp_priv->bgs_increment = 0;
2535 } else {
2536 if (bsp_priv->bgs_increment > RK_FEPHY_BGS_MAX) {
2537 dev_err(dev, "%s: error bgs increment: %d\n",
2538 __func__, bsp_priv->bgs_increment);
2539 bsp_priv->bgs_increment = RK_FEPHY_BGS_MAX;
2540 }
2541 }
2542
2543 /* Read bgs from OTP if it exists */
2544 cell = nvmem_cell_get(dev, "bgs");
2545 if (IS_ERR(cell)) {
2546 if (PTR_ERR(cell) != -EPROBE_DEFER)
2547 dev_info(dev, "failed to get bgs cell: %ld, use default\n",
2548 PTR_ERR(cell));
2549 else
2550 return ERR_CAST(cell);
2551 } else {
2552 efuse_buf = nvmem_cell_read(cell, &len);
2553 nvmem_cell_put(cell);
2554 if (!IS_ERR(efuse_buf)) {
2555 if (len == 1)
2556 bsp_priv->otp_data = efuse_buf[0];
2557 kfree(efuse_buf);
2558 } else {
2559 dev_err(dev, "failed to get efuse buf, use default\n");
2560 }
2561 }
2562 }
2563 }
2564 dev_info(dev, "integrated PHY? (%s).\n",
2565 bsp_priv->integrated_phy ? "yes" : "no");
2566
2567 bsp_priv->pdev = pdev;
2568
2569 return bsp_priv;
2570 }
2571
rk_gmac_powerup(struct rk_priv_data * bsp_priv)2572 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
2573 {
2574 int ret;
2575 struct device *dev = &bsp_priv->pdev->dev;
2576
2577 ret = gmac_clk_enable(bsp_priv, true);
2578 if (ret)
2579 return ret;
2580
2581 /*rmii or rgmii*/
2582 switch (bsp_priv->phy_iface) {
2583 case PHY_INTERFACE_MODE_RGMII:
2584 dev_info(dev, "init for RGMII\n");
2585 if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
2586 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
2587 bsp_priv->rx_delay);
2588 break;
2589 case PHY_INTERFACE_MODE_RGMII_ID:
2590 dev_info(dev, "init for RGMII_ID\n");
2591 if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
2592 bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
2593 break;
2594 case PHY_INTERFACE_MODE_RGMII_RXID:
2595 dev_info(dev, "init for RGMII_RXID\n");
2596 if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
2597 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
2598 break;
2599 case PHY_INTERFACE_MODE_RGMII_TXID:
2600 dev_info(dev, "init for RGMII_TXID\n");
2601 if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
2602 bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
2603 break;
2604 case PHY_INTERFACE_MODE_RMII:
2605 dev_info(dev, "init for RMII\n");
2606 if (bsp_priv->ops && bsp_priv->ops->set_to_rmii)
2607 bsp_priv->ops->set_to_rmii(bsp_priv);
2608 break;
2609 case PHY_INTERFACE_MODE_SGMII:
2610 dev_info(dev, "init for SGMII\n");
2611 if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
2612 bsp_priv->ops->set_to_sgmii(bsp_priv);
2613 break;
2614 case PHY_INTERFACE_MODE_QSGMII:
2615 dev_info(dev, "init for QSGMII\n");
2616 if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
2617 bsp_priv->ops->set_to_qsgmii(bsp_priv);
2618 break;
2619 default:
2620 dev_err(dev, "NO interface defined!\n");
2621 }
2622
2623 ret = rk_gmac_phy_power_on(bsp_priv, true);
2624 if (ret) {
2625 gmac_clk_enable(bsp_priv, false);
2626 return ret;
2627 }
2628
2629 pm_runtime_get_sync(dev);
2630
2631 return 0;
2632 }
2633
rk_gmac_powerdown(struct rk_priv_data * gmac)2634 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
2635 {
2636 pm_runtime_put_sync(&gmac->pdev->dev);
2637
2638 rk_gmac_phy_power_on(gmac, false);
2639 gmac_clk_enable(gmac, false);
2640 }
2641
rk_fix_speed(void * priv,unsigned int speed)2642 static void rk_fix_speed(void *priv, unsigned int speed)
2643 {
2644 struct rk_priv_data *bsp_priv = priv;
2645 struct device *dev = &bsp_priv->pdev->dev;
2646
2647 switch (bsp_priv->phy_iface) {
2648 case PHY_INTERFACE_MODE_RGMII:
2649 case PHY_INTERFACE_MODE_RGMII_ID:
2650 case PHY_INTERFACE_MODE_RGMII_RXID:
2651 case PHY_INTERFACE_MODE_RGMII_TXID:
2652 if (bsp_priv->ops && bsp_priv->ops->set_rgmii_speed)
2653 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
2654 break;
2655 case PHY_INTERFACE_MODE_RMII:
2656 if (bsp_priv->ops && bsp_priv->ops->set_rmii_speed)
2657 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
2658 break;
2659 case PHY_INTERFACE_MODE_SGMII:
2660 case PHY_INTERFACE_MODE_QSGMII:
2661 break;
2662 default:
2663 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
2664 }
2665 }
2666
rk_integrated_phy_power(void * priv,bool up)2667 static int rk_integrated_phy_power(void *priv, bool up)
2668 {
2669 struct rk_priv_data *bsp_priv = priv;
2670
2671 if (!bsp_priv->integrated_phy || !bsp_priv->ops ||
2672 !bsp_priv->ops->integrated_phy_power)
2673 return 0;
2674
2675 bsp_priv->ops->integrated_phy_power(bsp_priv, up);
2676
2677 return 0;
2678 }
2679
dwmac_rk_set_rgmii_delayline(struct stmmac_priv * priv,int tx_delay,int rx_delay)2680 void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
2681 int tx_delay, int rx_delay)
2682 {
2683 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv;
2684
2685 if (bsp_priv->ops->set_to_rgmii) {
2686 bsp_priv->ops->set_to_rgmii(bsp_priv, tx_delay, rx_delay);
2687 bsp_priv->tx_delay = tx_delay;
2688 bsp_priv->rx_delay = rx_delay;
2689 }
2690 }
2691 EXPORT_SYMBOL(dwmac_rk_set_rgmii_delayline);
2692
dwmac_rk_get_rgmii_delayline(struct stmmac_priv * priv,int * tx_delay,int * rx_delay)2693 void dwmac_rk_get_rgmii_delayline(struct stmmac_priv *priv,
2694 int *tx_delay, int *rx_delay)
2695 {
2696 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv;
2697
2698 if (!bsp_priv->ops->set_to_rgmii)
2699 return;
2700
2701 *tx_delay = bsp_priv->tx_delay;
2702 *rx_delay = bsp_priv->rx_delay;
2703 }
2704 EXPORT_SYMBOL(dwmac_rk_get_rgmii_delayline);
2705
dwmac_rk_get_phy_interface(struct stmmac_priv * priv)2706 int dwmac_rk_get_phy_interface(struct stmmac_priv *priv)
2707 {
2708 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv;
2709
2710 return bsp_priv->phy_iface;
2711 }
2712 EXPORT_SYMBOL(dwmac_rk_get_phy_interface);
2713
rk_get_eth_addr(void * priv,unsigned char * addr)2714 static void rk_get_eth_addr(void *priv, unsigned char *addr)
2715 {
2716 struct rk_priv_data *bsp_priv = priv;
2717 struct device *dev = &bsp_priv->pdev->dev;
2718 unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2719 int ret, id = bsp_priv->bus_id;
2720
2721 if (is_valid_ether_addr(addr))
2722 goto out;
2723
2724 if (id < 0 || id >= MAX_ETH) {
2725 dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
2726 return;
2727 }
2728
2729 ret = rk_vendor_read(LAN_MAC_ID, ethaddr, ETH_ALEN * MAX_ETH);
2730 if (ret <= 0 ||
2731 !is_valid_ether_addr(ðaddr[id * ETH_ALEN])) {
2732 dev_err(dev, "%s: rk_vendor_read eth mac address failed (%d)\n",
2733 __func__, ret);
2734 random_ether_addr(ðaddr[id * ETH_ALEN]);
2735 memcpy(addr, ðaddr[id * ETH_ALEN], ETH_ALEN);
2736 dev_err(dev, "%s: generate random eth mac address: %pM\n", __func__, addr);
2737
2738 ret = rk_vendor_write(LAN_MAC_ID, ethaddr, ETH_ALEN * MAX_ETH);
2739 if (ret != 0)
2740 dev_err(dev, "%s: rk_vendor_write eth mac address failed (%d)\n",
2741 __func__, ret);
2742
2743 ret = rk_vendor_read(LAN_MAC_ID, ethaddr, ETH_ALEN * MAX_ETH);
2744 if (ret != ETH_ALEN * MAX_ETH)
2745 dev_err(dev, "%s: id: %d rk_vendor_read eth mac address failed (%d)\n",
2746 __func__, id, ret);
2747 } else {
2748 memcpy(addr, ðaddr[id * ETH_ALEN], ETH_ALEN);
2749 }
2750
2751 out:
2752 dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
2753 }
2754
rk_gmac_probe(struct platform_device * pdev)2755 static int rk_gmac_probe(struct platform_device *pdev)
2756 {
2757 struct plat_stmmacenet_data *plat_dat;
2758 struct stmmac_resources stmmac_res;
2759 const struct rk_gmac_ops *data;
2760 int ret;
2761
2762 data = of_device_get_match_data(&pdev->dev);
2763 if (!data) {
2764 dev_err(&pdev->dev, "no of match data provided\n");
2765 return -EINVAL;
2766 }
2767
2768 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
2769 if (ret)
2770 return ret;
2771
2772 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
2773 if (IS_ERR(plat_dat))
2774 return PTR_ERR(plat_dat);
2775
2776 if (!of_device_is_compatible(pdev->dev.of_node, "snps,dwmac-4.20a"))
2777 plat_dat->has_gmac = true;
2778
2779 plat_dat->sph_disable = true;
2780 plat_dat->fix_mac_speed = rk_fix_speed;
2781 plat_dat->get_eth_addr = rk_get_eth_addr;
2782 plat_dat->integrated_phy_power = rk_integrated_phy_power;
2783
2784 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
2785 if (IS_ERR(plat_dat->bsp_priv)) {
2786 ret = PTR_ERR(plat_dat->bsp_priv);
2787 goto err_remove_config_dt;
2788 }
2789
2790 ret = rk_gmac_clk_init(plat_dat);
2791 if (ret)
2792 goto err_remove_config_dt;
2793
2794 ret = rk_gmac_powerup(plat_dat->bsp_priv);
2795 if (ret)
2796 goto err_remove_config_dt;
2797
2798 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
2799 if (ret)
2800 goto err_gmac_powerdown;
2801
2802 ret = dwmac_rk_create_loopback_sysfs(&pdev->dev);
2803 if (ret)
2804 goto err_gmac_powerdown;
2805
2806 return 0;
2807
2808 err_gmac_powerdown:
2809 rk_gmac_powerdown(plat_dat->bsp_priv);
2810 err_remove_config_dt:
2811 stmmac_remove_config_dt(pdev, plat_dat);
2812
2813 return ret;
2814 }
2815
rk_gmac_remove(struct platform_device * pdev)2816 static int rk_gmac_remove(struct platform_device *pdev)
2817 {
2818 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
2819 int ret = stmmac_dvr_remove(&pdev->dev);
2820
2821 rk_gmac_powerdown(bsp_priv);
2822 dwmac_rk_remove_loopback_sysfs(&pdev->dev);
2823
2824 return ret;
2825 }
2826
2827 #ifdef CONFIG_PM_SLEEP
rk_gmac_suspend(struct device * dev)2828 static int rk_gmac_suspend(struct device *dev)
2829 {
2830 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2831 int ret = stmmac_suspend(dev);
2832
2833 /* Keep the PHY up if we use Wake-on-Lan. */
2834 if (!device_may_wakeup(dev)) {
2835 rk_gmac_powerdown(bsp_priv);
2836 bsp_priv->suspended = true;
2837 }
2838
2839 return ret;
2840 }
2841
rk_gmac_resume(struct device * dev)2842 static int rk_gmac_resume(struct device *dev)
2843 {
2844 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2845
2846 /* The PHY was up for Wake-on-Lan. */
2847 if (bsp_priv->suspended) {
2848 rk_gmac_powerup(bsp_priv);
2849 bsp_priv->suspended = false;
2850 }
2851
2852 return stmmac_resume(dev);
2853 }
2854 #endif /* CONFIG_PM_SLEEP */
2855
2856 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
2857
2858 static const struct of_device_id rk_gmac_dwmac_match[] = {
2859 #ifdef CONFIG_CPU_PX30
2860 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
2861 #endif
2862 #ifdef CONFIG_CPU_RK1808
2863 { .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
2864 #endif
2865 #ifdef CONFIG_CPU_RK312X
2866 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2867 #endif
2868 #ifdef CONFIG_CPU_RK322X
2869 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2870 #endif
2871 #ifdef CONFIG_CPU_RK3288
2872 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2873 #endif
2874 #ifdef CONFIG_CPU_RK3308
2875 { .compatible = "rockchip,rk3308-mac", .data = &rk3308_ops },
2876 #endif
2877 #ifdef CONFIG_CPU_RK3328
2878 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2879 #endif
2880 #ifdef CONFIG_CPU_RK3366
2881 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2882 #endif
2883 #ifdef CONFIG_CPU_RK3368
2884 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2885 #endif
2886 #ifdef CONFIG_CPU_RK3399
2887 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2888 #endif
2889 #ifdef CONFIG_CPU_RK3528
2890 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
2891 #endif
2892 #ifdef CONFIG_CPU_RK3562
2893 { .compatible = "rockchip,rk3562-gmac", .data = &rk3562_ops },
2894 #endif
2895 #ifdef CONFIG_CPU_RK3568
2896 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2897 #endif
2898 #ifdef CONFIG_CPU_RK3588
2899 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2900 #endif
2901 #ifdef CONFIG_CPU_RV1106
2902 { .compatible = "rockchip,rv1106-gmac", .data = &rv1106_ops },
2903 #endif
2904 #ifdef CONFIG_CPU_RV1108
2905 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2906 #endif
2907 #ifdef CONFIG_CPU_RV1126
2908 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2909 #endif
2910 { }
2911 };
2912 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
2913
2914 static struct platform_driver rk_gmac_dwmac_driver = {
2915 .probe = rk_gmac_probe,
2916 .remove = rk_gmac_remove,
2917 .driver = {
2918 .name = "rk_gmac-dwmac",
2919 .pm = &rk_gmac_pm_ops,
2920 .of_match_table = rk_gmac_dwmac_match,
2921 },
2922 };
2923 module_platform_driver(rk_gmac_dwmac_driver);
2924
2925 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
2926 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
2927 MODULE_LICENSE("GPL");
2928