1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for the ARC EMAC 10100 (hardware revision 5)
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Contributors:
8*4882a593Smuzhiyun * Amit Bhor
9*4882a593Smuzhiyun * Sameer Dhavale
10*4882a593Smuzhiyun * Vineet Gupta
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/crc32.h>
14*4882a593Smuzhiyun #include <linux/etherdevice.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/of_address.h>
19*4882a593Smuzhiyun #include <linux/of_irq.h>
20*4882a593Smuzhiyun #include <linux/of_mdio.h>
21*4882a593Smuzhiyun #include <linux/of_net.h>
22*4882a593Smuzhiyun #include <linux/of_platform.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "emac.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static void arc_emac_restart(struct net_device *ndev);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun * arc_emac_tx_avail - Return the number of available slots in the tx ring.
30*4882a593Smuzhiyun * @priv: Pointer to ARC EMAC private data structure.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * returns: the number of slots available for transmission in tx the ring.
33*4882a593Smuzhiyun */
arc_emac_tx_avail(struct arc_emac_priv * priv)34*4882a593Smuzhiyun static inline int arc_emac_tx_avail(struct arc_emac_priv *priv)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /**
40*4882a593Smuzhiyun * arc_emac_adjust_link - Adjust the PHY link duplex.
41*4882a593Smuzhiyun * @ndev: Pointer to the net_device structure.
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * This function is called to change the duplex setting after auto negotiation
44*4882a593Smuzhiyun * is done by the PHY.
45*4882a593Smuzhiyun */
arc_emac_adjust_link(struct net_device * ndev)46*4882a593Smuzhiyun static void arc_emac_adjust_link(struct net_device *ndev)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
49*4882a593Smuzhiyun struct phy_device *phy_dev = ndev->phydev;
50*4882a593Smuzhiyun unsigned int reg, state_changed = 0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (priv->link != phy_dev->link) {
53*4882a593Smuzhiyun priv->link = phy_dev->link;
54*4882a593Smuzhiyun state_changed = 1;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (priv->speed != phy_dev->speed) {
58*4882a593Smuzhiyun priv->speed = phy_dev->speed;
59*4882a593Smuzhiyun state_changed = 1;
60*4882a593Smuzhiyun if (priv->set_mac_speed)
61*4882a593Smuzhiyun priv->set_mac_speed(priv, priv->speed);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (priv->duplex != phy_dev->duplex) {
65*4882a593Smuzhiyun reg = arc_reg_get(priv, R_CTRL);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (phy_dev->duplex == DUPLEX_FULL)
68*4882a593Smuzhiyun reg |= ENFL_MASK;
69*4882a593Smuzhiyun else
70*4882a593Smuzhiyun reg &= ~ENFL_MASK;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun arc_reg_set(priv, R_CTRL, reg);
73*4882a593Smuzhiyun priv->duplex = phy_dev->duplex;
74*4882a593Smuzhiyun state_changed = 1;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (state_changed)
78*4882a593Smuzhiyun phy_print_status(phy_dev);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /**
82*4882a593Smuzhiyun * arc_emac_get_drvinfo - Get EMAC driver information.
83*4882a593Smuzhiyun * @ndev: Pointer to net_device structure.
84*4882a593Smuzhiyun * @info: Pointer to ethtool_drvinfo structure.
85*4882a593Smuzhiyun *
86*4882a593Smuzhiyun * This implements ethtool command for getting the driver information.
87*4882a593Smuzhiyun * Issue "ethtool -i ethX" under linux prompt to execute this function.
88*4882a593Smuzhiyun */
arc_emac_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)89*4882a593Smuzhiyun static void arc_emac_get_drvinfo(struct net_device *ndev,
90*4882a593Smuzhiyun struct ethtool_drvinfo *info)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun strlcpy(info->driver, priv->drv_name, sizeof(info->driver));
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct ethtool_ops arc_emac_ethtool_ops = {
98*4882a593Smuzhiyun .get_drvinfo = arc_emac_get_drvinfo,
99*4882a593Smuzhiyun .get_link = ethtool_op_get_link,
100*4882a593Smuzhiyun .get_link_ksettings = phy_ethtool_get_link_ksettings,
101*4882a593Smuzhiyun .set_link_ksettings = phy_ethtool_set_link_ksettings,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define FIRST_OR_LAST_MASK (FIRST_MASK | LAST_MASK)
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /**
107*4882a593Smuzhiyun * arc_emac_tx_clean - clears processed by EMAC Tx BDs.
108*4882a593Smuzhiyun * @ndev: Pointer to the network device.
109*4882a593Smuzhiyun */
arc_emac_tx_clean(struct net_device * ndev)110*4882a593Smuzhiyun static void arc_emac_tx_clean(struct net_device *ndev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
113*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
114*4882a593Smuzhiyun unsigned int i;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun for (i = 0; i < TX_BD_NUM; i++) {
117*4882a593Smuzhiyun unsigned int *txbd_dirty = &priv->txbd_dirty;
118*4882a593Smuzhiyun struct arc_emac_bd *txbd = &priv->txbd[*txbd_dirty];
119*4882a593Smuzhiyun struct buffer_state *tx_buff = &priv->tx_buff[*txbd_dirty];
120*4882a593Smuzhiyun struct sk_buff *skb = tx_buff->skb;
121*4882a593Smuzhiyun unsigned int info = le32_to_cpu(txbd->info);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if ((info & FOR_EMAC) || !txbd->data || !skb)
124*4882a593Smuzhiyun break;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (unlikely(info & (DROP | DEFR | LTCL | UFLO))) {
127*4882a593Smuzhiyun stats->tx_errors++;
128*4882a593Smuzhiyun stats->tx_dropped++;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (info & DEFR)
131*4882a593Smuzhiyun stats->tx_carrier_errors++;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (info & LTCL)
134*4882a593Smuzhiyun stats->collisions++;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (info & UFLO)
137*4882a593Smuzhiyun stats->tx_fifo_errors++;
138*4882a593Smuzhiyun } else if (likely(info & FIRST_OR_LAST_MASK)) {
139*4882a593Smuzhiyun stats->tx_packets++;
140*4882a593Smuzhiyun stats->tx_bytes += skb->len;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun dma_unmap_single(ndev->dev.parent, dma_unmap_addr(tx_buff, addr),
144*4882a593Smuzhiyun dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* return the sk_buff to system */
147*4882a593Smuzhiyun dev_consume_skb_irq(skb);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun txbd->data = 0;
150*4882a593Smuzhiyun txbd->info = 0;
151*4882a593Smuzhiyun tx_buff->skb = NULL;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun *txbd_dirty = (*txbd_dirty + 1) % TX_BD_NUM;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Ensure that txbd_dirty is visible to tx() before checking
157*4882a593Smuzhiyun * for queue stopped.
158*4882a593Smuzhiyun */
159*4882a593Smuzhiyun smp_mb();
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (netif_queue_stopped(ndev) && arc_emac_tx_avail(priv))
162*4882a593Smuzhiyun netif_wake_queue(ndev);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /**
166*4882a593Smuzhiyun * arc_emac_rx - processing of Rx packets.
167*4882a593Smuzhiyun * @ndev: Pointer to the network device.
168*4882a593Smuzhiyun * @budget: How many BDs to process on 1 call.
169*4882a593Smuzhiyun *
170*4882a593Smuzhiyun * returns: Number of processed BDs
171*4882a593Smuzhiyun *
172*4882a593Smuzhiyun * Iterate through Rx BDs and deliver received packages to upper layer.
173*4882a593Smuzhiyun */
arc_emac_rx(struct net_device * ndev,int budget)174*4882a593Smuzhiyun static int arc_emac_rx(struct net_device *ndev, int budget)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
177*4882a593Smuzhiyun unsigned int work_done;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun for (work_done = 0; work_done < budget; work_done++) {
180*4882a593Smuzhiyun unsigned int *last_rx_bd = &priv->last_rx_bd;
181*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
182*4882a593Smuzhiyun struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
183*4882a593Smuzhiyun struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
184*4882a593Smuzhiyun unsigned int pktlen, info = le32_to_cpu(rxbd->info);
185*4882a593Smuzhiyun struct sk_buff *skb;
186*4882a593Smuzhiyun dma_addr_t addr;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun if (unlikely((info & OWN_MASK) == FOR_EMAC))
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* Make a note that we saw a packet at this BD.
192*4882a593Smuzhiyun * So next time, driver starts from this + 1
193*4882a593Smuzhiyun */
194*4882a593Smuzhiyun *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (unlikely((info & FIRST_OR_LAST_MASK) !=
197*4882a593Smuzhiyun FIRST_OR_LAST_MASK)) {
198*4882a593Smuzhiyun /* We pre-allocate buffers of MTU size so incoming
199*4882a593Smuzhiyun * packets won't be split/chained.
200*4882a593Smuzhiyun */
201*4882a593Smuzhiyun if (net_ratelimit())
202*4882a593Smuzhiyun netdev_err(ndev, "incomplete packet received\n");
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* Return ownership to EMAC */
205*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
206*4882a593Smuzhiyun stats->rx_errors++;
207*4882a593Smuzhiyun stats->rx_length_errors++;
208*4882a593Smuzhiyun continue;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* Prepare the BD for next cycle. netif_receive_skb()
212*4882a593Smuzhiyun * only if new skb was allocated and mapped to avoid holes
213*4882a593Smuzhiyun * in the RX fifo.
214*4882a593Smuzhiyun */
215*4882a593Smuzhiyun skb = netdev_alloc_skb_ip_align(ndev, EMAC_BUFFER_SIZE);
216*4882a593Smuzhiyun if (unlikely(!skb)) {
217*4882a593Smuzhiyun if (net_ratelimit())
218*4882a593Smuzhiyun netdev_err(ndev, "cannot allocate skb\n");
219*4882a593Smuzhiyun /* Return ownership to EMAC */
220*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
221*4882a593Smuzhiyun stats->rx_errors++;
222*4882a593Smuzhiyun stats->rx_dropped++;
223*4882a593Smuzhiyun continue;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun addr = dma_map_single(ndev->dev.parent, (void *)skb->data,
227*4882a593Smuzhiyun EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
228*4882a593Smuzhiyun if (dma_mapping_error(ndev->dev.parent, addr)) {
229*4882a593Smuzhiyun if (net_ratelimit())
230*4882a593Smuzhiyun netdev_err(ndev, "cannot map dma buffer\n");
231*4882a593Smuzhiyun dev_kfree_skb(skb);
232*4882a593Smuzhiyun /* Return ownership to EMAC */
233*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
234*4882a593Smuzhiyun stats->rx_errors++;
235*4882a593Smuzhiyun stats->rx_dropped++;
236*4882a593Smuzhiyun continue;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* unmap previosly mapped skb */
240*4882a593Smuzhiyun dma_unmap_single(ndev->dev.parent, dma_unmap_addr(rx_buff, addr),
241*4882a593Smuzhiyun dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun pktlen = info & LEN_MASK;
244*4882a593Smuzhiyun stats->rx_packets++;
245*4882a593Smuzhiyun stats->rx_bytes += pktlen;
246*4882a593Smuzhiyun skb_put(rx_buff->skb, pktlen);
247*4882a593Smuzhiyun rx_buff->skb->dev = ndev;
248*4882a593Smuzhiyun rx_buff->skb->protocol = eth_type_trans(rx_buff->skb, ndev);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun netif_receive_skb(rx_buff->skb);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun rx_buff->skb = skb;
253*4882a593Smuzhiyun dma_unmap_addr_set(rx_buff, addr, addr);
254*4882a593Smuzhiyun dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun rxbd->data = cpu_to_le32(addr);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* Make sure pointer to data buffer is set */
259*4882a593Smuzhiyun wmb();
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Return ownership to EMAC */
262*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return work_done;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /**
269*4882a593Smuzhiyun * arc_emac_rx_miss_handle - handle R_MISS register
270*4882a593Smuzhiyun * @ndev: Pointer to the net_device structure.
271*4882a593Smuzhiyun */
arc_emac_rx_miss_handle(struct net_device * ndev)272*4882a593Smuzhiyun static void arc_emac_rx_miss_handle(struct net_device *ndev)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
275*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
276*4882a593Smuzhiyun unsigned int miss;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun miss = arc_reg_get(priv, R_MISS);
279*4882a593Smuzhiyun if (miss) {
280*4882a593Smuzhiyun stats->rx_errors += miss;
281*4882a593Smuzhiyun stats->rx_missed_errors += miss;
282*4882a593Smuzhiyun priv->rx_missed_errors += miss;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /**
287*4882a593Smuzhiyun * arc_emac_rx_stall_check - check RX stall
288*4882a593Smuzhiyun * @ndev: Pointer to the net_device structure.
289*4882a593Smuzhiyun * @budget: How many BDs requested to process on 1 call.
290*4882a593Smuzhiyun * @work_done: How many BDs processed
291*4882a593Smuzhiyun *
292*4882a593Smuzhiyun * Under certain conditions EMAC stop reception of incoming packets and
293*4882a593Smuzhiyun * continuously increment R_MISS register instead of saving data into
294*4882a593Smuzhiyun * provided buffer. This function detect that condition and restart
295*4882a593Smuzhiyun * EMAC.
296*4882a593Smuzhiyun */
arc_emac_rx_stall_check(struct net_device * ndev,int budget,unsigned int work_done)297*4882a593Smuzhiyun static void arc_emac_rx_stall_check(struct net_device *ndev,
298*4882a593Smuzhiyun int budget, unsigned int work_done)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
301*4882a593Smuzhiyun struct arc_emac_bd *rxbd;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (work_done)
304*4882a593Smuzhiyun priv->rx_missed_errors = 0;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (priv->rx_missed_errors && budget) {
307*4882a593Smuzhiyun rxbd = &priv->rxbd[priv->last_rx_bd];
308*4882a593Smuzhiyun if (le32_to_cpu(rxbd->info) & FOR_EMAC) {
309*4882a593Smuzhiyun arc_emac_restart(ndev);
310*4882a593Smuzhiyun priv->rx_missed_errors = 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /**
316*4882a593Smuzhiyun * arc_emac_poll - NAPI poll handler.
317*4882a593Smuzhiyun * @napi: Pointer to napi_struct structure.
318*4882a593Smuzhiyun * @budget: How many BDs to process on 1 call.
319*4882a593Smuzhiyun *
320*4882a593Smuzhiyun * returns: Number of processed BDs
321*4882a593Smuzhiyun */
arc_emac_poll(struct napi_struct * napi,int budget)322*4882a593Smuzhiyun static int arc_emac_poll(struct napi_struct *napi, int budget)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct net_device *ndev = napi->dev;
325*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
326*4882a593Smuzhiyun unsigned int work_done;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun arc_emac_rx_miss_handle(ndev);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun work_done = arc_emac_rx(ndev, budget);
331*4882a593Smuzhiyun if (work_done < budget) {
332*4882a593Smuzhiyun napi_complete_done(napi, work_done);
333*4882a593Smuzhiyun arc_reg_or(priv, R_ENABLE, RXINT_MASK);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun arc_emac_rx_stall_check(ndev, budget, work_done);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun return work_done;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /**
342*4882a593Smuzhiyun * arc_emac_intr - Global interrupt handler for EMAC.
343*4882a593Smuzhiyun * @irq: irq number.
344*4882a593Smuzhiyun * @dev_instance: device instance.
345*4882a593Smuzhiyun *
346*4882a593Smuzhiyun * returns: IRQ_HANDLED for all cases.
347*4882a593Smuzhiyun *
348*4882a593Smuzhiyun * ARC EMAC has only 1 interrupt line, and depending on bits raised in
349*4882a593Smuzhiyun * STATUS register we may tell what is a reason for interrupt to fire.
350*4882a593Smuzhiyun */
arc_emac_intr(int irq,void * dev_instance)351*4882a593Smuzhiyun static irqreturn_t arc_emac_intr(int irq, void *dev_instance)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun struct net_device *ndev = dev_instance;
354*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
355*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
356*4882a593Smuzhiyun unsigned int status;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun status = arc_reg_get(priv, R_STATUS);
359*4882a593Smuzhiyun status &= ~MDIO_MASK;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* Reset all flags except "MDIO complete" */
362*4882a593Smuzhiyun arc_reg_set(priv, R_STATUS, status);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun if (status & RXINT_MASK) {
365*4882a593Smuzhiyun if (likely(napi_schedule_prep(&priv->napi))) {
366*4882a593Smuzhiyun arc_reg_clr(priv, R_ENABLE, RXINT_MASK);
367*4882a593Smuzhiyun __napi_schedule(&priv->napi);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (status & ERR_MASK) {
372*4882a593Smuzhiyun /* MSER/RXCR/RXFR/RXFL interrupt fires on corresponding
373*4882a593Smuzhiyun * 8-bit error counter overrun.
374*4882a593Smuzhiyun */
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun if (status & MSER_MASK) {
377*4882a593Smuzhiyun stats->rx_missed_errors += 0x100;
378*4882a593Smuzhiyun stats->rx_errors += 0x100;
379*4882a593Smuzhiyun priv->rx_missed_errors += 0x100;
380*4882a593Smuzhiyun napi_schedule(&priv->napi);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun if (status & RXCR_MASK) {
384*4882a593Smuzhiyun stats->rx_crc_errors += 0x100;
385*4882a593Smuzhiyun stats->rx_errors += 0x100;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (status & RXFR_MASK) {
389*4882a593Smuzhiyun stats->rx_frame_errors += 0x100;
390*4882a593Smuzhiyun stats->rx_errors += 0x100;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if (status & RXFL_MASK) {
394*4882a593Smuzhiyun stats->rx_over_errors += 0x100;
395*4882a593Smuzhiyun stats->rx_errors += 0x100;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun return IRQ_HANDLED;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
arc_emac_poll_controller(struct net_device * dev)403*4882a593Smuzhiyun static void arc_emac_poll_controller(struct net_device *dev)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun disable_irq(dev->irq);
406*4882a593Smuzhiyun arc_emac_intr(dev->irq, dev);
407*4882a593Smuzhiyun enable_irq(dev->irq);
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /**
412*4882a593Smuzhiyun * arc_emac_open - Open the network device.
413*4882a593Smuzhiyun * @ndev: Pointer to the network device.
414*4882a593Smuzhiyun *
415*4882a593Smuzhiyun * returns: 0, on success or non-zero error value on failure.
416*4882a593Smuzhiyun *
417*4882a593Smuzhiyun * This function sets the MAC address, requests and enables an IRQ
418*4882a593Smuzhiyun * for the EMAC device and starts the Tx queue.
419*4882a593Smuzhiyun * It also connects to the phy device.
420*4882a593Smuzhiyun */
arc_emac_open(struct net_device * ndev)421*4882a593Smuzhiyun static int arc_emac_open(struct net_device *ndev)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
424*4882a593Smuzhiyun struct phy_device *phy_dev = ndev->phydev;
425*4882a593Smuzhiyun int i;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun phy_dev->autoneg = AUTONEG_ENABLE;
428*4882a593Smuzhiyun phy_dev->speed = 0;
429*4882a593Smuzhiyun phy_dev->duplex = 0;
430*4882a593Smuzhiyun linkmode_and(phy_dev->advertising, phy_dev->advertising,
431*4882a593Smuzhiyun phy_dev->supported);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun priv->last_rx_bd = 0;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* Allocate and set buffers for Rx BD's */
436*4882a593Smuzhiyun for (i = 0; i < RX_BD_NUM; i++) {
437*4882a593Smuzhiyun dma_addr_t addr;
438*4882a593Smuzhiyun unsigned int *last_rx_bd = &priv->last_rx_bd;
439*4882a593Smuzhiyun struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
440*4882a593Smuzhiyun struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun rx_buff->skb = netdev_alloc_skb_ip_align(ndev,
443*4882a593Smuzhiyun EMAC_BUFFER_SIZE);
444*4882a593Smuzhiyun if (unlikely(!rx_buff->skb))
445*4882a593Smuzhiyun return -ENOMEM;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun addr = dma_map_single(ndev->dev.parent, (void *)rx_buff->skb->data,
448*4882a593Smuzhiyun EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
449*4882a593Smuzhiyun if (dma_mapping_error(ndev->dev.parent, addr)) {
450*4882a593Smuzhiyun netdev_err(ndev, "cannot dma map\n");
451*4882a593Smuzhiyun dev_kfree_skb(rx_buff->skb);
452*4882a593Smuzhiyun return -ENOMEM;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun dma_unmap_addr_set(rx_buff, addr, addr);
455*4882a593Smuzhiyun dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun rxbd->data = cpu_to_le32(addr);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /* Make sure pointer to data buffer is set */
460*4882a593Smuzhiyun wmb();
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* Return ownership to EMAC */
463*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun priv->txbd_curr = 0;
469*4882a593Smuzhiyun priv->txbd_dirty = 0;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* Clean Tx BD's */
472*4882a593Smuzhiyun memset(priv->txbd, 0, TX_RING_SZ);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* Initialize logical address filter */
475*4882a593Smuzhiyun arc_reg_set(priv, R_LAFL, 0);
476*4882a593Smuzhiyun arc_reg_set(priv, R_LAFH, 0);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun /* Set BD ring pointers for device side */
479*4882a593Smuzhiyun arc_reg_set(priv, R_RX_RING, (unsigned int)priv->rxbd_dma);
480*4882a593Smuzhiyun arc_reg_set(priv, R_TX_RING, (unsigned int)priv->txbd_dma);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /* Enable interrupts */
483*4882a593Smuzhiyun arc_reg_set(priv, R_ENABLE, RXINT_MASK | ERR_MASK);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* Set CONTROL */
486*4882a593Smuzhiyun arc_reg_set(priv, R_CTRL,
487*4882a593Smuzhiyun (RX_BD_NUM << 24) | /* RX BD table length */
488*4882a593Smuzhiyun (TX_BD_NUM << 16) | /* TX BD table length */
489*4882a593Smuzhiyun TXRN_MASK | RXRN_MASK);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun napi_enable(&priv->napi);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /* Enable EMAC */
494*4882a593Smuzhiyun arc_reg_or(priv, R_CTRL, EN_MASK);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun phy_start(ndev->phydev);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun netif_start_queue(ndev);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return 0;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /**
504*4882a593Smuzhiyun * arc_emac_set_rx_mode - Change the receive filtering mode.
505*4882a593Smuzhiyun * @ndev: Pointer to the network device.
506*4882a593Smuzhiyun *
507*4882a593Smuzhiyun * This function enables/disables promiscuous or all-multicast mode
508*4882a593Smuzhiyun * and updates the multicast filtering list of the network device.
509*4882a593Smuzhiyun */
arc_emac_set_rx_mode(struct net_device * ndev)510*4882a593Smuzhiyun static void arc_emac_set_rx_mode(struct net_device *ndev)
511*4882a593Smuzhiyun {
512*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun if (ndev->flags & IFF_PROMISC) {
515*4882a593Smuzhiyun arc_reg_or(priv, R_CTRL, PROM_MASK);
516*4882a593Smuzhiyun } else {
517*4882a593Smuzhiyun arc_reg_clr(priv, R_CTRL, PROM_MASK);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun if (ndev->flags & IFF_ALLMULTI) {
520*4882a593Smuzhiyun arc_reg_set(priv, R_LAFL, ~0);
521*4882a593Smuzhiyun arc_reg_set(priv, R_LAFH, ~0);
522*4882a593Smuzhiyun } else if (ndev->flags & IFF_MULTICAST) {
523*4882a593Smuzhiyun struct netdev_hw_addr *ha;
524*4882a593Smuzhiyun unsigned int filter[2] = { 0, 0 };
525*4882a593Smuzhiyun int bit;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, ndev) {
528*4882a593Smuzhiyun bit = ether_crc_le(ETH_ALEN, ha->addr) >> 26;
529*4882a593Smuzhiyun filter[bit >> 5] |= 1 << (bit & 31);
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun arc_reg_set(priv, R_LAFL, filter[0]);
533*4882a593Smuzhiyun arc_reg_set(priv, R_LAFH, filter[1]);
534*4882a593Smuzhiyun } else {
535*4882a593Smuzhiyun arc_reg_set(priv, R_LAFL, 0);
536*4882a593Smuzhiyun arc_reg_set(priv, R_LAFH, 0);
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /**
542*4882a593Smuzhiyun * arc_free_tx_queue - free skb from tx queue
543*4882a593Smuzhiyun * @ndev: Pointer to the network device.
544*4882a593Smuzhiyun *
545*4882a593Smuzhiyun * This function must be called while EMAC disable
546*4882a593Smuzhiyun */
arc_free_tx_queue(struct net_device * ndev)547*4882a593Smuzhiyun static void arc_free_tx_queue(struct net_device *ndev)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
550*4882a593Smuzhiyun unsigned int i;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun for (i = 0; i < TX_BD_NUM; i++) {
553*4882a593Smuzhiyun struct arc_emac_bd *txbd = &priv->txbd[i];
554*4882a593Smuzhiyun struct buffer_state *tx_buff = &priv->tx_buff[i];
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun if (tx_buff->skb) {
557*4882a593Smuzhiyun dma_unmap_single(ndev->dev.parent,
558*4882a593Smuzhiyun dma_unmap_addr(tx_buff, addr),
559*4882a593Smuzhiyun dma_unmap_len(tx_buff, len),
560*4882a593Smuzhiyun DMA_TO_DEVICE);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* return the sk_buff to system */
563*4882a593Smuzhiyun dev_kfree_skb_irq(tx_buff->skb);
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun txbd->info = 0;
567*4882a593Smuzhiyun txbd->data = 0;
568*4882a593Smuzhiyun tx_buff->skb = NULL;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /**
573*4882a593Smuzhiyun * arc_free_rx_queue - free skb from rx queue
574*4882a593Smuzhiyun * @ndev: Pointer to the network device.
575*4882a593Smuzhiyun *
576*4882a593Smuzhiyun * This function must be called while EMAC disable
577*4882a593Smuzhiyun */
arc_free_rx_queue(struct net_device * ndev)578*4882a593Smuzhiyun static void arc_free_rx_queue(struct net_device *ndev)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
581*4882a593Smuzhiyun unsigned int i;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun for (i = 0; i < RX_BD_NUM; i++) {
584*4882a593Smuzhiyun struct arc_emac_bd *rxbd = &priv->rxbd[i];
585*4882a593Smuzhiyun struct buffer_state *rx_buff = &priv->rx_buff[i];
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (rx_buff->skb) {
588*4882a593Smuzhiyun dma_unmap_single(ndev->dev.parent,
589*4882a593Smuzhiyun dma_unmap_addr(rx_buff, addr),
590*4882a593Smuzhiyun dma_unmap_len(rx_buff, len),
591*4882a593Smuzhiyun DMA_FROM_DEVICE);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun /* return the sk_buff to system */
594*4882a593Smuzhiyun dev_kfree_skb_irq(rx_buff->skb);
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun rxbd->info = 0;
598*4882a593Smuzhiyun rxbd->data = 0;
599*4882a593Smuzhiyun rx_buff->skb = NULL;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun /**
604*4882a593Smuzhiyun * arc_emac_stop - Close the network device.
605*4882a593Smuzhiyun * @ndev: Pointer to the network device.
606*4882a593Smuzhiyun *
607*4882a593Smuzhiyun * This function stops the Tx queue, disables interrupts and frees the IRQ for
608*4882a593Smuzhiyun * the EMAC device.
609*4882a593Smuzhiyun * It also disconnects the PHY device associated with the EMAC device.
610*4882a593Smuzhiyun */
arc_emac_stop(struct net_device * ndev)611*4882a593Smuzhiyun static int arc_emac_stop(struct net_device *ndev)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun napi_disable(&priv->napi);
616*4882a593Smuzhiyun netif_stop_queue(ndev);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun phy_stop(ndev->phydev);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun /* Disable interrupts */
621*4882a593Smuzhiyun arc_reg_clr(priv, R_ENABLE, RXINT_MASK | ERR_MASK);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* Disable EMAC */
624*4882a593Smuzhiyun arc_reg_clr(priv, R_CTRL, EN_MASK);
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /* Return the sk_buff to system */
627*4882a593Smuzhiyun arc_free_tx_queue(ndev);
628*4882a593Smuzhiyun arc_free_rx_queue(ndev);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun return 0;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /**
634*4882a593Smuzhiyun * arc_emac_stats - Get system network statistics.
635*4882a593Smuzhiyun * @ndev: Pointer to net_device structure.
636*4882a593Smuzhiyun *
637*4882a593Smuzhiyun * Returns the address of the device statistics structure.
638*4882a593Smuzhiyun * Statistics are updated in interrupt handler.
639*4882a593Smuzhiyun */
arc_emac_stats(struct net_device * ndev)640*4882a593Smuzhiyun static struct net_device_stats *arc_emac_stats(struct net_device *ndev)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
643*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
644*4882a593Smuzhiyun unsigned long miss, rxerr;
645*4882a593Smuzhiyun u8 rxcrc, rxfram, rxoflow;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun rxerr = arc_reg_get(priv, R_RXERR);
648*4882a593Smuzhiyun miss = arc_reg_get(priv, R_MISS);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun rxcrc = rxerr;
651*4882a593Smuzhiyun rxfram = rxerr >> 8;
652*4882a593Smuzhiyun rxoflow = rxerr >> 16;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun stats->rx_errors += miss;
655*4882a593Smuzhiyun stats->rx_errors += rxcrc + rxfram + rxoflow;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun stats->rx_over_errors += rxoflow;
658*4882a593Smuzhiyun stats->rx_frame_errors += rxfram;
659*4882a593Smuzhiyun stats->rx_crc_errors += rxcrc;
660*4882a593Smuzhiyun stats->rx_missed_errors += miss;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun return stats;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun /**
666*4882a593Smuzhiyun * arc_emac_tx - Starts the data transmission.
667*4882a593Smuzhiyun * @skb: sk_buff pointer that contains data to be Transmitted.
668*4882a593Smuzhiyun * @ndev: Pointer to net_device structure.
669*4882a593Smuzhiyun *
670*4882a593Smuzhiyun * returns: NETDEV_TX_OK, on success
671*4882a593Smuzhiyun * NETDEV_TX_BUSY, if any of the descriptors are not free.
672*4882a593Smuzhiyun *
673*4882a593Smuzhiyun * This function is invoked from upper layers to initiate transmission.
674*4882a593Smuzhiyun */
arc_emac_tx(struct sk_buff * skb,struct net_device * ndev)675*4882a593Smuzhiyun static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
678*4882a593Smuzhiyun unsigned int len, *txbd_curr = &priv->txbd_curr;
679*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
680*4882a593Smuzhiyun __le32 *info = &priv->txbd[*txbd_curr].info;
681*4882a593Smuzhiyun dma_addr_t addr;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun arc_emac_tx_clean(ndev);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun if (skb_padto(skb, ETH_ZLEN))
686*4882a593Smuzhiyun return NETDEV_TX_OK;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun len = max_t(unsigned int, ETH_ZLEN, skb->len);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun if (unlikely(!arc_emac_tx_avail(priv))) {
691*4882a593Smuzhiyun netif_stop_queue(ndev);
692*4882a593Smuzhiyun netdev_err(ndev, "BUG! Tx Ring full when queue awake!\n");
693*4882a593Smuzhiyun return NETDEV_TX_BUSY;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun addr = dma_map_single(ndev->dev.parent, (void *)skb->data, len,
697*4882a593Smuzhiyun DMA_TO_DEVICE);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun if (unlikely(dma_mapping_error(ndev->dev.parent, addr))) {
700*4882a593Smuzhiyun stats->tx_dropped++;
701*4882a593Smuzhiyun stats->tx_errors++;
702*4882a593Smuzhiyun dev_kfree_skb_any(skb);
703*4882a593Smuzhiyun return NETDEV_TX_OK;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun dma_unmap_addr_set(&priv->tx_buff[*txbd_curr], addr, addr);
706*4882a593Smuzhiyun dma_unmap_len_set(&priv->tx_buff[*txbd_curr], len, len);
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun priv->txbd[*txbd_curr].data = cpu_to_le32(addr);
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun /* Make sure pointer to data buffer is set */
711*4882a593Smuzhiyun wmb();
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun skb_tx_timestamp(skb);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun *info = cpu_to_le32(FOR_EMAC | FIRST_OR_LAST_MASK | len);
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun /* Make sure info word is set */
718*4882a593Smuzhiyun wmb();
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun priv->tx_buff[*txbd_curr].skb = skb;
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun /* Increment index to point to the next BD */
723*4882a593Smuzhiyun *txbd_curr = (*txbd_curr + 1) % TX_BD_NUM;
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun /* Ensure that tx_clean() sees the new txbd_curr before
726*4882a593Smuzhiyun * checking the queue status. This prevents an unneeded wake
727*4882a593Smuzhiyun * of the queue in tx_clean().
728*4882a593Smuzhiyun */
729*4882a593Smuzhiyun smp_mb();
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun if (!arc_emac_tx_avail(priv)) {
732*4882a593Smuzhiyun netif_stop_queue(ndev);
733*4882a593Smuzhiyun /* Refresh tx_dirty */
734*4882a593Smuzhiyun smp_mb();
735*4882a593Smuzhiyun if (arc_emac_tx_avail(priv))
736*4882a593Smuzhiyun netif_start_queue(ndev);
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun arc_reg_set(priv, R_STATUS, TXPL_MASK);
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun return NETDEV_TX_OK;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
arc_emac_set_address_internal(struct net_device * ndev)744*4882a593Smuzhiyun static void arc_emac_set_address_internal(struct net_device *ndev)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
747*4882a593Smuzhiyun unsigned int addr_low, addr_hi;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun addr_low = le32_to_cpu(*(__le32 *)&ndev->dev_addr[0]);
750*4882a593Smuzhiyun addr_hi = le16_to_cpu(*(__le16 *)&ndev->dev_addr[4]);
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun arc_reg_set(priv, R_ADDRL, addr_low);
753*4882a593Smuzhiyun arc_reg_set(priv, R_ADDRH, addr_hi);
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /**
757*4882a593Smuzhiyun * arc_emac_set_address - Set the MAC address for this device.
758*4882a593Smuzhiyun * @ndev: Pointer to net_device structure.
759*4882a593Smuzhiyun * @p: 6 byte Address to be written as MAC address.
760*4882a593Smuzhiyun *
761*4882a593Smuzhiyun * This function copies the HW address from the sockaddr structure to the
762*4882a593Smuzhiyun * net_device structure and updates the address in HW.
763*4882a593Smuzhiyun *
764*4882a593Smuzhiyun * returns: -EBUSY if the net device is busy or 0 if the address is set
765*4882a593Smuzhiyun * successfully.
766*4882a593Smuzhiyun */
arc_emac_set_address(struct net_device * ndev,void * p)767*4882a593Smuzhiyun static int arc_emac_set_address(struct net_device *ndev, void *p)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun struct sockaddr *addr = p;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun if (netif_running(ndev))
772*4882a593Smuzhiyun return -EBUSY;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun if (!is_valid_ether_addr(addr->sa_data))
775*4882a593Smuzhiyun return -EADDRNOTAVAIL;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun arc_emac_set_address_internal(ndev);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun return 0;
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun /**
785*4882a593Smuzhiyun * arc_emac_restart - Restart EMAC
786*4882a593Smuzhiyun * @ndev: Pointer to net_device structure.
787*4882a593Smuzhiyun *
788*4882a593Smuzhiyun * This function do hardware reset of EMAC in order to restore
789*4882a593Smuzhiyun * network packets reception.
790*4882a593Smuzhiyun */
arc_emac_restart(struct net_device * ndev)791*4882a593Smuzhiyun static void arc_emac_restart(struct net_device *ndev)
792*4882a593Smuzhiyun {
793*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
794*4882a593Smuzhiyun struct net_device_stats *stats = &ndev->stats;
795*4882a593Smuzhiyun int i;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun if (net_ratelimit())
798*4882a593Smuzhiyun netdev_warn(ndev, "restarting stalled EMAC\n");
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun netif_stop_queue(ndev);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun /* Disable interrupts */
803*4882a593Smuzhiyun arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun /* Disable EMAC */
806*4882a593Smuzhiyun arc_reg_clr(priv, R_CTRL, EN_MASK);
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun /* Return the sk_buff to system */
809*4882a593Smuzhiyun arc_free_tx_queue(ndev);
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun /* Clean Tx BD's */
812*4882a593Smuzhiyun priv->txbd_curr = 0;
813*4882a593Smuzhiyun priv->txbd_dirty = 0;
814*4882a593Smuzhiyun memset(priv->txbd, 0, TX_RING_SZ);
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun for (i = 0; i < RX_BD_NUM; i++) {
817*4882a593Smuzhiyun struct arc_emac_bd *rxbd = &priv->rxbd[i];
818*4882a593Smuzhiyun unsigned int info = le32_to_cpu(rxbd->info);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun if (!(info & FOR_EMAC)) {
821*4882a593Smuzhiyun stats->rx_errors++;
822*4882a593Smuzhiyun stats->rx_dropped++;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun /* Return ownership to EMAC */
825*4882a593Smuzhiyun rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun priv->last_rx_bd = 0;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /* Make sure info is visible to EMAC before enable */
830*4882a593Smuzhiyun wmb();
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun /* Enable interrupts */
833*4882a593Smuzhiyun arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /* Enable EMAC */
836*4882a593Smuzhiyun arc_reg_or(priv, R_CTRL, EN_MASK);
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun netif_start_queue(ndev);
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun static const struct net_device_ops arc_emac_netdev_ops = {
842*4882a593Smuzhiyun .ndo_open = arc_emac_open,
843*4882a593Smuzhiyun .ndo_stop = arc_emac_stop,
844*4882a593Smuzhiyun .ndo_start_xmit = arc_emac_tx,
845*4882a593Smuzhiyun .ndo_set_mac_address = arc_emac_set_address,
846*4882a593Smuzhiyun .ndo_get_stats = arc_emac_stats,
847*4882a593Smuzhiyun .ndo_set_rx_mode = arc_emac_set_rx_mode,
848*4882a593Smuzhiyun .ndo_do_ioctl = phy_do_ioctl_running,
849*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
850*4882a593Smuzhiyun .ndo_poll_controller = arc_emac_poll_controller,
851*4882a593Smuzhiyun #endif
852*4882a593Smuzhiyun };
853*4882a593Smuzhiyun
arc_emac_probe(struct net_device * ndev,int interface)854*4882a593Smuzhiyun int arc_emac_probe(struct net_device *ndev, int interface)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun struct device *dev = ndev->dev.parent;
857*4882a593Smuzhiyun struct resource res_regs;
858*4882a593Smuzhiyun struct device_node *phy_node;
859*4882a593Smuzhiyun struct phy_device *phydev = NULL;
860*4882a593Smuzhiyun struct arc_emac_priv *priv;
861*4882a593Smuzhiyun const char *mac_addr;
862*4882a593Smuzhiyun unsigned int id, clock_frequency, irq;
863*4882a593Smuzhiyun int err;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun /* Get PHY from device tree */
866*4882a593Smuzhiyun phy_node = of_parse_phandle(dev->of_node, "phy", 0);
867*4882a593Smuzhiyun if (!phy_node) {
868*4882a593Smuzhiyun dev_err(dev, "failed to retrieve phy description from device tree\n");
869*4882a593Smuzhiyun return -ENODEV;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /* Get EMAC registers base address from device tree */
873*4882a593Smuzhiyun err = of_address_to_resource(dev->of_node, 0, &res_regs);
874*4882a593Smuzhiyun if (err) {
875*4882a593Smuzhiyun dev_err(dev, "failed to retrieve registers base from device tree\n");
876*4882a593Smuzhiyun err = -ENODEV;
877*4882a593Smuzhiyun goto out_put_node;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /* Get IRQ from device tree */
881*4882a593Smuzhiyun irq = irq_of_parse_and_map(dev->of_node, 0);
882*4882a593Smuzhiyun if (!irq) {
883*4882a593Smuzhiyun dev_err(dev, "failed to retrieve <irq> value from device tree\n");
884*4882a593Smuzhiyun err = -ENODEV;
885*4882a593Smuzhiyun goto out_put_node;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun ndev->netdev_ops = &arc_emac_netdev_ops;
889*4882a593Smuzhiyun ndev->ethtool_ops = &arc_emac_ethtool_ops;
890*4882a593Smuzhiyun ndev->watchdog_timeo = TX_TIMEOUT;
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun priv = netdev_priv(ndev);
893*4882a593Smuzhiyun priv->dev = dev;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun priv->regs = devm_ioremap_resource(dev, &res_regs);
896*4882a593Smuzhiyun if (IS_ERR(priv->regs)) {
897*4882a593Smuzhiyun err = PTR_ERR(priv->regs);
898*4882a593Smuzhiyun goto out_put_node;
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun if (priv->clk) {
904*4882a593Smuzhiyun err = clk_prepare_enable(priv->clk);
905*4882a593Smuzhiyun if (err) {
906*4882a593Smuzhiyun dev_err(dev, "failed to enable clock\n");
907*4882a593Smuzhiyun goto out_put_node;
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun clock_frequency = clk_get_rate(priv->clk);
911*4882a593Smuzhiyun } else {
912*4882a593Smuzhiyun /* Get CPU clock frequency from device tree */
913*4882a593Smuzhiyun if (of_property_read_u32(dev->of_node, "clock-frequency",
914*4882a593Smuzhiyun &clock_frequency)) {
915*4882a593Smuzhiyun dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
916*4882a593Smuzhiyun err = -EINVAL;
917*4882a593Smuzhiyun goto out_put_node;
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun id = arc_reg_get(priv, R_ID);
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun /* Check for EMAC revision 5 or 7, magic number */
924*4882a593Smuzhiyun if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
925*4882a593Smuzhiyun dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
926*4882a593Smuzhiyun err = -ENODEV;
927*4882a593Smuzhiyun goto out_clken;
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun /* Set poll rate so that it polls every 1 ms */
932*4882a593Smuzhiyun arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun ndev->irq = irq;
935*4882a593Smuzhiyun dev_info(dev, "IRQ is %d\n", ndev->irq);
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /* Register interrupt handler for device */
938*4882a593Smuzhiyun err = devm_request_irq(dev, ndev->irq, arc_emac_intr, 0,
939*4882a593Smuzhiyun ndev->name, ndev);
940*4882a593Smuzhiyun if (err) {
941*4882a593Smuzhiyun dev_err(dev, "could not allocate IRQ\n");
942*4882a593Smuzhiyun goto out_clken;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun /* Get MAC address from device tree */
946*4882a593Smuzhiyun mac_addr = of_get_mac_address(dev->of_node);
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun if (!IS_ERR(mac_addr))
949*4882a593Smuzhiyun ether_addr_copy(ndev->dev_addr, mac_addr);
950*4882a593Smuzhiyun else
951*4882a593Smuzhiyun eth_hw_addr_random(ndev);
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun arc_emac_set_address_internal(ndev);
954*4882a593Smuzhiyun dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun /* Do 1 allocation instead of 2 separate ones for Rx and Tx BD rings */
957*4882a593Smuzhiyun priv->rxbd = dmam_alloc_coherent(dev, RX_RING_SZ + TX_RING_SZ,
958*4882a593Smuzhiyun &priv->rxbd_dma, GFP_KERNEL);
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun if (!priv->rxbd) {
961*4882a593Smuzhiyun dev_err(dev, "failed to allocate data buffers\n");
962*4882a593Smuzhiyun err = -ENOMEM;
963*4882a593Smuzhiyun goto out_clken;
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun priv->txbd = priv->rxbd + RX_BD_NUM;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
969*4882a593Smuzhiyun dev_dbg(dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
970*4882a593Smuzhiyun (unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun err = arc_mdio_probe(priv);
973*4882a593Smuzhiyun if (err) {
974*4882a593Smuzhiyun dev_err(dev, "failed to probe MII bus\n");
975*4882a593Smuzhiyun goto out_clken;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
979*4882a593Smuzhiyun interface);
980*4882a593Smuzhiyun if (!phydev) {
981*4882a593Smuzhiyun dev_err(dev, "of_phy_connect() failed\n");
982*4882a593Smuzhiyun err = -ENODEV;
983*4882a593Smuzhiyun goto out_mdio;
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun dev_info(dev, "connected to %s phy with id 0x%x\n",
987*4882a593Smuzhiyun phydev->drv->name, phydev->phy_id);
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun netif_napi_add(ndev, &priv->napi, arc_emac_poll, ARC_EMAC_NAPI_WEIGHT);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun err = register_netdev(ndev);
992*4882a593Smuzhiyun if (err) {
993*4882a593Smuzhiyun dev_err(dev, "failed to register network device\n");
994*4882a593Smuzhiyun goto out_netif_api;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun of_node_put(phy_node);
998*4882a593Smuzhiyun return 0;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun out_netif_api:
1001*4882a593Smuzhiyun netif_napi_del(&priv->napi);
1002*4882a593Smuzhiyun phy_disconnect(phydev);
1003*4882a593Smuzhiyun out_mdio:
1004*4882a593Smuzhiyun arc_mdio_remove(priv);
1005*4882a593Smuzhiyun out_clken:
1006*4882a593Smuzhiyun if (priv->clk)
1007*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
1008*4882a593Smuzhiyun out_put_node:
1009*4882a593Smuzhiyun of_node_put(phy_node);
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun return err;
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arc_emac_probe);
1014*4882a593Smuzhiyun
arc_emac_remove(struct net_device * ndev)1015*4882a593Smuzhiyun int arc_emac_remove(struct net_device *ndev)
1016*4882a593Smuzhiyun {
1017*4882a593Smuzhiyun struct arc_emac_priv *priv = netdev_priv(ndev);
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun phy_disconnect(ndev->phydev);
1020*4882a593Smuzhiyun arc_mdio_remove(priv);
1021*4882a593Smuzhiyun unregister_netdev(ndev);
1022*4882a593Smuzhiyun netif_napi_del(&priv->napi);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun if (!IS_ERR(priv->clk))
1025*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun return 0;
1028*4882a593Smuzhiyun }
1029*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arc_emac_remove);
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun MODULE_AUTHOR("Alexey Brodkin <abrodkin@synopsys.com>");
1032*4882a593Smuzhiyun MODULE_DESCRIPTION("ARC EMAC driver");
1033*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1034