1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 * Rockchip CAN driver
5 */
6
7 #include <linux/module.h>
8 #include <linux/uaccess.h>
9 #include <linux/can.h>
10 #include <linux/can/dev.h>
11 #include <linux/can/error.h>
12 #include <linux/can/led.h>
13 #include <linux/clk.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/of_device.h>
18 #include <linux/reset.h>
19 #include <linux/pm_runtime.h>
20
21 #define DRV_NAME "rockchip_can"
22
23 #define CAN_MODE 0x00
24 #define RESET_MODE 0
25 #define WORK_MODE BIT(0)
26 #define SELF_TEST_EN BIT(2)
27 #define MODE_AUTO_RETX BIT(10)
28
29 #define CAN_CMD 0x04
30 #define TX_REQ BIT(0)
31
32 #define CAN_STATE 0x08
33 #define RX_BUF_FULL BIT(0)
34 #define TX_BUF_FULL BIT(1)
35 #define RX_PERIOD BIT(2)
36 #define TX_PERIOD BIT(3)
37 #define ERR_WARN BIT(4)
38 #define BUS_OFF BIT(5)
39
40 #define CAN_INT 0x0C
41
42 #define CAN_INT_MASK 0x10
43 #define RX_FINISH BIT(0)
44 #define TX_FINISH BIT(1)
45 #define ERR_WARN_INT BIT(2)
46 #define RX_BUF_OV BIT(3)
47 #define PASSIVE_ERR BIT(4)
48 #define TX_LOSTARB BIT(5)
49 #define BUS_ERR_INT BIT(6)
50
51 /* Bit Timing Register */
52 #define CAN_BTT 0x18
53 #define MODE_3_SAMPLES BIT(16)
54 #define BT_SJW_SHIFT 14
55 #define BT_SJW_MASK GENMASK(15, 14)
56 #define BT_BRP_SHIFT 8
57 #define BT_BRP_MASK GENMASK(13, 8)
58 #define BT_TSEG2_SHIFT 4
59 #define BT_TSEG2_MASK GENMASK(6, 4)
60 #define BT_TSEG1_SHIFT 0
61 #define BT_TSEG1_MASK GENMASK(3, 0)
62
63 #define CAN_LOSTARB_CODE 0x28
64
65 #define CAN_ERR_CODE 0x2c
66 #define ERR_TYPE_MASK GENMASK(24, 22)
67 #define ERR_TYPE_SHIFT 22
68 #define BIT_ERR 0
69 #define STUFF_ERR 1
70 #define FORM_ERR 2
71 #define ACK_ERR 3
72 #define CRC_ERR 4
73 #define ERR_DIR_RX BIT(21)
74 #define ERR_LOC_MASK GENMASK(13, 0)
75
76 #define CAN_RX_ERR_CNT 0x34
77
78 #define CAN_TX_ERR_CNT 0x38
79
80 #define CAN_ID 0x3c
81
82 #define CAN_ID_MASK 0x40
83
84 #define CAN_TX_FRM_INFO 0x50
85 #define CAN_EFF BIT(7)
86 #define CAN_RTR BIT(6)
87 #define CAN_DLC_MASK GENMASK(3, 0)
88 #define CAN_DLC(x) ((x) & GENMASK(3, 0))
89
90 #define CAN_TX_ID 0x54
91 #define CAN_TX_ID_MASK 0x1fffffff
92
93 #define CAN_TX_DATA1 0x58
94
95 #define CAN_TX_DATA2 0x5c
96
97 #define CAN_RX_FRM_INFO 0x60
98
99 #define CAN_RX_ID 0x64
100
101 #define CAN_RX_DATA1 0x68
102
103 #define CAN_RX_DATA2 0x6c
104
105 #define CAN_RX_FILTER_MASK 0x1fffffff
106
107 #define CAN_VERSION 0x70
108
109 struct rockchip_can {
110 struct can_priv can;
111 void __iomem *base;
112 struct device *dev;
113 struct clk_bulk_data *clks;
114 int num_clks;
115 struct reset_control *reset;
116 };
117
118 static const struct can_bittiming_const rockchip_can_bittiming_const = {
119 .name = DRV_NAME,
120 .tseg1_min = 1,
121 .tseg1_max = 16,
122 .tseg2_min = 1,
123 .tseg2_max = 8,
124 .sjw_max = 4,
125 .brp_min = 1,
126 .brp_max = 128,
127 .brp_inc = 2,
128 };
129
rockchip_can_write_cmdreg(struct rockchip_can * rcan,u8 val)130 static void rockchip_can_write_cmdreg(struct rockchip_can *rcan, u8 val)
131 {
132 writel(val, rcan->base + CAN_CMD);
133 }
134
set_reset_mode(struct net_device * ndev)135 static int set_reset_mode(struct net_device *ndev)
136 {
137 struct rockchip_can *rcan = netdev_priv(ndev);
138
139 reset_control_assert(rcan->reset);
140 udelay(2);
141 reset_control_deassert(rcan->reset);
142
143 writel(0, rcan->base + CAN_MODE);
144
145 return 0;
146 }
147
set_normal_mode(struct net_device * ndev)148 static int set_normal_mode(struct net_device *ndev)
149 {
150 struct rockchip_can *rcan = netdev_priv(ndev);
151 u32 val;
152
153 val = readl(rcan->base + CAN_MODE);
154 val |= WORK_MODE | MODE_AUTO_RETX;
155 writel(val, rcan->base + CAN_MODE);
156
157 return 0;
158 }
159
160 /* bittiming is called in reset_mode only */
rockchip_can_set_bittiming(struct net_device * ndev)161 static int rockchip_can_set_bittiming(struct net_device *ndev)
162 {
163 struct rockchip_can *rcan = netdev_priv(ndev);
164 struct can_bittiming *bt = &rcan->can.bittiming;
165 u32 cfg;
166
167 cfg = ((bt->sjw - 1) << BT_SJW_SHIFT) |
168 (((bt->brp >> 1) - 1) << BT_BRP_SHIFT) |
169 ((bt->phase_seg2 - 1) << BT_TSEG2_SHIFT) |
170 ((bt->prop_seg + bt->phase_seg1 - 1));
171 if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
172 cfg |= MODE_3_SAMPLES;
173
174 writel(cfg, rcan->base + CAN_BTT);
175
176 netdev_dbg(ndev, "setting BITTIMING=0x%08x brp: %d bitrate:%d\n",
177 cfg, bt->brp, bt->bitrate);
178
179 return 0;
180 }
181
rockchip_can_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)182 static int rockchip_can_get_berr_counter(const struct net_device *ndev,
183 struct can_berr_counter *bec)
184 {
185 struct rockchip_can *rcan = netdev_priv(ndev);
186 int err;
187
188 err = pm_runtime_get_sync(rcan->dev);
189 if (err < 0) {
190 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
191 __func__, err);
192 return err;
193 }
194
195 bec->rxerr = readl(rcan->base + CAN_RX_ERR_CNT);
196 bec->txerr = readl(rcan->base + CAN_TX_ERR_CNT);
197
198 pm_runtime_put(rcan->dev);
199
200 netdev_dbg(ndev, "%s\n", __func__);
201 return 0;
202 }
203
rockchip_can_start(struct net_device * ndev)204 static int rockchip_can_start(struct net_device *ndev)
205 {
206 struct rockchip_can *rcan = netdev_priv(ndev);
207
208 /* we need to enter the reset mode */
209 set_reset_mode(ndev);
210
211 writel(0, rcan->base + CAN_INT_MASK);
212
213 /* RECEIVING FILTER, accept all */
214 writel(0, rcan->base + CAN_ID);
215 writel(CAN_RX_FILTER_MASK, rcan->base + CAN_ID_MASK);
216
217 rockchip_can_set_bittiming(ndev);
218
219 set_normal_mode(ndev);
220
221 rcan->can.state = CAN_STATE_ERROR_ACTIVE;
222
223 netdev_dbg(ndev, "%s\n", __func__);
224 return 0;
225 }
226
rockchip_can_stop(struct net_device * ndev)227 static int rockchip_can_stop(struct net_device *ndev)
228 {
229 struct rockchip_can *rcan = netdev_priv(ndev);
230 u32 val;
231
232 rcan->can.state = CAN_STATE_STOPPED;
233 /* we need to enter reset mode */
234 set_reset_mode(ndev);
235
236 /* disable all interrupts */
237 val = RX_FINISH | TX_FINISH | ERR_WARN_INT |
238 RX_BUF_OV | PASSIVE_ERR | TX_LOSTARB |
239 BUS_ERR_INT;
240
241 writel(val, rcan->base + CAN_INT_MASK);
242 netdev_dbg(ndev, "%s\n", __func__);
243 return 0;
244 }
245
rockchip_can_set_mode(struct net_device * ndev,enum can_mode mode)246 static int rockchip_can_set_mode(struct net_device *ndev, enum can_mode mode)
247 {
248 int err;
249
250 netdev_dbg(ndev, "can set mode: 0x%x\n", mode);
251
252 switch (mode) {
253 case CAN_MODE_START:
254 err = rockchip_can_start(ndev);
255 if (err) {
256 netdev_err(ndev, "starting CAN controller failed!\n");
257 return err;
258 }
259 if (netif_queue_stopped(ndev))
260 netif_wake_queue(ndev);
261 break;
262
263 default:
264 return -EOPNOTSUPP;
265 }
266
267 return 0;
268 }
269
270 /* transmit a CAN message
271 * message layout in the sk_buff should be like this:
272 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77
273 * [ can_id ] [flags] [len] [can data (up to 8 bytes]
274 */
rockchip_can_start_xmit(struct sk_buff * skb,struct net_device * ndev)275 static int rockchip_can_start_xmit(struct sk_buff *skb, struct net_device *ndev)
276 {
277 struct rockchip_can *rcan = netdev_priv(ndev);
278 struct can_frame *cf = (struct can_frame *)skb->data;
279 canid_t id;
280 u8 dlc;
281 u32 fi;
282 u32 data1 = 0, data2 = 0;
283
284 if (can_dropped_invalid_skb(ndev, skb))
285 return NETDEV_TX_OK;
286
287 netif_stop_queue(ndev);
288
289 id = cf->can_id;
290 dlc = cf->can_dlc;
291 fi = dlc;
292
293 if (id & CAN_RTR_FLAG) {
294 fi |= CAN_RTR;
295 fi &= ~CAN_DLC_MASK;
296 }
297
298 if (id & CAN_EFF_FLAG)
299 fi |= CAN_EFF;
300
301 rockchip_can_write_cmdreg(rcan, 0);
302
303 writel(id & CAN_TX_ID_MASK, rcan->base + CAN_TX_ID);
304 if (!(id & CAN_RTR_FLAG)) {
305 data1 = le32_to_cpup((__le32 *)&cf->data[0]);
306 data2 = le32_to_cpup((__le32 *)&cf->data[4]);
307 writel(data1, rcan->base + CAN_TX_DATA1);
308 writel(data2, rcan->base + CAN_TX_DATA2);
309 }
310
311 writel(fi, rcan->base + CAN_TX_FRM_INFO);
312 can_put_echo_skb(skb, ndev, 0);
313
314 rockchip_can_write_cmdreg(rcan, TX_REQ);
315 netdev_dbg(ndev, "TX: can_id:0x%08x dlc: %d mode: 0x%08x data: 0x%08x 0x%08x\n",
316 cf->can_id, cf->can_dlc, rcan->can.ctrlmode, data1, data2);
317
318 return NETDEV_TX_OK;
319 }
320
rockchip_can_rx(struct net_device * ndev)321 static void rockchip_can_rx(struct net_device *ndev)
322 {
323 struct rockchip_can *rcan = netdev_priv(ndev);
324 struct net_device_stats *stats = &ndev->stats;
325 struct can_frame *cf;
326 struct sk_buff *skb;
327 canid_t id;
328 u8 fi;
329 u32 data1 = 0, data2 = 0;
330
331 /* create zero'ed CAN frame buffer */
332 skb = alloc_can_skb(ndev, &cf);
333 if (!skb)
334 return;
335
336 fi = readl(rcan->base + CAN_RX_FRM_INFO);
337 cf->can_dlc = get_can_dlc(fi & CAN_DLC_MASK);
338 id = readl(rcan->base + CAN_RX_ID);
339 if (fi & CAN_EFF)
340 id |= CAN_EFF_FLAG;
341
342 /* remote frame ? */
343 if (fi & CAN_RTR) {
344 id |= CAN_RTR_FLAG;
345 } else {
346 data1 = readl(rcan->base + CAN_RX_DATA1);
347 data2 = readl(rcan->base + CAN_RX_DATA2);
348 }
349
350 cf->can_id = id;
351 *(__le32 *)(cf->data + 0) = cpu_to_le32(data1);
352 *(__le32 *)(cf->data + 4) = cpu_to_le32(data2);
353
354 stats->rx_packets++;
355 stats->rx_bytes += cf->can_dlc;
356 netif_rx(skb);
357
358 can_led_event(ndev, CAN_LED_EVENT_RX);
359
360 netdev_dbg(ndev, "%s can_id:0x%08x fi: 0x%08x dlc: %d data: 0x%08x 0x%08x\n",
361 __func__, cf->can_id, fi, cf->can_dlc,
362 data1, data2);
363 }
364
rockchip_can_clean_rx_info(struct rockchip_can * rcan)365 static void rockchip_can_clean_rx_info(struct rockchip_can *rcan)
366 {
367 readl(rcan->base + CAN_RX_FRM_INFO);
368 readl(rcan->base + CAN_RX_ID);
369 readl(rcan->base + CAN_RX_DATA1);
370 readl(rcan->base + CAN_RX_DATA2);
371 }
372
rockchip_can_err(struct net_device * ndev,u8 isr)373 static int rockchip_can_err(struct net_device *ndev, u8 isr)
374 {
375 struct rockchip_can *rcan = netdev_priv(ndev);
376 struct net_device_stats *stats = &ndev->stats;
377 enum can_state state = rcan->can.state;
378 enum can_state rx_state, tx_state;
379 struct can_frame *cf;
380 struct sk_buff *skb;
381 unsigned int rxerr, txerr;
382 u32 ecc, alc;
383 u32 sta_reg;
384
385 skb = alloc_can_err_skb(ndev, &cf);
386
387 rxerr = readl(rcan->base + CAN_RX_ERR_CNT);
388 txerr = readl(rcan->base + CAN_TX_ERR_CNT);
389 sta_reg = readl(rcan->base + CAN_STATE);
390
391 if (skb) {
392 cf->data[6] = txerr;
393 cf->data[7] = rxerr;
394 }
395
396 if (isr & RX_BUF_OV) {
397 /* data overrun interrupt */
398 netdev_dbg(ndev, "data overrun interrupt\n");
399 if (likely(skb)) {
400 cf->can_id |= CAN_ERR_CRTL;
401 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
402 }
403 stats->rx_over_errors++;
404 stats->rx_errors++;
405
406 /* reset the CAN IP by entering reset mode
407 * ignoring timeout error
408 */
409 set_reset_mode(ndev);
410 set_normal_mode(ndev);
411 }
412
413 if (isr & ERR_WARN_INT) {
414 /* error warning interrupt */
415 netdev_dbg(ndev, "error warning interrupt\n");
416
417 if (sta_reg & BUS_OFF)
418 state = CAN_STATE_BUS_OFF;
419 else if (sta_reg & ERR_WARN)
420 state = CAN_STATE_ERROR_WARNING;
421 else
422 state = CAN_STATE_ERROR_ACTIVE;
423 }
424
425 if (isr & BUS_ERR_INT) {
426 /* bus error interrupt */
427 netdev_dbg(ndev, "bus error interrupt\n");
428 rcan->can.can_stats.bus_error++;
429 stats->rx_errors++;
430
431 if (likely(skb)) {
432 ecc = readl(rcan->base + CAN_ERR_CODE);
433
434 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
435
436 switch ((ecc & ERR_TYPE_MASK) >> ERR_TYPE_SHIFT) {
437 case BIT_ERR:
438 cf->data[2] |= CAN_ERR_PROT_BIT;
439 break;
440 case FORM_ERR:
441 cf->data[2] |= CAN_ERR_PROT_FORM;
442 break;
443 case STUFF_ERR:
444 cf->data[2] |= CAN_ERR_PROT_STUFF;
445 break;
446 default:
447 cf->data[3] = ecc & ERR_LOC_MASK;
448 break;
449 }
450 /* error occurred during transmission? */
451 if ((ecc & ERR_DIR_RX) == 0)
452 cf->data[2] |= CAN_ERR_PROT_TX;
453 }
454 }
455
456 if (isr & PASSIVE_ERR) {
457 /* error passive interrupt */
458 netdev_dbg(ndev, "error passive interrupt\n");
459 if (state == CAN_STATE_ERROR_PASSIVE)
460 state = CAN_STATE_ERROR_WARNING;
461 else
462 state = CAN_STATE_ERROR_PASSIVE;
463 }
464 if (isr & TX_LOSTARB) {
465 /* arbitration lost interrupt */
466 netdev_dbg(ndev, "arbitration lost interrupt\n");
467 alc = readl(rcan->base + CAN_LOSTARB_CODE);
468 rcan->can.can_stats.arbitration_lost++;
469 stats->tx_errors++;
470 if (likely(skb)) {
471 cf->can_id |= CAN_ERR_LOSTARB;
472 cf->data[0] = alc;
473 }
474 }
475
476 if (state != rcan->can.state) {
477 tx_state = txerr >= rxerr ? state : 0;
478 rx_state = txerr <= rxerr ? state : 0;
479
480 if (likely(skb))
481 can_change_state(ndev, cf, tx_state, rx_state);
482 else
483 rcan->can.state = state;
484 if (state == CAN_STATE_BUS_OFF)
485 can_bus_off(ndev);
486 }
487
488 if (likely(skb)) {
489 stats->rx_packets++;
490 stats->rx_bytes += cf->can_dlc;
491 netif_rx(skb);
492 } else {
493 return -ENOMEM;
494 }
495
496 return 0;
497 }
498
rockchip_can_interrupt(int irq,void * dev_id)499 static irqreturn_t rockchip_can_interrupt(int irq, void *dev_id)
500 {
501 struct net_device *ndev = (struct net_device *)dev_id;
502 struct rockchip_can *rcan = netdev_priv(ndev);
503 struct net_device_stats *stats = &ndev->stats;
504 u8 err_int = ERR_WARN_INT | RX_BUF_OV | PASSIVE_ERR |
505 TX_LOSTARB | BUS_ERR_INT;
506 u8 isr;
507
508 isr = readl(rcan->base + CAN_INT);
509 if (isr & TX_FINISH) {
510 /* transmission complete interrupt */
511 stats->tx_bytes += readl(rcan->base + CAN_TX_FRM_INFO) &
512 CAN_DLC_MASK;
513 stats->tx_packets++;
514 rockchip_can_write_cmdreg(rcan, 0);
515 can_get_echo_skb(ndev, 0);
516 netif_wake_queue(ndev);
517 can_led_event(ndev, CAN_LED_EVENT_TX);
518 }
519
520 if (isr & RX_FINISH)
521 rockchip_can_rx(ndev);
522
523 if (isr & err_int) {
524 rockchip_can_clean_rx_info(rcan);
525 if (rockchip_can_err(ndev, isr))
526 netdev_err(ndev, "can't allocate buffer - clearing pending interrupts\n");
527 }
528
529 writel(isr, rcan->base + CAN_INT);
530 rockchip_can_clean_rx_info(rcan);
531 netdev_dbg(ndev, "isr: 0x%x\n", isr);
532 return IRQ_HANDLED;
533 }
534
rockchip_can_open(struct net_device * ndev)535 static int rockchip_can_open(struct net_device *ndev)
536 {
537 struct rockchip_can *rcan = netdev_priv(ndev);
538 int err;
539
540 /* common open */
541 err = open_candev(ndev);
542 if (err)
543 return err;
544
545 err = pm_runtime_get_sync(rcan->dev);
546 if (err < 0) {
547 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
548 __func__, err);
549 goto exit;
550 }
551
552 err = rockchip_can_start(ndev);
553 if (err) {
554 netdev_err(ndev, "could not start CAN peripheral\n");
555 goto exit_can_start;
556 }
557
558 can_led_event(ndev, CAN_LED_EVENT_OPEN);
559 netif_start_queue(ndev);
560
561 netdev_dbg(ndev, "%s\n", __func__);
562 return 0;
563
564 exit_can_start:
565 pm_runtime_put(rcan->dev);
566 exit:
567 close_candev(ndev);
568 return err;
569 }
570
rockchip_can_close(struct net_device * ndev)571 static int rockchip_can_close(struct net_device *ndev)
572 {
573 struct rockchip_can *rcan = netdev_priv(ndev);
574
575 netif_stop_queue(ndev);
576 rockchip_can_stop(ndev);
577 close_candev(ndev);
578 can_led_event(ndev, CAN_LED_EVENT_STOP);
579 pm_runtime_put(rcan->dev);
580
581 netdev_dbg(ndev, "%s\n", __func__);
582 return 0;
583 }
584
585 static const struct net_device_ops rockchip_can_netdev_ops = {
586 .ndo_open = rockchip_can_open,
587 .ndo_stop = rockchip_can_close,
588 .ndo_start_xmit = rockchip_can_start_xmit,
589 };
590
591 /**
592 * rockchip_can_suspend - Suspend method for the driver
593 * @dev: Address of the device structure
594 *
595 * Put the driver into low power mode.
596 * Return: 0 on success and failure value on error
597 */
rockchip_can_suspend(struct device * dev)598 static int __maybe_unused rockchip_can_suspend(struct device *dev)
599 {
600 struct net_device *ndev = dev_get_drvdata(dev);
601
602 if (netif_running(ndev)) {
603 netif_stop_queue(ndev);
604 netif_device_detach(ndev);
605 rockchip_can_stop(ndev);
606 }
607
608 return pm_runtime_force_suspend(dev);
609 }
610
611 /**
612 * rockchip_can_resume - Resume from suspend
613 * @dev: Address of the device structure
614 *
615 * Resume operation after suspend.
616 * Return: 0 on success and failure value on error
617 */
rockchip_can_resume(struct device * dev)618 static int __maybe_unused rockchip_can_resume(struct device *dev)
619 {
620 struct net_device *ndev = dev_get_drvdata(dev);
621 int ret;
622
623 ret = pm_runtime_force_resume(dev);
624 if (ret) {
625 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
626 return ret;
627 }
628
629 if (netif_running(ndev)) {
630 ret = rockchip_can_start(ndev);
631 if (ret) {
632 dev_err(dev, "rockchip_can_chip_start failed on resume\n");
633 return ret;
634 }
635
636 netif_device_attach(ndev);
637 netif_start_queue(ndev);
638 }
639
640 return 0;
641 }
642
643 /**
644 * rockchip_can_runtime_suspend - Runtime suspend method for the driver
645 * @dev: Address of the device structure
646 *
647 * Put the driver into low power mode.
648 * Return: 0 always
649 */
rockchip_can_runtime_suspend(struct device * dev)650 static int __maybe_unused rockchip_can_runtime_suspend(struct device *dev)
651 {
652 struct net_device *ndev = dev_get_drvdata(dev);
653 struct rockchip_can *rcan = netdev_priv(ndev);
654
655 clk_bulk_disable_unprepare(rcan->num_clks, rcan->clks);
656
657 return 0;
658 }
659
660 /**
661 * rockchip_can_runtime_resume - Runtime resume from suspend
662 * @dev: Address of the device structure
663 *
664 * Resume operation after suspend.
665 * Return: 0 on success and failure value on error
666 */
rockchip_can_runtime_resume(struct device * dev)667 static int __maybe_unused rockchip_can_runtime_resume(struct device *dev)
668 {
669 struct net_device *ndev = dev_get_drvdata(dev);
670 struct rockchip_can *rcan = netdev_priv(ndev);
671 int ret;
672
673 ret = clk_bulk_prepare_enable(rcan->num_clks, rcan->clks);
674 if (ret) {
675 dev_err(dev, "Cannot enable clock.\n");
676 return ret;
677 }
678
679 return 0;
680 }
681
682 static const struct dev_pm_ops rockchip_can_dev_pm_ops = {
683 SET_SYSTEM_SLEEP_PM_OPS(rockchip_can_suspend, rockchip_can_resume)
684 SET_RUNTIME_PM_OPS(rockchip_can_runtime_suspend,
685 rockchip_can_runtime_resume, NULL)
686 };
687
688 static const struct of_device_id rockchip_can_of_match[] = {
689 {.compatible = "rockchip,can-1.0"},
690 {},
691 };
692 MODULE_DEVICE_TABLE(of, rockchip_can_of_match);
693
rockchip_can_probe(struct platform_device * pdev)694 static int rockchip_can_probe(struct platform_device *pdev)
695 {
696 struct net_device *ndev;
697 struct rockchip_can *rcan;
698 struct resource *res;
699 void __iomem *addr;
700 int err, irq;
701
702 irq = platform_get_irq(pdev, 0);
703 if (irq < 0) {
704 dev_err(&pdev->dev, "could not get a valid irq\n");
705 return -ENODEV;
706 }
707
708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
709 addr = devm_ioremap_resource(&pdev->dev, res);
710 if (IS_ERR(addr))
711 return -EBUSY;
712
713 ndev = alloc_candev(sizeof(struct rockchip_can), 1);
714 if (!ndev) {
715 dev_err(&pdev->dev, "could not allocate memory for CAN device\n");
716 return -ENOMEM;
717 }
718
719 ndev->netdev_ops = &rockchip_can_netdev_ops;
720 ndev->irq = irq;
721 ndev->flags |= IFF_ECHO;
722
723 rcan = netdev_priv(ndev);
724
725 /* register interrupt handler */
726 err = devm_request_irq(&pdev->dev, ndev->irq, rockchip_can_interrupt,
727 0, ndev->name, ndev);
728 if (err) {
729 dev_err(&pdev->dev, "request_irq err: %d\n", err);
730 return err;
731 }
732
733 rcan->reset = devm_reset_control_array_get(&pdev->dev, false, false);
734 if (IS_ERR(rcan->reset)) {
735 if (PTR_ERR(rcan->reset) != -EPROBE_DEFER)
736 dev_err(&pdev->dev, "failed to get rcan reset lines\n");
737 return PTR_ERR(rcan->reset);
738 }
739
740 rcan->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rcan->clks);
741 if (rcan->num_clks < 1) {
742 dev_err(&pdev->dev, "bus clock not found\n");
743 return -ENODEV;
744 }
745
746 rcan->dev = &pdev->dev;
747 rcan->can.clock.freq = clk_get_rate(rcan->clks[0].clk);
748 rcan->can.bittiming_const = &rockchip_can_bittiming_const;
749 rcan->can.do_set_mode = rockchip_can_set_mode;
750 rcan->can.do_get_berr_counter = rockchip_can_get_berr_counter;
751 rcan->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
752 CAN_CTRLMODE_LISTENONLY |
753 CAN_CTRLMODE_LOOPBACK |
754 CAN_CTRLMODE_3_SAMPLES;
755 rcan->base = addr;
756 platform_set_drvdata(pdev, ndev);
757 SET_NETDEV_DEV(ndev, &pdev->dev);
758
759 pm_runtime_enable(&pdev->dev);
760 err = pm_runtime_get_sync(&pdev->dev);
761 if (err < 0) {
762 dev_err(&pdev->dev, "%s: pm_runtime_get failed(%d)\n",
763 __func__, err);
764 goto err_pmdisable;
765 }
766
767 err = register_candev(ndev);
768 if (err) {
769 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
770 DRV_NAME, err);
771 goto err_disableclks;
772 }
773
774 devm_can_led_init(ndev);
775
776 pm_runtime_put(&pdev->dev);
777
778 return 0;
779
780 err_disableclks:
781 pm_runtime_put(&pdev->dev);
782 err_pmdisable:
783 pm_runtime_disable(&pdev->dev);
784 free_candev(ndev);
785
786 return err;
787 }
788
rockchip_can_remove(struct platform_device * pdev)789 static int rockchip_can_remove(struct platform_device *pdev)
790 {
791 struct net_device *ndev = platform_get_drvdata(pdev);
792
793 unregister_netdev(ndev);
794 pm_runtime_disable(&pdev->dev);
795 free_candev(ndev);
796
797 return 0;
798 }
799
800 static struct platform_driver rockchip_can_driver = {
801 .driver = {
802 .name = DRV_NAME,
803 .pm = &rockchip_can_dev_pm_ops,
804 .of_match_table = rockchip_can_of_match,
805 },
806 .probe = rockchip_can_probe,
807 .remove = rockchip_can_remove,
808 };
809 module_platform_driver(rockchip_can_driver);
810
811 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
812 MODULE_LICENSE("GPL");
813 MODULE_DESCRIPTION("Rockchip CAN Drivers");
814