1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 * Rockchip CANFD driver
5 */
6
7 #include <linux/delay.h>
8 #include <linux/iopoll.h>
9 #include <linux/pinctrl/consumer.h>
10 #include <linux/clk.h>
11 #include <linux/errno.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/skbuff.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/types.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
30
31 /* registers definition */
32 enum rockchip_canfd_reg {
33 CAN_MODE = 0x00,
34 CAN_CMD = 0x04,
35 CAN_STATE = 0x08,
36 CAN_INT = 0x0c,
37 CAN_INT_MASK = 0x10,
38 CAN_LOSTARB_CODE = 0x28,
39 CAN_ERR_CODE = 0x2c,
40 CAN_RX_ERR_CNT = 0x34,
41 CAN_TX_ERR_CNT = 0x38,
42 CAN_IDCODE = 0x3c,
43 CAN_IDMASK = 0x40,
44 CAN_TX_CHECK_FIC = 0x50,
45 CAN_NBTP = 0x100,
46 CAN_DBTP = 0x104,
47 CAN_TDCR = 0x108,
48 CAN_TSCC = 0x10c,
49 CAN_TSCV = 0x110,
50 CAN_TXEFC = 0x114,
51 CAN_RXFC = 0x118,
52 CAN_AFC = 0x11c,
53 CAN_IDCODE0 = 0x120,
54 CAN_IDMASK0 = 0x124,
55 CAN_IDCODE1 = 0x128,
56 CAN_IDMASK1 = 0x12c,
57 CAN_IDCODE2 = 0x130,
58 CAN_IDMASK2 = 0x134,
59 CAN_IDCODE3 = 0x138,
60 CAN_IDMASK3 = 0x13c,
61 CAN_IDCODE4 = 0x140,
62 CAN_IDMASK4 = 0x144,
63 CAN_TXFIC = 0x200,
64 CAN_TXID = 0x204,
65 CAN_TXDAT0 = 0x208,
66 CAN_TXDAT1 = 0x20c,
67 CAN_TXDAT2 = 0x210,
68 CAN_TXDAT3 = 0x214,
69 CAN_TXDAT4 = 0x218,
70 CAN_TXDAT5 = 0x21c,
71 CAN_TXDAT6 = 0x220,
72 CAN_TXDAT7 = 0x224,
73 CAN_TXDAT8 = 0x228,
74 CAN_TXDAT9 = 0x22c,
75 CAN_TXDAT10 = 0x230,
76 CAN_TXDAT11 = 0x234,
77 CAN_TXDAT12 = 0x238,
78 CAN_TXDAT13 = 0x23c,
79 CAN_TXDAT14 = 0x240,
80 CAN_TXDAT15 = 0x244,
81 CAN_RXFIC = 0x300,
82 CAN_RXID = 0x304,
83 CAN_RXTS = 0x308,
84 CAN_RXDAT0 = 0x30c,
85 CAN_RXDAT1 = 0x310,
86 CAN_RXDAT2 = 0x314,
87 CAN_RXDAT3 = 0x318,
88 CAN_RXDAT4 = 0x31c,
89 CAN_RXDAT5 = 0x320,
90 CAN_RXDAT6 = 0x324,
91 CAN_RXDAT7 = 0x328,
92 CAN_RXDAT8 = 0x32c,
93 CAN_RXDAT9 = 0x330,
94 CAN_RXDAT10 = 0x334,
95 CAN_RXDAT11 = 0x338,
96 CAN_RXDAT12 = 0x33c,
97 CAN_RXDAT13 = 0x340,
98 CAN_RXDAT14 = 0x344,
99 CAN_RXDAT15 = 0x348,
100 CAN_RXFRD = 0x400,
101 CAN_TXEFRD = 0x500,
102 };
103
104 enum {
105 ROCKCHIP_CANFD_MODE = 0,
106 ROCKCHIP_CAN_MODE,
107 ROCKCHIP_RK3568_CAN_MODE,
108 };
109
110 #define DATE_LENGTH_12_BYTE (0x9)
111 #define DATE_LENGTH_16_BYTE (0xa)
112 #define DATE_LENGTH_20_BYTE (0xb)
113 #define DATE_LENGTH_24_BYTE (0xc)
114 #define DATE_LENGTH_32_BYTE (0xd)
115 #define DATE_LENGTH_48_BYTE (0xe)
116 #define DATE_LENGTH_64_BYTE (0xf)
117
118 #define CAN_TX0_REQ BIT(0)
119 #define CAN_TX1_REQ BIT(1)
120 #define CAN_TX_REQ_FULL ((CAN_TX0_REQ) | (CAN_TX1_REQ))
121
122 #define MODE_FDOE BIT(15)
123 #define MODE_BRSD BIT(13)
124 #define MODE_SPACE_RX BIT(12)
125 #define MODE_AUTO_RETX BIT(10)
126 #define MODE_RXSORT BIT(7)
127 #define MODE_TXORDER BIT(6)
128 #define MODE_RXSTX BIT(5)
129 #define MODE_LBACK BIT(4)
130 #define MODE_SILENT BIT(3)
131 #define MODE_SELF_TEST BIT(2)
132 #define MODE_SLEEP BIT(1)
133 #define RESET_MODE 0
134 #define WORK_MODE BIT(0)
135
136 #define RX_FINISH_INT BIT(0)
137 #define TX_FINISH_INT BIT(1)
138 #define ERR_WARN_INT BIT(2)
139 #define RX_BUF_OV_INT BIT(3)
140 #define PASSIVE_ERR_INT BIT(4)
141 #define TX_LOSTARB_INT BIT(5)
142 #define BUS_ERR_INT BIT(6)
143 #define RX_FIFO_FULL_INT BIT(7)
144 #define RX_FIFO_OV_INT BIT(8)
145 #define BUS_OFF_INT BIT(9)
146 #define BUS_OFF_RECOVERY_INT BIT(10)
147 #define TSC_OV_INT BIT(11)
148 #define TXE_FIFO_OV_INT BIT(12)
149 #define TXE_FIFO_FULL_INT BIT(13)
150 #define WAKEUP_INT BIT(14)
151
152 #define ERR_TYPE_MASK GENMASK(28, 26)
153 #define ERR_TYPE_SHIFT 26
154 #define BIT_ERR 0
155 #define STUFF_ERR 1
156 #define FORM_ERR 2
157 #define ACK_ERR 3
158 #define CRC_ERR 4
159 #define ERR_DIR_RX BIT(25)
160 #define ERR_LOC_MASK GENMASK(15, 0)
161
162 /* Nominal Bit Timing & Prescaler Register (NBTP) */
163 #define NBTP_MODE_3_SAMPLES BIT(31)
164 #define NBTP_NSJW_SHIFT 24
165 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
166 #define NBTP_NBRP_SHIFT 16
167 #define NBTP_NBRP_MASK (0xff << NBTP_NBRP_SHIFT)
168 #define NBTP_NTSEG2_SHIFT 8
169 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
170 #define NBTP_NTSEG1_SHIFT 0
171 #define NBTP_NTSEG1_MASK (0x7f << NBTP_NTSEG1_SHIFT)
172
173 /* Data Bit Timing & Prescaler Register (DBTP) */
174 #define DBTP_MODE_3_SAMPLES BIT(21)
175 #define DBTP_DSJW_SHIFT 17
176 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
177 #define DBTP_DBRP_SHIFT 9
178 #define DBTP_DBRP_MASK (0xff << DBTP_DBRP_SHIFT)
179 #define DBTP_DTSEG2_SHIFT 5
180 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
181 #define DBTP_DTSEG1_SHIFT 0
182 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
183
184 /* Transmitter Delay Compensation Register (TDCR) */
185 #define TDCR_TDCO_SHIFT 1
186 #define TDCR_TDCO_MASK (0x3f << TDCR_TDCO_SHIFT)
187 #define TDCR_TDC_ENABLE BIT(0)
188
189 #define TX_FD_ENABLE BIT(5)
190 #define TX_FD_BRS_ENABLE BIT(4)
191
192 #define FIFO_ENABLE BIT(0)
193 #define RX_FIFO_CNT0_SHIFT 4
194 #define RX_FIFO_CNT0_MASK (0x7 << RX_FIFO_CNT0_SHIFT)
195 #define RX_FIFO_CNT1_SHIFT 5
196 #define RX_FIFO_CNT1_MASK (0x7 << RX_FIFO_CNT1_SHIFT)
197
198 #define FORMAT_SHIFT 7
199 #define FORMAT_MASK (0x1 << FORMAT_SHIFT)
200 #define RTR_SHIFT 6
201 #define RTR_MASK (0x1 << RTR_SHIFT)
202 #define FDF_SHIFT 5
203 #define FDF_MASK (0x1 << FDF_SHIFT)
204 #define BRS_SHIFT 4
205 #define BRS_MASK (0x1 << BRS_SHIFT)
206 #define DLC_SHIFT 0
207 #define DLC_MASK (0xF << DLC_SHIFT)
208
209 #define CAN_RF_SIZE 0x48
210 #define CAN_TEF_SIZE 0x8
211 #define CAN_TXEFRD_OFFSET(n) (CAN_TXEFRD + CAN_TEF_SIZE * (n))
212 #define CAN_RXFRD_OFFSET(n) (CAN_RXFRD + CAN_RF_SIZE * (n))
213
214 #define CAN_RX_FILTER_MASK 0x1fffffff
215
216 #define DRV_NAME "forlinx_canfd"
217
218 /* rockchip_canfd private data structure */
219
220 struct rockchip_canfd {
221 struct can_priv can;
222 struct device *dev;
223 struct clk_bulk_data *clks;
224 int num_clks;
225 struct reset_control *reset;
226 void __iomem *base;
227 u32 irqstatus;
228 unsigned long mode;
229 int rx_fifo_shift;
230 u32 rx_fifo_mask;
231 bool txtorx;
232 u32 tx_invalid[4];
233 struct delayed_work tx_err_work;
234 };
235
rockchip_canfd_read(const struct rockchip_canfd * priv,enum rockchip_canfd_reg reg)236 static inline u32 rockchip_canfd_read(const struct rockchip_canfd *priv,
237 enum rockchip_canfd_reg reg)
238 {
239 return readl(priv->base + reg);
240 }
241
rockchip_canfd_write(const struct rockchip_canfd * priv,enum rockchip_canfd_reg reg,u32 val)242 static inline void rockchip_canfd_write(const struct rockchip_canfd *priv,
243 enum rockchip_canfd_reg reg, u32 val)
244 {
245 writel(val, priv->base + reg);
246 }
247
248 static const struct can_bittiming_const rockchip_canfd_bittiming_const = {
249 .name = DRV_NAME,
250 .tseg1_min = 1,
251 .tseg1_max = 128,
252 .tseg2_min = 1,
253 .tseg2_max = 128,
254 .sjw_max = 128,
255 .brp_min = 1,
256 .brp_max = 256,
257 .brp_inc = 2,
258 };
259
260 static const struct can_bittiming_const rockchip_canfd_data_bittiming_const = {
261 .name = DRV_NAME,
262 .tseg1_min = 1,
263 .tseg1_max = 32,
264 .tseg2_min = 1,
265 .tseg2_max = 16,
266 .sjw_max = 16,
267 .brp_min = 1,
268 .brp_max = 256,
269 .brp_inc = 2,
270 };
271
set_reset_mode(struct net_device * ndev)272 static int set_reset_mode(struct net_device *ndev)
273 {
274 struct rockchip_canfd *rcan = netdev_priv(ndev);
275
276 reset_control_assert(rcan->reset);
277 udelay(2);
278 reset_control_deassert(rcan->reset);
279
280 rockchip_canfd_write(rcan, CAN_MODE, 0);
281
282 netdev_dbg(ndev, "%s MODE=0x%08x\n", __func__,
283 rockchip_canfd_read(rcan, CAN_MODE));
284
285 return 0;
286 }
287
set_normal_mode(struct net_device * ndev)288 static int set_normal_mode(struct net_device *ndev)
289 {
290 struct rockchip_canfd *rcan = netdev_priv(ndev);
291 u32 val;
292
293 val = rockchip_canfd_read(rcan, CAN_MODE);
294 val |= WORK_MODE;
295 if (rcan->mode >= ROCKCHIP_CAN_MODE && rcan->txtorx)
296 val |= MODE_RXSTX;
297 rockchip_canfd_write(rcan, CAN_MODE, val);
298
299 netdev_dbg(ndev, "%s MODE=0x%08x\n", __func__,
300 rockchip_canfd_read(rcan, CAN_MODE));
301 return 0;
302 }
303
304 /* bittiming is called in reset_mode only */
rockchip_canfd_set_bittiming(struct net_device * ndev)305 static int rockchip_canfd_set_bittiming(struct net_device *ndev)
306 {
307 struct rockchip_canfd *rcan = netdev_priv(ndev);
308 const struct can_bittiming *bt = &rcan->can.bittiming;
309 const struct can_bittiming *dbt = &rcan->can.data_bittiming;
310 u16 brp, sjw, tseg1, tseg2;
311 u32 reg_btp;
312
313 brp = (bt->brp >> 1) - 1;
314 sjw = bt->sjw - 1;
315 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
316 tseg2 = bt->phase_seg2 - 1;
317 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
318 (tseg1 << NBTP_NTSEG1_SHIFT) |
319 (tseg2 << NBTP_NTSEG2_SHIFT);
320
321 if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
322 reg_btp |= NBTP_MODE_3_SAMPLES;
323
324 rockchip_canfd_write(rcan, CAN_NBTP, reg_btp);
325
326 if (rcan->can.ctrlmode & CAN_CTRLMODE_FD) {
327 reg_btp = 0;
328 brp = (dbt->brp >> 1) - 1;
329 sjw = dbt->sjw - 1;
330 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
331 tseg2 = dbt->phase_seg2 - 1;
332
333 if (dbt->bitrate > 2200000) {
334 u32 tdco;
335
336 /* Equation based on Bosch's ROCKCHIP_CAN User Manual's
337 * Transmitter Delay Compensation Section
338 */
339 tdco = (rcan->can.clock.freq / dbt->bitrate) * 2 / 3;
340 /* Max valid TDCO value is 63 */
341 if (tdco > 63)
342 tdco = 63;
343
344 rockchip_canfd_write(rcan, CAN_TDCR,
345 (tdco << TDCR_TDCO_SHIFT) |
346 TDCR_TDC_ENABLE);
347 }
348
349 reg_btp |= (brp << DBTP_DBRP_SHIFT) |
350 (sjw << DBTP_DSJW_SHIFT) |
351 (tseg1 << DBTP_DTSEG1_SHIFT) |
352 (tseg2 << DBTP_DTSEG2_SHIFT);
353
354 if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
355 reg_btp |= DBTP_MODE_3_SAMPLES;
356
357 rockchip_canfd_write(rcan, CAN_DBTP, reg_btp);
358 }
359
360 netdev_dbg(ndev, "%s NBTP=0x%08x, DBTP=0x%08x, TDCR=0x%08x\n", __func__,
361 rockchip_canfd_read(rcan, CAN_NBTP),
362 rockchip_canfd_read(rcan, CAN_DBTP),
363 rockchip_canfd_read(rcan, CAN_TDCR));
364 return 0;
365 }
366
rockchip_canfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)367 static int rockchip_canfd_get_berr_counter(const struct net_device *ndev,
368 struct can_berr_counter *bec)
369 {
370 struct rockchip_canfd *rcan = netdev_priv(ndev);
371 int err;
372
373 err = pm_runtime_get_sync(rcan->dev);
374 if (err < 0) {
375 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
376 __func__, err);
377 return err;
378 }
379
380 bec->rxerr = rockchip_canfd_read(rcan, CAN_RX_ERR_CNT);
381 bec->txerr = rockchip_canfd_read(rcan, CAN_TX_ERR_CNT);
382
383 pm_runtime_put(rcan->dev);
384
385 netdev_dbg(ndev, "%s RX_ERR_CNT=0x%08x, TX_ERR_CNT=0x%08x\n", __func__,
386 rockchip_canfd_read(rcan, CAN_RX_ERR_CNT),
387 rockchip_canfd_read(rcan, CAN_TX_ERR_CNT));
388
389 return 0;
390 }
391
rockchip_canfd_start(struct net_device * ndev)392 static int rockchip_canfd_start(struct net_device *ndev)
393 {
394 struct rockchip_canfd *rcan = netdev_priv(ndev);
395 u32 val;
396
397 /* we need to enter the reset mode */
398 set_reset_mode(ndev);
399
400 rockchip_canfd_write(rcan, CAN_INT_MASK, 0);
401
402 /* RECEIVING FILTER, accept all */
403 rockchip_canfd_write(rcan, CAN_IDCODE, 0);
404 rockchip_canfd_write(rcan, CAN_IDMASK, CAN_RX_FILTER_MASK);
405 rockchip_canfd_write(rcan, CAN_IDCODE0, 0);
406 rockchip_canfd_write(rcan, CAN_IDMASK0, CAN_RX_FILTER_MASK);
407 rockchip_canfd_write(rcan, CAN_IDCODE1, 0);
408 rockchip_canfd_write(rcan, CAN_IDMASK1, CAN_RX_FILTER_MASK);
409 rockchip_canfd_write(rcan, CAN_IDCODE2, 0);
410 rockchip_canfd_write(rcan, CAN_IDMASK2, CAN_RX_FILTER_MASK);
411 rockchip_canfd_write(rcan, CAN_IDCODE3, 0);
412 rockchip_canfd_write(rcan, CAN_IDMASK3, CAN_RX_FILTER_MASK);
413 rockchip_canfd_write(rcan, CAN_IDCODE4, 0);
414 rockchip_canfd_write(rcan, CAN_IDMASK4, CAN_RX_FILTER_MASK);
415
416 /* set mode */
417 val = rockchip_canfd_read(rcan, CAN_MODE);
418
419 /* rx fifo enable */
420 rockchip_canfd_write(rcan, CAN_RXFC,
421 rockchip_canfd_read(rcan, CAN_RXFC) | FIFO_ENABLE);
422
423 /* Mode */
424 val |= MODE_FDOE;
425
426 /* Loopback Mode */
427 if (rcan->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
428 val |= MODE_SELF_TEST | MODE_LBACK;
429
430 val |= MODE_AUTO_RETX;
431
432 rockchip_canfd_write(rcan, CAN_MODE, val);
433
434 rockchip_canfd_set_bittiming(ndev);
435
436 set_normal_mode(ndev);
437
438 rcan->can.state = CAN_STATE_ERROR_ACTIVE;
439
440 netdev_dbg(ndev, "%s MODE=0x%08x, INT_MASK=0x%08x\n", __func__,
441 rockchip_canfd_read(rcan, CAN_MODE),
442 rockchip_canfd_read(rcan, CAN_INT_MASK));
443
444 return 0;
445 }
446
rockchip_canfd_stop(struct net_device * ndev)447 static int rockchip_canfd_stop(struct net_device *ndev)
448 {
449 struct rockchip_canfd *rcan = netdev_priv(ndev);
450
451 rcan->can.state = CAN_STATE_STOPPED;
452 /* we need to enter reset mode */
453 set_reset_mode(ndev);
454
455 /* disable all interrupts */
456 rockchip_canfd_write(rcan, CAN_INT_MASK, 0xffff);
457
458 netdev_dbg(ndev, "%s MODE=0x%08x, INT_MASK=0x%08x\n", __func__,
459 rockchip_canfd_read(rcan, CAN_MODE),
460 rockchip_canfd_read(rcan, CAN_INT_MASK));
461 return 0;
462 }
463
rockchip_canfd_set_mode(struct net_device * ndev,enum can_mode mode)464 static int rockchip_canfd_set_mode(struct net_device *ndev,
465 enum can_mode mode)
466 {
467 int err;
468
469 switch (mode) {
470 case CAN_MODE_START:
471 err = rockchip_canfd_start(ndev);
472 if (err) {
473 netdev_err(ndev, "starting CAN controller failed!\n");
474 return err;
475 }
476 if (netif_queue_stopped(ndev))
477 netif_wake_queue(ndev);
478 break;
479
480 default:
481 return -EOPNOTSUPP;
482 }
483
484 return 0;
485 }
486
rockchip_canfd_tx_err_delay_work(struct work_struct * work)487 static void rockchip_canfd_tx_err_delay_work(struct work_struct *work)
488 {
489 struct rockchip_canfd *rcan =
490 container_of(work, struct rockchip_canfd, tx_err_work.work);
491 u32 mode, err_code, id;
492
493 id = rockchip_canfd_read(rcan, CAN_TXID);
494 err_code = rockchip_canfd_read(rcan, CAN_ERR_CODE);
495 if (err_code & 0x1fe0000) {
496 mode = rockchip_canfd_read(rcan, CAN_MODE);
497 rockchip_canfd_write(rcan, CAN_MODE, 0);
498 rockchip_canfd_write(rcan, CAN_MODE, mode);
499 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
500 schedule_delayed_work(&rcan->tx_err_work, 1);
501 } else if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && id & CAN_EFF_FLAG) {
502 schedule_delayed_work(&rcan->tx_err_work, 1);
503 }
504 }
505
506 /* transmit a CAN message
507 * message layout in the sk_buff should be like this:
508 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77
509 * [ can_id ] [flags] [len] [can data (up to 8 bytes]
510 */
rockchip_canfd_start_xmit(struct sk_buff * skb,struct net_device * ndev)511 static int rockchip_canfd_start_xmit(struct sk_buff *skb,
512 struct net_device *ndev)
513 {
514 struct rockchip_canfd *rcan = netdev_priv(ndev);
515 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
516 u32 id, dlc;
517 u32 cmd = CAN_TX0_REQ;
518 int i;
519 unsigned long flags;
520
521 if (can_dropped_invalid_skb(ndev, skb))
522 return NETDEV_TX_OK;
523
524 netif_stop_queue(ndev);
525
526 if (rockchip_canfd_read(rcan, CAN_CMD) & CAN_TX0_REQ)
527 cmd = CAN_TX1_REQ;
528
529 /* Watch carefully on the bit sequence */
530 if (cf->can_id & CAN_EFF_FLAG) {
531 /* Extended CAN ID format */
532 id = cf->can_id & CAN_EFF_MASK;
533 dlc = can_len2dlc(cf->len) & DLC_MASK;
534 dlc |= FORMAT_MASK;
535
536 /* Extended frames remote TX request */
537 if (cf->can_id & CAN_RTR_FLAG)
538 dlc |= RTR_MASK;
539 } else {
540 /* Standard CAN ID format */
541 id = cf->can_id & CAN_SFF_MASK;
542 dlc = can_len2dlc(cf->len) & DLC_MASK;
543
544 /* Standard frames remote TX request */
545 if (cf->can_id & CAN_RTR_FLAG)
546 dlc |= RTR_MASK;
547 }
548
549 if ((rcan->can.ctrlmode & CAN_CTRLMODE_FD) && can_is_canfd_skb(skb)) {
550 dlc |= TX_FD_ENABLE;
551 if (cf->flags & CANFD_BRS)
552 dlc |= TX_FD_BRS_ENABLE;
553 }
554
555 if (!rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && cf->can_id & CAN_EFF_FLAG) {
556 /* Two frames are sent consecutively.
557 * Before the first frame is tx finished,
558 * the register of the second frame is configured.
559 * Don't be interrupted in the middle.
560 */
561 local_irq_save(flags);
562 rockchip_canfd_write(rcan, CAN_TXID, rcan->tx_invalid[1]);
563 rockchip_canfd_write(rcan, CAN_TXFIC, rcan->tx_invalid[0]);
564 rockchip_canfd_write(rcan, CAN_TXDAT0, rcan->tx_invalid[2]);
565 rockchip_canfd_write(rcan, CAN_TXDAT1, rcan->tx_invalid[3]);
566 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
567 rockchip_canfd_write(rcan, CAN_TXID, id);
568 rockchip_canfd_write(rcan, CAN_TXFIC, dlc);
569 for (i = 0; i < cf->len; i += 4)
570 rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
571 *(u32 *)(cf->data + i));
572 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
573 local_irq_restore(flags);
574 can_put_echo_skb(skb, ndev, 0);
575
576 return NETDEV_TX_OK;
577 }
578
579 rockchip_canfd_write(rcan, CAN_TXID, id);
580 rockchip_canfd_write(rcan, CAN_TXFIC, dlc);
581
582 for (i = 0; i < cf->len; i += 4)
583 rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
584 *(u32 *)(cf->data + i));
585
586 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
587
588 if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && cf->can_id & CAN_EFF_FLAG)
589 schedule_delayed_work(&rcan->tx_err_work, 1);
590
591 can_put_echo_skb(skb, ndev, 0);
592
593 return NETDEV_TX_OK;
594 }
595
rockchip_canfd_rx(struct net_device * ndev)596 static int rockchip_canfd_rx(struct net_device *ndev)
597 {
598 struct rockchip_canfd *rcan = netdev_priv(ndev);
599 struct net_device_stats *stats = &ndev->stats;
600 struct canfd_frame *cf;
601 struct sk_buff *skb;
602 u32 id_rockchip_canfd, dlc;
603 int i = 0;
604 u32 __maybe_unused ts, ret;
605 u32 data[16] = {0};
606
607 dlc = rockchip_canfd_read(rcan, CAN_RXFRD);
608 id_rockchip_canfd = rockchip_canfd_read(rcan, CAN_RXFRD);
609 ts = rockchip_canfd_read(rcan, CAN_RXFRD);
610 for (i = 0; i < 16; i++)
611 data[i] = rockchip_canfd_read(rcan, CAN_RXFRD);
612
613 if (rcan->mode >= ROCKCHIP_CAN_MODE) {
614 /* may be an empty frame */
615 if (!dlc && !id_rockchip_canfd)
616 return 1;
617
618 if (rcan->txtorx) {
619 if (rockchip_canfd_read(rcan, CAN_TX_CHECK_FIC) & FORMAT_MASK) {
620 ret = rockchip_canfd_read(rcan, CAN_TXID) & CAN_SFF_MASK;
621 if (id_rockchip_canfd == ret) {
622 rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC,
623 ts | CAN_TX0_REQ);
624 return 1;
625 }
626 }
627 }
628 }
629
630 /* create zero'ed CAN frame buffer */
631 if (dlc & FDF_MASK)
632 skb = alloc_canfd_skb(ndev, &cf);
633 else
634 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
635 if (!skb) {
636 stats->rx_dropped++;
637 return 1;
638 }
639
640 /* Change CAN data length format to socketCAN data format */
641 if (dlc & FDF_MASK)
642 cf->len = can_dlc2len(dlc & DLC_MASK);
643 else
644 cf->len = get_can_dlc(dlc & DLC_MASK);
645
646 /* Change CAN ID format to socketCAN ID format */
647 if (dlc & FORMAT_MASK) {
648 /* The received frame is an Extended format frame */
649 cf->can_id = id_rockchip_canfd;
650 cf->can_id |= CAN_EFF_FLAG;
651 if (dlc & RTR_MASK)
652 cf->can_id |= CAN_RTR_FLAG;
653 } else {
654 /* The received frame is a standard format frame */
655 cf->can_id = id_rockchip_canfd;
656 if (dlc & RTR_MASK)
657 cf->can_id |= CAN_RTR_FLAG;
658 }
659
660 if (dlc & BRS_MASK)
661 cf->flags |= CANFD_BRS;
662
663 if (!(cf->can_id & CAN_RTR_FLAG)) {
664 /* Change CAN data format to socketCAN data format */
665 for (i = 0; i < cf->len; i += 4)
666 *(u32 *)(cf->data + i) = data[i / 4];
667 }
668
669 stats->rx_packets++;
670 stats->rx_bytes += cf->len;
671 netif_rx(skb);
672
673 can_led_event(ndev, CAN_LED_EVENT_RX);
674
675 return 1;
676 }
677
rockchip_canfd_err(struct net_device * ndev,u32 isr)678 static int rockchip_canfd_err(struct net_device *ndev, u32 isr)
679 {
680 struct rockchip_canfd *rcan = netdev_priv(ndev);
681 struct net_device_stats *stats = &ndev->stats;
682 struct can_frame *cf;
683 struct sk_buff *skb;
684 unsigned int rxerr, txerr;
685 u32 sta_reg;
686
687 skb = alloc_can_err_skb(ndev, &cf);
688
689 rxerr = rockchip_canfd_read(rcan, CAN_RX_ERR_CNT);
690 txerr = rockchip_canfd_read(rcan, CAN_TX_ERR_CNT);
691 sta_reg = rockchip_canfd_read(rcan, CAN_STATE);
692
693 if (skb) {
694 cf->data[6] = txerr;
695 cf->data[7] = rxerr;
696 }
697
698 if (isr & BUS_OFF_INT) {
699 rcan->can.state = CAN_STATE_BUS_OFF;
700 rcan->can.can_stats.bus_off++;
701 cf->can_id |= CAN_ERR_BUSOFF;
702 } else if (isr & ERR_WARN_INT) {
703 rcan->can.can_stats.error_warning++;
704 rcan->can.state = CAN_STATE_ERROR_WARNING;
705 /* error warning state */
706 if (likely(skb)) {
707 cf->can_id |= CAN_ERR_CRTL;
708 cf->data[1] = (txerr > rxerr) ?
709 CAN_ERR_CRTL_TX_WARNING :
710 CAN_ERR_CRTL_RX_WARNING;
711 cf->data[6] = txerr;
712 cf->data[7] = rxerr;
713 }
714 } else if (isr & PASSIVE_ERR_INT) {
715 rcan->can.can_stats.error_passive++;
716 rcan->can.state = CAN_STATE_ERROR_PASSIVE;
717 /* error passive state */
718 cf->can_id |= CAN_ERR_CRTL;
719 cf->data[1] = (txerr > rxerr) ?
720 CAN_ERR_CRTL_TX_WARNING :
721 CAN_ERR_CRTL_RX_WARNING;
722 cf->data[6] = txerr;
723 cf->data[7] = rxerr;
724 }
725
726 if (rcan->can.state >= CAN_STATE_BUS_OFF ||
727 ((sta_reg & 0x20) == 0x20))
728 can_bus_off(ndev);
729
730 stats->rx_packets++;
731 stats->rx_bytes += cf->can_dlc;
732 netif_rx(skb);
733
734 return 0;
735 }
736
rockchip_canfd_interrupt(int irq,void * dev_id)737 static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
738 {
739 struct net_device *ndev = (struct net_device *)dev_id;
740 struct rockchip_canfd *rcan = netdev_priv(ndev);
741 struct net_device_stats *stats = &ndev->stats;
742 u32 err_int = ERR_WARN_INT | RX_BUF_OV_INT | PASSIVE_ERR_INT |
743 TX_LOSTARB_INT | BUS_ERR_INT | BUS_OFF_INT;
744 u32 isr;
745 u32 dlc = 0;
746 u32 quota, work_done = 0;
747
748 isr = rockchip_canfd_read(rcan, CAN_INT);
749 if (isr & TX_FINISH_INT) {
750 //Check whether the interrupt is triggered by TX1
751 //Avoid frame ID misalignment
752 //by forlinx-manic
753 if ((rockchip_canfd_read(rcan, CAN_CMD) & CAN_TX0_REQ) || (rockchip_canfd_read(rcan, CAN_CMD) & CAN_TX1_REQ))
754 {
755 return IRQ_HANDLED;
756 }
757
758 dlc = rockchip_canfd_read(rcan, CAN_TXFIC);
759 /* transmission complete interrupt */
760 if (dlc & FDF_MASK)
761 stats->tx_bytes += can_dlc2len(dlc & DLC_MASK);
762 else
763 stats->tx_bytes += (dlc & DLC_MASK);
764 stats->tx_packets++;
765 if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && dlc & FORMAT_MASK) {
766 cancel_delayed_work(&rcan->tx_err_work);
767 rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, FORMAT_MASK);
768 quota = (rockchip_canfd_read(rcan, CAN_RXFC) &
769 rcan->rx_fifo_mask) >>
770 rcan->rx_fifo_shift;
771 if (quota) {
772 while (work_done < quota)
773 work_done += rockchip_canfd_rx(ndev);
774 }
775 if (rockchip_canfd_read(rcan, CAN_TX_CHECK_FIC) & CAN_TX0_REQ)
776 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
777 rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, 0);
778 }
779 rockchip_canfd_write(rcan, CAN_CMD, 0);
780 can_get_echo_skb(ndev, 0);
781 netif_wake_queue(ndev);
782 can_led_event(ndev, CAN_LED_EVENT_TX);
783 }
784
785 if (isr & RX_FINISH_INT) {
786 quota = (rockchip_canfd_read(rcan, CAN_RXFC) & rcan->rx_fifo_mask) >>
787 rcan->rx_fifo_shift;
788 if (quota) {
789 while (work_done < quota)
790 work_done += rockchip_canfd_rx(ndev);
791 }
792 }
793
794 if (isr & err_int) {
795 /* error interrupt */
796 if (rockchip_canfd_err(ndev, isr))
797 netdev_err(ndev, "can't allocate buffer - clearing pending interrupts\n");
798 }
799
800 rockchip_canfd_write(rcan, CAN_INT, isr);
801 return IRQ_HANDLED;
802 }
803
rockchip_canfd_open(struct net_device * ndev)804 static int rockchip_canfd_open(struct net_device *ndev)
805 {
806 struct rockchip_canfd *rcan = netdev_priv(ndev);
807 int err;
808
809 /* common open */
810 err = open_candev(ndev);
811 if (err)
812 return err;
813
814 err = pm_runtime_get_sync(rcan->dev);
815 if (err < 0) {
816 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
817 __func__, err);
818 goto exit;
819 }
820
821 err = rockchip_canfd_start(ndev);
822 if (err) {
823 netdev_err(ndev, "could not start CAN peripheral\n");
824 goto exit_can_start;
825 }
826
827 can_led_event(ndev, CAN_LED_EVENT_OPEN);
828 netif_start_queue(ndev);
829
830 netdev_dbg(ndev, "%s\n", __func__);
831 return 0;
832
833 exit_can_start:
834 pm_runtime_put(rcan->dev);
835 exit:
836 close_candev(ndev);
837 return err;
838 }
839
rockchip_canfd_close(struct net_device * ndev)840 static int rockchip_canfd_close(struct net_device *ndev)
841 {
842 struct rockchip_canfd *rcan = netdev_priv(ndev);
843
844 netif_stop_queue(ndev);
845 rockchip_canfd_stop(ndev);
846 close_candev(ndev);
847 can_led_event(ndev, CAN_LED_EVENT_STOP);
848 pm_runtime_put(rcan->dev);
849 cancel_delayed_work_sync(&rcan->tx_err_work);
850
851 netdev_dbg(ndev, "%s\n", __func__);
852 return 0;
853 }
854
855 static const struct net_device_ops rockchip_canfd_netdev_ops = {
856 .ndo_open = rockchip_canfd_open,
857 .ndo_stop = rockchip_canfd_close,
858 .ndo_start_xmit = rockchip_canfd_start_xmit,
859 .ndo_change_mtu = can_change_mtu,
860 };
861
862 /**
863 * rockchip_canfd_suspend - Suspend method for the driver
864 * @dev: Address of the device structure
865 *
866 * Put the driver into low power mode.
867 * Return: 0 on success and failure value on error
868 */
rockchip_canfd_suspend(struct device * dev)869 static int __maybe_unused rockchip_canfd_suspend(struct device *dev)
870 {
871 struct net_device *ndev = dev_get_drvdata(dev);
872
873 if (netif_running(ndev)) {
874 netif_stop_queue(ndev);
875 netif_device_detach(ndev);
876 rockchip_canfd_stop(ndev);
877 }
878
879 return pm_runtime_force_suspend(dev);
880 }
881
882 /**
883 * rockchip_canfd_resume - Resume from suspend
884 * @dev: Address of the device structure
885 *
886 * Resume operation after suspend.
887 * Return: 0 on success and failure value on error
888 */
rockchip_canfd_resume(struct device * dev)889 static int __maybe_unused rockchip_canfd_resume(struct device *dev)
890 {
891 struct net_device *ndev = dev_get_drvdata(dev);
892 int ret;
893
894 ret = pm_runtime_force_resume(dev);
895 if (ret) {
896 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
897 return ret;
898 }
899
900 if (netif_running(ndev)) {
901 ret = rockchip_canfd_start(ndev);
902 if (ret) {
903 dev_err(dev, "rockchip_canfd_chip_start failed on resume\n");
904 return ret;
905 }
906
907 netif_device_attach(ndev);
908 netif_start_queue(ndev);
909 }
910
911 return 0;
912 }
913
914 /**
915 * rockchip_canfd_runtime_suspend - Runtime suspend method for the driver
916 * @dev: Address of the device structure
917 *
918 * Put the driver into low power mode.
919 * Return: 0 always
920 */
rockchip_canfd_runtime_suspend(struct device * dev)921 static int __maybe_unused rockchip_canfd_runtime_suspend(struct device *dev)
922 {
923 struct net_device *ndev = dev_get_drvdata(dev);
924 struct rockchip_canfd *rcan = netdev_priv(ndev);
925
926 clk_bulk_disable_unprepare(rcan->num_clks, rcan->clks);
927
928 return 0;
929 }
930
931 /**
932 * rockchip_canfd_runtime_resume - Runtime resume from suspend
933 * @dev: Address of the device structure
934 *
935 * Resume operation after suspend.
936 * Return: 0 on success and failure value on error
937 */
rockchip_canfd_runtime_resume(struct device * dev)938 static int __maybe_unused rockchip_canfd_runtime_resume(struct device *dev)
939 {
940 struct net_device *ndev = dev_get_drvdata(dev);
941 struct rockchip_canfd *rcan = netdev_priv(ndev);
942 int ret;
943
944 ret = clk_bulk_prepare_enable(rcan->num_clks, rcan->clks);
945 if (ret) {
946 dev_err(dev, "Cannot enable clock.\n");
947 return ret;
948 }
949
950 return 0;
951 }
952
953 static const struct dev_pm_ops rockchip_canfd_dev_pm_ops = {
954 SET_SYSTEM_SLEEP_PM_OPS(rockchip_canfd_suspend, rockchip_canfd_resume)
955 SET_RUNTIME_PM_OPS(rockchip_canfd_runtime_suspend,
956 rockchip_canfd_runtime_resume, NULL)
957 };
958
959 static const struct of_device_id rockchip_canfd_of_match[] = {
960 {
961 .compatible = "forlinx,rk3568-can-2.0",
962 .data = (void *)ROCKCHIP_RK3568_CAN_MODE
963 },
964 };
965 MODULE_DEVICE_TABLE(of, rockchip_canfd_of_match);
966
rockchip_canfd_probe(struct platform_device * pdev)967 static int rockchip_canfd_probe(struct platform_device *pdev)
968 {
969 struct net_device *ndev;
970 struct rockchip_canfd *rcan;
971 struct resource *res;
972 void __iomem *addr;
973 int err, irq;
974
975 irq = platform_get_irq(pdev, 0);
976 if (irq < 0) {
977 dev_err(&pdev->dev, "could not get a valid irq\n");
978 return -ENODEV;
979 }
980
981 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 addr = devm_ioremap_resource(&pdev->dev, res);
983 if (IS_ERR(addr))
984 return -EBUSY;
985
986 ndev = alloc_candev(sizeof(struct rockchip_canfd), 1);
987 if (!ndev) {
988 dev_err(&pdev->dev, "could not allocate memory for CANFD device\n");
989 return -ENOMEM;
990 }
991 rcan = netdev_priv(ndev);
992
993 /* register interrupt handler */
994 err = devm_request_irq(&pdev->dev, irq, rockchip_canfd_interrupt,
995 0, ndev->name, ndev);
996 if (err) {
997 dev_err(&pdev->dev, "request_irq err: %d\n", err);
998 return err;
999 }
1000
1001 rcan->reset = devm_reset_control_array_get(&pdev->dev, false, false);
1002 if (IS_ERR(rcan->reset)) {
1003 if (PTR_ERR(rcan->reset) != -EPROBE_DEFER)
1004 dev_err(&pdev->dev, "failed to get canfd reset lines\n");
1005 return PTR_ERR(rcan->reset);
1006 }
1007 rcan->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rcan->clks);
1008 if (rcan->num_clks < 1)
1009 return -ENODEV;
1010
1011 rcan->mode = (unsigned long)of_device_get_match_data(&pdev->dev);
1012
1013 rcan->base = addr;
1014 rcan->can.clock.freq = clk_get_rate(rcan->clks[0].clk);
1015 rcan->dev = &pdev->dev;
1016 rcan->can.state = CAN_STATE_STOPPED;
1017 switch (rcan->mode) {
1018 case ROCKCHIP_CANFD_MODE:
1019 rcan->can.bittiming_const = &rockchip_canfd_bittiming_const;
1020 rcan->can.data_bittiming_const = &rockchip_canfd_data_bittiming_const;
1021 rcan->can.do_set_mode = rockchip_canfd_set_mode;
1022 rcan->can.do_get_berr_counter = rockchip_canfd_get_berr_counter;
1023 rcan->can.do_set_bittiming = rockchip_canfd_set_bittiming;
1024 rcan->can.do_set_data_bittiming = rockchip_canfd_set_bittiming;
1025 rcan->can.ctrlmode = CAN_CTRLMODE_FD;
1026 /* IFI CANFD can do both Bosch FD and ISO FD */
1027 rcan->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1028 CAN_CTRLMODE_FD;
1029 rcan->rx_fifo_shift = RX_FIFO_CNT0_SHIFT;
1030 rcan->rx_fifo_mask = RX_FIFO_CNT0_MASK;
1031 break;
1032 case ROCKCHIP_CAN_MODE:
1033 case ROCKCHIP_RK3568_CAN_MODE:
1034 rcan->can.bittiming_const = &rockchip_canfd_bittiming_const;
1035 rcan->can.do_set_mode = rockchip_canfd_set_mode;
1036 rcan->can.do_get_berr_counter = rockchip_canfd_get_berr_counter;
1037 rcan->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
1038 CAN_CTRLMODE_LISTENONLY |
1039 CAN_CTRLMODE_LOOPBACK |
1040 CAN_CTRLMODE_3_SAMPLES;
1041 rcan->rx_fifo_shift = RX_FIFO_CNT0_SHIFT;
1042 rcan->rx_fifo_mask = RX_FIFO_CNT0_MASK;
1043 break;
1044 default:
1045 return -EINVAL;
1046 }
1047
1048 if (rcan->mode == ROCKCHIP_CAN_MODE) {
1049 rcan->rx_fifo_shift = RX_FIFO_CNT1_SHIFT;
1050 rcan->rx_fifo_mask = RX_FIFO_CNT1_MASK;
1051 }
1052
1053 if (device_property_read_u32_array(&pdev->dev,
1054 "rockchip,tx-invalid-info",
1055 rcan->tx_invalid, 4))
1056 rcan->txtorx = 1;
1057
1058 ndev->netdev_ops = &rockchip_canfd_netdev_ops;
1059 ndev->irq = irq;
1060 ndev->flags |= IFF_ECHO;
1061 rcan->can.restart_ms = 1;
1062
1063 INIT_DELAYED_WORK(&rcan->tx_err_work, rockchip_canfd_tx_err_delay_work);
1064
1065 platform_set_drvdata(pdev, ndev);
1066 SET_NETDEV_DEV(ndev, &pdev->dev);
1067
1068 pm_runtime_enable(&pdev->dev);
1069 err = pm_runtime_get_sync(&pdev->dev);
1070 if (err < 0) {
1071 dev_err(&pdev->dev, "%s: pm_runtime_get failed(%d)\n",
1072 __func__, err);
1073 goto err_pmdisable;
1074 }
1075
1076 err = register_candev(ndev);
1077 if (err) {
1078 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1079 DRV_NAME, err);
1080 goto err_disableclks;
1081 }
1082
1083 devm_can_led_init(ndev);
1084
1085 return 0;
1086
1087 err_disableclks:
1088 pm_runtime_put(&pdev->dev);
1089 err_pmdisable:
1090 pm_runtime_disable(&pdev->dev);
1091 free_candev(ndev);
1092
1093 return err;
1094 }
1095
rockchip_canfd_remove(struct platform_device * pdev)1096 static int rockchip_canfd_remove(struct platform_device *pdev)
1097 {
1098 struct net_device *ndev = platform_get_drvdata(pdev);
1099
1100 unregister_netdev(ndev);
1101 pm_runtime_disable(&pdev->dev);
1102 free_candev(ndev);
1103
1104 return 0;
1105 }
1106
1107 static struct platform_driver rockchip_canfd_driver = {
1108 .driver = {
1109 .name = DRV_NAME,
1110 .pm = &rockchip_canfd_dev_pm_ops,
1111 .of_match_table = rockchip_canfd_of_match,
1112 },
1113 .probe = rockchip_canfd_probe,
1114 .remove = rockchip_canfd_remove,
1115 };
1116 module_platform_driver(rockchip_canfd_driver);
1117
1118 MODULE_AUTHOR("Elaine Zhang <zhangqing@rock-chips.com>");
1119 MODULE_LICENSE("GPL");
1120 MODULE_DESCRIPTION("Rockchip CANFD Drivers");
1121