1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Author:
4 * Chuanhong Guo <gch981213@gmail.com>
5 */
6
7 #include <linux/device.h>
8 #include <linux/kernel.h>
9 #include <linux/mtd/spinand.h>
10
11 #define SPINAND_MFR_GIGADEVICE 0xC8
12
13 #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
14 #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
15
16 #define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
17 #define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
18
19 #define GD5FXGQXXEXXG_REG_STATUS2 0xf0
20
21 #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
22 #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
23 #define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
24 #define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
25
26 static SPINAND_OP_VARIANTS(read_cache_variants,
27 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
28 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
29 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
30 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
31 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
32 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
33
34 static SPINAND_OP_VARIANTS(read_cache_variants_f,
35 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
36 SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
37 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
38 SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
39 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
40 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
41
42 static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
43 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
44 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
45 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
46 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
47 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
48 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
49
50 static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
51 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
52 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
53 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
54 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
55 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
56 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
57
58 static SPINAND_OP_VARIANTS(write_cache_variants,
59 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
60 SPINAND_PROG_LOAD(true, 0, NULL, 0));
61
62 static SPINAND_OP_VARIANTS(update_cache_variants,
63 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
64 SPINAND_PROG_LOAD(false, 0, NULL, 0));
65
gd5fxgq4xa_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)66 static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
67 struct mtd_oob_region *region)
68 {
69 if (section > 3)
70 return -ERANGE;
71
72 region->offset = (16 * section) + 8;
73 region->length = 8;
74
75 return 0;
76 }
77
gd5fxgq4xa_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)78 static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
79 struct mtd_oob_region *region)
80 {
81 if (section > 3)
82 return -ERANGE;
83
84 if (section) {
85 region->offset = 16 * section;
86 region->length = 8;
87 } else {
88 /* section 0 has one byte reserved for bad block mark */
89 region->offset = 1;
90 region->length = 7;
91 }
92 return 0;
93 }
94
95 static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
96 .ecc = gd5fxgq4xa_ooblayout_ecc,
97 .free = gd5fxgq4xa_ooblayout_free,
98 };
99
gd5fxgq4xa_ecc_get_status(struct spinand_device * spinand,u8 status)100 static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
101 u8 status)
102 {
103 switch (status & STATUS_ECC_MASK) {
104 case STATUS_ECC_NO_BITFLIPS:
105 return 0;
106
107 case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
108 /* 1-7 bits are flipped. return the maximum. */
109 return 7;
110
111 case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
112 return 8;
113
114 case STATUS_ECC_UNCOR_ERROR:
115 return -EBADMSG;
116
117 default:
118 break;
119 }
120
121 return -EINVAL;
122 }
123
gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)124 static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
125 struct mtd_oob_region *region)
126 {
127 if (section)
128 return -ERANGE;
129
130 region->offset = 64;
131 region->length = 64;
132
133 return 0;
134 }
135
gd5fxgqx_variant2_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)136 static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
137 struct mtd_oob_region *region)
138 {
139 if (section)
140 return -ERANGE;
141
142 /* Reserve 1 bytes for the BBM. */
143 region->offset = 1;
144 region->length = 63;
145
146 return 0;
147 }
148
149 /* Valid for Q4/Q5 and Q6 (untested) devices */
150 static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
151 .ecc = gd5fxgqx_variant2_ooblayout_ecc,
152 .free = gd5fxgqx_variant2_ooblayout_free,
153 };
154
gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)155 static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
156 struct mtd_oob_region *oobregion)
157 {
158 if (section)
159 return -ERANGE;
160
161 oobregion->offset = 128;
162 oobregion->length = 128;
163
164 return 0;
165 }
166
gd5fxgq4xc_ooblayout_256_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)167 static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
168 struct mtd_oob_region *oobregion)
169 {
170 if (section)
171 return -ERANGE;
172
173 oobregion->offset = 1;
174 oobregion->length = 127;
175
176 return 0;
177 }
178
179 static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
180 .ecc = gd5fxgq4xc_ooblayout_256_ecc,
181 .free = gd5fxgq4xc_ooblayout_256_free,
182 };
183
gd5fxgqx_variant3_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)184 static int gd5fxgqx_variant3_ooblayout_ecc(struct mtd_info *mtd, int section,
185 struct mtd_oob_region *region)
186 {
187 return -ERANGE;
188 }
189
gd5fxgqx_variant3_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)190 static int gd5fxgqx_variant3_ooblayout_free(struct mtd_info *mtd, int section,
191 struct mtd_oob_region *region)
192 {
193 if (section)
194 return -ERANGE;
195
196 /* Reserve 1 bytes for the BBM. */
197 region->offset = 1;
198 region->length = 63;
199
200 return 0;
201 }
202
203 static const struct mtd_ooblayout_ops gd5fxgqx_variant3_ooblayout = {
204 .ecc = gd5fxgqx_variant3_ooblayout_ecc,
205 .free = gd5fxgqx_variant3_ooblayout_free,
206 };
207
gd5fxgq4uexxg_ecc_get_status(struct spinand_device * spinand,u8 status)208 static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
209 u8 status)
210 {
211 u8 status2;
212 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
213 &status2);
214 int ret;
215
216 switch (status & STATUS_ECC_MASK) {
217 case STATUS_ECC_NO_BITFLIPS:
218 return 0;
219
220 case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
221 /*
222 * Read status2 register to determine a more fine grained
223 * bit error status
224 */
225 ret = spi_mem_exec_op(spinand->spimem, &op);
226 if (ret)
227 return ret;
228
229 /*
230 * 4 ... 7 bits are flipped (1..4 can't be detected, so
231 * report the maximum of 4 in this case
232 */
233 /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
234 return ((status & STATUS_ECC_MASK) >> 2) |
235 ((status2 & STATUS_ECC_MASK) >> 4);
236
237 case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
238 return 8;
239
240 case STATUS_ECC_UNCOR_ERROR:
241 return -EBADMSG;
242
243 default:
244 break;
245 }
246
247 return -EINVAL;
248 }
249
gd5fxgq5xexxg_ecc_get_status(struct spinand_device * spinand,u8 status)250 static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
251 u8 status)
252 {
253 u8 status2;
254 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
255 &status2);
256 int ret;
257
258 switch (status & STATUS_ECC_MASK) {
259 case STATUS_ECC_NO_BITFLIPS:
260 return 0;
261
262 case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
263 /*
264 * Read status2 register to determine a more fine grained
265 * bit error status
266 */
267 ret = spi_mem_exec_op(spinand->spimem, &op);
268 if (ret)
269 return ret;
270
271 /*
272 * 1 ... 4 bits are flipped (and corrected)
273 */
274 /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
275 return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
276
277 case STATUS_ECC_UNCOR_ERROR:
278 return -EBADMSG;
279
280 default:
281 break;
282 }
283
284 return -EINVAL;
285 }
286
gd5fxgq4ufxxg_ecc_get_status(struct spinand_device * spinand,u8 status)287 static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
288 u8 status)
289 {
290 switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
291 case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
292 return 0;
293
294 case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
295 return 3;
296
297 case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
298 return -EBADMSG;
299
300 default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
301 return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
302 }
303
304 return -EINVAL;
305 }
306
307 static const struct spinand_info gigadevice_spinand_table[] = {
308 SPINAND_INFO("GD5F1GQ4xA",
309 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
310 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
311 NAND_ECCREQ(8, 512),
312 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
313 &write_cache_variants,
314 &update_cache_variants),
315 SPINAND_HAS_QE_BIT,
316 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
317 gd5fxgq4xa_ecc_get_status)),
318 SPINAND_INFO("GD5F2GQ4xA",
319 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
320 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
321 NAND_ECCREQ(8, 512),
322 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
323 &write_cache_variants,
324 &update_cache_variants),
325 SPINAND_HAS_QE_BIT,
326 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
327 gd5fxgq4xa_ecc_get_status)),
328 SPINAND_INFO("GD5F4GQ4xA",
329 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
330 NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
331 NAND_ECCREQ(8, 512),
332 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
333 &write_cache_variants,
334 &update_cache_variants),
335 SPINAND_HAS_QE_BIT,
336 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
337 gd5fxgq4xa_ecc_get_status)),
338 SPINAND_INFO("GD5F4GQ4RC",
339 SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68),
340 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
341 NAND_ECCREQ(8, 512),
342 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
343 &write_cache_variants,
344 &update_cache_variants),
345 SPINAND_HAS_QE_BIT,
346 SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
347 gd5fxgq4ufxxg_ecc_get_status)),
348 SPINAND_INFO("GD5F4GQ4UC",
349 SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68),
350 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
351 NAND_ECCREQ(8, 512),
352 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
353 &write_cache_variants,
354 &update_cache_variants),
355 SPINAND_HAS_QE_BIT,
356 SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
357 gd5fxgq4ufxxg_ecc_get_status)),
358 SPINAND_INFO("GD5F1GQ4UExxG",
359 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
360 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
361 NAND_ECCREQ(8, 512),
362 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
363 &write_cache_variants,
364 &update_cache_variants),
365 SPINAND_HAS_QE_BIT,
366 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
367 gd5fxgq4uexxg_ecc_get_status)),
368 SPINAND_INFO("GD5F1GQ4RExxG",
369 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
370 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
371 NAND_ECCREQ(8, 512),
372 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
373 &write_cache_variants,
374 &update_cache_variants),
375 SPINAND_HAS_QE_BIT,
376 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
377 gd5fxgq4uexxg_ecc_get_status)),
378 SPINAND_INFO("GD5F2GQ4UExxG",
379 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
380 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
381 NAND_ECCREQ(8, 512),
382 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
383 &write_cache_variants,
384 &update_cache_variants),
385 SPINAND_HAS_QE_BIT,
386 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
387 gd5fxgq4uexxg_ecc_get_status)),
388 SPINAND_INFO("GD5F2GQ4RExxG",
389 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
390 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
391 NAND_ECCREQ(8, 512),
392 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
393 &write_cache_variants,
394 &update_cache_variants),
395 SPINAND_HAS_QE_BIT,
396 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
397 gd5fxgq4uexxg_ecc_get_status)),
398 SPINAND_INFO("GD5F1GQ4UFxxG",
399 SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
400 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
401 NAND_ECCREQ(8, 512),
402 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
403 &write_cache_variants,
404 &update_cache_variants),
405 SPINAND_HAS_QE_BIT,
406 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
407 gd5fxgq4ufxxg_ecc_get_status)),
408 SPINAND_INFO("GD5F1GQ5UExxG",
409 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
410 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
411 NAND_ECCREQ(4, 512),
412 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
413 &write_cache_variants,
414 &update_cache_variants),
415 SPINAND_HAS_QE_BIT,
416 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
417 gd5fxgq5xexxg_ecc_get_status)),
418 SPINAND_INFO("GD5F1GQ5RExxG",
419 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
420 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
421 NAND_ECCREQ(4, 512),
422 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
423 &write_cache_variants,
424 &update_cache_variants),
425 SPINAND_HAS_QE_BIT,
426 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
427 gd5fxgq5xexxg_ecc_get_status)),
428 SPINAND_INFO("GD5F2GQ5UExxG",
429 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
430 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
431 NAND_ECCREQ(4, 512),
432 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
433 &write_cache_variants,
434 &update_cache_variants),
435 SPINAND_HAS_QE_BIT,
436 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
437 gd5fxgq5xexxg_ecc_get_status)),
438 SPINAND_INFO("GD5F2GQ5RExxG",
439 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
440 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
441 NAND_ECCREQ(4, 512),
442 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
443 &write_cache_variants,
444 &update_cache_variants),
445 SPINAND_HAS_QE_BIT,
446 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
447 gd5fxgq5xexxg_ecc_get_status)),
448 SPINAND_INFO("GD5F4GQ6UExxG",
449 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
450 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
451 NAND_ECCREQ(4, 512),
452 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
453 &write_cache_variants,
454 &update_cache_variants),
455 SPINAND_HAS_QE_BIT,
456 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
457 gd5fxgq5xexxg_ecc_get_status)),
458 SPINAND_INFO("GD5F4GQ6RExxG",
459 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
460 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
461 NAND_ECCREQ(4, 512),
462 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
463 &write_cache_variants,
464 &update_cache_variants),
465 SPINAND_HAS_QE_BIT,
466 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
467 gd5fxgq5xexxg_ecc_get_status)),
468 SPINAND_INFO("GD5F1GM7UExxG",
469 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
470 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
471 NAND_ECCREQ(8, 512),
472 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
473 &write_cache_variants,
474 &update_cache_variants),
475 SPINAND_HAS_QE_BIT,
476 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
477 gd5fxgq4uexxg_ecc_get_status)),
478 SPINAND_INFO("GD5F1GM7RExxG",
479 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
480 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
481 NAND_ECCREQ(8, 512),
482 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
483 &write_cache_variants,
484 &update_cache_variants),
485 SPINAND_HAS_QE_BIT,
486 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
487 gd5fxgq4uexxg_ecc_get_status)),
488 SPINAND_INFO("GD5F2GM7UExxG",
489 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
490 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
491 NAND_ECCREQ(8, 512),
492 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
493 &write_cache_variants,
494 &update_cache_variants),
495 SPINAND_HAS_QE_BIT,
496 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
497 gd5fxgq4uexxg_ecc_get_status)),
498 SPINAND_INFO("GD5F2GM7RExxG",
499 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
500 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
501 NAND_ECCREQ(8, 512),
502 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
503 &write_cache_variants,
504 &update_cache_variants),
505 SPINAND_HAS_QE_BIT,
506 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
507 gd5fxgq4uexxg_ecc_get_status)),
508 SPINAND_INFO("GD5F4GM8UExxG",
509 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
510 NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
511 NAND_ECCREQ(8, 512),
512 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
513 &write_cache_variants,
514 &update_cache_variants),
515 SPINAND_HAS_QE_BIT,
516 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
517 gd5fxgq4uexxg_ecc_get_status)),
518 SPINAND_INFO("GD5F4GM8RExxG",
519 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
520 NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
521 NAND_ECCREQ(8, 512),
522 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
523 &write_cache_variants,
524 &update_cache_variants),
525 SPINAND_HAS_QE_BIT,
526 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
527 gd5fxgq4uexxg_ecc_get_status)),
528 SPINAND_INFO("GD5F1GQ4UExxH",
529 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd9),
530 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
531 NAND_ECCREQ(8, 512),
532 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
533 &write_cache_variants,
534 &update_cache_variants),
535 SPINAND_HAS_QE_BIT,
536 SPINAND_ECCINFO(&gd5fxgqx_variant3_ooblayout,
537 gd5fxgq4xa_ecc_get_status)),
538 };
539
540 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
541 };
542
543 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
544 .id = SPINAND_MFR_GIGADEVICE,
545 .name = "GigaDevice",
546 .chips = gigadevice_spinand_table,
547 .nchips = ARRAY_SIZE(gigadevice_spinand_table),
548 .ops = &gigadevice_spinand_manuf_ops,
549 };
550