1 /*
2 * Driver for Rockchip TSP Controller
3 *
4 * Copyright (C) 2012-2016 ROCKCHIP, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/err.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/io.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/gpio.h>
29 #include <linux/of.h>
30 #include <linux/of_gpio.h>
31 #include <linux/miscdevice.h>
32 #include <linux/slab.h>
33 #include <linux/highmem.h>
34 #include <linux/dvb/ca.h>
35 #include <linux/of_device.h>
36 #include <linux/iopoll.h>
37
38 #include <linux/rockchip/cpu.h>
39 #include <linux/rockchip/grf.h>
40 #include <linux/rockchip/cpu.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/regmap.h>
43 #include <linux/rk_tsp_api.h>
44 #include "rockchip_tsp.h"
45
46 #define MODE_NAME "rockchip-tsp"
47
48 #ifdef RK_TSP_DEBUG
49 #define TSP_DEBUG(x...) pr_info(x)
50 #else
51 #define TSP_DEBUG(x...)
52 #endif
53
54 /* if HZ=300, 3.3ms per */
55 #define TIME_CNT_PER_SECOND HZ
56
57 #define TSP_TIMEOUT_US 1000
58 #define PACKET_SIZE (188)
59
60 /* 132.2M bps max */
61 #define TS_CYC_BUF_LEN ((PACKET_SIZE * 300 * 300) / HZ)
62
63 /* 66.1M bps max */
64 #define TS_CYC_BUF_LEN_PSI ((PACKET_SIZE * 150 * 300) / HZ)
65 #define SECTION_CYC_BUF_LEN ((1024 * 24 * 300) / HZ)
66
67 #define TSP_TIMER_DELAY (HZ / TIME_CNT_PER_SECOND)
68 #define TSP_CW_ORDER_NUM_SEL 0
69 #define TSP_LLP_LEN (1024 * 4)
70
71 static struct tsp_dev *tdev;
72
73 static void rockchip_ts_filter_config(struct tsp_dev *dev,
74 struct tsp_ctx *ctx);
75 static void rockchip_demux_dma_config(struct tsp_dev *dev,
76 struct tsp_ctx *ctx);
77 static void rockchip_enable_pid_irq(struct tsp_dev *dev, int id);
78 static void rockchip_sec_filter_config(struct tsp_dev *dev,
79 struct tsp_ctx *tctx);
grf_field_write(struct tsp_dev * dev,enum grf_fields id,unsigned int val)80 static void grf_field_write(struct tsp_dev *dev, enum grf_fields id,
81 unsigned int val)
82 {
83 const u32 field = dev->pdata->grf_reg_fields[id];
84 u16 reg;
85 u8 msb, lsb;
86
87 if (!field)
88 return;
89
90 reg = (field >> 16) & 0xffff;
91 lsb = (field >> 8) & 0xff;
92 msb = (field >> 0) & 0xff;
93
94 regmap_write(dev->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
95 }
96
rockchip_tsp_clk_enable(struct tsp_dev * dev)97 static int rockchip_tsp_clk_enable(struct tsp_dev *dev)
98 {
99 if (clk_prepare_enable(dev->tsp_aclk)) {
100 pr_err("Couldn't enable clock 'aclk'\n");
101 return -ENOENT;
102 }
103
104 if (clk_prepare_enable(dev->tsp_clk)) {
105 pr_err("Couldn't enable clock 'clk'\n");
106 return -ENOENT;
107 }
108 clk_set_rate(dev->tsp_clk, 150 * 1000 * 1000);
109
110 if (clk_prepare_enable(dev->tsp_hclk)) {
111 pr_err("Couldn't enable clock 'hclk'\n");
112 clk_disable_unprepare(dev->tsp_hclk);
113 return -ENOENT;
114 }
115 clk_set_rate(dev->tsp_hclk, 150 * 1000 * 1000);
116
117 return 0;
118 }
119
rockchip_tsp_clk_disable(struct tsp_dev * dev)120 static void rockchip_tsp_clk_disable(struct tsp_dev *dev)
121 {
122 clk_disable_unprepare(dev->tsp_hclk);
123 clk_disable_unprepare(dev->tsp_clk);
124 clk_disable_unprepare(dev->tsp_aclk);
125 }
126
TSP_RD(struct tsp_dev * dev,uint reg)127 static uint TSP_RD(struct tsp_dev *dev, uint reg)
128 {
129 uint val;
130
131 val = __raw_readl(((dev)->ioaddr + (reg)));
132
133 return val;
134 }
135
TSP_WR(struct tsp_dev * dev,uint reg,uint val)136 static void TSP_WR(struct tsp_dev *dev, uint reg, uint val)
137 {
138 __raw_writel((val), ((dev)->ioaddr + (reg)));
139 }
140
rockchip_tsp_clear_interrupt(struct tsp_dev * dev)141 static void rockchip_tsp_clear_interrupt(struct tsp_dev *dev)
142 {
143 uint reg_val = 0;
144
145 reg_val = TSP_RD(dev, PTI0_DMA_STS);
146 TSP_WR(dev, PTI0_DMA_STS, reg_val);
147 reg_val = TSP_RD(dev, PTI0_PID_STS0);
148 TSP_WR(dev, PTI0_PID_STS0, reg_val);
149 reg_val = TSP_RD(dev, PTI0_PID_STS1);
150 TSP_WR(dev, PTI0_PID_STS1, reg_val);
151 reg_val = TSP_RD(dev, PTI0_PID_STS2);
152 TSP_WR(dev, PTI0_PID_STS2, reg_val);
153 reg_val = TSP_RD(dev, PTI0_PID_STS3);
154 TSP_WR(dev, PTI0_PID_STS3, reg_val);
155 }
156
rockchip_tsp_reset_all_channel(struct tsp_dev * dev)157 static void rockchip_tsp_reset_all_channel(struct tsp_dev *dev)
158 {
159 int i;
160 uint reg_val = 0;
161 int ret;
162
163 for (i = 0; i < 64; i++) {
164 /* pid channel clear */
165 TSP_WR(dev, PTI0_PID0_CTRL + 4 * i, 1 << 1);
166
167 ret = readl_poll_timeout(dev->ioaddr + PTI0_PID0_CTRL + 4 * i,
168 reg_val, !(reg_val & 0x03), 100,
169 TSP_TIMEOUT_US);
170 if (ret)
171 dev_err(dev->dev, "failed to clear pid channel\n");
172 }
173 }
174
rockchip_tsp_reset_one_channel(struct tsp_dev * dev,int id)175 static void rockchip_tsp_reset_one_channel(struct tsp_dev *dev, int id)
176 {
177 uint reg_val = 0;
178 int ret;
179
180 /* pid channel clear */
181 TSP_WR(dev, PTI0_PID0_CTRL + 4 * id, 1 << 1);
182 if (id < 64 && id >= 0) {
183 ret = readl_poll_timeout(dev->ioaddr + PTI0_PID0_CTRL + 4 * id,
184 reg_val, !(reg_val & 0x03), 100,
185 TSP_TIMEOUT_US);
186 if (ret)
187 dev_err(dev->dev, "failed to clear pid channel\n");
188 }
189 }
190
rockchip_tsp_soft_reset(struct tsp_dev * dev)191 static void rockchip_tsp_soft_reset(struct tsp_dev *dev)
192 {
193 uint reg_val = 0;
194 int ret;
195
196 /* pti0 soft reset */
197 TSP_WR(dev, PTI0_CTRL, 1);
198
199 ret = readl_poll_timeout(dev->ioaddr + PTI0_CTRL,
200 reg_val, !(reg_val & 0x01), 100,
201 TSP_TIMEOUT_US);
202 if (ret)
203 dev_err(dev->dev, "failed to reset pti0\n");
204 }
205
rockchip_tsp_gcfg(struct tsp_dev * dev)206 static void rockchip_tsp_gcfg(struct tsp_dev *dev)
207 {
208 int reg_val = 0;
209
210 reg_val |= ((4 << 4) | 0x01);
211 TSP_WR(dev, TSP_GCFG, reg_val);
212 }
213
rockchip_tsp_grf_config(struct tsp_dev * dev)214 static void rockchip_tsp_grf_config(struct tsp_dev *dev)
215 {
216 if (dev->pdata->soc_type == RK312X) {
217 grf_field_write(dev, TSP_D0, 1);
218 grf_field_write(dev, TSP_D1, 1);
219 grf_field_write(dev, TSP_D2, 1);
220 grf_field_write(dev, TSP_D3, 1);
221 grf_field_write(dev, TSP_D4, 1);
222 grf_field_write(dev, TSP_D5M0, 1);
223 grf_field_write(dev, TSP_D6M0, 1);
224 grf_field_write(dev, TSP_D7M0, 1);
225 grf_field_write(dev, TSP_SYNCM0, 1);
226 grf_field_write(dev, TSP_FAIL, 1);
227 grf_field_write(dev, TSP_VALID, 1);
228 grf_field_write(dev, TSP_CLK, 1);
229 } else if (dev->pdata->soc_type == RK3328) {
230 grf_field_write(dev, TSP_SYNCM1, 3);
231 grf_field_write(dev, TSP_IO_GROUP_SEL, 1);
232 }
233 }
234
rockchip_tsp_hsadc_config(struct tsp_dev * dev)235 static int rockchip_tsp_hsadc_config(struct tsp_dev *dev)
236 {
237 uint reg_ctrl = 0;
238
239 if (dev->serial_parallel_mode == 0) {
240 reg_ctrl = 1 << 21 | 0 << 19 | 0 << 18 | 2 << 16 |
241 1 << 13 | SERIAL_SYNC_VALID_MODE |
242 TSI_SEL | 3 << 4 | 3 << 1;
243 } else {
244 reg_ctrl = 0 << 19 | 0 << 18 | 2 << 16 |
245 1 << 13 | PARALLEL_SYNC_VALID_MODE |
246 TSI_SEL | 3 << 4 | 3 << 1;
247 }
248
249 TSP_WR(dev, PTI0_CTRL, reg_ctrl);
250
251 return 0;
252 }
253
rockchip_tsp_init(struct tsp_dev * dev)254 static void rockchip_tsp_init(struct tsp_dev *dev)
255 {
256 rockchip_tsp_gcfg(dev);
257 rockchip_tsp_clear_interrupt(dev);
258 rockchip_tsp_reset_all_channel(dev);
259 rockchip_tsp_soft_reset(dev);
260 rockchip_tsp_grf_config(dev);
261 rockchip_tsp_hsadc_config(dev);
262 mutex_init(&dev->ts_mutex);
263 dev->tsp_start_descram = 0;
264 }
265
rockchip_find_next_package(const u8 * buf,size_t count)266 static inline int rockchip_find_next_package(const u8 *buf, size_t count)
267 {
268 int pos = 0;
269
270 while (pos < count) {
271 if (buf[pos] == 0x47 &&
272 buf[pos + 188] == 0x47 &&
273 buf[pos + 188 + 188] == 0x47)
274 break;
275
276 pos++;
277 }
278
279 return pos;
280 }
281
rockchip_feed_sec_buf(struct tsp_dev * dev)282 static void rockchip_feed_sec_buf(struct tsp_dev *dev)
283 {
284 struct tsp_ctx *ctx, *ctx_temp;
285 unsigned long flags;
286 uint data_len, data_len_head, data_len_tail;
287 uint phy_base, phy_write;
288 u8 *write_addr, *read_addr, *top_addr, *base_addr;
289 int index, pid;
290 int temp;
291 int offset;
292
293 spin_lock_irqsave(&dev->list_lock, flags);
294 list_for_each_entry_safe(ctx, ctx_temp, &dev->pid_list, pid_list) {
295 index = ctx->index;
296 read_addr = ctx->read;
297 top_addr = ctx->top;
298 base_addr = ctx->base;
299 pid = ctx->pid;
300 temp = PTI0_PID0_WRITE + index * 16;
301 phy_write = TSP_RD(dev, temp);
302 temp = PTI0_PID0_BASE + index * 16;
303 phy_base = TSP_RD(dev, temp);
304
305 /* get virtual write address */
306 offset = phy_write - phy_base;
307 write_addr = base_addr + offset;
308
309 if (write_addr > top_addr || write_addr < base_addr)
310 dev_err(dev->dev, "%s:%d, write addr is error!",
311 __func__, __LINE__);
312
313 if (read_addr > top_addr || read_addr < base_addr)
314 dev_err(dev->dev, "%s:%d, read addr is error!",
315 __func__, __LINE__);
316
317 if (ctx->filter_type == TSP_SECTION_FILTER) {
318 u32 ctrl_val, cfg_val;
319
320 ctrl_val = TSP_RD(dev, PTI0_PID0_CTRL + 4 * index);
321 if (!(ctrl_val & 0x01))
322 pr_err("PID0_CTRL is error:0x%x, channel id=%d\n",
323 ctrl_val, index);
324
325 cfg_val = TSP_RD(dev, PTI0_PID0_CFG + 20 * index);
326 if (cfg_val == 0)
327 pr_err("PID0_CFG is error:0x%x, channel_id=%d\n",
328 cfg_val, index);
329
330 if ((!(ctrl_val & 0x01)) || cfg_val == 0)
331 rockchip_sec_filter_config(dev, ctx);
332
333 if (write_addr > read_addr) {
334 data_len = write_addr - read_addr;
335 ctx->get_data_callback(read_addr,
336 data_len, pid);
337 read_addr += data_len;
338 } else if (write_addr < read_addr) {
339 data_len_tail = top_addr - read_addr;
340
341 ctx->get_data_callback(read_addr,
342 data_len_tail, pid);
343
344 data_len_head = write_addr - base_addr;
345
346 ctx->get_data_callback(base_addr,
347 data_len_head, pid);
348 read_addr = base_addr + data_len_head;
349 }
350 }
351 ctx->read = read_addr;
352 }
353 spin_unlock_irqrestore(&dev->list_lock, flags);
354 }
355
356 #define GET_PACKET_SYNC_FROM_DMX
rockchip_handle_ts_data(struct tsp_ctx * ctx)357 static u8 *rockchip_handle_ts_data(struct tsp_ctx *ctx)
358 {
359 int data_len;
360 u8 *read_addr = ctx->read;
361 u8 *write_addr = ctx->write;
362
363 data_len = write_addr - read_addr;
364
365 #ifdef GET_PACKET_SYNC_FROM_DMX
366 if (data_len > 0)
367 ctx->get_data_callback(read_addr, data_len, ctx->pid);
368
369 read_addr = write_addr;
370 #else
371 if (data_len >= PACKET_SIZE && read_addr[0] == 0x47) {
372 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
373 ctx->get_data_callback(read_addr, data_len, ctx->pid);
374 read_addr += data_len;
375 } else {
376 uint pos;
377
378 pos = rockchip_find_next_package(read_addr, data_len);
379 if (pos < data_len) {
380 read_addr += pos;
381 data_len -= pos;
382 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
383 ctx->get_data_callback(read_addr, data_len, ctx->pid);
384 read_addr += data_len;
385 } else {
386 read_addr += data_len;
387 }
388 }
389 #endif
390
391 return read_addr;
392 }
393
rockchip_handle_ts_tail(struct tsp_ctx * ctx)394 static u8 *rockchip_handle_ts_tail(struct tsp_ctx *ctx)
395 {
396 int data_len;
397 u8 *base_addr = ctx->base;
398 u8 *top_addr = ctx->top;
399 u8 *read_addr = ctx->read;
400
401 data_len = top_addr - read_addr;
402 #ifdef GET_PACKET_SYNC_FROM_DMX
403 if (data_len > 0)
404 ctx->get_data_callback(read_addr, data_len, ctx->pid);
405
406 read_addr = base_addr;
407 #else
408 if (data_len >= PACKET_SIZE && read_addr[0] == 0x47) {
409 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
410 ctx->get_data_callback(read_addr, data_len, ctx->pid);
411 read_addr += data_len;
412 } else if (data_len > PACKET_SIZE * 3) {
413 uint pos;
414
415 pos = rockchip_find_next_package(read_addr, data_len);
416 if (pos < data_len) {
417 read_addr += pos;
418 data_len -= pos;
419 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
420
421 ctx->get_data_callback(read_addr, data_len, ctx->pid);
422 read_addr += data_len;
423 } else {
424 read_addr += data_len;
425 }
426 }
427 #endif
428
429 return read_addr;
430 }
431
rockchip_handle_ts_head(struct tsp_ctx * ctx)432 static u8 *rockchip_handle_ts_head(struct tsp_ctx *ctx)
433 {
434 int data_len;
435 u8 *read_addr;
436 u8 *base_addr = ctx->base;
437 u8 *write_addr = ctx->write;
438
439 data_len = write_addr - base_addr;
440 #ifdef GET_PACKET_SYNC_FROM_DMX
441 if (data_len > 0)
442 ctx->get_data_callback(base_addr, data_len, ctx->pid);
443
444 read_addr = write_addr;
445 #else
446 if (data_len >= PACKET_SIZE && base_addr[0] == 0x47) {
447 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
448
449 ctx->get_data_callback(base_addr, data_len, ctx->pid);
450 read_addr = base_addr;
451 read_addr += data_len;
452 } else if (data_len > PACKET_SIZE * 3) {
453 uint pos;
454
455 pos = rockchip_find_next_package(base_addr, data_len);
456 if (pos < data_len) {
457 read_addr = base_addr + pos;
458 data_len -= pos;
459 data_len = (data_len / PACKET_SIZE) * PACKET_SIZE;
460 ctx->get_data_callback(read_addr, data_len, ctx->pid);
461 read_addr += data_len;
462 } else {
463 read_addr = base_addr + data_len;
464 }
465 } else {
466 /* data_len_head == 0 */
467 read_addr = base_addr;
468 }
469 #endif
470
471 return read_addr;
472 }
473
rockchip_tsp_reset_regs(struct tsp_dev * dev)474 void rockchip_tsp_reset_regs(struct tsp_dev *dev)
475 {
476 unsigned long flags;
477 struct tsp_ctx *ctx, *ctx_temp;
478
479 rockchip_tsp_clear_interrupt(dev);
480 rockchip_tsp_soft_reset(dev);
481
482 rockchip_tsp_gcfg(dev);
483 rockchip_tsp_grf_config(dev);
484 rockchip_tsp_hsadc_config(dev);
485
486 spin_lock_irqsave(&dev->list_lock, flags);
487 list_for_each_entry_safe(ctx, ctx_temp, &dev->pid_list, pid_list) {
488 if (ctx->base)
489 memset(ctx->base, 0, ctx->buf_len);
490
491 if (ctx->filter_type == TSP_TS_FILTER) {
492 rockchip_demux_dma_config(dev, ctx);
493 rockchip_ts_filter_config(dev, ctx);
494 } else if (ctx->filter_type == TSP_SECTION_FILTER) {
495 rockchip_demux_dma_config(dev, ctx);
496 rockchip_sec_filter_config(dev, ctx);
497 rockchip_enable_pid_irq(dev, ctx->index);
498 }
499 }
500 spin_unlock_irqrestore(&dev->list_lock, flags);
501 }
502
rockchip_feed_ts_buf(struct tsp_dev * dev)503 static void rockchip_feed_ts_buf(struct tsp_dev *dev)
504 {
505 struct tsp_ctx *ctx, *ctx_temp;
506 int id;
507 int temp;
508 u32 phy_base, phy_write;
509 int offset;
510 u32 ctrl_val, cfg_val, state_val, erro_state_occur;
511 unsigned long flags;
512 #ifdef TSP_DESCRAM_TIMER_CHECK
513 int tsp_live_no_data_interval = 1;
514 #endif
515 static int tsp_normal_no_data_interval;
516
517 spin_lock_irqsave(&dev->list_lock, flags);
518 list_for_each_entry_safe(ctx, ctx_temp, &dev->pid_list, pid_list) {
519 id = ctx->index;
520 temp = PTI0_PID0_WRITE + id * 16;
521 phy_write = TSP_RD(dev, temp);
522 temp = PTI0_PID0_BASE + id * 16;
523 phy_base = TSP_RD(dev, temp);
524
525 /* get virtual write address */
526 offset = phy_write - phy_base;
527 ctx->write = ctx->base + offset;
528
529 if (ctx->write > ctx->top || ctx->write < ctx->base) {
530 pr_err("%s:%d, write addr is error!",
531 __func__, __LINE__);
532 continue;
533 }
534 if (ctx->read > ctx->top || ctx->read < ctx->base) {
535 pr_err("%s:%d, read addr is error!",
536 __func__, __LINE__);
537 continue;
538 }
539
540 /*ts*/
541 if (ctx->filter_type == TSP_TS_FILTER) {
542 ctrl_val = TSP_RD(dev, PTI0_PID0_CTRL + 4 * id);
543 if (!(ctrl_val & 0x01))
544 pr_err("CTRL is error: 0x%x, channel id = %d\n",
545 ctrl_val, id);
546 cfg_val = TSP_RD(dev, PTI0_PID0_CFG + 20 * id);
547 if ((cfg_val & 0x30) != 0x30)
548 pr_err("CFG is error: 0x%x, channel id = %d\n",
549 cfg_val, id);
550
551 erro_state_occur = 0;
552 if ((!(ctrl_val & 0x01)) || ((cfg_val & 0x30) != 0x30))
553 erro_state_occur = 1;
554
555 if (id < 32) {
556 state_val = TSP_RD(dev, PTI0_PID_STS2);
557 if (state_val & (1 << id)) {
558 erro_state_occur = 1;
559 pr_err("err channel id = %d\n", id);
560 state_val |= (1 << id);
561 TSP_WR(dev, PTI0_PID_STS2, state_val);
562 }
563 } else {
564 state_val = TSP_RD(dev, PTI0_PID_STS3);
565 if (state_val & (1 << (id - 32))) {
566 erro_state_occur = 1;
567 pr_err("err channel id = %d\n", id);
568 state_val |= (1 << (id - 32));
569 TSP_WR(dev, PTI0_PID_STS3, state_val);
570 }
571 }
572
573 if (erro_state_occur != 0) {
574 spin_unlock_irqrestore(&dev->list_lock, flags);
575 goto error;
576 }
577
578 if (ctx->write > ctx->read) {
579 #ifdef TSP_DESCRAM_TIMER_CHECK
580 tsp_live_no_data_interval = 0;
581 #endif
582 tsp_normal_no_data_interval = 0;
583 ctx->read = (u8 *)rockchip_handle_ts_data(ctx);
584 } else if (ctx->write < ctx->read) {
585 #ifdef TSP_DESCRAM_TIMER_CHECK
586 tsp_live_no_data_interval = 0;
587 #endif
588 tsp_normal_no_data_interval = 0;
589 /* tail */
590 ctx->read = rockchip_handle_ts_tail(ctx);
591
592 /* head */
593 ctx->read = rockchip_handle_ts_head(ctx);
594 }
595 }
596 }
597 spin_unlock_irqrestore(&dev->list_lock, flags);
598
599 #ifdef TSP_DESCRAM_TIMER_CHECK
600 if (tsp_live_no_data_interval != 0 &&
601 dev->tsp_start_descram != 0) {
602 goto error;
603 }
604
605 if (tsp_normal_no_data_interval++ > TIME_CNT_PER_SECOND &&
606 dev->tsp_start_descram == 0) {
607 tsp_normal_no_data_interval = 0;
608 goto error;
609 }
610 #else
611 if (tsp_normal_no_data_interval++ > TIME_CNT_PER_SECOND) {
612 tsp_normal_no_data_interval = 0;
613 goto error;
614 }
615 #endif
616
617 return;
618 error:
619 rockchip_tsp_reset_regs(dev);
620 }
621
rockchip_tsp_interrupt(int irq,void * dev_id)622 static irqreturn_t rockchip_tsp_interrupt(int irq, void *dev_id)
623 {
624 uint reg_val;
625 struct platform_device *pdev = dev_id;
626 struct tsp_dev *dev = platform_get_drvdata(pdev);
627
628 if (irq == dev->tsp_irq) {
629 reg_val = TSP_RD(dev, PTI0_PID_STS0);
630 if (reg_val != 0) {
631 TSP_WR(dev, PTI0_PID_STS0, reg_val);
632 queue_work(dev->sec_queue, &dev->sec_work);
633 }
634
635 reg_val = TSP_RD(dev, PTI0_PID_STS1);
636 if (reg_val != 0) {
637 TSP_WR(dev, PTI0_PID_STS1, reg_val);
638 queue_work(dev->sec_queue, &dev->sec_work);
639 }
640
641 reg_val = TSP_RD(dev, PTI0_DMA_STS);
642 if (reg_val & 0x03)
643 TSP_WR(dev, PTI0_DMA_STS, reg_val);
644 }
645
646 return IRQ_HANDLED;
647 }
648
rockchip_ts_work(struct work_struct * work)649 static void rockchip_ts_work(struct work_struct *work)
650 {
651 struct tsp_dev *dev;
652
653 dev = container_of(work, struct tsp_dev, ts_work);
654
655 mutex_lock(&dev->ts_mutex);
656 rockchip_feed_ts_buf(dev);
657 mutex_unlock(&dev->ts_mutex);
658 }
659
rockchip_ts_timer_handler(unsigned long data)660 static void rockchip_ts_timer_handler(unsigned long data)
661 {
662 struct tsp_dev *dev = (struct tsp_dev *)data;
663
664 queue_work(dev->ts_queue, &dev->ts_work);
665 mod_timer(&dev->timer, jiffies + TSP_TIMER_DELAY);
666 }
667
rockchip_ts_timer(struct tsp_dev * dev)668 static void rockchip_ts_timer(struct tsp_dev *dev)
669 {
670 dev->ts_queue = create_workqueue("ts_wqueue");
671 INIT_WORK(&dev->ts_work, rockchip_ts_work);
672
673 /* Register timer */
674 setup_timer(&dev->timer, rockchip_ts_timer_handler,
675 (unsigned long)dev);
676 mod_timer(&dev->timer, jiffies + TSP_TIMER_DELAY);
677 }
678
rockchip_sec_work(struct work_struct * work)679 static void rockchip_sec_work(struct work_struct *work)
680 {
681 struct tsp_dev *dev;
682
683 dev = container_of(work, struct tsp_dev, sec_work);
684
685 mutex_lock(&dev->ts_mutex);
686 rockchip_feed_sec_buf(dev);
687 mutex_unlock(&dev->ts_mutex);
688 }
689
rockchip_sec_queue(struct tsp_dev * dev)690 static void rockchip_sec_queue(struct tsp_dev *dev)
691 {
692 dev->sec_queue = create_workqueue("sec_wqueue");
693 INIT_WORK(&dev->sec_work, rockchip_sec_work);
694 }
695
rockchip_demux_dma_config(struct tsp_dev * dev,struct tsp_ctx * ctx)696 static void rockchip_demux_dma_config(struct tsp_dev *dev,
697 struct tsp_ctx *ctx)
698 {
699 u32 id = ctx->index;
700 u32 dlen = ctx->buf_len;
701 u32 dma_buf = ctx->dma_buf;
702
703 TSP_WR(dev, PTI0_PID0_BASE + id * 16, dma_buf);
704 TSP_WR(dev, PTI0_PID0_TOP + id * 16, dma_buf + dlen);
705 TSP_WR(dev, PTI0_PID0_READ + id * 16, dma_buf);
706 TSP_WR(dev, PTI0_PID0_WRITE + id * 16, dma_buf);
707 }
708
rockchip_demux_alloc(struct tsp_dev * dev,struct tsp_ctx * tctx)709 static int rockchip_demux_alloc(struct tsp_dev *dev, struct tsp_ctx *tctx)
710 {
711 int count = 3;
712
713 while (count--) {
714 tctx->base = dma_alloc_writecombine(dev->dev, tctx->buf_len,
715 &tctx->dma_buf, GFP_KERNEL);
716 if (tctx->base) {
717 memset(tctx->base, 0, tctx->buf_len);
718 break;
719 }
720 }
721
722 if (!tctx->base) {
723 pr_err("%s:%d, alloc cyc buf fail!!\n", __func__, __LINE__);
724 return -ENOMEM;
725 }
726 tctx->top = tctx->base + tctx->buf_len;
727 tctx->write = tctx->base;
728 tctx->read = tctx->base;
729 return 0;
730 }
731
rockchip_demux_free(struct tsp_dev * dev,struct tsp_ctx * ctx)732 static void rockchip_demux_free(struct tsp_dev *dev, struct tsp_ctx *ctx)
733 {
734 if (ctx->base) {
735 dma_free_writecombine(dev->dev, ctx->buf_len,
736 ctx->base, ctx->dma_buf);
737 ctx->base = NULL;
738 }
739 }
740
rockchip_ts_filter_config(struct tsp_dev * dev,struct tsp_ctx * ctx)741 static void rockchip_ts_filter_config(struct tsp_dev *dev, struct tsp_ctx *ctx)
742 {
743 int pid = ctx->pid;
744 u32 id = ctx->index;
745 u32 reg_val;
746 u32 ctrl_reg;
747
748 TSP_WR(dev, PTI0_PID0_CTRL + 4 * id, pid << 3 | 0 << 2 | 1);
749 TSP_WR(dev, PTI0_PID0_CFG + 20 * id, 3 << 4);
750
751 /* cw order num & descram on */
752 reg_val = TSP_RD(dev, PTI0_PID0_CTRL + 4 * id);
753 ctrl_reg = reg_val | (TSP_CW_ORDER_NUM_SEL << 16) | (0 << 2);
754 TSP_WR(dev, PTI0_PID0_CTRL + 4 * id, ctrl_reg);
755 }
756
rockchip_sec_filter_config(struct tsp_dev * dev,struct tsp_ctx * tctx)757 static void rockchip_sec_filter_config(struct tsp_dev *dev,
758 struct tsp_ctx *tctx)
759 {
760 int pid = tctx->pid;
761 u32 id = tctx->index;
762 u32 cfg = 0;
763 u32 filter0 = 0;
764 u32 filter1 = 0;
765 u8 byte0 = tctx->filter_byte[0];
766 u8 byte3 = tctx->filter_byte[3];
767 u8 byte4 = tctx->filter_byte[4];
768 u8 byte5 = tctx->filter_byte[5];
769 u8 byte6 = tctx->filter_byte[6];
770 u8 byte7 = tctx->filter_byte[7];
771 int use_hardware_filter = 0;
772
773 if (use_hardware_filter != 0) {
774 if (tctx->filter_mask[0] == 0xFF) {
775 cfg |= (1 << 16);
776 filter0 |= byte0;
777 }
778
779 if (tctx->filter_mask[3] == 0xFF) {
780 cfg |= (1 << 17);
781 filter0 |= (byte3 << 8);
782 }
783
784 if (tctx->filter_mask[4] == 0xFF) {
785 cfg |= (1 << 18);
786 filter0 |= (byte4 << 16);
787 }
788
789 if (tctx->filter_mask[5] == 0xFF) {
790 cfg |= (1 << 19);
791 filter0 |= byte5 << 24;
792 }
793
794 if (tctx->filter_mask[6] == 0xFF) {
795 cfg |= (1 << 20);
796 filter1 |= byte6;
797 }
798
799 if (tctx->filter_mask[7] == 0xFF) {
800 cfg |= (1 << 21);
801 filter1 |= byte7 << 8;
802 }
803 }
804
805 cfg |= (2 << 8);
806
807 TSP_WR(dev, PTI0_PID0_CTRL + 4 * id, pid << 3 | 1);
808 TSP_WR(dev, PTI0_PID0_CFG + 20 * id, cfg);
809 TSP_WR(dev, PTI0_PID0_FILT_0 + 20 * id, filter0);
810 TSP_WR(dev, PTI0_PID0_FILT_1 + 20 * id, filter1);
811 TSP_WR(dev, PTI0_PID0_FILT_2 + 20 * id, 0);
812 TSP_WR(dev, PTI0_PID0_FILT_3 + 20 * id, 0);
813 }
814
rockchip_enable_pid_irq(struct tsp_dev * dev,int id)815 static void rockchip_enable_pid_irq(struct tsp_dev *dev, int id)
816 {
817 u32 val;
818
819 if (id < 32) {
820 val = TSP_RD(dev, PTI0_PID_INT_ENA0);
821 TSP_WR(dev, PTI0_PID_INT_ENA0, val | (1 << id));
822 val = TSP_RD(dev, PTI0_PID_INT_ENA2);
823 TSP_WR(dev, PTI0_PID_INT_ENA2, val | (1 << id));
824
825 } else {
826 val = TSP_RD(dev, PTI0_PID_INT_ENA1);
827 TSP_WR(dev, PTI0_PID_INT_ENA1, val | (1 << (id - 32)));
828 val = TSP_RD(dev, PTI0_PID_INT_ENA3);
829 TSP_WR(dev, PTI0_PID_INT_ENA3, val | (1 << (id - 32)));
830 }
831 }
832
rockchip_init_pid_list(struct tsp_dev * dev)833 static void rockchip_init_pid_list(struct tsp_dev *dev)
834 {
835 INIT_LIST_HEAD(&dev->pid_list);
836 spin_lock_init(&dev->list_lock);
837 }
838
rockchip_exit_pid_list(struct tsp_dev * dev)839 static void rockchip_exit_pid_list(struct tsp_dev *dev)
840 {
841 struct tsp_ctx *ctx, *ctx_temp;
842 unsigned long flags;
843
844 spin_lock_irqsave(&dev->list_lock, flags);
845 list_for_each_entry_safe(ctx, ctx_temp,
846 &dev->pid_list, pid_list) {
847 list_del(&ctx->pid_list);
848 rockchip_tsp_reset_one_channel(dev, ctx->index);
849 rockchip_demux_free(dev, ctx);
850 kfree(ctx);
851 ctx = NULL;
852 }
853 spin_unlock_irqrestore(&dev->list_lock, flags);
854 }
855
rockchip_tsp_open(void)856 int rockchip_tsp_open(void)
857 {
858 int ret = 0;
859 struct tsp_dev *dev = tdev;
860
861 if (dev->is_open != 0)
862 return 0;
863
864 dev->is_open = 1;
865
866 rockchip_tsp_clk_enable(dev);
867 rockchip_init_pid_list(dev);
868 rockchip_tsp_init(dev);
869 rockchip_ts_timer(dev);
870 rockchip_sec_queue(dev);
871
872 return ret;
873 }
874
rockchip_tsp_close(void)875 int rockchip_tsp_close(void)
876 {
877 struct tsp_dev *dev = tdev;
878
879 if (dev->is_open == 0)
880 return 0;
881
882 del_timer_sync(&dev->timer);
883 rockchip_tsp_clear_interrupt(dev);
884 rockchip_tsp_reset_all_channel(dev);
885 rockchip_tsp_soft_reset(dev);
886 rockchip_tsp_clk_disable(dev);
887
888 if (dev->ts_queue) {
889 destroy_workqueue(dev->ts_queue);
890 dev->ts_queue = NULL;
891 }
892
893 if (dev->sec_queue) {
894 destroy_workqueue(dev->sec_queue);
895 dev->sec_queue = NULL;
896 }
897
898 rockchip_exit_pid_list(dev);
899 dev->is_open = 0;
900
901 return 0;
902 }
903
rockchip_tsp_stop_channel(struct rockchip_tsp_channel_info * info)904 void rockchip_tsp_stop_channel(struct rockchip_tsp_channel_info *info)
905 {
906 int pid, index;
907 unsigned long flags;
908 struct tsp_ctx *ctx, *ctx_temp, *ctx_to_free[64];
909 struct tsp_dev *dev = tdev;
910 int i = 0, cnt = 0;
911
912 for (i = 0; i < 64; i++)
913 ctx_to_free[i] = NULL;
914
915 if (info->pid > 0x1FFF || info->index >= 64)
916 return;
917
918 mutex_lock(&dev->ts_mutex);
919 pid = info->pid;
920 index = info->index;
921 rockchip_tsp_reset_one_channel(dev, index);
922
923 spin_lock_irqsave(&dev->list_lock, flags);
924 list_for_each_entry_safe(ctx, ctx_temp,
925 &dev->pid_list, pid_list) {
926 if (ctx->pid == pid && ctx->index == index) {
927 list_del(&ctx->pid_list);
928 ctx_to_free[cnt] = ctx;
929 cnt++;
930 }
931 }
932 spin_unlock_irqrestore(&dev->list_lock, flags);
933
934 for (i = 0; i < 64; i++) {
935 if (ctx_to_free[i]) {
936 rockchip_demux_free(dev, ctx_to_free[i]);
937 kfree(ctx_to_free[i]);
938 ctx_to_free[i] = NULL;
939 }
940 }
941 mutex_unlock(&dev->ts_mutex);
942 }
943
rockchip_tsp_start_channel(struct rockchip_tsp_channel_info * info)944 int rockchip_tsp_start_channel(struct rockchip_tsp_channel_info *info)
945 {
946 struct tsp_ctx *ctx;
947 struct tsp_dev *dev = tdev;
948 unsigned long flags;
949 int ret = 0;
950 int type;
951
952 if (!info) {
953 pr_err("channel_info is null!!\n");
954 return -ENODEV;
955 }
956
957 if (info->pid > 0x1FFF || info->index >= 64)
958 return -EINVAL;
959
960 mutex_lock(&dev->ts_mutex);
961 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
962 if (!ctx) {
963 ret = -ENOMEM;
964 goto out;
965 }
966 ctx->pid = info->pid;
967 ctx->index = info->index;
968 ctx->get_data_callback = info->get_data_callback;
969 type = info->type;
970
971 if (type == TSP_DMX_TYPE_TS) {
972 ctx->filter_type = TSP_TS_FILTER;
973 if (info->type == TSP_DMX_TYPE_SEC)
974 ctx->buf_len = TS_CYC_BUF_LEN_PSI;
975 else
976 ctx->buf_len = TS_CYC_BUF_LEN;
977
978 ret = rockchip_demux_alloc(dev, ctx);
979 if (ret)
980 goto out;
981
982 rockchip_demux_dma_config(dev, ctx);
983 rockchip_ts_filter_config(dev, ctx);
984 spin_lock_irqsave(&dev->list_lock, flags);
985 list_add(&ctx->pid_list, &dev->pid_list);
986 spin_unlock_irqrestore(&dev->list_lock, flags);
987 } else if (type == TSP_DMX_TYPE_SEC) {
988 ctx->filter_type = TSP_SECTION_FILTER;
989 ctx->buf_len = SECTION_CYC_BUF_LEN;
990 memcpy(ctx->filter_byte, info->filter_value,
991 TSP_DMX_FILTER_SIZE);
992 memcpy(ctx->filter_mask, info->filter_mask,
993 TSP_DMX_FILTER_SIZE);
994
995 ret = rockchip_demux_alloc(dev, ctx);
996 if (ret)
997 goto out;
998
999 rockchip_demux_dma_config(dev, ctx);
1000 rockchip_sec_filter_config(dev, ctx);
1001 rockchip_enable_pid_irq(dev, ctx->index);
1002 spin_lock_irqsave(&dev->list_lock, flags);
1003 list_add(&ctx->pid_list, &dev->pid_list);
1004 spin_unlock_irqrestore(&dev->list_lock, flags);
1005 }
1006
1007 out:
1008 if (ret)
1009 kfree(ctx);
1010 mutex_unlock(&dev->ts_mutex);
1011 return ret;
1012 }
1013
rockchip_tsp_probe(struct platform_device * pdev)1014 static int rockchip_tsp_probe(struct platform_device *pdev)
1015 {
1016 int err = -ENODEV;
1017 struct tsp_dev *pdata;
1018 struct device *dev = &pdev->dev;
1019 struct resource *res;
1020 struct device_node *np = dev->of_node;
1021
1022 /* get I/O memory resource */
1023 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1024 if (!res) {
1025 dev_err(dev, "failed to get I/O memory resource\n");
1026 return -ENODEV;
1027 }
1028
1029 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1030 if (!pdata)
1031 return -ENOMEM;
1032
1033 /* request I/O memory */
1034 if (!devm_request_mem_region(dev, res->start,
1035 resource_size(res), pdev->name)) {
1036 dev_err(dev, "request I/O memory fial\n");
1037 return -EBUSY;
1038 }
1039 pdata->ioaddr = devm_ioremap(dev, res->start, resource_size(res));
1040
1041 pdata->tsp_aclk = clk_get(dev, "aclk_tsp");
1042 if (IS_ERR(pdata->tsp_aclk)) {
1043 dev_err(dev, "failed to find tsp aclk source\n");
1044 err = PTR_ERR(pdata->tsp_aclk);
1045 return err;
1046 }
1047
1048 pdata->tsp_hclk = clk_get(dev, "hclk_tsp");
1049 if (IS_ERR(pdata->tsp_hclk)) {
1050 dev_err(dev, "failed to find tsp hclk source\n");
1051 err = PTR_ERR(pdata->tsp_hclk);
1052 return err;
1053 }
1054
1055 pdata->tsp_clk = clk_get(dev, "clk_tsp");
1056 if (IS_ERR(pdata->tsp_clk)) {
1057 dev_err(dev, "failed to find tsp clk source\n");
1058 err = PTR_ERR(pdata->tsp_clk);
1059 return err;
1060 }
1061
1062 pdata->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1063 if (IS_ERR(pdata->grf)) {
1064 pdata->grf = NULL;
1065 dev_err(dev, "failed to find tsp grf base.\n");
1066 }
1067
1068 pdata->tsp_irq = platform_get_irq_byname(pdev, "irq_tsp");
1069 if (pdata->tsp_irq < 0) {
1070 err = pdata->tsp_irq;
1071 dev_warn(dev, "tsp interrupt is not available.\n");
1072 return err;
1073 }
1074
1075 err = devm_request_irq(dev, pdata->tsp_irq,
1076 rockchip_tsp_interrupt,
1077 IRQF_SHARED, pdev->name, pdev);
1078 if (err < 0) {
1079 dev_warn(dev, "tsp interrupt is not available.\n");
1080 return err;
1081 }
1082
1083 of_property_read_u32(dev->of_node, "serial_parallel_mode",
1084 &pdata->serial_parallel_mode);
1085
1086 pdata->dev = dev;
1087 pdata->pdata = of_device_get_match_data(dev);
1088 platform_set_drvdata(pdev, pdata);
1089 tdev = pdata;
1090 tdev->is_open = 0;
1091
1092 dev_info(dev, "rk tsp driver registered\n");
1093
1094 return 0;
1095 }
1096
rockchip_tsp_remove(struct platform_device * pdev)1097 static int rockchip_tsp_remove(struct platform_device *pdev)
1098 {
1099 struct tsp_dev *pdata = platform_get_drvdata(pdev);
1100
1101 if (!pdata)
1102 return -ENODEV;
1103
1104 tdev = NULL;
1105 platform_set_drvdata(pdev, NULL);
1106 return 0;
1107 }
1108
1109 #ifdef CONFIG_OF
1110 static const u32 rk312x_grf_reg_fields[MAX_FIELDS] = {
1111 [TSP_D0] = GRF_REG_FIELD(0xec, 0, 0),
1112 [TSP_D1] = GRF_REG_FIELD(0xec, 2, 2),
1113 [TSP_D2] = GRF_REG_FIELD(0xec, 4, 4),
1114 [TSP_D3] = GRF_REG_FIELD(0xec, 6, 6),
1115 [TSP_D4] = GRF_REG_FIELD(0xec, 8, 8),
1116 [TSP_D5M0] = GRF_REG_FIELD(0xec, 10, 10),
1117 [TSP_D6M0] = GRF_REG_FIELD(0xec, 12, 12),
1118 [TSP_D7M0] = GRF_REG_FIELD(0xec, 14, 14),
1119 [TSP_SYNCM0] = GRF_REG_FIELD(0xf0, 0, 0),
1120 [TSP_FAIL] = GRF_REG_FIELD(0xf0, 2, 2),
1121 [TSP_VALID] = GRF_REG_FIELD(0xf0, 4, 4),
1122 [TSP_CLK] = GRF_REG_FIELD(0xf0, 6, 6),
1123 };
1124
1125 static const struct rockchip_tsp_plat_data rk312x_socdata = {
1126 .soc_type = RK312X,
1127 .grf_reg_fields = rk312x_grf_reg_fields,
1128 };
1129
1130 static const u32 rk3228_grf_reg_fields[MAX_FIELDS] = {
1131 };
1132
1133 static const struct rockchip_tsp_plat_data rk3228_socdata = {
1134 .soc_type = RK3228,
1135 .grf_reg_fields = rk3228_grf_reg_fields,
1136 };
1137
1138 static const u32 rk3328_grf_reg_fields[MAX_FIELDS] = {
1139 [TSP_SYNCM1] = GRF_REG_FIELD(0x28, 0, 2),
1140 [TSP_IO_GROUP_SEL] = GRF_REG_FIELD(0x50, 8, 8),
1141 };
1142
1143 static const struct rockchip_tsp_plat_data rk3328_socdata = {
1144 .soc_type = RK3328,
1145 .grf_reg_fields = rk3328_grf_reg_fields,
1146 };
1147
1148 static const struct of_device_id rockchip_tsp_dt_match[] = {
1149 { .compatible = "rockchip,rk312x-tsp", .data = &rk312x_socdata, },
1150 { .compatible = "rockchip,rk3228-tsp", .data = &rk3228_socdata, },
1151 { .compatible = "rockchip,rk3328-tsp", .data = &rk3328_socdata, },
1152 { },
1153 };
1154 MODULE_DEVICE_TABLE(of, rockchip_tsp_dt_match);
1155 #endif /* CONFIG_OF */
1156
1157 static struct platform_driver rk_tsp_driver = {
1158 .probe = rockchip_tsp_probe,
1159 .remove = rockchip_tsp_remove,
1160 .driver = {
1161 .name = MODE_NAME,
1162 .of_match_table = of_match_ptr(rockchip_tsp_dt_match),
1163 },
1164 };
1165
rockchip_tsp_mod_init(void)1166 static int __init rockchip_tsp_mod_init(void)
1167 {
1168 return platform_driver_register(&rk_tsp_driver);
1169 }
1170
rockchip_tsp_mod_exit(void)1171 static void __exit rockchip_tsp_mod_exit(void)
1172 {
1173 platform_driver_unregister(&rk_tsp_driver);
1174 }
1175
1176 subsys_initcall(rockchip_tsp_mod_init);
1177 module_exit(rockchip_tsp_mod_exit);
1178
1179 MODULE_DESCRIPTION("Rockchip Transport Stream Processing hw support.");
1180 MODULE_LICENSE("GPL v2");
1181 MODULE_AUTHOR("Jerry Xu <xbl@rock-chips.com>");
1182 MODULE_ALIAS("platform:" MODE_NAME);
1183