1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/pm_runtime.h>
7 #include <linux/slab.h>
8 #include <media/v4l2-common.h>
9 #include <media/v4l2-event.h>
10 #include <media/v4l2-fh.h>
11 #include <media/v4l2-ioctl.h>
12 #include <media/v4l2-mc.h>
13 #include <media/v4l2-subdev.h>
14 #include <media/videobuf2-dma-contig.h>
15 #include <media/videobuf2-dma-sg.h>
16 #include <linux/rk-isp1-config.h>
17
18 #include "dev.h"
19 #include "regs.h"
20
set_y_addr(struct rkispp_stream * stream,u32 val)21 static void set_y_addr(struct rkispp_stream *stream, u32 val)
22 {
23 rkispp_write(stream->isppdev, stream->config->reg.cur_y_base, val);
24 }
25
set_uv_addr(struct rkispp_stream * stream,u32 val)26 static void set_uv_addr(struct rkispp_stream *stream, u32 val)
27 {
28 rkispp_write(stream->isppdev, stream->config->reg.cur_uv_base, val);
29 }
30
31
update_mi(struct rkispp_stream * stream)32 static void update_mi(struct rkispp_stream *stream)
33 {
34 struct rkispp_device *dev = stream->isppdev;
35 struct rkispp_dummy_buffer *dummy_buf;
36 u32 val;
37
38 if (stream->curr_buf) {
39 val = stream->curr_buf->buff_addr[RKISPP_PLANE_Y];
40 set_y_addr(stream, val);
41 val = stream->curr_buf->buff_addr[RKISPP_PLANE_UV];
42 set_uv_addr(stream, val);
43 }
44
45 if (stream->type == STREAM_OUTPUT && !stream->curr_buf) {
46 dummy_buf = &dev->hw_dev->dummy_buf;
47 set_y_addr(stream, dummy_buf->dma_addr);
48 set_uv_addr(stream, dummy_buf->dma_addr);
49 }
50
51 v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
52 "%s stream:%d Y:0x%x UV:0x%x\n",
53 __func__, stream->id,
54 rkispp_read(dev, stream->config->reg.cur_y_base),
55 rkispp_read(dev, stream->config->reg.cur_uv_base));
56 }
57
config_fec(struct rkispp_device * dev)58 static int config_fec(struct rkispp_device *dev)
59 {
60 struct rkispp_params_vdev *params_vdev = &dev->params_vdev[PARAM_VDEV_FEC];
61 struct rkispp_stream_vdev *vdev;
62 struct rkispp_stream *stream = NULL;
63 struct rkispp_fec_head *fec_data;
64 struct rkispp_hw_dev *hw = dev->hw_dev;
65 u32 fmt, mult = 1, mesh_size;
66 u32 in_width, in_height;
67 u32 addr_offs, max_w, max_h;
68 u32 addryf, addrxf, addryi, addrxi;
69
70 vdev = &dev->stream_vdev;
71 vdev->fec.is_end = true;
72 if (!(vdev->module_ens & ISPP_MODULE_FEC))
73 return 0;
74
75 if (dev->inp == INP_DDR) {
76 stream = &vdev->stream[STREAM_II];
77 fmt = stream->out_cap_fmt.wr_fmt;
78 } else {
79 fmt = FMT_YUV422;
80 }
81
82 in_width = dev->ispp_sdev.in_fmt.width;
83 in_height = dev->ispp_sdev.in_fmt.height;
84 max_w = hw->max_in.w ? hw->max_in.w : in_width;
85 max_h = hw->max_in.h ? hw->max_in.h : in_height;
86 addr_offs = max_w * max_h;
87 vdev->fec.uv_offset = addr_offs;
88
89 if (stream) {
90 stream->config->frame_end_id = FEC_INT;
91 stream->config->reg.cur_y_base = RKISPP_FEC_RD_Y_BASE;
92 stream->config->reg.cur_uv_base = RKISPP_FEC_RD_UV_BASE;
93 stream->config->reg.cur_y_base_shd = RKISPP_FEC_RD_Y_BASE_SHD;
94 stream->config->reg.cur_uv_base_shd = RKISPP_FEC_RD_UV_BASE_SHD;
95 }
96
97
98 if (fmt & FMT_YUYV)
99 mult = 2;
100 rkispp_set_bits(dev, RKISPP_FEC_CTRL, FMT_RD_MASK, fmt);
101
102 rkispp_write(dev, RKISPP_FEC_RD_VIR_STRIDE, ALIGN(in_width * mult, 16) >> 2);
103 rkispp_write(dev, RKISPP_FEC_SRC_SIZE, in_height << 16 | in_width);
104
105 fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[0].vaddr;
106 if (fec_data) {
107 rkispp_prepare_buffer(dev, ¶ms_vdev->buf_fec[0]);
108 addrxf = params_vdev->buf_fec[0].dma_addr + fec_data->meshxf_oft;
109 addryf = params_vdev->buf_fec[0].dma_addr + fec_data->meshyf_oft;
110 addrxi = params_vdev->buf_fec[0].dma_addr + fec_data->meshxi_oft;
111 addryi = params_vdev->buf_fec[0].dma_addr + fec_data->meshyi_oft;
112 rkispp_write(dev, RKISPP_FEC_MESH_XFRA_BASE, addrxf);
113 rkispp_write(dev, RKISPP_FEC_MESH_YFRA_BASE, addryf);
114 rkispp_write(dev, RKISPP_FEC_MESH_XINT_BASE, addrxi);
115 rkispp_write(dev, RKISPP_FEC_MESH_YINT_BASE, addryi);
116
117 stream = &vdev->stream[STREAM_MB];
118 if (stream->out_fmt.width > 1920) {
119 mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 1);
120 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, SW_MESH_DENSITY);
121 } else {
122 mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 0);
123 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, 0);
124 }
125 rkispp_write(dev, RKISPP_FEC_MESH_SIZE, mesh_size);
126 }
127
128 stream = &vdev->stream[STREAM_MB];
129 if (!stream->streaming) {
130 rkispp_write(dev, RKISPP_FEC_WR_Y_BASE, hw->dummy_buf.dma_addr);
131 rkispp_write(dev, RKISPP_FEC_WR_UV_BASE, hw->dummy_buf.dma_addr);
132 }
133
134 if (vdev->monitor.is_en) {
135 init_completion(&vdev->monitor.fec.cmpl);
136 schedule_work(&vdev->monitor.fec.work);
137 }
138 rkispp_set_clk_rate(dev->hw_dev->clks[0], dev->hw_dev->core_clk_max);
139 v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
140 "%s size:%dx%d ctrl:0x%x core_ctrl:0x%x\n",
141 __func__, in_width, in_height,
142 rkispp_read(dev, RKISPP_FEC_CTRL),
143 rkispp_read(dev, RKISPP_FEC_CORE_CTRL));
144 return 0;
145 }
146
fec_free_buf(struct rkispp_device * dev)147 static void fec_free_buf(struct rkispp_device *dev)
148 {
149 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
150 struct list_head *list = &vdev->fec.list_rd;
151 struct rkisp_ispp_buf *dbufs;
152
153 if (vdev->fec.cur_rd)
154 vdev->fec.cur_rd = NULL;
155 while (!list_empty(list)) {
156 dbufs = get_list_buf(list, true);
157 if (dbufs->is_isp)
158 v4l2_subdev_call(dev->ispp_sdev.remote_sd,
159 video, s_rx_buffer, dbufs, NULL);
160 else
161 get_list_buf(list, false);
162 }
163 }
164
config_modules(struct rkispp_device * dev)165 static int config_modules(struct rkispp_device *dev)
166 {
167 struct rkispp_params_vdev *params_vdev;
168 int ret;
169
170 v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
171 "stream module ens:0x%x\n", dev->stream_vdev.module_ens);
172 dev->stream_vdev.monitor.monitoring_module = 0;
173 dev->stream_vdev.monitor.restart_module = 0;
174 dev->stream_vdev.monitor.is_restart = false;
175 dev->stream_vdev.monitor.retry = 0;
176 init_completion(&dev->stream_vdev.monitor.cmpl);
177
178 ret = config_fec(dev);
179 if (ret < 0)
180 goto free_fec;
181
182 /* config default params */
183 params_vdev = &dev->params_vdev[PARAM_VDEV_FEC];
184 params_vdev->params_ops->rkispp_params_cfg(params_vdev, 0);
185
186 return 0;
187 free_fec:
188 fec_free_buf(dev);
189 return ret;
190 }
191
fec_work_event(struct rkispp_device * dev,void * buff_rd,bool is_isr,bool is_quick)192 static void fec_work_event(struct rkispp_device *dev,
193 void *buff_rd,
194 bool is_isr, bool is_quick)
195 {
196 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
197 struct rkispp_monitor *monitor = &vdev->monitor;
198 struct list_head *list = &vdev->fec.list_rd;
199 void __iomem *base = dev->hw_dev->base_addr;
200 struct rkispp_stream *stream = &vdev->stream[STREAM_II];
201 unsigned long lock_flags = 0, lock_flags1 = 0;
202 bool is_start = false;
203 struct rkisp_ispp_reg *reg_buf = NULL;
204 struct rkispp_buffer *inbuf;
205 struct v4l2_subdev *sd = NULL;
206 u32 val;
207 struct rkisp_ispp_buf *buf_rd = buff_rd;
208
209 if (!(vdev->module_ens & ISPP_MODULE_FEC))
210 return;
211 if (dev->inp == INP_ISP)
212 sd = dev->ispp_sdev.remote_sd;
213 spin_lock_irqsave(&vdev->fec.buf_lock, lock_flags);
214 /* event from fec frame end */
215 if (!buf_rd && is_isr) {
216 vdev->fec.is_end = true;
217 if (vdev->fec.cur_rd) {
218 if (sd) {
219 v4l2_subdev_call(sd, video, s_rx_buffer, vdev->fec.cur_rd, NULL);
220 } else if (stream->streaming && vdev->fec.cur_rd->priv) {
221 inbuf = vdev->fec.cur_rd->priv;
222 vb2_buffer_done(&inbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
223 }
224 vdev->fec.cur_rd = NULL;
225 }
226 }
227 spin_lock_irqsave(&monitor->lock, lock_flags1);
228 if (monitor->is_restart && buf_rd) {
229 list_add_tail(&buf_rd->list, list);
230 goto restart_unlock;
231 }
232
233 if (buf_rd && vdev->fec.is_end && list_empty(list)) {
234 /* fec read buf from nr */
235 vdev->fec.cur_rd = buf_rd;
236 } else if (vdev->fec.is_end && !list_empty(list)) {
237 /* fec read buf from list
238 * fec processing slow than nr
239 * new read buf from nr into list
240 */
241 vdev->fec.cur_rd = get_list_buf(list, true);
242 if (buf_rd)
243 list_add_tail(&buf_rd->list, list);
244 } else if (!vdev->fec.is_end && buf_rd) {
245 /* fec no idle
246 * new read buf from nr into list
247 */
248 list_add_tail(&buf_rd->list, list);
249 }
250
251 if (vdev->fec.cur_rd && vdev->fec.is_end) {
252 if (vdev->fec.cur_rd->priv) {
253 inbuf = vdev->fec.cur_rd->priv;
254 val = inbuf->buff_addr[RKISPP_PLANE_Y];
255 rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
256 val = inbuf->buff_addr[RKISPP_PLANE_UV];
257 rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
258 } else {
259 struct rkispp_isp_buf_pool *buf;
260
261 buf = get_pool_buf(dev, vdev->fec.cur_rd);
262 val = buf->dma[GROUP_BUF_PIC];
263 rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
264 val += vdev->fec.uv_offset;
265 rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
266 }
267 is_start = true;
268 }
269
270 if (is_start) {
271 u32 seq = 0;
272 u64 timestamp = 0;
273
274 if (vdev->fec.cur_rd) {
275 seq = vdev->fec.cur_rd->frame_id;
276 timestamp = vdev->fec.cur_rd->frame_timestamp;
277 dev->ispp_sdev.frm_sync_seq = seq;
278 dev->ispp_sdev.frame_timestamp = timestamp;
279 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x00, SW_FEC_EN);
280 }
281
282 stream = &vdev->stream[STREAM_MB];
283 if (stream->streaming && !stream->is_cfg)
284 secure_config_mb(stream);
285
286 if (!dev->hw_dev->is_single)
287 rkispp_update_regs(dev, RKISPP_CTRL, RKISPP_FEC_SRC_SIZE);
288 writel(FEC_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
289
290 v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
291 "FEC start seq:%d | Y_SHD rd:0x%x\n",
292 seq, readl(base + RKISPP_FEC_RD_Y_BASE_SHD));
293 v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
294 "%s stream:%d Y:0x%x UV:0x%x\n",
295 __func__, stream->id,
296 rkispp_read(dev, stream->config->reg.cur_y_base),
297 rkispp_read(dev, stream->config->reg.cur_uv_base));
298 vdev->fec.dbg.id = seq;
299 vdev->fec.dbg.timestamp = ktime_get_ns();
300 if (monitor->is_en) {
301 monitor->fec.time = vdev->fec.dbg.interval / 1000 / 1000;
302 monitor->monitoring_module |= MONITOR_FEC;
303 if (!completion_done(&monitor->fec.cmpl))
304 complete(&monitor->fec.cmpl);
305 }
306
307 if (stream->is_reg_withstream)
308 rkispp_find_regbuf_by_id(dev, ®_buf, dev->dev_id, seq);
309
310 if (!dev->hw_dev->is_shutdown)
311 writel(FEC_ST, base + RKISPP_CTRL_STRT);
312
313 vdev->fec.is_end = false;
314 }
315 restart_unlock:
316 spin_unlock_irqrestore(&monitor->lock, lock_flags1);
317 spin_unlock_irqrestore(&vdev->fec.buf_lock, lock_flags);
318
319 }
320
rkispp_module_work_event(struct rkispp_device * dev,void * buf_rd,void * buf_wr,u32 module,bool is_isr)321 static void rkispp_module_work_event(struct rkispp_device *dev,
322 void *buf_rd, void *buf_wr,
323 u32 module, bool is_isr)
324 {
325
326 if (dev->hw_dev->is_shutdown)
327 return;
328
329 if (dev->ispp_sdev.state != ISPP_STOP)
330 fec_work_event(dev, buf_rd, is_isr, false);
331
332 /* cur frame (tnr->nr->fec) done for next frame
333 * fec start at nr end if fec enable, and fec can async with
334 * tnr different frames for single device.
335 * tnr->nr->fec frame0
336 * |->tnr->nr->fec frame1
337 */
338 if (is_isr && !buf_rd && !buf_wr) {
339 dev->stream_vdev.monitor.retry = 0;
340 rkispp_event_handle(dev, CMD_QUEUE_DMABUF, NULL);
341
342 }
343
344 if (dev->ispp_sdev.state == ISPP_STOP) {
345 if ((module & ISPP_MODULE_FEC) && buf_rd) {
346 struct rkisp_ispp_buf *buf = buf_rd;
347
348 if (buf->is_isp)
349 v4l2_subdev_call(dev->ispp_sdev.remote_sd,
350 video, s_rx_buffer, buf, NULL);
351 }
352 if (!dev->hw_dev->is_idle)
353 dev->hw_dev->is_idle = true;
354 }
355 }
356
rkispp_destroy_buf(struct rkispp_stream * stream)357 static void rkispp_destroy_buf(struct rkispp_stream *stream)
358 {
359 struct rkispp_device *dev = stream->isppdev;
360 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
361
362 if (atomic_read(&vdev->refcnt) == 1) {
363 vdev->irq_ends = 0;
364 fec_free_buf(dev);
365 rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
366 }
367 }
368
start_isp(struct rkispp_device * dev)369 static int start_isp(struct rkispp_device *dev)
370 {
371 struct rkispp_subdev *ispp_sdev = &dev->ispp_sdev;
372 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
373 struct rkispp_stream *stream;
374 struct rkisp_ispp_mode mode;
375 int ret;
376
377 if (dev->inp != INP_ISP || ispp_sdev->state)
378 return 0;
379
380 if (dev->stream_sync) {
381 stream = &vdev->stream[STREAM_MB];
382 if (stream->linked && !stream->streaming)
383 return 0;
384 } else if (atomic_read(&vdev->refcnt) > 1) {
385 return 0;
386 }
387
388 rkispp_start_3a_run(dev);
389
390 mutex_lock(&dev->hw_dev->dev_lock);
391
392 mode.work_mode = ISP_ISPP_422;
393 mode.buf_num = 1;
394 mode.buf_num += RKISP_BUF_MAX + 2 * (dev->hw_dev->dev_num - 1);
395
396 ret = v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
397 RKISP_ISPP_CMD_SET_MODE, &mode);
398 if (ret)
399 goto err;
400
401 ret = config_modules(dev);
402 if (ret) {
403 rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
404 mode.work_mode = ISP_ISPP_INIT_FAIL;
405 v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
406 RKISP_ISPP_CMD_SET_MODE, &mode);
407 goto err;
408 }
409
410 if (dev->hw_dev->is_single)
411 writel(ALL_FORCE_UPD, dev->hw_dev->base_addr + RKISPP_CTRL_UPDATE);
412 stream = &vdev->stream[STREAM_MB];
413 if (stream->streaming)
414 stream->is_upd = true;
415 if (dev->isp_mode & ISP_ISPP_QUICK)
416 rkispp_set_bits(dev, RKISPP_CTRL_QUICK, 0, GLB_QUICK_EN);
417
418 dev->isr_cnt = 0;
419 dev->isr_err_cnt = 0;
420 ret = v4l2_subdev_call(&ispp_sdev->sd, video, s_stream, true);
421 err:
422 mutex_unlock(&dev->hw_dev->dev_lock);
423 return ret;
424 }
425
check_to_force_update(struct rkispp_device * dev,u32 mis_val)426 static void check_to_force_update(struct rkispp_device *dev, u32 mis_val)
427 {
428 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
429 struct rkispp_stream *stream;
430 u32 mask = FEC_INT;
431
432 vdev->irq_ends |= (mis_val & mask);
433 v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
434 "irq_ends:0x%x mask:0x%x\n",
435 vdev->irq_ends, mask);
436 if (vdev->irq_ends != mask)
437 return;
438 vdev->irq_ends = 0;
439 if (mis_val & FEC_INT)
440 rkispp_module_work_event(dev, NULL, NULL,
441 ISPP_MODULE_FEC, true);
442
443 stream = &vdev->stream[STREAM_MB];
444 if (stream->streaming)
445 stream->is_upd = true;
446
447 }
448
449 static struct rkispp_stream_ops rkispp_stream_ops = {
450 .config_modules = config_modules,
451 .destroy_buf = rkispp_destroy_buf,
452 .fec_work_event = fec_work_event,
453 .start_isp = start_isp,
454 .check_to_force_update = check_to_force_update,
455 .update_mi = update_mi,
456 .rkispp_module_work_event = rkispp_module_work_event,
457 };
458
rkispp_stream_init_ops_v20(struct rkispp_stream_vdev * stream_vdev)459 void rkispp_stream_init_ops_v20(struct rkispp_stream_vdev *stream_vdev)
460 {
461 stream_vdev->stream_ops = &rkispp_stream_ops;
462 }
463