1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include <linux/pm_runtime.h>
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-event.h>
39 #include <media/v4l2-fh.h>
40 #include <media/v4l2-ioctl.h>
41 #include <media/v4l2-subdev.h>
42 #include <media/videobuf2-dma-contig.h>
43 #include "dev.h"
44 #include "regs.h"
45
46 /*
47 * NOTE:
48 * 1. There are two capture video devices in rkisp1, selfpath and mainpath
49 * 2. Two capture device have separated memory-interface/crop/scale units.
50 * 3. Besides describing stream hardware, this file also contain entries
51 * for pipeline operations.
52 * 4. The register read/write operations in this file are put into regs.c.
53 */
54
55 /*
56 * differences between selfpatch and mainpath
57 * available mp sink input: isp
58 * available sp sink input : isp, dma(TODO)
59 * available mp sink pad fmts: yuv422, raw
60 * available sp sink pad fmts: yuv422, yuv420......
61 * available mp source fmts: yuv, raw, jpeg(TODO)
62 * available sp source fmts: yuv, rgb
63 */
64
65 #define CIF_ISP_REQ_BUFS_MIN 0
66 #define CIF_ISP_REQ_BUFS_MAX 8
67
68 #define STREAM_PAD_SINK 0
69 #define STREAM_PAD_SOURCE 1
70
71 #define STREAM_MAX_MP_RSZ_OUTPUT_WIDTH 4416
72 #define STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT 3312
73 #define STREAM_MAX_SP_RSZ_OUTPUT_WIDTH 1920
74 #define STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT 1920
75 #define STREAM_MIN_RSZ_OUTPUT_WIDTH 32
76 #define STREAM_MIN_RSZ_OUTPUT_HEIGHT 16
77 #define STREAM_OUTPUT_STEP_WISE 8
78
79 #define STREAM_MAX_MP_SP_INPUT_WIDTH STREAM_MAX_MP_RSZ_OUTPUT_WIDTH
80 #define STREAM_MAX_MP_SP_INPUT_HEIGHT STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT
81 #define STREAM_MIN_MP_SP_INPUT_WIDTH 32
82 #define STREAM_MIN_MP_SP_INPUT_HEIGHT 32
83
84 /* Get xsubs and ysubs for fourcc formats
85 *
86 * @xsubs: horizontal color samples in a 4*4 matrix, for yuv
87 * @ysubs: vertical color samples in a 4*4 matrix, for yuv
88 */
fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)89 int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
90 {
91 switch (fcc) {
92 case V4L2_PIX_FMT_GREY:
93 case V4L2_PIX_FMT_YUV444M:
94 *xsubs = 1;
95 *ysubs = 1;
96 break;
97 case V4L2_PIX_FMT_YUYV:
98 case V4L2_PIX_FMT_YVYU:
99 case V4L2_PIX_FMT_VYUY:
100 case V4L2_PIX_FMT_YUV422P:
101 case V4L2_PIX_FMT_NV16:
102 case V4L2_PIX_FMT_NV61:
103 case V4L2_PIX_FMT_YVU422M:
104 *xsubs = 2;
105 *ysubs = 1;
106 break;
107 case V4L2_PIX_FMT_NV21:
108 case V4L2_PIX_FMT_NV12:
109 case V4L2_PIX_FMT_NV21M:
110 case V4L2_PIX_FMT_NV12M:
111 case V4L2_PIX_FMT_YUV420:
112 case V4L2_PIX_FMT_YVU420:
113 *xsubs = 2;
114 *ysubs = 2;
115 break;
116 default:
117 return -EINVAL;
118 }
119
120 return 0;
121 }
122
mbus_code_xysubs(u32 code,u32 * xsubs,u32 * ysubs)123 static int mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs)
124 {
125 switch (code) {
126 case MEDIA_BUS_FMT_YUYV8_2X8:
127 case MEDIA_BUS_FMT_YUYV8_1X16:
128 case MEDIA_BUS_FMT_YVYU8_1X16:
129 case MEDIA_BUS_FMT_UYVY8_1X16:
130 case MEDIA_BUS_FMT_VYUY8_1X16:
131 *xsubs = 2;
132 *ysubs = 1;
133 break;
134 default:
135 return -EINVAL;
136 }
137
138 return 0;
139 }
140
mbus_code_sp_in_fmt(u32 in_mbus_code,u32 out_fourcc,u32 * format)141 static int mbus_code_sp_in_fmt(u32 in_mbus_code, u32 out_fourcc,
142 u32 *format)
143 {
144 switch (in_mbus_code) {
145 case MEDIA_BUS_FMT_YUYV8_2X8:
146 *format = MI_CTRL_SP_INPUT_YUV422;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 /*
153 * Only SP can support output format of YCbCr4:0:0,
154 * and the input format of SP must be YCbCr4:0:0
155 * when outputting YCbCr4:0:0.
156 * The output format of isp is YCbCr4:2:2,
157 * so the CbCr data is discarded here.
158 */
159 if (out_fourcc == V4L2_PIX_FMT_GREY)
160 *format = MI_CTRL_SP_INPUT_YUV400;
161
162 return 0;
163 }
164
165 static const struct capture_fmt mp_fmts[] = {
166 /* yuv422 */
167 {
168 .fourcc = V4L2_PIX_FMT_YUYV,
169 .fmt_type = FMT_YUV,
170 .bpp = { 16 },
171 .cplanes = 1,
172 .mplanes = 1,
173 .uv_swap = 0,
174 .write_format = MI_CTRL_MP_WRITE_YUVINT,
175 }, {
176 .fourcc = V4L2_PIX_FMT_YUV422P,
177 .fmt_type = FMT_YUV,
178 .bpp = { 8, 4, 4 },
179 .cplanes = 3,
180 .mplanes = 1,
181 .uv_swap = 0,
182 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
183 }, {
184 .fourcc = V4L2_PIX_FMT_NV16,
185 .fmt_type = FMT_YUV,
186 .bpp = { 8, 16 },
187 .cplanes = 2,
188 .mplanes = 1,
189 .uv_swap = 0,
190 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
191 }, {
192 .fourcc = V4L2_PIX_FMT_NV61,
193 .fmt_type = FMT_YUV,
194 .bpp = { 8, 16 },
195 .cplanes = 2,
196 .mplanes = 1,
197 .uv_swap = 1,
198 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
199 }, {
200 .fourcc = V4L2_PIX_FMT_YUV422M,
201 .fmt_type = FMT_YUV,
202 .bpp = { 8, 8, 8 },
203 .cplanes = 3,
204 .mplanes = 3,
205 .uv_swap = 0,
206 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
207 },
208 /* yuv420 */
209 {
210 .fourcc = V4L2_PIX_FMT_NV21,
211 .fmt_type = FMT_YUV,
212 .bpp = { 8, 16 },
213 .cplanes = 2,
214 .mplanes = 1,
215 .uv_swap = 1,
216 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
217 }, {
218 .fourcc = V4L2_PIX_FMT_NV12,
219 .fmt_type = FMT_YUV,
220 .bpp = { 8, 16 },
221 .cplanes = 2,
222 .mplanes = 1,
223 .uv_swap = 0,
224 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
225 }, {
226 .fourcc = V4L2_PIX_FMT_NV21M,
227 .fmt_type = FMT_YUV,
228 .bpp = { 8, 16 },
229 .cplanes = 2,
230 .mplanes = 2,
231 .uv_swap = 1,
232 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
233 }, {
234 .fourcc = V4L2_PIX_FMT_NV12M,
235 .fmt_type = FMT_YUV,
236 .bpp = { 8, 16 },
237 .cplanes = 2,
238 .mplanes = 2,
239 .uv_swap = 0,
240 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
241 }, {
242 .fourcc = V4L2_PIX_FMT_YUV420,
243 .fmt_type = FMT_YUV,
244 .bpp = { 8, 8, 8 },
245 .cplanes = 3,
246 .mplanes = 1,
247 .uv_swap = 0,
248 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
249 },
250 /* yuv444 */
251 {
252 .fourcc = V4L2_PIX_FMT_YUV444M,
253 .fmt_type = FMT_YUV,
254 .bpp = { 8, 8, 8 },
255 .cplanes = 3,
256 .mplanes = 3,
257 .uv_swap = 0,
258 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
259 },
260 /* raw */
261 {
262 .fourcc = V4L2_PIX_FMT_SRGGB8,
263 .fmt_type = FMT_BAYER,
264 .bpp = { 8 },
265 .mplanes = 1,
266 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
267 }, {
268 .fourcc = V4L2_PIX_FMT_SGRBG8,
269 .fmt_type = FMT_BAYER,
270 .bpp = { 8 },
271 .mplanes = 1,
272 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
273 }, {
274 .fourcc = V4L2_PIX_FMT_SGBRG8,
275 .fmt_type = FMT_BAYER,
276 .bpp = { 8 },
277 .mplanes = 1,
278 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
279 }, {
280 .fourcc = V4L2_PIX_FMT_SBGGR8,
281 .fmt_type = FMT_BAYER,
282 .bpp = { 8 },
283 .mplanes = 1,
284 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
285 }, {
286 .fourcc = V4L2_PIX_FMT_SRGGB10,
287 .fmt_type = FMT_BAYER,
288 .bpp = { 10 },
289 .mplanes = 1,
290 .write_format = MI_CTRL_MP_WRITE_RAW12,
291 }, {
292 .fourcc = V4L2_PIX_FMT_SGRBG10,
293 .fmt_type = FMT_BAYER,
294 .bpp = { 10 },
295 .mplanes = 1,
296 .write_format = MI_CTRL_MP_WRITE_RAW12,
297 }, {
298 .fourcc = V4L2_PIX_FMT_SGBRG10,
299 .fmt_type = FMT_BAYER,
300 .bpp = { 10 },
301 .mplanes = 1,
302 .write_format = MI_CTRL_MP_WRITE_RAW12,
303 }, {
304 .fourcc = V4L2_PIX_FMT_SBGGR10,
305 .fmt_type = FMT_BAYER,
306 .bpp = { 10 },
307 .mplanes = 1,
308 .write_format = MI_CTRL_MP_WRITE_RAW12,
309 }, {
310 .fourcc = V4L2_PIX_FMT_SRGGB12,
311 .fmt_type = FMT_BAYER,
312 .bpp = { 12 },
313 .mplanes = 1,
314 .write_format = MI_CTRL_MP_WRITE_RAW12,
315 }, {
316 .fourcc = V4L2_PIX_FMT_SGRBG12,
317 .fmt_type = FMT_BAYER,
318 .bpp = { 12 },
319 .mplanes = 1,
320 .write_format = MI_CTRL_MP_WRITE_RAW12,
321 }, {
322 .fourcc = V4L2_PIX_FMT_SGBRG12,
323 .fmt_type = FMT_BAYER,
324 .bpp = { 12 },
325 .mplanes = 1,
326 .write_format = MI_CTRL_MP_WRITE_RAW12,
327 }, {
328 .fourcc = V4L2_PIX_FMT_SBGGR12,
329 .fmt_type = FMT_BAYER,
330 .bpp = { 12 },
331 .mplanes = 1,
332 .write_format = MI_CTRL_MP_WRITE_RAW12,
333 },
334 };
335
336 static const struct capture_fmt sp_fmts[] = {
337 /* yuv422 */
338 {
339 .fourcc = V4L2_PIX_FMT_YUYV,
340 .fmt_type = FMT_YUV,
341 .bpp = { 16 },
342 .cplanes = 1,
343 .mplanes = 1,
344 .uv_swap = 0,
345 .write_format = MI_CTRL_SP_WRITE_INT,
346 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
347 }, {
348 .fourcc = V4L2_PIX_FMT_YUV422P,
349 .fmt_type = FMT_YUV,
350 .bpp = { 8, 8, 8 },
351 .cplanes = 3,
352 .mplanes = 1,
353 .uv_swap = 0,
354 .write_format = MI_CTRL_SP_WRITE_PLA,
355 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
356 }, {
357 .fourcc = V4L2_PIX_FMT_NV16,
358 .fmt_type = FMT_YUV,
359 .bpp = { 8, 16 },
360 .cplanes = 2,
361 .mplanes = 1,
362 .uv_swap = 0,
363 .write_format = MI_CTRL_SP_WRITE_SPLA,
364 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
365 }, {
366 .fourcc = V4L2_PIX_FMT_NV61,
367 .fmt_type = FMT_YUV,
368 .bpp = { 8, 16 },
369 .cplanes = 2,
370 .mplanes = 1,
371 .uv_swap = 1,
372 .write_format = MI_CTRL_SP_WRITE_SPLA,
373 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
374 }, {
375 .fourcc = V4L2_PIX_FMT_YUV422M,
376 .fmt_type = FMT_YUV,
377 .bpp = { 8, 8, 8 },
378 .cplanes = 3,
379 .mplanes = 3,
380 .uv_swap = 0,
381 .write_format = MI_CTRL_SP_WRITE_PLA,
382 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
383 },
384 /* yuv420 */
385 {
386 .fourcc = V4L2_PIX_FMT_NV21,
387 .fmt_type = FMT_YUV,
388 .bpp = { 8, 16 },
389 .cplanes = 2,
390 .mplanes = 1,
391 .uv_swap = 1,
392 .write_format = MI_CTRL_SP_WRITE_SPLA,
393 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
394 }, {
395 .fourcc = V4L2_PIX_FMT_NV12,
396 .fmt_type = FMT_YUV,
397 .bpp = { 8, 16 },
398 .cplanes = 2,
399 .mplanes = 1,
400 .uv_swap = 0,
401 .write_format = MI_CTRL_SP_WRITE_SPLA,
402 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
403 }, {
404 .fourcc = V4L2_PIX_FMT_NV21M,
405 .fmt_type = FMT_YUV,
406 .bpp = { 8, 16 },
407 .cplanes = 2,
408 .mplanes = 2,
409 .uv_swap = 1,
410 .write_format = MI_CTRL_SP_WRITE_SPLA,
411 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
412 }, {
413 .fourcc = V4L2_PIX_FMT_NV12M,
414 .fmt_type = FMT_YUV,
415 .bpp = { 8, 16 },
416 .cplanes = 2,
417 .mplanes = 2,
418 .uv_swap = 0,
419 .write_format = MI_CTRL_SP_WRITE_SPLA,
420 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
421 }, {
422 .fourcc = V4L2_PIX_FMT_YUV420,
423 .fmt_type = FMT_YUV,
424 .bpp = { 8, 8, 8 },
425 .cplanes = 3,
426 .mplanes = 1,
427 .uv_swap = 0,
428 .write_format = MI_CTRL_SP_WRITE_PLA,
429 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
430 },
431 /* yuv444 */
432 {
433 .fourcc = V4L2_PIX_FMT_YUV444M,
434 .fmt_type = FMT_YUV,
435 .bpp = { 8, 8, 8 },
436 .cplanes = 3,
437 .mplanes = 3,
438 .uv_swap = 0,
439 .write_format = MI_CTRL_SP_WRITE_PLA,
440 .output_format = MI_CTRL_SP_OUTPUT_YUV444,
441 },
442 /* yuv400 */
443 {
444 .fourcc = V4L2_PIX_FMT_GREY,
445 .fmt_type = FMT_YUV,
446 .bpp = { 8 },
447 .cplanes = 1,
448 .mplanes = 1,
449 .uv_swap = 0,
450 .write_format = MI_CTRL_SP_WRITE_PLA,
451 .output_format = MI_CTRL_SP_OUTPUT_YUV400,
452 },
453 /* rgb */
454 {
455 .fourcc = V4L2_PIX_FMT_XBGR32,
456 .fmt_type = FMT_RGB,
457 .bpp = { 32 },
458 .mplanes = 1,
459 .write_format = MI_CTRL_SP_WRITE_PLA,
460 .output_format = MI_CTRL_SP_OUTPUT_RGB888,
461 }, {
462 .fourcc = V4L2_PIX_FMT_RGB565,
463 .fmt_type = FMT_RGB,
464 .bpp = { 16 },
465 .mplanes = 1,
466 .write_format = MI_CTRL_SP_WRITE_PLA,
467 .output_format = MI_CTRL_SP_OUTPUT_RGB565,
468 }
469 };
470
471 static const struct capture_fmt raw_fmts[] = {
472 /* raw */
473 {
474 .fourcc = V4L2_PIX_FMT_SRGGB8,
475 .fmt_type = FMT_BAYER,
476 .bpp = { 8 },
477 .mplanes = 1,
478 }, {
479 .fourcc = V4L2_PIX_FMT_SGRBG8,
480 .fmt_type = FMT_BAYER,
481 .bpp = { 8 },
482 .mplanes = 1,
483 }, {
484 .fourcc = V4L2_PIX_FMT_SGBRG8,
485 .fmt_type = FMT_BAYER,
486 .bpp = { 8 },
487 .mplanes = 1,
488 }, {
489 .fourcc = V4L2_PIX_FMT_SBGGR8,
490 .fmt_type = FMT_BAYER,
491 .bpp = { 8 },
492 .mplanes = 1,
493 }, {
494 .fourcc = V4L2_PIX_FMT_SRGGB10,
495 .fmt_type = FMT_BAYER,
496 .bpp = { 10 },
497 .mplanes = 1,
498 }, {
499 .fourcc = V4L2_PIX_FMT_SGRBG10,
500 .fmt_type = FMT_BAYER,
501 .bpp = { 10 },
502 .mplanes = 1,
503 }, {
504 .fourcc = V4L2_PIX_FMT_SGBRG10,
505 .fmt_type = FMT_BAYER,
506 .bpp = { 10 },
507 .mplanes = 1,
508 }, {
509 .fourcc = V4L2_PIX_FMT_SBGGR10,
510 .fmt_type = FMT_BAYER,
511 .bpp = { 10 },
512 .mplanes = 1,
513 }, {
514 .fourcc = V4L2_PIX_FMT_SRGGB12,
515 .fmt_type = FMT_BAYER,
516 .bpp = { 12 },
517 .mplanes = 1,
518 }, {
519 .fourcc = V4L2_PIX_FMT_SGRBG12,
520 .fmt_type = FMT_BAYER,
521 .bpp = { 12 },
522 .mplanes = 1,
523 }, {
524 .fourcc = V4L2_PIX_FMT_SGBRG12,
525 .fmt_type = FMT_BAYER,
526 .bpp = { 12 },
527 .mplanes = 1,
528 }, {
529 .fourcc = V4L2_PIX_FMT_SBGGR12,
530 .fmt_type = FMT_BAYER,
531 .bpp = { 12 },
532 .mplanes = 1,
533 },
534 };
535
536 static struct stream_config rkisp1_mp_stream_config = {
537 .fmts = mp_fmts,
538 .fmt_size = ARRAY_SIZE(mp_fmts),
539 /* constraints */
540 .max_rsz_width = STREAM_MAX_MP_RSZ_OUTPUT_WIDTH,
541 .max_rsz_height = STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT,
542 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
543 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
544 /* registers */
545 .rsz = {
546 .ctrl = CIF_MRSZ_CTRL,
547 .scale_hy = CIF_MRSZ_SCALE_HY,
548 .scale_hcr = CIF_MRSZ_SCALE_HCR,
549 .scale_hcb = CIF_MRSZ_SCALE_HCB,
550 .scale_vy = CIF_MRSZ_SCALE_VY,
551 .scale_vc = CIF_MRSZ_SCALE_VC,
552 .scale_lut = CIF_MRSZ_SCALE_LUT,
553 .scale_lut_addr = CIF_MRSZ_SCALE_LUT_ADDR,
554 .scale_hy_shd = CIF_MRSZ_SCALE_HY_SHD,
555 .scale_hcr_shd = CIF_MRSZ_SCALE_HCR_SHD,
556 .scale_hcb_shd = CIF_MRSZ_SCALE_HCB_SHD,
557 .scale_vy_shd = CIF_MRSZ_SCALE_VY_SHD,
558 .scale_vc_shd = CIF_MRSZ_SCALE_VC_SHD,
559 .phase_hy = CIF_MRSZ_PHASE_HY,
560 .phase_hc = CIF_MRSZ_PHASE_HC,
561 .phase_vy = CIF_MRSZ_PHASE_VY,
562 .phase_vc = CIF_MRSZ_PHASE_VC,
563 .ctrl_shd = CIF_MRSZ_CTRL_SHD,
564 .phase_hy_shd = CIF_MRSZ_PHASE_HY_SHD,
565 .phase_hc_shd = CIF_MRSZ_PHASE_HC_SHD,
566 .phase_vy_shd = CIF_MRSZ_PHASE_VY_SHD,
567 .phase_vc_shd = CIF_MRSZ_PHASE_VC_SHD,
568 },
569 .dual_crop = {
570 .ctrl = CIF_DUAL_CROP_CTRL,
571 .yuvmode_mask = CIF_DUAL_CROP_MP_MODE_YUV,
572 .rawmode_mask = CIF_DUAL_CROP_MP_MODE_RAW,
573 .h_offset = CIF_DUAL_CROP_M_H_OFFS,
574 .v_offset = CIF_DUAL_CROP_M_V_OFFS,
575 .h_size = CIF_DUAL_CROP_M_H_SIZE,
576 .v_size = CIF_DUAL_CROP_M_V_SIZE,
577 },
578 .mi = {
579 .y_size_init = CIF_MI_MP_Y_SIZE_INIT,
580 .cb_size_init = CIF_MI_MP_CB_SIZE_INIT,
581 .cr_size_init = CIF_MI_MP_CR_SIZE_INIT,
582 .y_base_ad_init = CIF_MI_MP_Y_BASE_AD_INIT,
583 .cb_base_ad_init = CIF_MI_MP_CB_BASE_AD_INIT,
584 .cr_base_ad_init = CIF_MI_MP_CR_BASE_AD_INIT,
585 .y_offs_cnt_init = CIF_MI_MP_Y_OFFS_CNT_INIT,
586 .cb_offs_cnt_init = CIF_MI_MP_CB_OFFS_CNT_INIT,
587 .cr_offs_cnt_init = CIF_MI_MP_CR_OFFS_CNT_INIT,
588 },
589 };
590
591 static struct stream_config rkisp1_sp_stream_config = {
592 .fmts = sp_fmts,
593 .fmt_size = ARRAY_SIZE(sp_fmts),
594 /* constraints */
595 .max_rsz_width = STREAM_MAX_SP_RSZ_OUTPUT_WIDTH,
596 .max_rsz_height = STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT,
597 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
598 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
599 /* registers */
600 .rsz = {
601 .ctrl = CIF_SRSZ_CTRL,
602 .scale_hy = CIF_SRSZ_SCALE_HY,
603 .scale_hcr = CIF_SRSZ_SCALE_HCR,
604 .scale_hcb = CIF_SRSZ_SCALE_HCB,
605 .scale_vy = CIF_SRSZ_SCALE_VY,
606 .scale_vc = CIF_SRSZ_SCALE_VC,
607 .scale_lut = CIF_SRSZ_SCALE_LUT,
608 .scale_lut_addr = CIF_SRSZ_SCALE_LUT_ADDR,
609 .scale_hy_shd = CIF_SRSZ_SCALE_HY_SHD,
610 .scale_hcr_shd = CIF_SRSZ_SCALE_HCR_SHD,
611 .scale_hcb_shd = CIF_SRSZ_SCALE_HCB_SHD,
612 .scale_vy_shd = CIF_SRSZ_SCALE_VY_SHD,
613 .scale_vc_shd = CIF_SRSZ_SCALE_VC_SHD,
614 .phase_hy = CIF_SRSZ_PHASE_HY,
615 .phase_hc = CIF_SRSZ_PHASE_HC,
616 .phase_vy = CIF_SRSZ_PHASE_VY,
617 .phase_vc = CIF_SRSZ_PHASE_VC,
618 .ctrl_shd = CIF_SRSZ_CTRL_SHD,
619 .phase_hy_shd = CIF_SRSZ_PHASE_HY_SHD,
620 .phase_hc_shd = CIF_SRSZ_PHASE_HC_SHD,
621 .phase_vy_shd = CIF_SRSZ_PHASE_VY_SHD,
622 .phase_vc_shd = CIF_SRSZ_PHASE_VC_SHD,
623 },
624 .dual_crop = {
625 .ctrl = CIF_DUAL_CROP_CTRL,
626 .yuvmode_mask = CIF_DUAL_CROP_SP_MODE_YUV,
627 .rawmode_mask = CIF_DUAL_CROP_SP_MODE_RAW,
628 .h_offset = CIF_DUAL_CROP_S_H_OFFS,
629 .v_offset = CIF_DUAL_CROP_S_V_OFFS,
630 .h_size = CIF_DUAL_CROP_S_H_SIZE,
631 .v_size = CIF_DUAL_CROP_S_V_SIZE,
632 },
633 .mi = {
634 .y_size_init = CIF_MI_SP_Y_SIZE_INIT,
635 .cb_size_init = CIF_MI_SP_CB_SIZE_INIT,
636 .cr_size_init = CIF_MI_SP_CR_SIZE_INIT,
637 .y_base_ad_init = CIF_MI_SP_Y_BASE_AD_INIT,
638 .cb_base_ad_init = CIF_MI_SP_CB_BASE_AD_INIT,
639 .cr_base_ad_init = CIF_MI_SP_CR_BASE_AD_INIT,
640 .y_offs_cnt_init = CIF_MI_SP_Y_OFFS_CNT_INIT,
641 .cb_offs_cnt_init = CIF_MI_SP_CB_OFFS_CNT_INIT,
642 .cr_offs_cnt_init = CIF_MI_SP_CR_OFFS_CNT_INIT,
643 },
644 };
645
646 static struct stream_config rkisp1_raw_stream_config = {
647 .fmts = raw_fmts,
648 .fmt_size = ARRAY_SIZE(raw_fmts),
649 };
650
651 static const
find_fmt(struct rkisp1_stream * stream,const u32 pixelfmt)652 struct capture_fmt *find_fmt(struct rkisp1_stream *stream, const u32 pixelfmt)
653 {
654 const struct capture_fmt *fmt;
655 int i;
656
657 for (i = 0; i < stream->config->fmt_size; i++) {
658 fmt = &stream->config->fmts[i];
659 if (fmt->fourcc == pixelfmt)
660 return fmt;
661 }
662 return NULL;
663 }
664
665 /* configure dual-crop unit */
rkisp1_config_dcrop(struct rkisp1_stream * stream,bool async)666 static int rkisp1_config_dcrop(struct rkisp1_stream *stream, bool async)
667 {
668 struct rkisp1_device *dev = stream->ispdev;
669 struct v4l2_rect *dcrop = &stream->dcrop;
670 struct v4l2_rect *input_win;
671
672 /* dual-crop unit get data from isp */
673 input_win = rkisp1_get_isp_sd_win(&dev->isp_sdev);
674
675 if (dcrop->width == input_win->width &&
676 dcrop->height == input_win->height &&
677 dcrop->left == 0 && dcrop->top == 0) {
678 disable_dcrop(stream, async);
679 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
680 "stream %d crop disabled\n", stream->id);
681 return 0;
682 }
683
684 config_dcrop(stream, dcrop, async);
685
686 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
687 "stream %d crop: %dx%d -> %dx%d\n", stream->id,
688 input_win->width, input_win->height,
689 dcrop->width, dcrop->height);
690
691 return 0;
692 }
693
694 /* configure scale unit */
rkisp1_config_rsz(struct rkisp1_stream * stream,bool async)695 static int rkisp1_config_rsz(struct rkisp1_stream *stream, bool async)
696 {
697 struct rkisp1_device *dev = stream->ispdev;
698 struct v4l2_pix_format_mplane output_fmt = stream->out_fmt;
699 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
700 struct ispsd_out_fmt *input_isp_fmt =
701 rkisp1_get_ispsd_out_fmt(&dev->isp_sdev);
702 struct v4l2_rect in_y, in_c, out_y, out_c;
703 u32 xsubs_in = 1, ysubs_in = 1;
704 u32 xsubs_out = 1, ysubs_out = 1;
705
706 if (input_isp_fmt->fmt_type == FMT_BAYER)
707 goto disable;
708
709 /* set input and output sizes for scale calculation */
710 in_y.width = stream->dcrop.width;
711 in_y.height = stream->dcrop.height;
712 out_y.width = output_fmt.width;
713 out_y.height = output_fmt.height;
714
715 /* The size of Cb,Cr are related to the format */
716 if (mbus_code_xysubs(input_isp_fmt->mbus_code, &xsubs_in, &ysubs_in)) {
717 v4l2_err(&dev->v4l2_dev, "Not xsubs/ysubs found\n");
718 return -EINVAL;
719 }
720 in_c.width = in_y.width / xsubs_in;
721 in_c.height = in_y.height / ysubs_in;
722
723 if (output_isp_fmt->fmt_type == FMT_YUV) {
724 fcc_xysubs(output_isp_fmt->fourcc, &xsubs_out, &ysubs_out);
725 out_c.width = out_y.width / xsubs_out;
726 out_c.height = out_y.height / ysubs_out;
727 } else {
728 out_c.width = out_y.width / xsubs_in;
729 out_c.height = out_y.height / ysubs_in;
730 }
731
732 if (in_c.width == out_c.width && in_c.height == out_c.height)
733 goto disable;
734
735 /* set RSZ input and output */
736 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
737 "stream %d rsz/scale: %dx%d -> %dx%d\n",
738 stream->id, stream->dcrop.width, stream->dcrop.height,
739 output_fmt.width, output_fmt.height);
740 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
741 "chroma scaling %dx%d -> %dx%d\n",
742 in_c.width, in_c.height, out_c.width, out_c.height);
743
744 /* calculate and set scale */
745 config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
746
747 if (rkisp1_debug)
748 dump_rsz_regs(stream);
749
750 return 0;
751
752 disable:
753 disable_rsz(stream, async);
754
755 return 0;
756 }
757
758 /***************************** stream operations*******************************/
759
760 /*
761 * memory base addresses should be with respect
762 * to the burst alignment restriction for AXI.
763 */
calc_burst_len(struct rkisp1_stream * stream)764 static u32 calc_burst_len(struct rkisp1_stream *stream)
765 {
766 struct rkisp1_device *dev = stream->ispdev;
767 u32 y_size = stream->out_fmt.plane_fmt[0].bytesperline *
768 stream->out_fmt.height;
769 u32 cb_size = stream->out_fmt.plane_fmt[1].sizeimage;
770 u32 cr_size = stream->out_fmt.plane_fmt[2].sizeimage;
771 u32 cb_offs, cr_offs;
772 u32 bus, burst;
773 int i;
774
775 /* MI128bit and MI64bit */
776 bus = 8;
777 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13)
778 bus = 16;
779
780 /* y/c base addr: burstN * bus alignment */
781 cb_offs = y_size;
782 cr_offs = cr_size ? (cb_size + cb_offs) : 0;
783
784 if (!(cb_offs % (bus * 16)) &&
785 !(cr_offs % (bus * 16)))
786 burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
787 CIF_MI_CTRL_BURST_LEN_CHROM_16;
788 else if (!(cb_offs % (bus * 8)) &&
789 !(cr_offs % (bus * 8)))
790 burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
791 CIF_MI_CTRL_BURST_LEN_CHROM_8;
792 else
793 burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
794 CIF_MI_CTRL_BURST_LEN_CHROM_4;
795
796 if (cb_offs % (bus * 4) ||
797 cr_offs % (bus * 4))
798 v4l2_warn(&dev->v4l2_dev,
799 "%dx%d fmt:0x%x not support, should be %d aligned\n",
800 stream->out_fmt.width,
801 stream->out_fmt.height,
802 stream->out_fmt.pixelformat,
803 (cr_offs == 0) ? bus * 4 : bus * 16);
804
805 stream->burst = burst;
806 for (i = 0; i < RKISP1_MAX_STREAM; i++)
807 if (burst > dev->stream[i].burst)
808 burst = dev->stream[i].burst;
809
810 if (stream->interlaced) {
811 if (!stream->out_fmt.width % (bus * 16))
812 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
813 CIF_MI_CTRL_BURST_LEN_CHROM_16;
814 else if (!stream->out_fmt.width % (bus * 8))
815 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
816 CIF_MI_CTRL_BURST_LEN_CHROM_8;
817 else
818 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
819 CIF_MI_CTRL_BURST_LEN_CHROM_4;
820 if (stream->out_fmt.width % (bus * 4))
821 v4l2_warn(&dev->v4l2_dev,
822 "interlaced: width should be %d aligned\n",
823 bus * 4);
824 burst = min(stream->burst, burst);
825 stream->burst = burst;
826 }
827
828 return burst;
829 }
830
831 /*
832 * configure memory interface for mainpath
833 * This should only be called when stream-on
834 */
mp_config_mi(struct rkisp1_stream * stream)835 static int mp_config_mi(struct rkisp1_stream *stream)
836 {
837 void __iomem *base = stream->ispdev->base_addr;
838
839 /*
840 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
841 * memory plane formats, so calculate the size explicitly.
842 */
843 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
844 stream->out_fmt.height);
845 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
846 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
847 mi_frame_end_int_enable(stream);
848 if (stream->out_isp_fmt.uv_swap)
849 mp_set_uv_swap(base);
850
851 config_mi_ctrl(stream, calc_burst_len(stream));
852 mp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format);
853 mp_mi_ctrl_autoupdate_en(base);
854
855 return 0;
856 }
857
858 /*
859 * configure memory interface for selfpath
860 * This should only be called when stream-on
861 */
sp_config_mi(struct rkisp1_stream * stream)862 static int sp_config_mi(struct rkisp1_stream *stream)
863 {
864 void __iomem *base = stream->ispdev->base_addr;
865 struct rkisp1_device *dev = stream->ispdev;
866 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
867 struct ispsd_out_fmt *input_isp_fmt =
868 rkisp1_get_ispsd_out_fmt(&dev->isp_sdev);
869 u32 sp_in_fmt;
870
871 if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
872 output_isp_fmt->fourcc, &sp_in_fmt)) {
873 v4l2_err(&dev->v4l2_dev, "Can't find the input format\n");
874 return -EINVAL;
875 }
876
877 /*
878 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
879 * memory plane formats, so calculate the size explicitly.
880 */
881 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
882 stream->out_fmt.height);
883 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
884 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
885
886 sp_set_y_width(base, stream->out_fmt.width);
887 if (stream->interlaced) {
888 stream->u.sp.vir_offs =
889 stream->out_fmt.plane_fmt[0].bytesperline;
890 sp_set_y_height(base, stream->out_fmt.height / 2);
891 sp_set_y_line_length(base, stream->u.sp.y_stride * 2);
892 } else {
893 sp_set_y_height(base, stream->out_fmt.height);
894 sp_set_y_line_length(base, stream->u.sp.y_stride);
895 }
896
897 mi_frame_end_int_enable(stream);
898 if (output_isp_fmt->uv_swap)
899 sp_set_uv_swap(base);
900
901 config_mi_ctrl(stream, calc_burst_len(stream));
902 sp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format |
903 sp_in_fmt | output_isp_fmt->output_format);
904
905 sp_mi_ctrl_autoupdate_en(base);
906
907 return 0;
908 }
909
910 /*
911 * configure memory interface for rawpath
912 * This should only be called when stream-on
913 */
raw_config_mi(struct rkisp1_stream * stream)914 static int raw_config_mi(struct rkisp1_stream *stream)
915 {
916 void __iomem *base = stream->ispdev->base_addr;
917 struct rkisp1_device *dev = stream->ispdev;
918 struct v4l2_mbus_framefmt *in_frm;
919 u32 in_size;
920
921 if (!dev->active_sensor ||
922 (dev->active_sensor &&
923 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
924 if (stream->id == RKISP1_STREAM_RAW)
925 v4l2_err(&dev->v4l2_dev,
926 "only mipi sensor support raw path\n");
927 return -EINVAL;
928 }
929
930 if (dev->stream[RKISP1_STREAM_RAW].streaming)
931 return 0;
932
933 in_frm = &dev->active_sensor->fmt.format;
934
935 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
936 "stream:%d input %dx%d\n",
937 stream->id, in_frm->width, in_frm->height);
938
939 /* raw output size equal to sensor input size */
940 if (stream->id == RKISP1_STREAM_RAW) {
941 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
942 } else {
943 struct rkisp1_stream *raw = &dev->stream[RKISP1_STREAM_RAW];
944
945 in_size = raw->out_fmt.plane_fmt[0].sizeimage;
946 }
947
948 dmatx0_set_pic_size(base, in_frm->width, in_frm->height);
949 dmatx0_set_pic_off(base, 0);
950 dmatx0_ctrl(base,
951 CIF_ISP_CSI0_DMATX0_VC(1) |
952 CIF_ISP_CSI0_DMATX0_SIMG_SWP |
953 CIF_ISP_CSI0_DMATX0_SIMG_MODE);
954 mi_raw0_set_size(base, in_size);
955 mi_raw0_set_offs(base, 0);
956 mi_raw0_set_length(base, 0);
957 mi_raw0_set_irq_offs(base, 0);
958 /* dummy buf for raw first address shadow */
959 mi_raw0_set_addr(base, stream->dummy_buf.dma_addr);
960 mi_ctrl2(base, CIF_MI_CTRL2_MIPI_RAW0_AUTO_UPDATE);
961 if (stream->id == RKISP1_STREAM_RAW)
962 stream->u.raw.pre_stop = false;
963
964 return 0;
965 }
966
mp_enable_mi(struct rkisp1_stream * stream)967 static void mp_enable_mi(struct rkisp1_stream *stream)
968 {
969 void __iomem *base = stream->ispdev->base_addr;
970 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
971
972 mi_ctrl_mp_disable(base);
973 if (isp_fmt->fmt_type == FMT_BAYER)
974 mi_ctrl_mpraw_enable(base);
975 else if (isp_fmt->fmt_type == FMT_YUV)
976 mi_ctrl_mpyuv_enable(base);
977 }
978
sp_enable_mi(struct rkisp1_stream * stream)979 static void sp_enable_mi(struct rkisp1_stream *stream)
980 {
981 void __iomem *base = stream->ispdev->base_addr;
982
983 mi_ctrl_spyuv_enable(base);
984 }
985
raw_enable_mi(struct rkisp1_stream * stream)986 static void raw_enable_mi(struct rkisp1_stream *stream)
987 {
988 void __iomem *base = stream->ispdev->base_addr;
989
990 mi_mipi_raw0_enable(base);
991 }
992
mp_disable_mi(struct rkisp1_stream * stream)993 static void mp_disable_mi(struct rkisp1_stream *stream)
994 {
995 void __iomem *base = stream->ispdev->base_addr;
996
997 mi_ctrl_mp_disable(base);
998 }
999
sp_disable_mi(struct rkisp1_stream * stream)1000 static void sp_disable_mi(struct rkisp1_stream *stream)
1001 {
1002 void __iomem *base = stream->ispdev->base_addr;
1003
1004 mi_ctrl_spyuv_disable(base);
1005 }
1006
update_dmatx0(struct rkisp1_stream * stream)1007 static void update_dmatx0(struct rkisp1_stream *stream)
1008 {
1009 void __iomem *base = stream->ispdev->base_addr;
1010 struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
1011
1012 if (stream->next_buf)
1013 mi_raw0_set_addr(base,
1014 stream->next_buf->buff_addr[RKISP1_PLANE_Y]);
1015 else
1016 mi_raw0_set_addr(base, dummy_buf->dma_addr);
1017 }
1018
1019 /* Update buffer info to memory interface, it's called in interrupt */
update_mi(struct rkisp1_stream * stream)1020 static void update_mi(struct rkisp1_stream *stream)
1021 {
1022 struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
1023
1024 /* The dummy space allocated by dma_alloc_coherent is used, we can
1025 * throw data to it if there is no available buffer.
1026 */
1027 if (stream->next_buf) {
1028 mi_set_y_addr(stream,
1029 stream->next_buf->buff_addr[RKISP1_PLANE_Y]);
1030 mi_set_cb_addr(stream,
1031 stream->next_buf->buff_addr[RKISP1_PLANE_CB]);
1032 mi_set_cr_addr(stream,
1033 stream->next_buf->buff_addr[RKISP1_PLANE_CR]);
1034 } else {
1035 v4l2_dbg(1, rkisp1_debug, &stream->ispdev->v4l2_dev,
1036 "stream %d: to dummy buf\n", stream->id);
1037 mi_set_y_addr(stream, dummy_buf->dma_addr);
1038 mi_set_cb_addr(stream, dummy_buf->dma_addr);
1039 mi_set_cr_addr(stream, dummy_buf->dma_addr);
1040 }
1041
1042 mi_set_y_offset(stream, 0);
1043 mi_set_cb_offset(stream, 0);
1044 mi_set_cr_offset(stream, 0);
1045 }
1046
mp_stop_mi(struct rkisp1_stream * stream)1047 static void mp_stop_mi(struct rkisp1_stream *stream)
1048 {
1049 if (!stream->streaming)
1050 return;
1051 mi_frame_end_int_clear(stream);
1052 stream->ops->disable_mi(stream);
1053 }
1054
sp_stop_mi(struct rkisp1_stream * stream)1055 static void sp_stop_mi(struct rkisp1_stream *stream)
1056 {
1057 if (!stream->streaming)
1058 return;
1059 mi_frame_end_int_clear(stream);
1060 stream->ops->disable_mi(stream);
1061 }
1062
raw_stop_mi(struct rkisp1_stream * stream)1063 static void raw_stop_mi(struct rkisp1_stream *stream)
1064 {
1065 void __iomem *base = stream->ispdev->base_addr;
1066
1067 if (!stream->streaming)
1068 return;
1069 mi_mipi_raw0_disable(base);
1070 }
1071
1072 static struct streams_ops rkisp1_mp_streams_ops = {
1073 .config_mi = mp_config_mi,
1074 .enable_mi = mp_enable_mi,
1075 .disable_mi = mp_disable_mi,
1076 .stop_mi = mp_stop_mi,
1077 .set_data_path = mp_set_data_path,
1078 .is_stream_stopped = mp_is_stream_stopped,
1079 .update_mi = update_mi,
1080 };
1081
1082 static struct streams_ops rkisp1_sp_streams_ops = {
1083 .config_mi = sp_config_mi,
1084 .enable_mi = sp_enable_mi,
1085 .disable_mi = sp_disable_mi,
1086 .stop_mi = sp_stop_mi,
1087 .set_data_path = sp_set_data_path,
1088 .is_stream_stopped = sp_is_stream_stopped,
1089 .update_mi = update_mi,
1090 };
1091
1092 static struct streams_ops rkisp1_raw_streams_ops = {
1093 .config_mi = raw_config_mi,
1094 .enable_mi = raw_enable_mi,
1095 .stop_mi = raw_stop_mi,
1096 .update_mi = update_dmatx0,
1097 };
1098
1099 /*
1100 * This function is called when a frame end come. The next frame
1101 * is processing and we should set up buffer for next-next frame,
1102 * otherwise it will overflow.
1103 */
mi_frame_end(struct rkisp1_stream * stream)1104 static int mi_frame_end(struct rkisp1_stream *stream)
1105 {
1106 struct rkisp1_device *isp_dev = stream->ispdev;
1107 struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev;
1108 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1109 bool interlaced = stream->interlaced;
1110 unsigned long lock_flags = 0;
1111 int i = 0;
1112
1113 if (stream->curr_buf &&
1114 (!interlaced ||
1115 (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1116 stream->u.sp.field == RKISP_FIELD_EVEN))) {
1117 u64 ns = ktime_get_ns();
1118
1119 /* Dequeue a filled buffer */
1120 for (i = 0; i < isp_fmt->mplanes; i++) {
1121 u32 payload_size =
1122 stream->out_fmt.plane_fmt[i].sizeimage;
1123 vb2_set_plane_payload(
1124 &stream->curr_buf->vb.vb2_buf, i,
1125 payload_size);
1126 }
1127 stream->curr_buf->vb.sequence =
1128 atomic_read(&isp_sd->frm_sync_seq) - 1;
1129 stream->curr_buf->vb.vb2_buf.timestamp = ns;
1130 vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
1131 VB2_BUF_STATE_DONE);
1132 stream->curr_buf = NULL;
1133 }
1134
1135 if (!interlaced ||
1136 (stream->curr_buf == stream->next_buf &&
1137 stream->u.sp.field == RKISP_FIELD_ODD)) {
1138 /* Next frame is writing to it
1139 * Interlaced: odd field next buffer address
1140 */
1141 stream->curr_buf = stream->next_buf;
1142 stream->next_buf = NULL;
1143
1144 /* Set up an empty buffer for the next-next frame */
1145 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1146 if (!list_empty(&stream->buf_queue)) {
1147 stream->next_buf =
1148 list_first_entry(&stream->buf_queue,
1149 struct rkisp1_buffer,
1150 queue);
1151 list_del(&stream->next_buf->queue);
1152 }
1153 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1154 } else if (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1155 stream->u.sp.field == RKISP_FIELD_EVEN) {
1156 /* Interlaced: event field next buffer address */
1157 if (stream->next_buf) {
1158 stream->next_buf->buff_addr[RKISP1_PLANE_Y] +=
1159 stream->u.sp.vir_offs;
1160 stream->next_buf->buff_addr[RKISP1_PLANE_CB] +=
1161 stream->u.sp.vir_offs;
1162 stream->next_buf->buff_addr[RKISP1_PLANE_CR] +=
1163 stream->u.sp.vir_offs;
1164 }
1165 stream->curr_buf = stream->next_buf;
1166 }
1167
1168 stream->ops->update_mi(stream);
1169
1170 if (interlaced)
1171 stream->u.sp.field_rec = stream->u.sp.field;
1172
1173 return 0;
1174 }
1175
1176 /***************************** vb2 operations*******************************/
1177
1178 /*
1179 * Set flags and wait, it should stop in interrupt.
1180 * If it didn't, stop it by force.
1181 */
rkisp1_stream_stop(struct rkisp1_stream * stream)1182 static void rkisp1_stream_stop(struct rkisp1_stream *stream)
1183 {
1184 struct rkisp1_device *dev = stream->ispdev;
1185 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1186 int ret = 0;
1187
1188 stream->stopping = true;
1189 stream->ops->stop_mi(stream);
1190 if (dev->isp_state == ISP_START &&
1191 dev->isp_inp != INP_DMARX_ISP) {
1192 ret = wait_event_timeout(stream->done,
1193 !stream->streaming,
1194 msecs_to_jiffies(1000));
1195 if (!ret) {
1196 v4l2_warn(v4l2_dev, "waiting on event return error %d\n", ret);
1197 stream->stopping = false;
1198 stream->streaming = false;
1199 }
1200 } else {
1201 stream->stopping = false;
1202 stream->streaming = false;
1203 }
1204
1205 if (stream->id != RKISP1_STREAM_RAW) {
1206 disable_dcrop(stream, true);
1207 disable_rsz(stream, true);
1208 }
1209
1210 stream->burst =
1211 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1212 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1213 stream->interlaced = false;
1214 }
1215
1216 /*
1217 * Most of registers inside rockchip isp1 have shadow register since
1218 * they must be not changed during processing a frame.
1219 * Usually, each sub-module updates its shadow register after
1220 * processing the last pixel of a frame.
1221 */
rkisp1_start(struct rkisp1_stream * stream)1222 static int rkisp1_start(struct rkisp1_stream *stream)
1223 {
1224 void __iomem *base = stream->ispdev->base_addr;
1225 struct rkisp1_device *dev = stream->ispdev;
1226 bool other_streaming = false;
1227 int i, ret;
1228
1229 for (i = 0; i < RKISP1_MAX_STREAM; i++) {
1230 if (i != stream->id &&
1231 dev->stream[i].streaming) {
1232 other_streaming = true;
1233 break;
1234 }
1235 }
1236
1237 /* stream raw need mi_cfg_upd to update first base address shadow
1238 * config raw in first stream (sp/mp), and enable when raw stream open.
1239 */
1240 if (!other_streaming &&
1241 stream->id == RKISP1_STREAM_RAW) {
1242 v4l2_err(&dev->v4l2_dev,
1243 "stream raw only support to open after stream mp/sp");
1244 return -EINVAL;
1245 }
1246
1247 #if RKISP1_RK3326_USE_OLDMIPI
1248 if (dev->isp_ver == ISP_V13)
1249 #else
1250 if (dev->isp_ver == ISP_V12 ||
1251 dev->isp_ver == ISP_V13)
1252 #endif
1253 raw_config_mi(stream);
1254
1255 if (stream->ops->set_data_path)
1256 stream->ops->set_data_path(base);
1257 ret = stream->ops->config_mi(stream);
1258 if (ret)
1259 return ret;
1260
1261 /* for mp/sp Set up an buffer for the next frame */
1262 if (stream->id != RKISP1_STREAM_RAW)
1263 mi_frame_end(stream);
1264 stream->ops->enable_mi(stream);
1265 /* It's safe to config ACTIVE and SHADOW regs for the
1266 * first stream. While when the second is starting, do NOT
1267 * force_cfg_update() because it also update the first one.
1268 *
1269 * The latter case would drop one more buf(that is 2) since
1270 * there's not buf in shadow when the second FE received. This's
1271 * also required because the sencond FE maybe corrupt especially
1272 * when run at 120fps.
1273 */
1274 if (!other_streaming) {
1275 force_cfg_update(base);
1276 mi_frame_end(stream);
1277 }
1278 stream->streaming = true;
1279
1280 return 0;
1281 }
1282
rkisp1_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])1283 static int rkisp1_queue_setup(struct vb2_queue *queue,
1284 unsigned int *num_buffers,
1285 unsigned int *num_planes,
1286 unsigned int sizes[],
1287 struct device *alloc_ctxs[])
1288 {
1289 struct rkisp1_stream *stream = queue->drv_priv;
1290 struct rkisp1_device *dev = stream->ispdev;
1291 const struct v4l2_pix_format_mplane *pixm = NULL;
1292 const struct capture_fmt *isp_fmt = NULL;
1293 u32 i;
1294
1295 pixm = &stream->out_fmt;
1296 isp_fmt = &stream->out_isp_fmt;
1297 *num_planes = isp_fmt->mplanes;
1298
1299 for (i = 0; i < isp_fmt->mplanes; i++) {
1300 const struct v4l2_plane_pix_format *plane_fmt;
1301
1302 plane_fmt = &pixm->plane_fmt[i];
1303 sizes[i] = plane_fmt->sizeimage;
1304 }
1305
1306 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
1307 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
1308
1309 return 0;
1310 }
1311
1312 /*
1313 * The vb2_buffer are stored in rkisp1_buffer, in order to unify
1314 * mplane buffer and none-mplane buffer.
1315 */
rkisp1_buf_queue(struct vb2_buffer * vb)1316 static void rkisp1_buf_queue(struct vb2_buffer *vb)
1317 {
1318 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1319 struct rkisp1_buffer *ispbuf = to_rkisp1_buffer(vbuf);
1320 struct vb2_queue *queue = vb->vb2_queue;
1321 struct rkisp1_stream *stream = queue->drv_priv;
1322 unsigned long lock_flags = 0;
1323 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
1324 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1325 int i;
1326
1327 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
1328 for (i = 0; i < isp_fmt->mplanes; i++) {
1329 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
1330 if (stream->id == RKISP1_STREAM_RAW) {
1331 /* for check dmatx to ddr complete */
1332 u32 sizeimage = pixm->plane_fmt[0].sizeimage;
1333 u32 *buf = vb2_plane_vaddr(vb, 0);
1334
1335 if (buf) {
1336 *buf = RKISP1_DMATX_CHECK;
1337 *(buf + sizeimage / 4 - 1) = RKISP1_DMATX_CHECK;
1338 }
1339 }
1340 }
1341
1342 /*
1343 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
1344 * memory plane formats, so calculate the size explicitly.
1345 */
1346 if (isp_fmt->mplanes == 1) {
1347 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
1348 ispbuf->buff_addr[i + 1] = (i == 0) ?
1349 ispbuf->buff_addr[i] +
1350 pixm->plane_fmt[i].bytesperline *
1351 pixm->height :
1352 ispbuf->buff_addr[i] +
1353 pixm->plane_fmt[i].sizeimage;
1354 }
1355 }
1356
1357 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1358
1359 /* XXX: replace dummy to speed up */
1360 if (stream->streaming &&
1361 !stream->next_buf &&
1362 !stream->interlaced &&
1363 stream->id != RKISP1_STREAM_RAW &&
1364 atomic_read(&stream->ispdev->isp_sdev.frm_sync_seq) == 0) {
1365 stream->next_buf = ispbuf;
1366 stream->ops->update_mi(stream);
1367 } else {
1368 list_add_tail(&ispbuf->queue, &stream->buf_queue);
1369 }
1370 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1371 }
1372
rkisp1_create_dummy_buf(struct rkisp1_stream * stream)1373 static int rkisp1_create_dummy_buf(struct rkisp1_stream *stream)
1374 {
1375 struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
1376 struct rkisp1_device *dev = stream->ispdev;
1377
1378 /* get a maximum size */
1379 dummy_buf->size = max3(stream->out_fmt.plane_fmt[0].bytesperline *
1380 stream->out_fmt.height,
1381 stream->out_fmt.plane_fmt[1].sizeimage,
1382 stream->out_fmt.plane_fmt[2].sizeimage);
1383 if (dev->active_sensor &&
1384 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY &&
1385 (dev->isp_ver == ISP_V12 ||
1386 dev->isp_ver == ISP_V13)) {
1387 u32 in_size;
1388 struct rkisp1_stream *raw = &dev->stream[RKISP1_STREAM_RAW];
1389
1390 in_size = raw->out_fmt.plane_fmt[0].sizeimage;
1391 dummy_buf->size = max(dummy_buf->size, in_size);
1392 }
1393
1394 dummy_buf->vaddr = dma_alloc_coherent(dev->dev, dummy_buf->size,
1395 &dummy_buf->dma_addr,
1396 GFP_KERNEL);
1397 if (!dummy_buf->vaddr) {
1398 v4l2_err(&dev->v4l2_dev,
1399 "Failed to allocate the memory for dummy buffer\n");
1400 return -ENOMEM;
1401 }
1402
1403 return 0;
1404 }
1405
rkisp1_destroy_dummy_buf(struct rkisp1_stream * stream)1406 static void rkisp1_destroy_dummy_buf(struct rkisp1_stream *stream)
1407 {
1408 struct rkisp1_dummy_buffer *dummy_buf = &stream->dummy_buf;
1409 struct rkisp1_device *dev = stream->ispdev;
1410
1411 dma_free_coherent(dev->dev, dummy_buf->size,
1412 dummy_buf->vaddr, dummy_buf->dma_addr);
1413 }
1414
rkisp1_stop_streaming(struct vb2_queue * queue)1415 static void rkisp1_stop_streaming(struct vb2_queue *queue)
1416 {
1417 struct rkisp1_stream *stream = queue->drv_priv;
1418 struct rkisp1_vdev_node *node = &stream->vnode;
1419 struct rkisp1_device *dev = stream->ispdev;
1420 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1421 struct rkisp1_buffer *buf;
1422 unsigned long lock_flags = 0;
1423 int ret;
1424
1425 rkisp1_stream_stop(stream);
1426 /* call to the other devices */
1427 media_pipeline_stop(&node->vdev.entity);
1428 ret = dev->pipe.set_stream(&dev->pipe, false);
1429 if (ret < 0)
1430 v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
1431 ret);
1432
1433 /* release buffers */
1434 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1435 if (stream->curr_buf) {
1436 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
1437 if (stream->curr_buf == stream->next_buf)
1438 stream->next_buf = NULL;
1439 stream->curr_buf = NULL;
1440 }
1441 if (stream->next_buf) {
1442 list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
1443 stream->next_buf = NULL;
1444 }
1445 while (!list_empty(&stream->buf_queue)) {
1446 buf = list_first_entry(&stream->buf_queue,
1447 struct rkisp1_buffer, queue);
1448 list_del(&buf->queue);
1449 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1450 }
1451 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1452
1453 ret = dev->pipe.close(&dev->pipe);
1454 if (ret < 0)
1455 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1456 rkisp1_destroy_dummy_buf(stream);
1457 }
1458
rkisp1_stream_start(struct rkisp1_stream * stream)1459 static int rkisp1_stream_start(struct rkisp1_stream *stream)
1460 {
1461 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
1462 struct rkisp1_device *dev = stream->ispdev;
1463 struct rkisp1_stream *other = &dev->stream[stream->id ^ 1];
1464 bool async = false;
1465 int ret;
1466
1467 /* STREAM RAW don't have rsz and dcrop */
1468 if (stream->id == RKISP1_STREAM_RAW)
1469 goto end;
1470
1471 if (other->streaming)
1472 async = true;
1473
1474 ret = rkisp1_config_rsz(stream, async);
1475 if (ret < 0) {
1476 v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret);
1477 return ret;
1478 }
1479
1480 /*
1481 * can't be async now, otherwise the latter started stream fails to
1482 * produce mi interrupt.
1483 */
1484 ret = rkisp1_config_dcrop(stream, false);
1485 if (ret < 0) {
1486 v4l2_err(v4l2_dev, "config dcrop failed with error %d\n", ret);
1487 return ret;
1488 }
1489
1490 end:
1491 return rkisp1_start(stream);
1492 }
1493
1494 static int
rkisp1_start_streaming(struct vb2_queue * queue,unsigned int count)1495 rkisp1_start_streaming(struct vb2_queue *queue, unsigned int count)
1496 {
1497 struct rkisp1_stream *stream = queue->drv_priv;
1498 struct rkisp1_vdev_node *node = &stream->vnode;
1499 struct rkisp1_device *dev = stream->ispdev;
1500 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1501 int ret;
1502 unsigned int i;
1503
1504 if (WARN_ON(stream->streaming))
1505 return -EBUSY;
1506
1507 if (dev->isp_inp != INP_DMARX_ISP) {
1508 /* Always update sensor info in case media topology changed */
1509 ret = rkisp1_update_sensor_info(dev);
1510 if (ret < 0) {
1511 v4l2_err(v4l2_dev,
1512 "update sensor info failed %d\n",
1513 ret);
1514 goto buffer_done;
1515 }
1516 }
1517
1518 if (dev->active_sensor &&
1519 dev->active_sensor->fmt.format.field ==
1520 V4L2_FIELD_INTERLACED) {
1521 if (stream->id != RKISP1_STREAM_SP) {
1522 v4l2_err(v4l2_dev,
1523 "only selfpath support interlaced\n");
1524 ret = -EINVAL;
1525 goto buffer_done;
1526 }
1527 stream->interlaced = true;
1528 stream->u.sp.field = RKISP_FIELD_INVAL;
1529 stream->u.sp.field_rec = RKISP_FIELD_INVAL;
1530 }
1531
1532 ret = rkisp1_create_dummy_buf(stream);
1533 if (ret < 0)
1534 goto buffer_done;
1535
1536 /* enable clocks/power-domains */
1537 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
1538 if (ret < 0) {
1539 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", ret);
1540 goto destroy_dummy_buf;
1541 }
1542
1543 /* configure stream hardware to start */
1544 ret = rkisp1_stream_start(stream);
1545 if (ret < 0) {
1546 v4l2_err(v4l2_dev, "start streaming failed\n");
1547 goto close_pipe;
1548 }
1549
1550 /* start sub-devices */
1551 ret = dev->pipe.set_stream(&dev->pipe, true);
1552 if (ret < 0)
1553 goto stop_stream;
1554
1555 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
1556 if (ret < 0) {
1557 v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n", ret);
1558 goto pipe_stream_off;
1559 }
1560
1561 return 0;
1562
1563 pipe_stream_off:
1564 dev->pipe.set_stream(&dev->pipe, false);
1565 stop_stream:
1566 rkisp1_stream_stop(stream);
1567 close_pipe:
1568 dev->pipe.close(&dev->pipe);
1569 destroy_dummy_buf:
1570 rkisp1_destroy_dummy_buf(stream);
1571 buffer_done:
1572 for (i = 0; i < queue->num_buffers; ++i) {
1573 struct vb2_buffer *vb;
1574
1575 vb = queue->bufs[i];
1576 if (vb->state == VB2_BUF_STATE_ACTIVE)
1577 vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED);
1578 }
1579
1580 return ret;
1581 }
1582
1583 static struct vb2_ops rkisp1_vb2_ops = {
1584 .queue_setup = rkisp1_queue_setup,
1585 .buf_queue = rkisp1_buf_queue,
1586 .wait_prepare = vb2_ops_wait_prepare,
1587 .wait_finish = vb2_ops_wait_finish,
1588 .stop_streaming = rkisp1_stop_streaming,
1589 .start_streaming = rkisp1_start_streaming,
1590 };
1591
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp1_stream * stream,enum v4l2_buf_type buf_type)1592 static int rkisp_init_vb2_queue(struct vb2_queue *q,
1593 struct rkisp1_stream *stream,
1594 enum v4l2_buf_type buf_type)
1595 {
1596 q->type = buf_type;
1597 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1598 q->drv_priv = stream;
1599 q->ops = &rkisp1_vb2_ops;
1600 q->mem_ops = &vb2_dma_contig_memops;
1601 q->buf_struct_size = sizeof(struct rkisp1_buffer);
1602 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
1603 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1604 q->lock = &stream->ispdev->apilock;
1605 q->dev = stream->ispdev->dev;
1606
1607 return vb2_queue_init(q);
1608 }
1609
1610 /*
1611 * Make sure max resize/output resolution is smaller than
1612 * isp sub device output size. This assumes it's not
1613 * recommended to use ISP scale-up function to get output size
1614 * that exceeds sensor max resolution.
1615 */
restrict_rsz_resolution(struct rkisp1_device * dev,const struct stream_config * config,struct v4l2_rect * max_rsz)1616 static void restrict_rsz_resolution(struct rkisp1_device *dev,
1617 const struct stream_config *config,
1618 struct v4l2_rect *max_rsz)
1619 {
1620 struct v4l2_rect *input_win;
1621
1622 input_win = rkisp1_get_isp_sd_win(&dev->isp_sdev);
1623 max_rsz->width = min_t(int, input_win->width, config->max_rsz_width);
1624 max_rsz->height = min_t(int, input_win->height, config->max_rsz_height);
1625 }
1626
rkisp1_set_fmt(struct rkisp1_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)1627 static int rkisp1_set_fmt(struct rkisp1_stream *stream,
1628 struct v4l2_pix_format_mplane *pixm,
1629 bool try)
1630 {
1631 const struct capture_fmt *fmt;
1632 const struct stream_config *config = stream->config;
1633 struct rkisp1_stream *other_stream;
1634 unsigned int imagsize = 0;
1635 unsigned int planes;
1636 u32 xsubs = 1, ysubs = 1;
1637 unsigned int i;
1638
1639 fmt = find_fmt(stream, pixm->pixelformat);
1640 if (!fmt) {
1641 v4l2_err(&stream->ispdev->v4l2_dev,
1642 "nonsupport pixelformat:%c%c%c%c\n",
1643 pixm->pixelformat,
1644 pixm->pixelformat >> 8,
1645 pixm->pixelformat >> 16,
1646 pixm->pixelformat >> 24);
1647 return -EINVAL;
1648 }
1649
1650 if (stream->id != RKISP1_STREAM_RAW) {
1651 struct v4l2_rect max_rsz;
1652
1653 other_stream =
1654 &stream->ispdev->stream[!stream->id ^ 1];
1655 /* do checks on resolution */
1656 restrict_rsz_resolution(stream->ispdev, config, &max_rsz);
1657 pixm->width = clamp_t(u32, pixm->width,
1658 config->min_rsz_width, max_rsz.width);
1659 pixm->height = clamp_t(u32, pixm->height,
1660 config->min_rsz_height, max_rsz.height);
1661 } else {
1662 other_stream =
1663 &stream->ispdev->stream[RKISP1_STREAM_MP];
1664 }
1665 pixm->num_planes = fmt->mplanes;
1666 pixm->field = V4L2_FIELD_NONE;
1667 /* get quantization from ispsd */
1668 pixm->quantization = stream->ispdev->isp_sdev.quantization;
1669
1670 /* output full range by default, take effect in isp_params */
1671 if (!pixm->quantization)
1672 pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1673 /* can not change quantization when stream-on */
1674 if (other_stream->streaming)
1675 pixm->quantization = other_stream->out_fmt.quantization;
1676
1677 /* calculate size */
1678 fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
1679 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
1680 for (i = 0; i < planes; i++) {
1681 struct v4l2_plane_pix_format *plane_fmt;
1682 unsigned int width, height, bytesperline;
1683
1684 plane_fmt = pixm->plane_fmt + i;
1685
1686 if (i == 0) {
1687 width = pixm->width;
1688 height = pixm->height;
1689 } else {
1690 width = pixm->width / xsubs;
1691 height = pixm->height / ysubs;
1692 }
1693
1694 bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
1695 /* stride is only available for sp stream and y plane */
1696 if (stream->id != RKISP1_STREAM_SP || i != 0 ||
1697 plane_fmt->bytesperline < bytesperline)
1698 plane_fmt->bytesperline = bytesperline;
1699
1700 plane_fmt->sizeimage = plane_fmt->bytesperline * height;
1701
1702 imagsize += plane_fmt->sizeimage;
1703 }
1704
1705 /* convert to non-MPLANE format.
1706 * it's important since we want to unify none-MPLANE
1707 * and MPLANE.
1708 */
1709 if (fmt->mplanes == 1)
1710 pixm->plane_fmt[0].sizeimage = imagsize;
1711
1712 if (!try) {
1713 stream->out_isp_fmt = *fmt;
1714 stream->out_fmt = *pixm;
1715
1716 if (stream->id == RKISP1_STREAM_SP) {
1717 stream->u.sp.y_stride =
1718 pixm->plane_fmt[0].bytesperline /
1719 DIV_ROUND_UP(fmt->bpp[0], 8);
1720 } else if (stream->id == RKISP1_STREAM_MP) {
1721 stream->u.mp.raw_enable = (fmt->fmt_type == FMT_BAYER);
1722 }
1723
1724 v4l2_dbg(1, rkisp1_debug, &stream->ispdev->v4l2_dev,
1725 "%s: stream: %d req(%d, %d) out(%d, %d)\n", __func__,
1726 stream->id, pixm->width, pixm->height,
1727 stream->out_fmt.width, stream->out_fmt.height);
1728 }
1729
1730 return 0;
1731 }
1732
rkisp1_fh_open(struct file * filp)1733 int rkisp1_fh_open(struct file *filp)
1734 {
1735 struct rkisp1_stream *stream = video_drvdata(filp);
1736 struct rkisp1_device *dev = stream->ispdev;
1737 int ret;
1738
1739 ret = v4l2_fh_open(filp);
1740 if (!ret) {
1741 atomic_inc(&dev->open_cnt);
1742 ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
1743 if (ret < 0)
1744 vb2_fop_release(filp);
1745 }
1746
1747 return ret;
1748 }
1749
rkisp1_fop_release(struct file * file)1750 int rkisp1_fop_release(struct file *file)
1751 {
1752 struct rkisp1_stream *stream = video_drvdata(file);
1753 struct rkisp1_device *dev = stream->ispdev;
1754 int ret;
1755
1756 ret = vb2_fop_release(file);
1757 if (!ret) {
1758 ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
1759 if (ret < 0)
1760 v4l2_err(&dev->v4l2_dev,
1761 "set pipeline power failed %d\n", ret);
1762 atomic_dec(&dev->open_cnt);
1763 }
1764 return ret;
1765 }
1766
rkisp1_set_stream_def_fmt(struct rkisp1_device * dev,u32 id,u32 width,u32 height,u32 pixelformat)1767 void rkisp1_set_stream_def_fmt(struct rkisp1_device *dev, u32 id,
1768 u32 width, u32 height, u32 pixelformat)
1769 {
1770 struct rkisp1_stream *stream = &dev->stream[id];
1771 struct v4l2_pix_format_mplane pixm;
1772
1773 memset(&pixm, 0, sizeof(pixm));
1774 pixm.pixelformat = pixelformat;
1775 pixm.width = width;
1776 pixm.height = height;
1777 rkisp1_set_fmt(stream, &pixm, false);
1778
1779 stream->dcrop.left = 0;
1780 stream->dcrop.top = 0;
1781 stream->dcrop.width = width;
1782 stream->dcrop.height = height;
1783 }
1784
1785 /************************* v4l2_file_operations***************************/
rkisp1_stream_init(struct rkisp1_device * dev,u32 id)1786 void rkisp1_stream_init(struct rkisp1_device *dev, u32 id)
1787 {
1788 struct rkisp1_stream *stream = &dev->stream[id];
1789
1790 memset(stream, 0, sizeof(*stream));
1791 stream->id = id;
1792 stream->ispdev = dev;
1793
1794 INIT_LIST_HEAD(&stream->buf_queue);
1795 init_waitqueue_head(&stream->done);
1796 spin_lock_init(&stream->vbq_lock);
1797 if (stream->id == RKISP1_STREAM_SP) {
1798 stream->ops = &rkisp1_sp_streams_ops;
1799 stream->config = &rkisp1_sp_stream_config;
1800 } else if (stream->id == RKISP1_STREAM_RAW) {
1801 stream->ops = &rkisp1_raw_streams_ops;
1802 stream->config = &rkisp1_raw_stream_config;
1803 } else {
1804 stream->ops = &rkisp1_mp_streams_ops;
1805 stream->config = &rkisp1_mp_stream_config;
1806 }
1807
1808 stream->streaming = false;
1809 stream->interlaced = false;
1810
1811 stream->burst =
1812 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1813 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1814 }
1815
1816 static const struct v4l2_file_operations rkisp1_fops = {
1817 .open = rkisp1_fh_open,
1818 .release = rkisp1_fop_release,
1819 .unlocked_ioctl = video_ioctl2,
1820 .poll = vb2_fop_poll,
1821 .mmap = vb2_fop_mmap,
1822 };
1823
1824 /*
1825 * mp and sp v4l2_ioctl_ops
1826 */
1827
rkisp1_enum_input(struct file * file,void * priv,struct v4l2_input * input)1828 static int rkisp1_enum_input(struct file *file, void *priv,
1829 struct v4l2_input *input)
1830 {
1831 if (input->index > 0)
1832 return -EINVAL;
1833
1834 input->type = V4L2_INPUT_TYPE_CAMERA;
1835 strlcpy(input->name, "Camera", sizeof(input->name));
1836
1837 return 0;
1838 }
1839
rkisp1_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1840 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1841 struct v4l2_format *f)
1842 {
1843 struct rkisp1_stream *stream = video_drvdata(file);
1844
1845 return rkisp1_set_fmt(stream, &f->fmt.pix_mp, true);
1846 }
1847
rkisp_enum_framesizes(struct file * file,void * prov,struct v4l2_frmsizeenum * fsize)1848 static int rkisp_enum_framesizes(struct file *file, void *prov,
1849 struct v4l2_frmsizeenum *fsize)
1850 {
1851 struct rkisp1_stream *stream = video_drvdata(file);
1852 const struct stream_config *config = stream->config;
1853 struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
1854 struct v4l2_frmsize_discrete *d = &fsize->discrete;
1855 const struct ispsd_out_fmt *input_isp_fmt;
1856 struct v4l2_rect max_rsz;
1857
1858 if (fsize->index != 0)
1859 return -EINVAL;
1860
1861 if (!find_fmt(stream, fsize->pixel_format))
1862 return -EINVAL;
1863
1864 restrict_rsz_resolution(stream->ispdev, config, &max_rsz);
1865
1866 input_isp_fmt = rkisp1_get_ispsd_out_fmt(&stream->ispdev->isp_sdev);
1867 if (input_isp_fmt->fmt_type == FMT_BAYER) {
1868 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1869 d->width = max_rsz.width;
1870 d->height = max_rsz.height;
1871 } else {
1872 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
1873 s->min_width = STREAM_MIN_RSZ_OUTPUT_WIDTH;
1874 s->min_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT;
1875 s->max_width = max_rsz.width;
1876 s->max_height = max_rsz.height;
1877 s->step_width = STREAM_OUTPUT_STEP_WISE;
1878 s->step_height = STREAM_OUTPUT_STEP_WISE;
1879 }
1880
1881 return 0;
1882 }
1883
rkisp_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)1884 static int rkisp_enum_frameintervals(struct file *file, void *fh,
1885 struct v4l2_frmivalenum *fival)
1886 {
1887 const struct rkisp1_stream *stream = video_drvdata(file);
1888 struct rkisp1_device *dev = stream->ispdev;
1889 struct rkisp1_sensor_info *sensor = dev->active_sensor;
1890 struct v4l2_subdev_frame_interval fi;
1891 int ret;
1892
1893 if (fival->index != 0)
1894 return -EINVAL;
1895
1896 if (!sensor) {
1897 /* TODO: active_sensor is NULL if using DMARX path */
1898 v4l2_err(&dev->v4l2_dev, "%s Not active sensor\n", __func__);
1899 return -ENODEV;
1900 }
1901
1902 ret = v4l2_subdev_call(sensor->sd, video, g_frame_interval, &fi);
1903 if (ret && ret != -ENOIOCTLCMD) {
1904 return ret;
1905 } else if (ret == -ENOIOCTLCMD) {
1906 /* Set a default value for sensors not implements ioctl */
1907 fi.interval.numerator = 1;
1908 fi.interval.denominator = 30;
1909 }
1910
1911 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
1912 fival->stepwise.step.numerator = 1;
1913 fival->stepwise.step.denominator = 1;
1914 fival->stepwise.max.numerator = 1;
1915 fival->stepwise.max.denominator = 1;
1916 fival->stepwise.min.numerator = fi.interval.numerator;
1917 fival->stepwise.min.denominator = fi.interval.denominator;
1918
1919 return 0;
1920 }
1921
rkisp1_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)1922 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1923 struct v4l2_fmtdesc *f)
1924 {
1925 struct rkisp1_stream *stream = video_drvdata(file);
1926 const struct capture_fmt *fmt = NULL;
1927
1928 if (f->index >= stream->config->fmt_size)
1929 return -EINVAL;
1930
1931 fmt = &stream->config->fmts[f->index];
1932 f->pixelformat = fmt->fourcc;
1933
1934 return 0;
1935 }
1936
rkisp1_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)1937 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
1938 void *priv, struct v4l2_format *f)
1939 {
1940 struct rkisp1_stream *stream = video_drvdata(file);
1941 struct video_device *vdev = &stream->vnode.vdev;
1942 struct rkisp1_vdev_node *node = vdev_to_node(vdev);
1943 struct rkisp1_device *dev = stream->ispdev;
1944
1945 if (vb2_is_busy(&node->buf_queue)) {
1946 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
1947 return -EBUSY;
1948 }
1949
1950 return rkisp1_set_fmt(stream, &f->fmt.pix_mp, false);
1951 }
1952
rkisp1_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1953 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1954 struct v4l2_format *f)
1955 {
1956 struct rkisp1_stream *stream = video_drvdata(file);
1957
1958 f->fmt.pix_mp = stream->out_fmt;
1959
1960 return 0;
1961 }
1962
rkisp1_g_selection(struct file * file,void * prv,struct v4l2_selection * sel)1963 static int rkisp1_g_selection(struct file *file, void *prv,
1964 struct v4l2_selection *sel)
1965 {
1966 struct rkisp1_stream *stream = video_drvdata(file);
1967 struct rkisp1_device *dev = stream->ispdev;
1968 struct v4l2_rect *dcrop = &stream->dcrop;
1969 struct v4l2_rect *input_win;
1970
1971 input_win = rkisp1_get_isp_sd_win(&dev->isp_sdev);
1972
1973 switch (sel->target) {
1974 case V4L2_SEL_TGT_CROP_BOUNDS:
1975 sel->r.width = input_win->width;
1976 sel->r.height = input_win->height;
1977 sel->r.left = 0;
1978 sel->r.top = 0;
1979 break;
1980 case V4L2_SEL_TGT_CROP:
1981 sel->r = *dcrop;
1982 break;
1983 default:
1984 return -EINVAL;
1985 }
1986
1987 return 0;
1988 }
1989
rkisp1_update_crop(struct rkisp1_stream * stream,struct v4l2_rect * sel,const struct v4l2_rect * in)1990 static struct v4l2_rect *rkisp1_update_crop(struct rkisp1_stream *stream,
1991 struct v4l2_rect *sel,
1992 const struct v4l2_rect *in)
1993 {
1994 /* Not crop for MP bayer raw data and RAW path */
1995 if ((stream->id == RKISP1_STREAM_MP &&
1996 stream->out_isp_fmt.fmt_type == FMT_BAYER) ||
1997 stream->id == RKISP1_STREAM_RAW) {
1998 sel->left = 0;
1999 sel->top = 0;
2000 sel->width = in->width;
2001 sel->height = in->height;
2002 return sel;
2003 }
2004
2005 sel->left = ALIGN(sel->left, 2);
2006 sel->width = ALIGN(sel->width, 2);
2007 sel->left = clamp_t(u32, sel->left, 0,
2008 in->width - STREAM_MIN_MP_SP_INPUT_WIDTH);
2009 sel->top = clamp_t(u32, sel->top, 0,
2010 in->height - STREAM_MIN_MP_SP_INPUT_HEIGHT);
2011 sel->width = clamp_t(u32, sel->width, STREAM_MIN_MP_SP_INPUT_WIDTH,
2012 in->width - sel->left);
2013 sel->height = clamp_t(u32, sel->height, STREAM_MIN_MP_SP_INPUT_HEIGHT,
2014 in->height - sel->top);
2015 return sel;
2016 }
2017
rkisp1_s_selection(struct file * file,void * prv,struct v4l2_selection * sel)2018 static int rkisp1_s_selection(struct file *file, void *prv,
2019 struct v4l2_selection *sel)
2020 {
2021 struct rkisp1_stream *stream = video_drvdata(file);
2022 struct video_device *vdev = &stream->vnode.vdev;
2023 struct rkisp1_vdev_node *node = vdev_to_node(vdev);
2024 struct rkisp1_device *dev = stream->ispdev;
2025 struct v4l2_rect *dcrop = &stream->dcrop;
2026 const struct v4l2_rect *input_win;
2027
2028 if (vb2_is_busy(&node->buf_queue)) {
2029 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
2030 return -EBUSY;
2031 }
2032
2033 input_win = rkisp1_get_isp_sd_win(&dev->isp_sdev);
2034
2035 if (sel->target != V4L2_SEL_TGT_CROP)
2036 return -EINVAL;
2037
2038 if (sel->flags != 0)
2039 return -EINVAL;
2040
2041 *dcrop = *rkisp1_update_crop(stream, &sel->r, input_win);
2042 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
2043 "stream %d crop(%d,%d)/%dx%d\n", stream->id,
2044 dcrop->left, dcrop->top, dcrop->width, dcrop->height);
2045
2046 return 0;
2047 }
2048
rkisp1_querycap(struct file * file,void * priv,struct v4l2_capability * cap)2049 static int rkisp1_querycap(struct file *file, void *priv,
2050 struct v4l2_capability *cap)
2051 {
2052 struct rkisp1_stream *stream = video_drvdata(file);
2053 struct device *dev = stream->ispdev->dev;
2054 struct video_device *vdev = video_devdata(file);
2055
2056 strlcpy(cap->card, vdev->name, sizeof(cap->card));
2057 snprintf(cap->driver, sizeof(cap->driver),
2058 "%s_v%d", dev->driver->name,
2059 stream->ispdev->isp_ver >> 4);
2060 snprintf(cap->bus_info, sizeof(cap->bus_info),
2061 "platform:%s", dev_name(dev));
2062
2063 return 0;
2064 }
2065
2066 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
2067 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2068 .vidioc_querybuf = vb2_ioctl_querybuf,
2069 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2070 .vidioc_qbuf = vb2_ioctl_qbuf,
2071 .vidioc_expbuf = vb2_ioctl_expbuf,
2072 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2073 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
2074 .vidioc_streamon = vb2_ioctl_streamon,
2075 .vidioc_streamoff = vb2_ioctl_streamoff,
2076 .vidioc_enum_input = rkisp1_enum_input,
2077 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
2078 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane,
2079 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
2080 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
2081 .vidioc_s_selection = rkisp1_s_selection,
2082 .vidioc_g_selection = rkisp1_g_selection,
2083 .vidioc_querycap = rkisp1_querycap,
2084 .vidioc_enum_frameintervals = rkisp_enum_frameintervals,
2085 .vidioc_enum_framesizes = rkisp_enum_framesizes,
2086 };
2087
rkisp1_unregister_stream_vdev(struct rkisp1_stream * stream)2088 static void rkisp1_unregister_stream_vdev(struct rkisp1_stream *stream)
2089 {
2090 media_entity_cleanup(&stream->vnode.vdev.entity);
2091 video_unregister_device(&stream->vnode.vdev);
2092 }
2093
rkisp1_unregister_stream_vdevs(struct rkisp1_device * dev)2094 void rkisp1_unregister_stream_vdevs(struct rkisp1_device *dev)
2095 {
2096 struct rkisp1_stream *mp_stream = &dev->stream[RKISP1_STREAM_MP];
2097 struct rkisp1_stream *sp_stream = &dev->stream[RKISP1_STREAM_SP];
2098 struct rkisp1_stream *raw_stream = &dev->stream[RKISP1_STREAM_RAW];
2099
2100 rkisp1_unregister_stream_vdev(mp_stream);
2101
2102 if (dev->isp_ver != ISP_V10_1)
2103 rkisp1_unregister_stream_vdev(sp_stream);
2104
2105 #if RKISP1_RK3326_USE_OLDMIPI
2106 if (dev->isp_ver == ISP_V13)
2107 #else
2108 if (dev->isp_ver == ISP_V12 ||
2109 dev->isp_ver == ISP_V13)
2110 #endif
2111 rkisp1_unregister_stream_vdev(raw_stream);
2112 }
2113
rkisp1_register_stream_vdev(struct rkisp1_stream * stream)2114 static int rkisp1_register_stream_vdev(struct rkisp1_stream *stream)
2115 {
2116 struct rkisp1_device *dev = stream->ispdev;
2117 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2118 struct video_device *vdev = &stream->vnode.vdev;
2119 struct rkisp1_vdev_node *node;
2120 int ret = 0;
2121 char *vdev_name;
2122
2123 switch (stream->id) {
2124 case RKISP1_STREAM_SP:
2125 vdev_name = SP_VDEV_NAME;
2126 if (dev->isp_ver == ISP_V10_1)
2127 return 0;
2128 break;
2129 case RKISP1_STREAM_MP:
2130 vdev_name = MP_VDEV_NAME;
2131 break;
2132 case RKISP1_STREAM_RAW:
2133 vdev_name = RAW_VDEV_NAME;
2134 #if RKISP1_RK3326_USE_OLDMIPI
2135 if (dev->isp_ver != ISP_V13)
2136 #else
2137 if (dev->isp_ver != ISP_V12 &&
2138 dev->isp_ver != ISP_V13)
2139 #endif
2140 return 0;
2141 break;
2142 default:
2143 v4l2_err(v4l2_dev, "Invalid stream\n");
2144 goto unreg;
2145 }
2146 strlcpy(vdev->name, vdev_name, sizeof(vdev->name));
2147 node = vdev_to_node(vdev);
2148
2149 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
2150 vdev->release = video_device_release_empty;
2151 vdev->fops = &rkisp1_fops;
2152 vdev->minor = -1;
2153 vdev->v4l2_dev = v4l2_dev;
2154 vdev->lock = &dev->apilock;
2155 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
2156 V4L2_CAP_STREAMING;
2157 video_set_drvdata(vdev, stream);
2158 vdev->vfl_dir = VFL_DIR_RX;
2159 node->pad.flags = MEDIA_PAD_FL_SINK;
2160
2161 rkisp_init_vb2_queue(&node->buf_queue, stream,
2162 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
2163 vdev->queue = &node->buf_queue;
2164
2165 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2166 if (ret < 0) {
2167 v4l2_err(v4l2_dev,
2168 "video_register_device failed with error %d\n", ret);
2169 return ret;
2170 }
2171
2172 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
2173 if (ret < 0)
2174 goto unreg;
2175
2176 return 0;
2177 unreg:
2178 video_unregister_device(vdev);
2179 return ret;
2180 }
2181
rkisp1_register_stream_vdevs(struct rkisp1_device * dev)2182 int rkisp1_register_stream_vdevs(struct rkisp1_device *dev)
2183 {
2184 struct rkisp1_stream *stream;
2185 int i, j, ret;
2186
2187 for (i = 0; i < RKISP1_MAX_STREAM; i++) {
2188 stream = &dev->stream[i];
2189 stream->ispdev = dev;
2190 ret = rkisp1_register_stream_vdev(stream);
2191 if (ret < 0)
2192 goto err;
2193 }
2194
2195 return 0;
2196 err:
2197 for (j = 0; j < i; j++) {
2198 stream = &dev->stream[j];
2199 rkisp1_unregister_stream_vdev(stream);
2200 }
2201
2202 return ret;
2203 }
2204
2205 /**************** Interrupter Handler ****************/
2206
rkisp1_mi_isr(u32 mis_val,struct rkisp1_device * dev)2207 void rkisp1_mi_isr(u32 mis_val, struct rkisp1_device *dev)
2208 {
2209 unsigned int i;
2210
2211 if (mis_val & CIF_MI_DMA_READY)
2212 rkisp1_dmarx_isr(mis_val, dev);
2213
2214 for (i = 0; i < ARRAY_SIZE(dev->stream); ++i) {
2215 struct rkisp1_stream *stream = &dev->stream[i];
2216
2217 if (!(mis_val & CIF_MI_FRAME(stream)))
2218 continue;
2219
2220 mi_frame_end_int_clear(stream);
2221
2222 if (stream->stopping) {
2223 /*
2224 * Make sure stream is actually stopped, whose state
2225 * can be read from the shadow register, before
2226 * wake_up() thread which would immediately free all
2227 * frame buffers. stop_mi() takes effect at the next
2228 * frame end that sync the configurations to shadow
2229 * regs.
2230 */
2231 if (stream->ops->is_stream_stopped(dev->base_addr)) {
2232 stream->stopping = false;
2233 stream->streaming = false;
2234 wake_up(&stream->done);
2235 }
2236 } else {
2237 mi_frame_end(stream);
2238 }
2239 }
2240 }
2241
rkisp1_mipi_dmatx0_end(u32 status,struct rkisp1_device * dev)2242 void rkisp1_mipi_dmatx0_end(u32 status, struct rkisp1_device *dev)
2243 {
2244 struct rkisp1_stream *stream = &dev->stream[RKISP1_STREAM_RAW];
2245 u32 *buf, end, timeout = 100;
2246
2247 if (!(status & 0x1) || !stream->streaming)
2248 return;
2249
2250 dmatx0_enable(dev->base_addr);
2251 if (stream->stopping) {
2252 /* update dmatx buf to other stream dummy buf if other
2253 * stream don't close, but dmatx is reopen.
2254 * dmatx first buf will write to this.
2255 */
2256 if (!stream->u.raw.pre_stop) {
2257 int i;
2258 struct rkisp1_stream *other = NULL;
2259
2260 for (i = 0; i < RKISP1_MAX_STREAM; i++) {
2261 if (i != stream->id &&
2262 dev->stream[i].streaming) {
2263 other = &dev->stream[i];
2264 break;
2265 }
2266 }
2267
2268 stream->u.raw.pre_stop = true;
2269 if (other) {
2270 mi_raw0_set_addr(dev->base_addr,
2271 other->dummy_buf.dma_addr);
2272 return;
2273 }
2274 }
2275
2276 if (stream->u.raw.pre_stop) {
2277 dmatx0_disable(dev->base_addr);
2278 stream->u.raw.pre_stop = false;
2279 stream->stopping = false;
2280 stream->streaming = false;
2281 wake_up(&stream->done);
2282 }
2283 } else {
2284 if (stream->curr_buf) {
2285 /* for check dmatx to ddr complete */
2286 u32 sizeimage = stream->out_fmt.plane_fmt[0].sizeimage;
2287
2288 buf = (u32 *)vb2_plane_vaddr(&stream->curr_buf->vb.vb2_buf, 0);
2289 if (!buf)
2290 goto out;
2291 end = *(buf + sizeimage / 4 - 1);
2292 while (end == RKISP1_DMATX_CHECK) {
2293 udelay(1);
2294 end = *(buf + sizeimage / 4 - 1);
2295 if (timeout-- == 0) {
2296 /* if shd don't update
2297 * check aclk_isp >= clk_isp
2298 * input equal to sensor output, no crop
2299 */
2300 v4l2_err(&dev->v4l2_dev,
2301 "dmatx to ddr timeout!\n"
2302 "base:0x%x shd:0x%x data:0x%x~0x%x\n",
2303 readl(dev->base_addr + CIF_MI_RAW0_BASE_AD_INIT),
2304 readl(dev->base_addr + CIF_MI_RAW0_BASE_AS_SHD),
2305 *buf, end);
2306 break;
2307 }
2308 }
2309 }
2310 out:
2311 mi_frame_end(stream);
2312 }
2313 }
2314