1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd. */ 3 4 #ifndef _RKISP_EXTERNAL_H 5 #define _RKISP_EXTERNAL_H 6 7 #define RKISP_VICAP_CMD_MODE \ 8 _IOWR('V', BASE_VIDIOC_PRIVATE + 0, struct rkisp_vicap_mode) 9 10 #define RKISP_VICAP_CMD_INIT_BUF \ 11 _IOW('V', BASE_VIDIOC_PRIVATE + 1, int) 12 13 #define RKISP_VICAP_CMD_RX_BUFFER_FREE \ 14 _IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_rx_buf) 15 16 #define RKISP_VICAP_BUF_CNT 3 17 #define RKISP_VICAP_BUF_CNT_MAX 8 18 #define RKISP_RX_BUF_POOL_MAX (RKISP_VICAP_BUF_CNT_MAX * 3) 19 20 struct rkisp_vicap_input { 21 u8 merge_num; 22 u8 index; 23 }; 24 25 enum rkisp_vicap_link { 26 RKISP_VICAP_ONLINE, 27 RKISP_VICAP_RDBK_AIQ, 28 RKISP_VICAP_RDBK_AUTO, 29 }; 30 31 struct rkisp_vicap_mode { 32 char *name; 33 enum rkisp_vicap_link rdbk_mode; 34 35 struct rkisp_vicap_input input; 36 }; 37 38 enum rx_buf_type { 39 BUF_SHORT, 40 BUF_MIDDLE, 41 BUF_LONG, 42 }; 43 44 struct rkisp_rx_buf { 45 struct list_head list; 46 struct dma_buf *dbuf; 47 dma_addr_t dma; 48 u64 timestamp; 49 u32 sequence; 50 u32 type; 51 u32 runtime_us; 52 53 bool is_init; 54 bool is_first; 55 56 bool is_resmem; 57 bool is_switch; 58 59 bool is_uncompact; 60 }; 61 62 #endif 63