1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include "dev.h"
14 #include "regs.h"
15
16 #define CIF_ISP_REQ_BUFS_MIN 0
17
18 static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19 static void rkisp_buf_queue(struct vb2_buffer *vb);
20 static int rkisp_create_dummy_buf(struct rkisp_stream *stream);
21
22 static const struct capture_fmt mp_fmts[] = {
23 /* yuv422 */
24 {
25 .fourcc = V4L2_PIX_FMT_YUYV,
26 .fmt_type = FMT_YUV,
27 .bpp = { 16 },
28 .cplanes = 1,
29 .mplanes = 1,
30 .uv_swap = 0,
31 .write_format = MI_CTRL_MP_WRITE_YUVINT,
32 }, {
33 .fourcc = V4L2_PIX_FMT_YUV422P,
34 .fmt_type = FMT_YUV,
35 .bpp = { 8, 4, 4 },
36 .cplanes = 3,
37 .mplanes = 1,
38 .uv_swap = 0,
39 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
40 }, {
41 .fourcc = V4L2_PIX_FMT_NV16,
42 .fmt_type = FMT_YUV,
43 .bpp = { 8, 16 },
44 .cplanes = 2,
45 .mplanes = 1,
46 .uv_swap = 0,
47 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
48 }, {
49 .fourcc = V4L2_PIX_FMT_NV61,
50 .fmt_type = FMT_YUV,
51 .bpp = { 8, 16 },
52 .cplanes = 2,
53 .mplanes = 1,
54 .uv_swap = 1,
55 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
56 }, {
57 .fourcc = V4L2_PIX_FMT_YUV422M,
58 .fmt_type = FMT_YUV,
59 .bpp = { 8, 8, 8 },
60 .cplanes = 3,
61 .mplanes = 3,
62 .uv_swap = 0,
63 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
64 },
65 /* yuv420 */
66 {
67 .fourcc = V4L2_PIX_FMT_NV21,
68 .fmt_type = FMT_YUV,
69 .bpp = { 8, 16 },
70 .cplanes = 2,
71 .mplanes = 1,
72 .uv_swap = 1,
73 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
74 }, {
75 .fourcc = V4L2_PIX_FMT_NV12,
76 .fmt_type = FMT_YUV,
77 .bpp = { 8, 16 },
78 .cplanes = 2,
79 .mplanes = 1,
80 .uv_swap = 0,
81 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
82 }, {
83 .fourcc = V4L2_PIX_FMT_NV21M,
84 .fmt_type = FMT_YUV,
85 .bpp = { 8, 16 },
86 .cplanes = 2,
87 .mplanes = 2,
88 .uv_swap = 1,
89 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
90 }, {
91 .fourcc = V4L2_PIX_FMT_NV12M,
92 .fmt_type = FMT_YUV,
93 .bpp = { 8, 16 },
94 .cplanes = 2,
95 .mplanes = 2,
96 .uv_swap = 0,
97 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
98 }, {
99 .fourcc = V4L2_PIX_FMT_YUV420,
100 .fmt_type = FMT_YUV,
101 .bpp = { 8, 8, 8 },
102 .cplanes = 3,
103 .mplanes = 1,
104 .uv_swap = 0,
105 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
106 },
107 /* yuv444 */
108 {
109 .fourcc = V4L2_PIX_FMT_YUV444M,
110 .fmt_type = FMT_YUV,
111 .bpp = { 8, 8, 8 },
112 .cplanes = 3,
113 .mplanes = 3,
114 .uv_swap = 0,
115 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
116 },
117 /* raw */
118 {
119 .fourcc = V4L2_PIX_FMT_SRGGB8,
120 .fmt_type = FMT_BAYER,
121 .bpp = { 8 },
122 .mplanes = 1,
123 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
124 }, {
125 .fourcc = V4L2_PIX_FMT_SGRBG8,
126 .fmt_type = FMT_BAYER,
127 .bpp = { 8 },
128 .mplanes = 1,
129 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
130 }, {
131 .fourcc = V4L2_PIX_FMT_SGBRG8,
132 .fmt_type = FMT_BAYER,
133 .bpp = { 8 },
134 .mplanes = 1,
135 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
136 }, {
137 .fourcc = V4L2_PIX_FMT_SBGGR8,
138 .fmt_type = FMT_BAYER,
139 .bpp = { 8 },
140 .mplanes = 1,
141 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
142 }, {
143 .fourcc = V4L2_PIX_FMT_SRGGB10,
144 .fmt_type = FMT_BAYER,
145 .bpp = { 10 },
146 .mplanes = 1,
147 .write_format = MI_CTRL_MP_WRITE_RAW12,
148 }, {
149 .fourcc = V4L2_PIX_FMT_SGRBG10,
150 .fmt_type = FMT_BAYER,
151 .bpp = { 10 },
152 .mplanes = 1,
153 .write_format = MI_CTRL_MP_WRITE_RAW12,
154 }, {
155 .fourcc = V4L2_PIX_FMT_SGBRG10,
156 .fmt_type = FMT_BAYER,
157 .bpp = { 10 },
158 .mplanes = 1,
159 .write_format = MI_CTRL_MP_WRITE_RAW12,
160 }, {
161 .fourcc = V4L2_PIX_FMT_SBGGR10,
162 .fmt_type = FMT_BAYER,
163 .bpp = { 10 },
164 .mplanes = 1,
165 .write_format = MI_CTRL_MP_WRITE_RAW12,
166 }, {
167 .fourcc = V4L2_PIX_FMT_SRGGB12,
168 .fmt_type = FMT_BAYER,
169 .bpp = { 12 },
170 .mplanes = 1,
171 .write_format = MI_CTRL_MP_WRITE_RAW12,
172 }, {
173 .fourcc = V4L2_PIX_FMT_SGRBG12,
174 .fmt_type = FMT_BAYER,
175 .bpp = { 12 },
176 .mplanes = 1,
177 .write_format = MI_CTRL_MP_WRITE_RAW12,
178 }, {
179 .fourcc = V4L2_PIX_FMT_SGBRG12,
180 .fmt_type = FMT_BAYER,
181 .bpp = { 12 },
182 .mplanes = 1,
183 .write_format = MI_CTRL_MP_WRITE_RAW12,
184 }, {
185 .fourcc = V4L2_PIX_FMT_SBGGR12,
186 .fmt_type = FMT_BAYER,
187 .bpp = { 12 },
188 .mplanes = 1,
189 .write_format = MI_CTRL_MP_WRITE_RAW12,
190 },
191 };
192
193 static const struct capture_fmt sp_fmts[] = {
194 /* yuv422 */
195 {
196 .fourcc = V4L2_PIX_FMT_YUYV,
197 .fmt_type = FMT_YUV,
198 .bpp = { 16 },
199 .cplanes = 1,
200 .mplanes = 1,
201 .uv_swap = 0,
202 .write_format = MI_CTRL_SP_WRITE_INT,
203 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
204 }, {
205 .fourcc = V4L2_PIX_FMT_YUV422P,
206 .fmt_type = FMT_YUV,
207 .bpp = { 8, 8, 8 },
208 .cplanes = 3,
209 .mplanes = 1,
210 .uv_swap = 0,
211 .write_format = MI_CTRL_SP_WRITE_PLA,
212 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
213 }, {
214 .fourcc = V4L2_PIX_FMT_NV16,
215 .fmt_type = FMT_YUV,
216 .bpp = { 8, 16 },
217 .cplanes = 2,
218 .mplanes = 1,
219 .uv_swap = 0,
220 .write_format = MI_CTRL_SP_WRITE_SPLA,
221 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
222 }, {
223 .fourcc = V4L2_PIX_FMT_NV61,
224 .fmt_type = FMT_YUV,
225 .bpp = { 8, 16 },
226 .cplanes = 2,
227 .mplanes = 1,
228 .uv_swap = 1,
229 .write_format = MI_CTRL_SP_WRITE_SPLA,
230 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
231 }, {
232 .fourcc = V4L2_PIX_FMT_YUV422M,
233 .fmt_type = FMT_YUV,
234 .bpp = { 8, 8, 8 },
235 .cplanes = 3,
236 .mplanes = 3,
237 .uv_swap = 0,
238 .write_format = MI_CTRL_SP_WRITE_PLA,
239 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
240 },
241 /* yuv420 */
242 {
243 .fourcc = V4L2_PIX_FMT_NV21,
244 .fmt_type = FMT_YUV,
245 .bpp = { 8, 16 },
246 .cplanes = 2,
247 .mplanes = 1,
248 .uv_swap = 1,
249 .write_format = MI_CTRL_SP_WRITE_SPLA,
250 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
251 }, {
252 .fourcc = V4L2_PIX_FMT_NV12,
253 .fmt_type = FMT_YUV,
254 .bpp = { 8, 16 },
255 .cplanes = 2,
256 .mplanes = 1,
257 .uv_swap = 0,
258 .write_format = MI_CTRL_SP_WRITE_SPLA,
259 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
260 }, {
261 .fourcc = V4L2_PIX_FMT_NV21M,
262 .fmt_type = FMT_YUV,
263 .bpp = { 8, 16 },
264 .cplanes = 2,
265 .mplanes = 2,
266 .uv_swap = 1,
267 .write_format = MI_CTRL_SP_WRITE_SPLA,
268 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
269 }, {
270 .fourcc = V4L2_PIX_FMT_NV12M,
271 .fmt_type = FMT_YUV,
272 .bpp = { 8, 16 },
273 .cplanes = 2,
274 .mplanes = 2,
275 .uv_swap = 0,
276 .write_format = MI_CTRL_SP_WRITE_SPLA,
277 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
278 }, {
279 .fourcc = V4L2_PIX_FMT_YUV420,
280 .fmt_type = FMT_YUV,
281 .bpp = { 8, 8, 8 },
282 .cplanes = 3,
283 .mplanes = 1,
284 .uv_swap = 0,
285 .write_format = MI_CTRL_SP_WRITE_PLA,
286 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
287 },
288 /* yuv444 */
289 {
290 .fourcc = V4L2_PIX_FMT_YUV444M,
291 .fmt_type = FMT_YUV,
292 .bpp = { 8, 8, 8 },
293 .cplanes = 3,
294 .mplanes = 3,
295 .uv_swap = 0,
296 .write_format = MI_CTRL_SP_WRITE_PLA,
297 .output_format = MI_CTRL_SP_OUTPUT_YUV444,
298 },
299 /* yuv400 */
300 {
301 .fourcc = V4L2_PIX_FMT_GREY,
302 .fmt_type = FMT_YUV,
303 .bpp = { 8 },
304 .cplanes = 1,
305 .mplanes = 1,
306 .uv_swap = 0,
307 .write_format = MI_CTRL_SP_WRITE_PLA,
308 .output_format = MI_CTRL_SP_OUTPUT_YUV400,
309 },
310 /* rgb */
311 {
312 .fourcc = V4L2_PIX_FMT_XBGR32,
313 .fmt_type = FMT_RGB,
314 .bpp = { 32 },
315 .mplanes = 1,
316 .write_format = MI_CTRL_SP_WRITE_PLA,
317 .output_format = MI_CTRL_SP_OUTPUT_RGB888,
318 }, {
319 .fourcc = V4L2_PIX_FMT_RGB565,
320 .fmt_type = FMT_RGB,
321 .bpp = { 16 },
322 .mplanes = 1,
323 .write_format = MI_CTRL_SP_WRITE_PLA,
324 .output_format = MI_CTRL_SP_OUTPUT_RGB565,
325 }
326 };
327
328 /* configure dual-crop unit */
rkisp_stream_config_dcrop(struct rkisp_stream * stream,bool async)329 static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
330 {
331 struct rkisp_device *dev = stream->ispdev;
332 struct v4l2_rect *dcrop = &stream->dcrop;
333 struct v4l2_rect *input_win;
334
335 /* dual-crop unit get data from isp */
336 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
337
338 if (dcrop->width == input_win->width &&
339 dcrop->height == input_win->height &&
340 dcrop->left == 0 && dcrop->top == 0) {
341 rkisp_disable_dcrop(stream, async);
342 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
343 "stream %d crop disabled\n", stream->id);
344 return 0;
345 }
346
347 rkisp_config_dcrop(stream, dcrop, async);
348
349 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
350 "stream %d crop: %dx%d -> %dx%d\n", stream->id,
351 input_win->width, input_win->height,
352 dcrop->width, dcrop->height);
353
354 return 0;
355 }
356
357 /* configure scale unit */
rkisp_stream_config_rsz(struct rkisp_stream * stream,bool async)358 static int rkisp_stream_config_rsz(struct rkisp_stream *stream, bool async)
359 {
360 struct rkisp_device *dev = stream->ispdev;
361 struct v4l2_pix_format_mplane output_fmt = stream->out_fmt;
362 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
363 struct ispsd_out_fmt *input_isp_fmt =
364 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
365 struct v4l2_rect in_y, in_c, out_y, out_c;
366 u32 xsubs_in = 1, ysubs_in = 1;
367 u32 xsubs_out = 1, ysubs_out = 1;
368
369 if (input_isp_fmt->fmt_type == FMT_BAYER)
370 goto disable;
371
372 /* set input and output sizes for scale calculation */
373 in_y.width = stream->dcrop.width;
374 in_y.height = stream->dcrop.height;
375 out_y.width = output_fmt.width;
376 out_y.height = output_fmt.height;
377
378 /* The size of Cb,Cr are related to the format */
379 if (rkisp_mbus_code_xysubs(input_isp_fmt->mbus_code, &xsubs_in, &ysubs_in)) {
380 v4l2_err(&dev->v4l2_dev, "Not xsubs/ysubs found\n");
381 return -EINVAL;
382 }
383 in_c.width = in_y.width / xsubs_in;
384 in_c.height = in_y.height / ysubs_in;
385
386 if (output_isp_fmt->fmt_type == FMT_YUV) {
387 rkisp_fcc_xysubs(output_isp_fmt->fourcc, &xsubs_out, &ysubs_out);
388 out_c.width = out_y.width / xsubs_out;
389 out_c.height = out_y.height / ysubs_out;
390 } else {
391 out_c.width = out_y.width / xsubs_in;
392 out_c.height = out_y.height / ysubs_in;
393 }
394
395 if (in_c.width == out_c.width && in_c.height == out_c.height)
396 goto disable;
397
398 /* set RSZ input and output */
399 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
400 "stream %d rsz/scale: %dx%d -> %dx%d\n",
401 stream->id, stream->dcrop.width, stream->dcrop.height,
402 output_fmt.width, output_fmt.height);
403 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
404 "chroma scaling %dx%d -> %dx%d\n",
405 in_c.width, in_c.height, out_c.width, out_c.height);
406
407 /* calculate and set scale */
408 rkisp_config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
409
410 if (rkisp_debug)
411 rkisp_dump_rsz_regs(stream);
412
413 return 0;
414
415 disable:
416 rkisp_disable_rsz(stream, async);
417
418 return 0;
419 }
420
421 /***************************** stream operations*******************************/
422
423 /*
424 * memory base addresses should be with respect
425 * to the burst alignment restriction for AXI.
426 */
calc_burst_len(struct rkisp_stream * stream)427 static u32 calc_burst_len(struct rkisp_stream *stream)
428 {
429 struct rkisp_device *dev = stream->ispdev;
430 u32 y_size = stream->out_fmt.plane_fmt[0].bytesperline *
431 stream->out_fmt.height;
432 u32 cb_size = stream->out_fmt.plane_fmt[1].sizeimage;
433 u32 cr_size = stream->out_fmt.plane_fmt[2].sizeimage;
434 u32 cb_offs, cr_offs;
435 u32 bus, burst;
436 int i;
437
438 /* MI128bit and MI64bit */
439 bus = 8;
440 if (dev->isp_ver == ISP_V12 ||
441 dev->isp_ver == ISP_V13)
442 bus = 16;
443
444 /* y/c base addr: burstN * bus alignment */
445 cb_offs = y_size;
446 cr_offs = cr_size ? (cb_size + cb_offs) : 0;
447
448 if (!(cb_offs % (bus * 16)) &&
449 !(cr_offs % (bus * 16)))
450 burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
451 CIF_MI_CTRL_BURST_LEN_CHROM_16;
452 else if (!(cb_offs % (bus * 8)) &&
453 !(cr_offs % (bus * 8)))
454 burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
455 CIF_MI_CTRL_BURST_LEN_CHROM_8;
456 else
457 burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
458 CIF_MI_CTRL_BURST_LEN_CHROM_4;
459
460 if (cb_offs % (bus * 4) ||
461 cr_offs % (bus * 4))
462 v4l2_warn(&dev->v4l2_dev,
463 "%dx%d fmt:0x%x not support, should be %d aligned\n",
464 stream->out_fmt.width,
465 stream->out_fmt.height,
466 stream->out_fmt.pixelformat,
467 (cr_offs == 0) ? bus * 4 : bus * 16);
468
469 stream->burst = burst;
470 for (i = 0; i < RKISP_MAX_STREAM; i++)
471 if (burst > dev->cap_dev.stream[i].burst)
472 burst = dev->cap_dev.stream[i].burst;
473
474 if (stream->interlaced) {
475 if (!stream->out_fmt.width % (bus * 16))
476 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
477 CIF_MI_CTRL_BURST_LEN_CHROM_16;
478 else if (!stream->out_fmt.width % (bus * 8))
479 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
480 CIF_MI_CTRL_BURST_LEN_CHROM_8;
481 else
482 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
483 CIF_MI_CTRL_BURST_LEN_CHROM_4;
484 if (stream->out_fmt.width % (bus * 4))
485 v4l2_warn(&dev->v4l2_dev,
486 "interlaced: width should be %d aligned\n",
487 bus * 4);
488 burst = min(stream->burst, burst);
489 stream->burst = burst;
490 }
491
492 return burst;
493 }
494
495 /*
496 * configure memory interface for mainpath
497 * This should only be called when stream-on
498 */
mp_config_mi(struct rkisp_stream * stream)499 static int mp_config_mi(struct rkisp_stream *stream)
500 {
501 void __iomem *base = stream->ispdev->base_addr;
502
503 /*
504 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
505 * memory plane formats, so calculate the size explicitly.
506 */
507 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
508 stream->out_fmt.height);
509 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
510 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
511 mi_frame_end_int_enable(stream);
512 if (stream->out_isp_fmt.uv_swap)
513 mp_set_uv_swap(base);
514
515 config_mi_ctrl(stream, calc_burst_len(stream));
516 mp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format);
517 mp_mi_ctrl_autoupdate_en(base);
518
519 /* set up first buffer */
520 mi_frame_end(stream, FRAME_INIT);
521 return 0;
522 }
523
mbus_code_sp_in_fmt(u32 in_mbus_code,u32 out_fourcc,u32 * format)524 static int mbus_code_sp_in_fmt(u32 in_mbus_code, u32 out_fourcc, u32 *format)
525 {
526 switch (in_mbus_code) {
527 case MEDIA_BUS_FMT_YUYV8_2X8:
528 *format = MI_CTRL_SP_INPUT_YUV422;
529 break;
530 default:
531 return -EINVAL;
532 }
533
534 /*
535 * Only SP can support output format of YCbCr4:0:0,
536 * and the input format of SP must be YCbCr4:0:0
537 * when outputting YCbCr4:0:0.
538 * The output format of isp is YCbCr4:2:2,
539 * so the CbCr data is discarded here.
540 */
541 if (out_fourcc == V4L2_PIX_FMT_GREY)
542 *format = MI_CTRL_SP_INPUT_YUV400;
543
544 return 0;
545 }
546
547 /*
548 * configure memory interface for selfpath
549 * This should only be called when stream-on
550 */
sp_config_mi(struct rkisp_stream * stream)551 static int sp_config_mi(struct rkisp_stream *stream)
552 {
553 void __iomem *base = stream->ispdev->base_addr;
554 struct rkisp_device *dev = stream->ispdev;
555 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
556 struct ispsd_out_fmt *input_isp_fmt =
557 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
558 u32 sp_in_fmt;
559
560 if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
561 output_isp_fmt->fourcc, &sp_in_fmt)) {
562 v4l2_err(&dev->v4l2_dev, "Can't find the input format\n");
563 return -EINVAL;
564 }
565
566 /*
567 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
568 * memory plane formats, so calculate the size explicitly.
569 */
570 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
571 stream->out_fmt.height);
572 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
573 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
574
575 sp_set_y_width(base, stream->out_fmt.width);
576 if (stream->interlaced) {
577 stream->u.sp.vir_offs =
578 stream->out_fmt.plane_fmt[0].bytesperline;
579 sp_set_y_height(base, stream->out_fmt.height / 2);
580 sp_set_y_line_length(base, stream->u.sp.y_stride * 2);
581 } else {
582 sp_set_y_height(base, stream->out_fmt.height);
583 sp_set_y_line_length(base, stream->u.sp.y_stride);
584 }
585
586 mi_frame_end_int_enable(stream);
587 if (output_isp_fmt->uv_swap)
588 sp_set_uv_swap(base);
589
590 config_mi_ctrl(stream, calc_burst_len(stream));
591 sp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format |
592 sp_in_fmt | output_isp_fmt->output_format);
593
594 sp_mi_ctrl_autoupdate_en(base);
595
596 /* set up first buffer */
597 mi_frame_end(stream, FRAME_INIT);
598 return 0;
599 }
600
mp_enable_mi(struct rkisp_stream * stream)601 static void mp_enable_mi(struct rkisp_stream *stream)
602 {
603 void __iomem *base = stream->ispdev->base_addr;
604 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
605
606 mi_ctrl_mp_disable(base);
607 if (isp_fmt->fmt_type == FMT_BAYER)
608 mi_ctrl_mpraw_enable(base);
609 else if (isp_fmt->fmt_type == FMT_YUV)
610 mi_ctrl_mpyuv_enable(base);
611 }
612
sp_enable_mi(struct rkisp_stream * stream)613 static void sp_enable_mi(struct rkisp_stream *stream)
614 {
615 void __iomem *base = stream->ispdev->base_addr;
616
617 mi_ctrl_spyuv_enable(base);
618 }
619
mp_disable_mi(struct rkisp_stream * stream)620 static void mp_disable_mi(struct rkisp_stream *stream)
621 {
622 struct rkisp_device *dev = stream->ispdev;
623 void __iomem *base = dev->base_addr;
624
625 mi_ctrl_mp_disable(base);
626 }
627
sp_disable_mi(struct rkisp_stream * stream)628 static void sp_disable_mi(struct rkisp_stream *stream)
629 {
630 void __iomem *base = stream->ispdev->base_addr;
631
632 mi_ctrl_spyuv_disable(base);
633 }
634
635 /* Update buffer info to memory interface, it's called in interrupt */
update_mi(struct rkisp_stream * stream)636 static void update_mi(struct rkisp_stream *stream)
637 {
638 struct rkisp_dummy_buffer *dummy_buf = &stream->ispdev->hw_dev->dummy_buf;
639 void __iomem *base = stream->ispdev->base_addr;
640
641 /* The dummy space allocated by dma_alloc_coherent is used, we can
642 * throw data to it if there is no available buffer.
643 */
644 if (stream->next_buf) {
645 mi_set_y_addr(stream,
646 stream->next_buf->buff_addr[RKISP_PLANE_Y]);
647 mi_set_cb_addr(stream,
648 stream->next_buf->buff_addr[RKISP_PLANE_CB]);
649 mi_set_cr_addr(stream,
650 stream->next_buf->buff_addr[RKISP_PLANE_CR]);
651 } else if (dummy_buf->mem_priv) {
652 mi_set_y_addr(stream, dummy_buf->dma_addr);
653 mi_set_cb_addr(stream, dummy_buf->dma_addr);
654 mi_set_cr_addr(stream, dummy_buf->dma_addr);
655 }
656
657 mi_set_y_offset(stream, 0);
658 mi_set_cb_offset(stream, 0);
659 mi_set_cr_offset(stream, 0);
660 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
661 "%s stream:%d Y:0x%x CB:0x%x CR:0x%x\n",
662 __func__, stream->id,
663 readl(base + stream->config->mi.y_base_ad_init),
664 readl(base + stream->config->mi.cb_base_ad_init),
665 readl(base + stream->config->mi.cr_base_ad_init));
666 }
667
mp_stop_mi(struct rkisp_stream * stream)668 static void mp_stop_mi(struct rkisp_stream *stream)
669 {
670 if (!stream->streaming)
671 return;
672 mi_frame_end_int_clear(stream);
673 stream->ops->disable_mi(stream);
674 }
675
sp_stop_mi(struct rkisp_stream * stream)676 static void sp_stop_mi(struct rkisp_stream *stream)
677 {
678 if (!stream->streaming)
679 return;
680 mi_frame_end_int_clear(stream);
681 stream->ops->disable_mi(stream);
682 }
683
684 static struct streams_ops rkisp_mp_streams_ops = {
685 .config_mi = mp_config_mi,
686 .enable_mi = mp_enable_mi,
687 .disable_mi = mp_disable_mi,
688 .stop_mi = mp_stop_mi,
689 .set_data_path = stream_data_path,
690 .is_stream_stopped = mp_is_stream_stopped,
691 .update_mi = update_mi,
692 .frame_end = mi_frame_end,
693 };
694
695 static struct streams_ops rkisp_sp_streams_ops = {
696 .config_mi = sp_config_mi,
697 .enable_mi = sp_enable_mi,
698 .disable_mi = sp_disable_mi,
699 .stop_mi = sp_stop_mi,
700 .set_data_path = stream_data_path,
701 .is_stream_stopped = sp_is_stream_stopped,
702 .update_mi = update_mi,
703 .frame_end = mi_frame_end,
704 };
705
706 /*
707 * This function is called when a frame end come. The next frame
708 * is processing and we should set up buffer for next-next frame,
709 * otherwise it will overflow.
710 */
mi_frame_end(struct rkisp_stream * stream,u32 state)711 static int mi_frame_end(struct rkisp_stream *stream, u32 state)
712 {
713 struct rkisp_device *dev = stream->ispdev;
714 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
715 bool interlaced = stream->interlaced;
716 unsigned long lock_flags = 0;
717 int i = 0;
718
719 if (stream->curr_buf &&
720 (!interlaced ||
721 (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
722 stream->u.sp.field == RKISP_FIELD_EVEN))) {
723 u64 ns = ktime_get_ns();
724
725 /* Dequeue a filled buffer */
726 for (i = 0; i < isp_fmt->mplanes; i++) {
727 u32 payload_size = stream->out_fmt.plane_fmt[i].sizeimage;
728
729 vb2_set_plane_payload(&stream->curr_buf->vb.vb2_buf, i, payload_size);
730 }
731 stream->curr_buf->vb.sequence = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
732 stream->curr_buf->vb.vb2_buf.timestamp = ns;
733 rkisp_stream_buf_done(stream, stream->curr_buf);
734 stream->curr_buf = NULL;
735 }
736
737 if (!interlaced ||
738 (stream->curr_buf == stream->next_buf &&
739 stream->u.sp.field == RKISP_FIELD_ODD)) {
740 /* Next frame is writing to it
741 * Interlaced: odd field next buffer address
742 */
743 stream->curr_buf = stream->next_buf;
744 stream->next_buf = NULL;
745
746 /* Set up an empty buffer for the next-next frame */
747 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
748 if (!list_empty(&stream->buf_queue)) {
749 stream->next_buf =
750 list_first_entry(&stream->buf_queue,
751 struct rkisp_buffer,
752 queue);
753 list_del(&stream->next_buf->queue);
754 }
755 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
756 } else if (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
757 stream->u.sp.field == RKISP_FIELD_EVEN) {
758 /* Interlaced: event field next buffer address */
759 if (stream->next_buf) {
760 stream->next_buf->buff_addr[RKISP_PLANE_Y] +=
761 stream->u.sp.vir_offs;
762 stream->next_buf->buff_addr[RKISP_PLANE_CB] +=
763 stream->u.sp.vir_offs;
764 stream->next_buf->buff_addr[RKISP_PLANE_CR] +=
765 stream->u.sp.vir_offs;
766 }
767 stream->curr_buf = stream->next_buf;
768 }
769
770 stream->ops->update_mi(stream);
771
772 if (interlaced)
773 stream->u.sp.field_rec = stream->u.sp.field;
774
775 return 0;
776 }
777
778 /***************************** vb2 operations*******************************/
779
780 /*
781 * Set flags and wait, it should stop in interrupt.
782 * If it didn't, stop it by force.
783 */
rkisp_stream_stop(struct rkisp_stream * stream)784 static void rkisp_stream_stop(struct rkisp_stream *stream)
785 {
786 struct rkisp_device *dev = stream->ispdev;
787 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
788 int ret = 0;
789
790 stream->stopping = true;
791 stream->ops->stop_mi(stream);
792 if ((dev->isp_state & ISP_START) &&
793 dev->isp_inp != INP_DMARX_ISP &&
794 !dev->hw_dev->is_shutdown) {
795 ret = wait_event_timeout(stream->done,
796 !stream->streaming,
797 msecs_to_jiffies(1000));
798 if (!ret)
799 v4l2_warn(v4l2_dev, "%s id:%d timeout\n",
800 __func__, stream->id);
801 }
802
803 stream->stopping = false;
804 stream->streaming = false;
805
806 if (stream->id == RKISP_STREAM_MP ||
807 stream->id == RKISP_STREAM_SP) {
808 rkisp_disable_dcrop(stream, true);
809 rkisp_disable_rsz(stream, true);
810 }
811
812 stream->burst =
813 CIF_MI_CTRL_BURST_LEN_LUM_16 |
814 CIF_MI_CTRL_BURST_LEN_CHROM_16;
815 stream->interlaced = false;
816 }
817
818 /*
819 * Most of registers inside rockchip isp1 have shadow register since
820 * they must be not changed during processing a frame.
821 * Usually, each sub-module updates its shadow register after
822 * processing the last pixel of a frame.
823 */
rkisp_start(struct rkisp_stream * stream)824 static int rkisp_start(struct rkisp_stream *stream)
825 {
826 int ret;
827
828 if (stream->ops->set_data_path)
829 stream->ops->set_data_path(stream);
830 ret = stream->ops->config_mi(stream);
831 if (ret)
832 return ret;
833
834 stream->ops->enable_mi(stream);
835 stream->streaming = true;
836
837 return 0;
838 }
839
rkisp_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])840 static int rkisp_queue_setup(struct vb2_queue *queue,
841 unsigned int *num_buffers,
842 unsigned int *num_planes,
843 unsigned int sizes[],
844 struct device *alloc_ctxs[])
845 {
846 struct rkisp_stream *stream = queue->drv_priv;
847 struct rkisp_device *dev = stream->ispdev;
848 const struct v4l2_pix_format_mplane *pixm = NULL;
849 const struct capture_fmt *isp_fmt = NULL;
850 u32 i;
851
852 pixm = &stream->out_fmt;
853 isp_fmt = &stream->out_isp_fmt;
854 *num_planes = isp_fmt->mplanes;
855
856 for (i = 0; i < isp_fmt->mplanes; i++) {
857 const struct v4l2_plane_pix_format *plane_fmt;
858
859 plane_fmt = &pixm->plane_fmt[i];
860 /* height to align with 16 when allocating memory
861 * so that Rockchip encoder can use DMA buffer directly
862 */
863 sizes[i] = (isp_fmt->fmt_type == FMT_YUV) ?
864 plane_fmt->sizeimage / pixm->height *
865 ALIGN(pixm->height, 16) :
866 plane_fmt->sizeimage;
867 }
868
869 rkisp_chk_tb_over(dev);
870 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
871 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
872
873 return rkisp_create_dummy_buf(stream);
874 }
875
876 /*
877 * The vb2_buffer are stored in rkisp_buffer, in order to unify
878 * mplane buffer and none-mplane buffer.
879 */
rkisp_buf_queue(struct vb2_buffer * vb)880 static void rkisp_buf_queue(struct vb2_buffer *vb)
881 {
882 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
883 struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf);
884 struct vb2_queue *queue = vb->vb2_queue;
885 struct rkisp_stream *stream = queue->drv_priv;
886 unsigned long lock_flags = 0;
887 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
888 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
889 struct sg_table *sgt;
890 int i;
891
892 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
893 for (i = 0; i < isp_fmt->mplanes; i++) {
894 vb2_plane_vaddr(vb, i);
895 if (stream->ispdev->hw_dev->is_dma_sg_ops) {
896 sgt = vb2_dma_sg_plane_desc(vb, i);
897 ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
898 } else {
899 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
900 }
901 }
902 /*
903 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
904 * memory plane formats, so calculate the size explicitly.
905 */
906 if (isp_fmt->mplanes == 1) {
907 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
908 ispbuf->buff_addr[i + 1] = (i == 0) ?
909 ispbuf->buff_addr[i] +
910 pixm->plane_fmt[i].bytesperline *
911 pixm->height :
912 ispbuf->buff_addr[i] +
913 pixm->plane_fmt[i].sizeimage;
914 }
915 }
916
917 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
918 "stream:%d queue buf:0x%x\n",
919 stream->id, ispbuf->buff_addr[0]);
920
921 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
922 list_add_tail(&ispbuf->queue, &stream->buf_queue);
923 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
924 }
925
rkisp_create_dummy_buf(struct rkisp_stream * stream)926 static int rkisp_create_dummy_buf(struct rkisp_stream *stream)
927 {
928 return rkisp_alloc_common_dummy_buf(stream->ispdev);
929 }
930
rkisp_destroy_dummy_buf(struct rkisp_stream * stream)931 static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream)
932 {
933 struct rkisp_device *dev = stream->ispdev;
934
935 rkisp_free_common_dummy_buf(dev);
936 }
937
destroy_buf_queue(struct rkisp_stream * stream,enum vb2_buffer_state state)938 static void destroy_buf_queue(struct rkisp_stream *stream,
939 enum vb2_buffer_state state)
940 {
941 unsigned long lock_flags = 0;
942 struct rkisp_buffer *buf;
943
944 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
945 if (stream->curr_buf) {
946 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
947 if (stream->curr_buf == stream->next_buf)
948 stream->next_buf = NULL;
949 stream->curr_buf = NULL;
950 }
951 if (stream->next_buf) {
952 list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
953 stream->next_buf = NULL;
954 }
955 while (!list_empty(&stream->buf_queue)) {
956 buf = list_first_entry(&stream->buf_queue,
957 struct rkisp_buffer, queue);
958 list_del(&buf->queue);
959 vb2_buffer_done(&buf->vb.vb2_buf, state);
960 }
961 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
962 }
963
rkisp_stop_streaming(struct vb2_queue * queue)964 static void rkisp_stop_streaming(struct vb2_queue *queue)
965 {
966 struct rkisp_stream *stream = queue->drv_priv;
967 struct rkisp_vdev_node *node = &stream->vnode;
968 struct rkisp_device *dev = stream->ispdev;
969 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
970 int ret;
971
972 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
973 "%s %d\n", __func__, stream->id);
974
975 if (!stream->streaming)
976 return;
977
978 rkisp_stream_stop(stream);
979 media_pipeline_stop(&node->vdev.entity);
980 ret = dev->pipe.set_stream(&dev->pipe, false);
981 if (ret < 0)
982 v4l2_err(v4l2_dev,
983 "pipeline stream-off failed:%d\n", ret);
984
985 /* release buffers */
986 destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
987
988 ret = dev->pipe.close(&dev->pipe);
989 if (ret < 0)
990 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
991 rkisp_destroy_dummy_buf(stream);
992 atomic_dec(&dev->cap_dev.refcnt);
993 tasklet_disable(&stream->buf_done_tasklet);
994 }
995
rkisp_stream_start(struct rkisp_stream * stream)996 static int rkisp_stream_start(struct rkisp_stream *stream)
997 {
998 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
999 struct rkisp_device *dev = stream->ispdev;
1000 struct rkisp_stream *other = &dev->cap_dev.stream[stream->id ^ 1];
1001 bool async = false;
1002 int ret;
1003
1004 if (other->streaming)
1005 async = true;
1006
1007 ret = rkisp_stream_config_rsz(stream, async);
1008 if (ret < 0) {
1009 v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret);
1010 return ret;
1011 }
1012
1013 /*
1014 * can't be async now, otherwise the latter started stream fails to
1015 * produce mi interrupt.
1016 */
1017 ret = rkisp_stream_config_dcrop(stream, false);
1018 if (ret < 0) {
1019 v4l2_err(v4l2_dev, "config dcrop failed with error %d\n", ret);
1020 return ret;
1021 }
1022
1023 return rkisp_start(stream);
1024 }
1025
1026 static int
rkisp_start_streaming(struct vb2_queue * queue,unsigned int count)1027 rkisp_start_streaming(struct vb2_queue *queue, unsigned int count)
1028 {
1029 struct rkisp_stream *stream = queue->drv_priv;
1030 struct rkisp_vdev_node *node = &stream->vnode;
1031 struct rkisp_device *dev = stream->ispdev;
1032 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1033 int ret = -1;
1034
1035 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1036 "%s %d\n", __func__, stream->id);
1037
1038 if (WARN_ON(stream->streaming))
1039 return -EBUSY;
1040
1041 atomic_inc(&dev->cap_dev.refcnt);
1042 if (!dev->isp_inp || !stream->linked) {
1043 v4l2_err(v4l2_dev, "check video link or isp input\n");
1044 goto buffer_done;
1045 }
1046
1047 if (atomic_read(&dev->cap_dev.refcnt) == 1 &&
1048 (dev->isp_inp & INP_CSI || dev->isp_inp & INP_DVP)) {
1049 /* update sensor info when first streaming */
1050 ret = rkisp_update_sensor_info(dev);
1051 if (ret < 0) {
1052 v4l2_err(v4l2_dev,
1053 "update sensor info failed %d\n",
1054 ret);
1055 goto buffer_done;
1056 }
1057 }
1058
1059 if (dev->active_sensor &&
1060 dev->active_sensor->fmt[0].format.field ==
1061 V4L2_FIELD_INTERLACED) {
1062 if (stream->id != RKISP_STREAM_SP) {
1063 v4l2_err(v4l2_dev,
1064 "only selfpath support interlaced\n");
1065 ret = -EINVAL;
1066 goto buffer_done;
1067 }
1068 stream->interlaced = true;
1069 stream->u.sp.field = RKISP_FIELD_INVAL;
1070 stream->u.sp.field_rec = RKISP_FIELD_INVAL;
1071 }
1072
1073 /* enable clocks/power-domains */
1074 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
1075 if (ret < 0) {
1076 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", ret);
1077 goto destroy_dummy_buf;
1078 }
1079
1080 /* configure stream hardware to start */
1081 ret = rkisp_stream_start(stream);
1082 if (ret < 0) {
1083 v4l2_err(v4l2_dev, "start streaming failed\n");
1084 goto close_pipe;
1085 }
1086
1087 /* start sub-devices */
1088 ret = dev->pipe.set_stream(&dev->pipe, true);
1089 if (ret < 0)
1090 goto stop_stream;
1091
1092 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
1093 if (ret < 0) {
1094 v4l2_err(&dev->v4l2_dev,
1095 "start pipeline failed %d\n", ret);
1096 goto pipe_stream_off;
1097 }
1098 tasklet_enable(&stream->buf_done_tasklet);
1099 return 0;
1100
1101 pipe_stream_off:
1102 dev->pipe.set_stream(&dev->pipe, false);
1103 stop_stream:
1104 rkisp_stream_stop(stream);
1105 close_pipe:
1106 dev->pipe.close(&dev->pipe);
1107 destroy_dummy_buf:
1108 rkisp_destroy_dummy_buf(stream);
1109 buffer_done:
1110 destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
1111 atomic_dec(&dev->cap_dev.refcnt);
1112 stream->streaming = false;
1113 return ret;
1114 }
1115
1116 static struct vb2_ops rkisp_vb2_ops = {
1117 .queue_setup = rkisp_queue_setup,
1118 .buf_queue = rkisp_buf_queue,
1119 .wait_prepare = vb2_ops_wait_prepare,
1120 .wait_finish = vb2_ops_wait_finish,
1121 .stop_streaming = rkisp_stop_streaming,
1122 .start_streaming = rkisp_start_streaming,
1123 };
1124
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp_stream * stream,enum v4l2_buf_type buf_type)1125 static int rkisp_init_vb2_queue(struct vb2_queue *q,
1126 struct rkisp_stream *stream,
1127 enum v4l2_buf_type buf_type)
1128 {
1129 q->type = buf_type;
1130 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1131 q->drv_priv = stream;
1132 q->ops = &rkisp_vb2_ops;
1133 q->mem_ops = stream->ispdev->hw_dev->mem_ops;
1134 q->buf_struct_size = sizeof(struct rkisp_buffer);
1135 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
1136 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1137 q->lock = &stream->ispdev->apilock;
1138 q->dev = stream->ispdev->hw_dev->dev;
1139 q->allow_cache_hints = 1;
1140 if (stream->ispdev->hw_dev->is_dma_contig)
1141 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
1142 q->gfp_flags = GFP_DMA32;
1143 return vb2_queue_init(q);
1144 }
1145
rkisp_stream_init(struct rkisp_device * dev,u32 id)1146 static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
1147 {
1148 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1149 struct rkisp_stream *stream;
1150 struct video_device *vdev;
1151 struct rkisp_vdev_node *node;
1152 int ret = 0;
1153
1154 stream = &cap_dev->stream[id];
1155 stream->id = id;
1156 stream->ispdev = dev;
1157 vdev = &stream->vnode.vdev;
1158
1159 INIT_LIST_HEAD(&stream->buf_queue);
1160 init_waitqueue_head(&stream->done);
1161 spin_lock_init(&stream->vbq_lock);
1162
1163 stream->linked = true;
1164 switch (id) {
1165 case RKISP_STREAM_SP:
1166 strlcpy(vdev->name, SP_VDEV_NAME,
1167 sizeof(vdev->name));
1168 stream->ops = &rkisp_sp_streams_ops;
1169 stream->config = &rkisp_sp_stream_config;
1170 stream->config->fmts = sp_fmts;
1171 stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1172 break;
1173 default:
1174 strlcpy(vdev->name, MP_VDEV_NAME,
1175 sizeof(vdev->name));
1176 stream->ops = &rkisp_mp_streams_ops;
1177 stream->config = &rkisp_mp_stream_config;
1178 stream->config->fmts = mp_fmts;
1179 stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1180 }
1181
1182 node = vdev_to_node(vdev);
1183 rkisp_init_vb2_queue(&node->buf_queue, stream,
1184 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
1185 ret = rkisp_register_stream_vdev(stream);
1186 if (ret < 0)
1187 return ret;
1188
1189 stream->streaming = false;
1190 stream->interlaced = false;
1191 stream->burst =
1192 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1193 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1194 atomic_set(&stream->sequence, 0);
1195 return 0;
1196 }
1197
rkisp_register_stream_v1x(struct rkisp_device * dev)1198 int rkisp_register_stream_v1x(struct rkisp_device *dev)
1199 {
1200 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1201 int ret;
1202
1203 ret = rkisp_stream_init(dev, RKISP_STREAM_MP);
1204 if (ret < 0)
1205 goto err;
1206 if (dev->isp_ver != ISP_V10_1) {
1207 ret = rkisp_stream_init(dev, RKISP_STREAM_SP);
1208 if (ret < 0)
1209 goto err_free_mp;
1210 }
1211
1212 return 0;
1213 err_free_mp:
1214 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_MP]);
1215 err:
1216 return ret;
1217 }
1218
rkisp_unregister_stream_v1x(struct rkisp_device * dev)1219 void rkisp_unregister_stream_v1x(struct rkisp_device *dev)
1220 {
1221 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1222 struct rkisp_stream *stream;
1223
1224 stream = &cap_dev->stream[RKISP_STREAM_MP];
1225 rkisp_unregister_stream_vdev(stream);
1226 if (dev->isp_ver != ISP_V10_1) {
1227 stream = &cap_dev->stream[RKISP_STREAM_SP];
1228 rkisp_unregister_stream_vdev(stream);
1229 }
1230 }
1231
rkisp_mi_v1x_isr(u32 mis_val,struct rkisp_device * dev)1232 void rkisp_mi_v1x_isr(u32 mis_val, struct rkisp_device *dev)
1233 {
1234 unsigned int i;
1235
1236 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
1237 "mi isr:0x%x\n", mis_val);
1238
1239 if (mis_val & CIF_MI_DMA_READY)
1240 rkisp_dmarx_isr(mis_val, dev);
1241
1242 for (i = 0; i < RKISP_MAX_STREAM; ++i) {
1243 struct rkisp_stream *stream = &dev->cap_dev.stream[i];
1244
1245 if (!(mis_val & CIF_MI_FRAME(stream)))
1246 continue;
1247
1248 mi_frame_end_int_clear(stream);
1249
1250 if (stream->stopping) {
1251 /*
1252 * Make sure stream is actually stopped, whose state
1253 * can be read from the shadow register, before
1254 * wake_up() thread which would immediately free all
1255 * frame buffers. stop_mi() takes effect at the next
1256 * frame end that sync the configurations to shadow
1257 * regs.
1258 */
1259 if (stream->ops->is_stream_stopped(stream)) {
1260 stream->stopping = false;
1261 stream->streaming = false;
1262 wake_up(&stream->done);
1263 }
1264 } else {
1265 mi_frame_end(stream, FRAME_IRQ);
1266 }
1267 }
1268 }
1269