1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Shunqing Chen <csq@rock-chips.com> 6 */ 7 8 #ifndef __RK_HDMIRX_HDCP_H__ 9 #define __RK_HDMIRX_HDCP_H__ 10 11 #include <linux/miscdevice.h> 12 13 #define HDCP_KEY_SIZE 308 14 #define HDCP_KEY_SEED_SIZE 2 15 16 #define KSV_LEN 5 17 #define HEADER 10 18 #define SHAMAX 20 19 20 #define PRIVATE_KEY_SIZE 280 21 #define KEY_SHA_SIZE 20 22 #define KEY_DATA_SIZE 314 23 #define VENDOR_DATA_SIZE (KEY_DATA_SIZE + 16) 24 25 #define HDMIRX_HDCP1X_ID 13 26 27 #define HDCP_SIG_MAGIC 0x4B534541 /* "AESK" */ 28 #define HDCP_FLG_AES 1 29 30 enum hdmirx_hdcp_enable { 31 HDCP_1X_ENABLE = 0x1, 32 HDCP_2X_ENABLE = 0x2, 33 }; 34 35 struct hdcp_key_data_t { 36 unsigned int signature; 37 unsigned int length; 38 unsigned int crc; 39 unsigned int flags; 40 unsigned char data[0]; 41 }; 42 43 struct rk_hdmirx_hdcp { 44 u8 enable; 45 u8 hdcp_support; 46 int hdcp2_enable; 47 int status; 48 49 struct miscdevice mdev; 50 bool keys_is_load; 51 bool test_key_load; 52 bool aes_encrypt; 53 struct device *dev; 54 struct rk_hdmirx_dev *hdmirx; 55 56 void (*write)(struct rk_hdmirx_dev *hdmirx, int reg, u32 val); 57 u32 (*read)(struct rk_hdmirx_dev *hdmirx, int reg); 58 void (*hpd_config)(struct rk_hdmirx_dev *hdmirx, bool en); 59 bool (*tx_5v_power)(struct rk_hdmirx_dev *hdmirx); 60 int (*hdcp_start)(struct rk_hdmirx_hdcp *hdcp); 61 int (*hdcp_stop)(struct rk_hdmirx_hdcp *hdcp); 62 void (*hdcp2_connect_ctrl)(struct rk_hdmirx_hdcp *hdcp, bool en); 63 }; 64 65 struct rk_hdmirx_hdcp *rk_hdmirx_hdcp_register(struct rk_hdmirx_hdcp *hdcp); 66 void rk_hdmirx_hdcp_unregister(struct rk_hdmirx_hdcp *hdcp); 67 68 #endif /* __RK_HDMIRX_HDCP_H__ */ 69