1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Dingxian Wen <shawn.wen@rock-chips.com>
6 */
7
8 #include <dt-bindings/soc/rockchip-system-status.h>
9 #include <linux/clk.h>
10 #include <linux/cpufreq.h>
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/extcon-provider.h>
15 #include <linux/fs.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/math64.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_platform.h>
24 #include <linux/of_reserved_mem.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regmap.h>
29 #include <linux/reset.h>
30 #include <linux/rk_hdmirx_config.h>
31 #include <linux/rockchip/rockchip_sip.h>
32 #include <linux/seq_file.h>
33 #include <linux/v4l2-dv-timings.h>
34 #include <linux/workqueue.h>
35 #include <media/cec.h>
36 #include <media/cec-notifier.h>
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-dv-timings.h>
41 #include <media/v4l2-event.h>
42 #include <media/v4l2-fh.h>
43 #include <media/v4l2-ioctl.h>
44 #include <media/videobuf2-dma-contig.h>
45 #include <media/videobuf2-v4l2.h>
46 #include <soc/rockchip/rockchip-system-status.h>
47 #include <sound/hdmi-codec.h>
48 #include "rk_hdmirx.h"
49 #include "rk_hdmirx_cec.h"
50 #include "rk_hdmirx_hdcp.h"
51
52 static struct class *hdmirx_class;
53 static int debug;
54 module_param(debug, int, 0644);
55 MODULE_PARM_DESC(debug, "debug level (0-3)");
56
57 #define RK_HDMIRX_DRVNAME "rk_hdmirx"
58 #define EDID_NUM_BLOCKS_MAX 2
59 #define EDID_BLOCK_SIZE 128
60 #define HDMIRX_DEFAULT_TIMING V4L2_DV_BT_CEA_640X480P59_94
61 #define HDMIRX_VDEV_NAME "stream_hdmirx"
62 #define HDMIRX_REQ_BUFS_MIN 2
63 #define HDMIRX_STORED_BIT_WIDTH 8
64 #define IREF_CLK_FREQ_HZ 428571429
65 #define MEMORY_ALIGN_ROUND_UP_BYTES 64
66 #define HDMIRX_PLANE_Y 0
67 #define HDMIRX_PLANE_CBCR 1
68 #define INIT_FIFO_STATE 64
69 #define RK_IRQ_HDMIRX_HDMI 210
70 #define FILTER_FRAME_CNT 6
71 #define CPU_LIMIT_FREQ_KHZ 1200000
72 #define WAIT_PHY_REG_TIME 50
73 #define WAIT_TIMER_LOCK_TIME 50
74 #define WAIT_SIGNAL_LOCK_TIME 600 /* if 5V present: 7ms each time */
75 #define NO_LOCK_CFG_RETRY_TIME 300
76 #define WAIT_LOCK_STABLE_TIME 20
77 #define WAIT_AVI_PKT_TIME 300
78
79 #define is_validfs(x) (x == 32000 || \
80 x == 44100 || \
81 x == 48000 || \
82 x == 88200 || \
83 x == 96000 || \
84 x == 176400 || \
85 x == 192000 || \
86 x == 768000)
87
88 struct hdmirx_audiostate {
89 struct platform_device *pdev;
90 u32 hdmirx_aud_clkrate;
91 u32 fs_audio;
92 u32 ch_audio;
93 u32 ctsn_flag;
94 u32 fifo_flag;
95 int init_state;
96 int pre_state;
97 bool fifo_int;
98 bool audio_enabled;
99 };
100
101 enum hdmirx_pix_fmt {
102 HDMIRX_RGB888 = 0,
103 HDMIRX_YUV422 = 1,
104 HDMIRX_YUV444 = 2,
105 HDMIRX_YUV420 = 3,
106 };
107
108 static const char * const pix_fmt_str[] = {
109 "RGB888",
110 "YUV422",
111 "YUV444",
112 "YUV420",
113 };
114
115 enum ddr_store_fmt {
116 STORE_RGB888 = 0,
117 STORE_RGBA_ARGB,
118 STORE_YUV420_8BIT,
119 STORE_YUV420_10BIT,
120 STORE_YUV422_8BIT,
121 STORE_YUV422_10BIT,
122 STORE_YUV444_8BIT,
123 STORE_YUV420_16BIT = 8,
124 STORE_YUV422_16BIT = 9,
125 };
126
127 enum hdmirx_reg_attr {
128 HDMIRX_ATTR_RW = 0,
129 HDMIRX_ATTR_RO = 1,
130 HDMIRX_ATTR_WO = 2,
131 HDMIRX_ATTR_RE = 3,
132 };
133
134 enum hdmirx_edid_version {
135 HDMIRX_EDID_USER = 0,
136 HDMIRX_EDID_340M = 1,
137 HDMIRX_EDID_600M = 2,
138 };
139
140 struct hdmirx_reg_table {
141 int reg_base;
142 int reg_end;
143 enum hdmirx_reg_attr attr;
144 };
145
146 struct hdmirx_buffer {
147 struct vb2_v4l2_buffer vb;
148 struct list_head queue;
149 union {
150 u32 buff_addr[VIDEO_MAX_PLANES];
151 void *vaddr[VIDEO_MAX_PLANES];
152 };
153 };
154
155 struct hdmirx_output_fmt {
156 u32 fourcc;
157 u8 cplanes;
158 u8 mplanes;
159 u8 bpp[VIDEO_MAX_PLANES];
160 };
161
162 struct hdmirx_stream {
163 struct rk_hdmirx_dev *hdmirx_dev;
164 struct video_device vdev;
165 struct vb2_queue buf_queue;
166 struct list_head buf_head;
167 struct hdmirx_buffer *curr_buf;
168 struct hdmirx_buffer *next_buf;
169 struct v4l2_pix_format_mplane pixm;
170 const struct hdmirx_output_fmt *out_fmt;
171 struct mutex vlock;
172 spinlock_t vbq_lock;
173 bool stopping;
174 wait_queue_head_t wq_stopped;
175 u32 frame_idx;
176 u32 line_flag_int_cnt;
177 u32 irq_stat;
178 };
179
180 struct rk_hdmirx_dev {
181 struct cec_notifier *cec_notifier;
182 struct cpufreq_policy *policy;
183 struct device *dev;
184 struct device *classdev;
185 struct device *codec_dev;
186 struct device_node *of_node;
187 struct hdmirx_stream stream;
188 struct v4l2_device v4l2_dev;
189 struct v4l2_ctrl_handler hdl;
190 struct v4l2_ctrl *detect_tx_5v_ctrl;
191 struct v4l2_dv_timings timings;
192 struct gpio_desc *hdmirx_det_gpio;
193 struct work_struct work_wdt_config;
194 struct delayed_work delayed_work_hotplug;
195 struct delayed_work delayed_work_res_change;
196 struct delayed_work delayed_work_audio;
197 struct delayed_work delayed_work_heartbeat;
198 struct delayed_work delayed_work_cec;
199 struct dentry *debugfs_dir;
200 struct freq_qos_request min_sta_freq_req;
201 struct hdmirx_audiostate audio_state;
202 struct extcon_dev *extcon;
203 struct hdmirx_cec *cec;
204 struct mutex stream_lock;
205 struct mutex work_lock;
206 struct pm_qos_request pm_qos;
207 struct reset_control *rst_a;
208 struct reset_control *rst_p;
209 struct reset_control *rst_ref;
210 struct reset_control *rst_biu;
211 struct clk_bulk_data *clks;
212 struct regmap *grf;
213 struct regmap *vo1_grf;
214 struct rk_hdmirx_hdcp *hdcp;
215 void __iomem *regs;
216 int edid_version;
217 int audio_present;
218 int hdmi_irq;
219 int dma_irq;
220 int det_irq;
221 enum hdmirx_pix_fmt pix_fmt;
222 bool avi_pkt_rcv;
223 bool cr_write_done;
224 bool cr_read_done;
225 bool timer_base_lock;
226 bool tmds_clk_ratio;
227 bool is_dvi_mode;
228 bool power_on;
229 bool initialized;
230 bool freq_qos_add;
231 bool get_timing;
232 bool cec_enable;
233 bool hpd_on;
234 bool force_off;
235 u8 hdcp_enable;
236 u32 num_clks;
237 u32 edid_blocks_written;
238 u32 hpd_trigger_level;
239 u32 cur_vic;
240 u32 cur_fmt_fourcc;
241 u32 cur_color_range;
242 u32 cur_color_space;
243 u32 color_depth;
244 u32 cpu_freq_khz;
245 u32 bound_cpu;
246 u32 fps;
247 u32 wdt_cfg_bound_cpu;
248 u8 edid[EDID_BLOCK_SIZE * 2];
249 hdmi_codec_plugged_cb plugged_cb;
250 spinlock_t rst_lock;
251 };
252
253 static const unsigned int hdmirx_extcon_cable[] = {
254 EXTCON_JACK_VIDEO_IN,
255 EXTCON_NONE,
256 };
257
258 static bool tx_5v_power_present(struct rk_hdmirx_dev *hdmirx_dev);
259 static void hdmirx_set_fmt(struct hdmirx_stream *stream,
260 struct v4l2_pix_format_mplane *pixm, bool try);
261 static void hdmirx_audio_set_state(struct rk_hdmirx_dev *hdmirx_dev, enum audio_stat stat);
262 static void hdmirx_audio_setup(struct rk_hdmirx_dev *hdmirx_dev);
263 static u32 hdmirx_audio_fs(struct rk_hdmirx_dev *hdmirx_dev);
264 static u32 hdmirx_audio_ch(struct rk_hdmirx_dev *hdmirx_dev);
265 static void hdmirx_audio_fifo_init(struct rk_hdmirx_dev *hdmirx_dev);
266 static void hdmirx_audio_handle_plugged_change(struct rk_hdmirx_dev *hdmirx_dev, bool plugged);
267 static void hdmirx_audio_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en);
268 static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
269 static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
270 static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev);
271 static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev);
272 static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en);
273
274 static u8 edid_init_data_340M[] = {
275 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
276 0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
277 0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
278 0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
279 0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
280 0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
281 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
282 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
283 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
284 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
285 0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00,
286 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
287 0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
288 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
289 0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
290 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,
291
292 0x02, 0x03, 0x2E, 0xF1, 0x51, 0x07, 0x16, 0x14,
293 0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
294 0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
295 0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
296 0x0C, 0x00, 0x30, 0x00, 0x00, 0x44, 0xE3, 0x05,
297 0x03, 0x01, 0xE3, 0x0E, 0x60, 0x61, 0x02, 0x3A,
298 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
299 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
302 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
303 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
305 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD2,
308 };
309
310 static u8 edid_init_data_600M[] = {
311 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
312 0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
313 0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
314 0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
315 0x09, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
316 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
317 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, 0xE8,
318 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
319 0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
320 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80,
321 0xB0, 0x58, 0x8A, 0x00, 0x20, 0xC2, 0x31, 0x00,
322 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
323 0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
324 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
325 0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
326 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x39,
327
328 0x02, 0x03, 0x22, 0xF2, 0x41, 0x61, 0x23, 0x09,
329 0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
330 0x0C, 0x00, 0x30, 0x00, 0x00, 0x78, 0x67, 0xD8,
331 0x5D, 0xC4, 0x01, 0x78, 0xC0, 0x00, 0xE3, 0x05,
332 0x03, 0x01, 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70,
333 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0xC4, 0x8E,
334 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00,
335 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
339 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
340 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
343 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65,
344 };
345
346 static char *hdmirx_color_space[8] = {
347 "xvYCC601", "xvYCC709", "sYCC601", "Adobe_YCC601",
348 "Adobe_RGB", "BT2020_YcCbcCrc", "BT2020_RGB_OR_YCbCr"
349 };
350
351 static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
352 .type = V4L2_DV_BT_656_1120,
353 .reserved = { 0 },
354 V4L2_INIT_BT_TIMINGS(640, 4096, /* min/max width */
355 480, 2160, /* min/max height */
356 20000000, 600000000, /* min/max pixelclock */
357 /* standards */
358 V4L2_DV_BT_STD_CEA861,
359 /* capabilities */
360 V4L2_DV_BT_CAP_PROGRESSIVE |
361 V4L2_DV_BT_CAP_INTERLACED)
362 };
363
364 static const struct hdmirx_output_fmt g_out_fmts[] = {
365 {
366 .fourcc = V4L2_PIX_FMT_BGR24,
367 .cplanes = 1,
368 .mplanes = 1,
369 .bpp = { 24 },
370 }, {
371 .fourcc = V4L2_PIX_FMT_NV24,
372 .cplanes = 2,
373 .mplanes = 1,
374 .bpp = { 8, 16 },
375 }, {
376 .fourcc = V4L2_PIX_FMT_NV16,
377 .cplanes = 2,
378 .mplanes = 1,
379 .bpp = { 8, 16 },
380 }, {
381 .fourcc = V4L2_PIX_FMT_NV12,
382 .cplanes = 2,
383 .mplanes = 1,
384 .bpp = { 8, 16 },
385 }
386 };
387
to_hdmirx_buffer(struct vb2_v4l2_buffer * vb)388 static inline struct hdmirx_buffer *to_hdmirx_buffer(struct vb2_v4l2_buffer *vb)
389 {
390 return container_of(vb, struct hdmirx_buffer, vb);
391 }
392
hdmirx_writel(struct rk_hdmirx_dev * hdmirx_dev,int reg,u32 val)393 static void hdmirx_writel(struct rk_hdmirx_dev *hdmirx_dev, int reg, u32 val)
394 {
395 unsigned long lock_flags = 0;
396
397 spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
398 writel(val, hdmirx_dev->regs + reg);
399 spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
400 }
401
hdmirx_readl(struct rk_hdmirx_dev * hdmirx_dev,int reg)402 static u32 hdmirx_readl(struct rk_hdmirx_dev *hdmirx_dev, int reg)
403 {
404 unsigned long lock_flags = 0;
405 u32 val;
406
407 spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
408 val = readl(hdmirx_dev->regs + reg);
409 spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
410 return val;
411 }
412
hdmirx_reset_dma(struct rk_hdmirx_dev * hdmirx_dev)413 static void hdmirx_reset_dma(struct rk_hdmirx_dev *hdmirx_dev)
414 {
415 unsigned long lock_flags = 0;
416
417 spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
418 reset_control_assert(hdmirx_dev->rst_a);
419 reset_control_deassert(hdmirx_dev->rst_a);
420 spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
421 }
422
hdmirx_reset_all(struct rk_hdmirx_dev * hdmirx_dev)423 static void hdmirx_reset_all(struct rk_hdmirx_dev *hdmirx_dev)
424 {
425 unsigned long lock_flags = 0;
426
427 spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
428 reset_control_assert(hdmirx_dev->rst_a);
429 reset_control_assert(hdmirx_dev->rst_p);
430 reset_control_assert(hdmirx_dev->rst_ref);
431 reset_control_assert(hdmirx_dev->rst_biu);
432 reset_control_deassert(hdmirx_dev->rst_a);
433 reset_control_deassert(hdmirx_dev->rst_p);
434 reset_control_deassert(hdmirx_dev->rst_ref);
435 reset_control_deassert(hdmirx_dev->rst_biu);
436 spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
437 }
438
hdmirx_update_bits(struct rk_hdmirx_dev * hdmirx_dev,int reg,u32 mask,u32 data)439 static void hdmirx_update_bits(struct rk_hdmirx_dev *hdmirx_dev, int reg, u32 mask,
440 u32 data)
441 {
442 unsigned long lock_flags = 0;
443 u32 val;
444
445 spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
446 val = readl(hdmirx_dev->regs + reg) & ~mask;
447 val |= (data & mask);
448 writel(val, hdmirx_dev->regs + reg);
449 spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
450 }
451
452 /*
453 * Before clearing interrupt need to read the interrupt status.
454 */
hdmirx_clear_interrupt(struct rk_hdmirx_dev * hdmirx_dev,u32 reg,u32 val)455 static inline void hdmirx_clear_interrupt(struct rk_hdmirx_dev *hdmirx_dev,
456 u32 reg, u32 val)
457 {
458 /* (interrupt status register) = (interrupt clear register) - 0x8 */
459 hdmirx_readl(hdmirx_dev, reg - 0x8);
460 hdmirx_writel(hdmirx_dev, reg, val);
461 }
462
hdmirx_subscribe_event(struct v4l2_fh * fh,const struct v4l2_event_subscription * sub)463 static int hdmirx_subscribe_event(struct v4l2_fh *fh,
464 const struct v4l2_event_subscription *sub)
465 {
466 switch (sub->type) {
467 case V4L2_EVENT_SOURCE_CHANGE:
468 if (fh->vdev->vfl_dir == VFL_DIR_RX)
469 return v4l2_src_change_event_subscribe(fh, sub);
470 break;
471 case V4L2_EVENT_CTRL:
472 return v4l2_ctrl_subscribe_event(fh, sub);
473 case RK_HDMIRX_V4L2_EVENT_SIGNAL_LOST:
474 return v4l2_event_subscribe(fh, sub, 0, NULL);
475
476 default:
477 return v4l2_ctrl_subscribe_event(fh, sub);
478 }
479
480 return -EINVAL;
481 }
482
port_no_link(struct rk_hdmirx_dev * hdmirx_dev)483 static bool port_no_link(struct rk_hdmirx_dev *hdmirx_dev)
484 {
485 return !tx_5v_power_present(hdmirx_dev);
486 }
487
signal_not_lock(struct rk_hdmirx_dev * hdmirx_dev)488 static bool signal_not_lock(struct rk_hdmirx_dev *hdmirx_dev)
489 {
490 u32 mu_status, dma_st10, cmu_st;
491
492 mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
493 dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
494 cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
495
496 if ((mu_status & TMDSVALID_STABLE_ST) &&
497 (dma_st10 & HDMIRX_LOCK) &&
498 (cmu_st & TMDSQPCLK_LOCKED_ST))
499 return false;
500
501 return true;
502 }
503
tx_5v_power_present(struct rk_hdmirx_dev * hdmirx_dev)504 static bool tx_5v_power_present(struct rk_hdmirx_dev *hdmirx_dev)
505 {
506 bool ret;
507 int val, i, cnt;
508
509 cnt = 0;
510 for (i = 0; i < 10; i++) {
511 usleep_range(1000, 1100);
512 val = gpiod_get_value(hdmirx_dev->hdmirx_det_gpio);
513 if (val > 0)
514 cnt++;
515 if (cnt >= 7)
516 break;
517 }
518
519 ret = (cnt >= 7) ? true : false;
520 v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret);
521
522 return ret;
523 }
524
hdmirx_g_dv_timings(struct file * file,void * _fh,struct v4l2_dv_timings * timings)525 static int hdmirx_g_dv_timings(struct file *file, void *_fh,
526 struct v4l2_dv_timings *timings)
527 {
528 struct hdmirx_stream *stream = video_drvdata(file);
529 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
530 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
531 u32 dma_cfg1;
532
533 *timings = hdmirx_dev->timings;
534 dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
535 v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
536 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
537
538 return 0;
539 }
540
hdmirx_s_dv_timings(struct file * file,void * _fh,struct v4l2_dv_timings * timings)541 static int hdmirx_s_dv_timings(struct file *file, void *_fh,
542 struct v4l2_dv_timings *timings)
543 {
544 struct hdmirx_stream *stream = video_drvdata(file);
545 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
546 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
547
548 if (!timings)
549 return -EINVAL;
550
551 if (debug)
552 v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
553 "hdmirx_s_dv_timings: ", timings, false);
554
555 if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
556 v4l2_dbg(1, debug, v4l2_dev,
557 "%s: timings out of range\n", __func__);
558 return -ERANGE;
559 }
560
561 /* Check if the timings are part of the CEA-861 timings. */
562 if (!v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap,
563 0, NULL, NULL))
564 return -EINVAL;
565
566 if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) {
567 v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__);
568 return 0;
569 }
570
571 /*
572 * Changing the timings implies a format change, which is not allowed
573 * while buffers for use with streaming have already been allocated.
574 */
575 if (vb2_is_busy(&stream->buf_queue))
576 return -EBUSY;
577
578 hdmirx_dev->timings = *timings;
579 /* Update the internal format */
580 hdmirx_set_fmt(stream, &stream->pixm, false);
581
582 return 0;
583 }
584
hdmirx_get_colordepth(struct rk_hdmirx_dev * hdmirx_dev)585 static void hdmirx_get_colordepth(struct rk_hdmirx_dev *hdmirx_dev)
586 {
587 u32 val, color_depth_reg;
588 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
589
590 val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
591 color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3;
592
593 switch (color_depth_reg) {
594 case 0x4:
595 hdmirx_dev->color_depth = 24;
596 break;
597 case 0x5:
598 hdmirx_dev->color_depth = 30;
599 break;
600 case 0x6:
601 hdmirx_dev->color_depth = 36;
602 break;
603 case 0x7:
604 hdmirx_dev->color_depth = 48;
605 break;
606
607 default:
608 hdmirx_dev->color_depth = 24;
609 break;
610 }
611
612 v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n",
613 __func__, hdmirx_dev->color_depth, color_depth_reg);
614 }
615
hdmirx_get_pix_fmt(struct rk_hdmirx_dev * hdmirx_dev)616 static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev)
617 {
618 u32 val;
619 int timeout = 10;
620 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
621
622 try_loop:
623 val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
624 hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK;
625
626 switch (hdmirx_dev->pix_fmt) {
627 case HDMIRX_RGB888:
628 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
629 break;
630 case HDMIRX_YUV422:
631 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16;
632 break;
633 case HDMIRX_YUV444:
634 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24;
635 break;
636 case HDMIRX_YUV420:
637 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12;
638 break;
639
640 default:
641 if (timeout-- > 0) {
642 usleep_range(200 * 1000, 200 * 1010);
643 v4l2_err(v4l2_dev, "%s: get format failed, read again!\n", __func__);
644 goto try_loop;
645 }
646 hdmirx_dev->pix_fmt = HDMIRX_RGB888;
647 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
648 v4l2_err(v4l2_dev,
649 "%s: err pix_fmt: %d, set RGB888 as default\n",
650 __func__, hdmirx_dev->pix_fmt);
651 break;
652 }
653
654 /*
655 * set avmute value to black
656 * RGB: R:bit[47:40], G:bit[31:24], B:bit[15:8]
657 * YUV444: Y:bit[47:40], U:bit[31:24], V:bit[15:8]
658 * YUV422: Y:bit[47:40], UV:bit[15:8]
659 * YUV420: Y:bit[47:40], Y:bit[31:24], UV:bit[15:8]
660 */
661 if (hdmirx_dev->pix_fmt == HDMIRX_RGB888) {
662 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
663 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x0);
664 } else if (hdmirx_dev->pix_fmt == HDMIRX_YUV444) {
665 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
666 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x80008000);
667 } else {
668 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
669 hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x00008000);
670 }
671
672 v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__,
673 pix_fmt_str[hdmirx_dev->pix_fmt]);
674 }
675
hdmirx_get_color_space(struct rk_hdmirx_dev * hdmirx_dev)676 static void hdmirx_get_color_space(struct rk_hdmirx_dev *hdmirx_dev)
677 {
678 u32 val;
679 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
680
681 /*
682 * Note: PKTDEC_AVIIF_PB3_0 contents only updated after
683 * reading pktdec_aviif_ph2_1 unless snapshot feature
684 * is disabled using pktdec_snapshot_bypass
685 */
686 hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
687 val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0);
688 hdmirx_dev->cur_color_space = (val & EXTEND_COLORIMETRY) >> 28;
689
690 v4l2_dbg(2, debug, v4l2_dev, "%s: video standard: %s\n", __func__,
691 hdmirx_color_space[hdmirx_dev->cur_color_space]);
692 }
693
hdmirx_get_color_range(struct rk_hdmirx_dev * hdmirx_dev)694 static void hdmirx_get_color_range(struct rk_hdmirx_dev *hdmirx_dev)
695 {
696 u32 val;
697 int color_range;
698 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
699
700 /*
701 * Note: PKTDEC_AVIIF_PB3_0 contents only updated after
702 * reading pktdec_aviif_ph2_1 unless snapshot feature
703 * is disabled using pktdec_snapshot_bypass
704 */
705 hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
706 val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0);
707 color_range = (val & RGB_QUANTIZATION_RANGE) >> 26;
708 if (hdmirx_dev->pix_fmt != HDMIRX_RGB888) {
709 hdmirx_dev->cur_color_range = color_range;
710 } else {
711 if (color_range != HDMIRX_DEFAULT_RANGE) {
712 hdmirx_dev->cur_color_range = color_range;
713 } else {
714 (hdmirx_dev->cur_vic) ?
715 (hdmirx_dev->cur_color_range = HDMIRX_LIMIT_RANGE) :
716 (hdmirx_dev->cur_color_range = HDMIRX_FULL_RANGE);
717 }
718 }
719
720 v4l2_dbg(2, debug, v4l2_dev, "%s: color_range: %s\n", __func__,
721 (hdmirx_dev->cur_color_range == HDMIRX_DEFAULT_RANGE) ? "default" :
722 (hdmirx_dev->cur_color_range == HDMIRX_FULL_RANGE ? "full" : "limit"));
723 }
724
hdmirx_get_timings(struct rk_hdmirx_dev * hdmirx_dev,struct v4l2_bt_timings * bt,bool from_dma)725 static void hdmirx_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
726 struct v4l2_bt_timings *bt, bool from_dma)
727 {
728 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
729 u32 hact, vact, htotal, vtotal, fps;
730 u32 hfp, hs, hbp, vfp, vs, vbp;
731 u32 val;
732
733 if (from_dma) {
734 hfp = 0;
735 val = hdmirx_readl(hdmirx_dev, DMA_STATUS2);
736 hact = (val >> 16) & 0xffff;
737 vact = val & 0xffff;
738 val = hdmirx_readl(hdmirx_dev, DMA_STATUS3);
739 htotal = (val >> 16) & 0xffff;
740 vtotal = val & 0xffff;
741 val = hdmirx_readl(hdmirx_dev, DMA_STATUS4);
742 hs = (val >> 16) & 0xffff;
743 vs = val & 0xffff;
744 val = hdmirx_readl(hdmirx_dev, DMA_STATUS5);
745 hbp = (val >> 16) & 0xffff;
746 vbp = val & 0xffff;
747 } else {
748 val = hdmirx_readl(hdmirx_dev, VMON_STATUS1);
749 hs = (val >> 16) & 0xffff;
750 hfp = val & 0xffff;
751 val = hdmirx_readl(hdmirx_dev, VMON_STATUS2);
752 hbp = val & 0xffff;
753 val = hdmirx_readl(hdmirx_dev, VMON_STATUS3);
754 htotal = (val >> 16) & 0xffff;
755 hact = val & 0xffff;
756 val = hdmirx_readl(hdmirx_dev, VMON_STATUS4);
757 vs = (val >> 16) & 0xffff;
758 vfp = val & 0xffff;
759 val = hdmirx_readl(hdmirx_dev, VMON_STATUS5);
760 vbp = val & 0xffff;
761 val = hdmirx_readl(hdmirx_dev, VMON_STATUS6);
762 vtotal = (val >> 16) & 0xffff;
763 vact = val & 0xffff;
764 }
765
766 if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) {
767 htotal *= 2;
768 hfp *= 2;
769 hbp *= 2;
770 hs *= 2;
771 if (!from_dma)
772 hact *= 2;
773 }
774
775 if (from_dma) {
776 hfp = htotal - hact - hs - hbp;
777 vfp = vtotal - vact - vs - vbp;
778 }
779
780 if (!from_dma)
781 hact = (hact * 24) / hdmirx_dev->color_depth;
782
783 fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal);
784 bt->width = hact;
785 bt->height = vact;
786 bt->hfrontporch = hfp;
787 bt->hsync = hs;
788 bt->hbackporch = hbp;
789 bt->vfrontporch = vfp;
790 bt->vsync = vs;
791 bt->vbackporch = vbp;
792 hdmirx_dev->fps = fps;
793
794 if (bt->interlaced == V4L2_DV_INTERLACED) {
795 bt->height *= 2;
796 bt->il_vfrontporch = bt->vfrontporch;
797 bt->il_vsync = bt->vsync + 1;
798 bt->il_vbackporch = bt->vbackporch;
799 }
800
801 v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl");
802 v4l2_dbg(1, debug, v4l2_dev,
803 "act:%ux%u%s, total:%ux%u, fps:%u, pixclk:%llu\n",
804 bt->width, bt->height, bt->interlaced ? "i" : "p",
805 htotal, vtotal, fps, bt->pixelclock);
806
807 v4l2_dbg(2, debug, v4l2_dev,
808 "hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n",
809 bt->hfrontporch, bt->hsync, bt->hbackporch,
810 bt->vfrontporch, bt->vsync, bt->vbackporch);
811 }
812
hdmirx_check_timing_valid(struct v4l2_bt_timings * bt)813 static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt)
814 {
815 if (bt->width < 100 || bt->width > 5000 ||
816 bt->height < 100 || bt->height > 5000)
817 return false;
818
819 if (bt->hsync == 0 || bt->hsync > 500 ||
820 bt->vsync == 0 || bt->vsync > 100)
821 return false;
822
823 if (bt->hbackporch == 0 || bt->hbackporch > 3000 ||
824 bt->vbackporch == 0 || bt->vbackporch > 3000)
825 return false;
826
827 if (bt->hfrontporch == 0 || bt->hfrontporch > 3000 ||
828 bt->vfrontporch == 0 || bt->vfrontporch > 3000)
829 return false;
830
831 return true;
832 }
833
hdmirx_get_detected_timings(struct rk_hdmirx_dev * hdmirx_dev,struct v4l2_dv_timings * timings,bool from_dma)834 static int hdmirx_get_detected_timings(struct rk_hdmirx_dev *hdmirx_dev,
835 struct v4l2_dv_timings *timings, bool from_dma)
836 {
837 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
838 struct v4l2_bt_timings *bt = &timings->bt;
839 u32 field_type, color_depth, deframer_st;
840 u32 val, tmdsqpclk_freq, pix_clk;
841 u64 tmp_data, tmds_clk;
842
843 memset(timings, 0, sizeof(struct v4l2_dv_timings));
844 timings->type = V4L2_DV_BT_656_1120;
845
846 val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
847 field_type = (val & HDMIRX_TYPE_MASK) >> 7;
848 hdmirx_get_pix_fmt(hdmirx_dev);
849 hdmirx_get_color_range(hdmirx_dev);
850 hdmirx_get_color_space(hdmirx_dev);
851 bt->interlaced = field_type & BIT(0) ?
852 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
853 hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
854 val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4);
855 hdmirx_dev->cur_vic = val & VIC_VAL_MASK;
856 hdmirx_get_colordepth(hdmirx_dev);
857 color_depth = hdmirx_dev->color_depth;
858 deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS);
859 hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true;
860 tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
861 tmds_clk = tmdsqpclk_freq * 4 * 1000U;
862 tmp_data = tmds_clk * 24;
863 do_div(tmp_data, color_depth);
864 pix_clk = tmp_data;
865 bt->pixelclock = tmds_clk;
866 if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
867 bt->pixelclock *= 2;
868 hdmirx_get_timings(hdmirx_dev, bt, from_dma);
869
870 v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu, pix_clk:%d\n", tmds_clk, pix_clk);
871 v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n",
872 bt->interlaced, hdmirx_dev->pix_fmt,
873 hdmirx_dev->cur_vic, hdmirx_dev->color_depth,
874 hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi");
875 v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st);
876
877 if (!hdmirx_check_timing_valid(bt))
878 return -EINVAL;
879
880 return 0;
881 }
882
hdmirx_try_to_get_timings(struct rk_hdmirx_dev * hdmirx_dev,struct v4l2_dv_timings * timings,int try_cnt)883 static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
884 struct v4l2_dv_timings *timings, int try_cnt)
885 {
886 int i, cnt = 0, ret = 0;
887 bool from_dma = false;
888 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
889 u32 last_w, last_h;
890 struct v4l2_bt_timings *bt = &timings->bt;
891 enum hdmirx_pix_fmt last_fmt;
892
893 last_w = 0;
894 last_h = 0;
895 last_fmt = HDMIRX_RGB888;
896
897 for (i = 0; i < try_cnt; i++) {
898 ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma);
899
900 if ((last_w == 0) && (last_h == 0)) {
901 last_w = bt->width;
902 last_h = bt->height;
903 }
904
905 if (ret || (last_w != bt->width) || (last_h != bt->height)
906 || (last_fmt != hdmirx_dev->pix_fmt))
907 cnt = 0;
908 else
909 cnt++;
910
911 if (cnt >= 8)
912 break;
913
914 last_w = bt->width;
915 last_h = bt->height;
916 last_fmt = hdmirx_dev->pix_fmt;
917 usleep_range(10*1000, 10*1100);
918 }
919
920 if (try_cnt > 8 && cnt < 8) {
921 v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable!\n", __func__);
922 ret = -EINVAL;
923 }
924
925 return ret;
926 }
927
hdmirx_query_dv_timings(struct file * file,void * _fh,struct v4l2_dv_timings * timings)928 static int hdmirx_query_dv_timings(struct file *file, void *_fh,
929 struct v4l2_dv_timings *timings)
930 {
931 int ret;
932 struct hdmirx_stream *stream = video_drvdata(file);
933 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
934 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
935
936 if (port_no_link(hdmirx_dev)) {
937 v4l2_err(v4l2_dev, "%s port has no link!\n", __func__);
938 return -ENOLINK;
939 }
940
941 if (signal_not_lock(hdmirx_dev)) {
942 v4l2_err(v4l2_dev, "%s signal is not locked!\n", __func__);
943 return -ENOLCK;
944 }
945
946 ret = hdmirx_get_detected_timings(hdmirx_dev, timings, false);
947 if (ret)
948 return ret;
949
950 if (debug)
951 v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
952 "query_dv_timings: ", timings, false);
953
954 if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
955 v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__);
956 return -ERANGE;
957 }
958
959 return 0;
960 }
961
hdmirx_cec_state_reconfiguration(struct rk_hdmirx_dev * hdmirx_dev,bool en)962 static void hdmirx_cec_state_reconfiguration(struct rk_hdmirx_dev *hdmirx_dev, bool en)
963 {
964 unsigned int irqs;
965
966 hdmirx_update_bits(hdmirx_dev, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
967 hdmirx_update_bits(hdmirx_dev, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE,
968 RX_AUTO_DRIVE_ACKNOWLEDGE);
969 hdmirx_writel(hdmirx_dev, CEC_ADDR, hdmirx_dev->cec->addresses);
970 irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
971 hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, irqs);
972
973 cec_queue_pin_hpd_event(hdmirx_dev->cec->adap, en, ktime_get());
974 }
975
hdmirx_delayed_work_cec(struct work_struct * work)976 static void hdmirx_delayed_work_cec(struct work_struct *work)
977 {
978 struct delayed_work *dwork = to_delayed_work(work);
979 struct rk_hdmirx_dev *hdmirx_dev = container_of(dwork,
980 struct rk_hdmirx_dev, delayed_work_cec);
981
982 cec_queue_pin_hpd_event(hdmirx_dev->cec->adap,
983 tx_5v_power_present(hdmirx_dev),
984 ktime_get());
985 }
986
hdmirx_hpd_config(struct rk_hdmirx_dev * hdmirx_dev,bool en)987 static void hdmirx_hpd_config(struct rk_hdmirx_dev *hdmirx_dev, bool en)
988 {
989 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
990 u32 level;
991
992 v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
993 __func__, en ? "en" : "dis",
994 hdmirx_dev->hpd_trigger_level);
995 if (!en)
996 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, 0);
997 hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW);
998 level = hdmirx_dev->hpd_trigger_level ? en : !en;
999 hdmirx_writel(hdmirx_dev, CORE_CONFIG, level);
1000 if (hdmirx_dev->cec && hdmirx_dev->cec->adap)
1001 hdmirx_cec_state_reconfiguration(hdmirx_dev, en);
1002 }
1003
hdmirx_hpd_ctrl(struct rk_hdmirx_dev * hdmirx_dev,bool en)1004 static void hdmirx_hpd_ctrl(struct rk_hdmirx_dev *hdmirx_dev, bool en)
1005 {
1006 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1007
1008 if (hdmirx_dev->force_off && en)
1009 return;
1010
1011 v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
1012 __func__, en ? "en" : "dis",
1013 hdmirx_dev->hpd_trigger_level);
1014 hdmirx_hpd_config(hdmirx_dev, en);
1015 if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp2_connect_ctrl) {
1016 regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON1,
1017 HDCP1_P0_GPIO_IN_SEL | HDCP1_P0_GPIO_IN_SEL << 16);
1018 hdmirx_dev->hdcp->hdcp2_connect_ctrl(hdmirx_dev->hdcp, en);
1019 }
1020 hdmirx_dev->hpd_on = en;
1021 }
1022
hdmirx_write_edid(struct rk_hdmirx_dev * hdmirx_dev,struct v4l2_edid * edid,bool hpd_up)1023 static int hdmirx_write_edid(struct rk_hdmirx_dev *hdmirx_dev,
1024 struct v4l2_edid *edid, bool hpd_up)
1025 {
1026 u32 i;
1027 u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1028 struct device *dev = hdmirx_dev->dev;
1029 char data[300];
1030
1031 memset(edid->reserved, 0, sizeof(edid->reserved));
1032 if (edid->pad != 0)
1033 return -EINVAL;
1034
1035 if (edid->start_block != 0)
1036 return -EINVAL;
1037
1038 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1039 edid->blocks = EDID_NUM_BLOCKS_MAX;
1040 return -E2BIG;
1041 }
1042
1043 if (edid->blocks == 0) {
1044 hdmirx_dev->edid_blocks_written = 0;
1045 return 0;
1046 }
1047
1048 memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid));
1049 hdmirx_hpd_ctrl(hdmirx_dev, false);
1050 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
1051 EDID_READ_EN_MASK |
1052 EDID_WRITE_EN_MASK |
1053 EDID_SLAVE_ADDR_MASK,
1054 EDID_READ_EN(0) |
1055 EDID_WRITE_EN(1) |
1056 EDID_SLAVE_ADDR(0x50));
1057 for (i = 0; i < edid_len; i++)
1058 hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid->edid[i]);
1059
1060 /* read out for debug */
1061 if (debug >= 2) {
1062 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
1063 EDID_READ_EN_MASK |
1064 EDID_WRITE_EN_MASK,
1065 EDID_READ_EN(1) |
1066 EDID_WRITE_EN(0));
1067 dev_info(dev, "%s: Read EDID: ======\n", __func__);
1068 edid_len = edid_len > sizeof(data) ? sizeof(data) : edid_len;
1069 memset(data, 0, sizeof(data));
1070 for (i = 0; i < edid_len; i++)
1071 data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14);
1072
1073 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, data,
1074 edid_len, false);
1075 }
1076
1077 /*
1078 * You must set EDID_READ_EN & EDID_WRITE_EN bit to 0,
1079 * when the read/write edid operation is completed.Otherwise, it
1080 * will affect the reading and writing of other registers
1081 */
1082 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
1083 EDID_READ_EN_MASK |
1084 EDID_WRITE_EN_MASK,
1085 EDID_READ_EN(0) |
1086 EDID_WRITE_EN(0));
1087
1088 hdmirx_dev->edid_blocks_written = edid->blocks;
1089 memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
1090 if (hpd_up) {
1091 if (tx_5v_power_present(hdmirx_dev))
1092 hdmirx_hpd_ctrl(hdmirx_dev, true);
1093 }
1094
1095 return 0;
1096 }
1097
hdmirx_set_edid(struct file * file,void * fh,struct v4l2_edid * edid)1098 static int hdmirx_set_edid(struct file *file, void *fh,
1099 struct v4l2_edid *edid)
1100 {
1101 struct hdmirx_stream *stream = video_drvdata(file);
1102 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1103
1104 disable_irq(hdmirx_dev->hdmi_irq);
1105 disable_irq(hdmirx_dev->dma_irq);
1106 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_DIS, RK_IRQ_HDMIRX_HDMI, 0);
1107
1108 if (tx_5v_power_present(hdmirx_dev))
1109 hdmirx_plugout(hdmirx_dev);
1110 hdmirx_write_edid(hdmirx_dev, edid, false);
1111 hdmirx_dev->edid_version = HDMIRX_EDID_USER;
1112
1113 enable_irq(hdmirx_dev->hdmi_irq);
1114 enable_irq(hdmirx_dev->dma_irq);
1115 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
1116 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
1117 &hdmirx_dev->delayed_work_hotplug,
1118 msecs_to_jiffies(1000));
1119
1120 return 0;
1121 }
1122
hdmirx_get_edid(struct file * file,void * fh,struct v4l2_edid * edid)1123 static int hdmirx_get_edid(struct file *file, void *fh,
1124 struct v4l2_edid *edid)
1125 {
1126 struct hdmirx_stream *stream = video_drvdata(file);
1127 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1128 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1129
1130 memset(edid->reserved, 0, sizeof(edid->reserved));
1131
1132 if (edid->pad != 0)
1133 return -EINVAL;
1134
1135 if (edid->start_block == 0 && edid->blocks == 0) {
1136 edid->blocks = hdmirx_dev->edid_blocks_written;
1137 return 0;
1138 }
1139
1140 if (hdmirx_dev->edid_blocks_written == 0)
1141 return -ENODATA;
1142
1143 if (edid->start_block >= hdmirx_dev->edid_blocks_written ||
1144 edid->blocks == 0)
1145 return -EINVAL;
1146
1147 if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written)
1148 edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block;
1149
1150 memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE);
1151
1152 v4l2_dbg(1, debug, v4l2_dev, "%s: Read EDID: =====\n", __func__);
1153 if (debug > 0)
1154 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
1155 edid->edid, edid->blocks * EDID_BLOCK_SIZE, false);
1156
1157 return 0;
1158 }
1159
hdmirx_dv_timings_cap(struct file * file,void * fh,struct v4l2_dv_timings_cap * cap)1160 static int hdmirx_dv_timings_cap(struct file *file, void *fh,
1161 struct v4l2_dv_timings_cap *cap)
1162 {
1163 *cap = hdmirx_timings_cap;
1164
1165 return 0;
1166 }
1167
hdmirx_enum_dv_timings(struct file * file,void * _fh,struct v4l2_enum_dv_timings * timings)1168 static int hdmirx_enum_dv_timings(struct file *file, void *_fh,
1169 struct v4l2_enum_dv_timings *timings)
1170 {
1171 return v4l2_enum_dv_timings_cap(timings, &hdmirx_timings_cap, NULL, NULL);
1172 }
1173
hdmirx_register_hdcp(struct device * dev,struct rk_hdmirx_dev * hdmirx_dev,u8 hdcp_enable)1174 static void hdmirx_register_hdcp(struct device *dev,
1175 struct rk_hdmirx_dev *hdmirx_dev,
1176 u8 hdcp_enable)
1177 {
1178 struct rk_hdmirx_hdcp hdmirx_hdcp = {
1179 .hdmirx = hdmirx_dev,
1180 .write = hdmirx_writel,
1181 .read = hdmirx_readl,
1182 .hpd_config = hdmirx_hpd_config,
1183 .tx_5v_power = tx_5v_power_present,
1184 .enable = hdcp_enable,
1185 .dev = hdmirx_dev->dev,
1186 };
1187
1188 hdmirx_dev->hdcp = rk_hdmirx_hdcp_register(&hdmirx_hdcp);
1189 }
1190
hdmirx_scdc_init(struct rk_hdmirx_dev * hdmirx_dev)1191 static void hdmirx_scdc_init(struct rk_hdmirx_dev *hdmirx_dev)
1192 {
1193 hdmirx_update_bits(hdmirx_dev, I2C_SLAVE_CONFIG1,
1194 I2C_SDA_OUT_HOLD_VALUE_QST_MASK |
1195 I2C_SDA_IN_HOLD_VALUE_QST_MASK,
1196 I2C_SDA_OUT_HOLD_VALUE_QST(0x80) |
1197 I2C_SDA_IN_HOLD_VALUE_QST(0x15));
1198 hdmirx_update_bits(hdmirx_dev, SCDC_REGBANK_CONFIG0,
1199 SCDC_SINKVERSION_QST_MASK,
1200 SCDC_SINKVERSION_QST(1));
1201 }
1202
wait_reg_bit_status(struct rk_hdmirx_dev * hdmirx_dev,u32 reg,u32 bit_mask,u32 expect_val,bool is_grf,u32 ms)1203 static int wait_reg_bit_status(struct rk_hdmirx_dev *hdmirx_dev,
1204 u32 reg, u32 bit_mask, u32 expect_val, bool is_grf, u32 ms)
1205 {
1206 u32 i, val;
1207 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1208
1209 for (i = 0; i < ms; i++) {
1210 if (is_grf)
1211 regmap_read(hdmirx_dev->grf, reg, &val);
1212 else
1213 val = hdmirx_readl(hdmirx_dev, reg);
1214
1215 if ((val & bit_mask) == expect_val) {
1216 v4l2_dbg(2, debug, v4l2_dev,
1217 "%s: i:%d, time: %dms\n", __func__, i, ms);
1218 break;
1219 }
1220
1221 usleep_range(1000, 1010);
1222 }
1223
1224 if (i == ms)
1225 return -1;
1226
1227 return 0;
1228 }
1229
hdmirx_phy_register_read(struct rk_hdmirx_dev * hdmirx_dev,u32 phy_reg,u32 * val)1230 static int hdmirx_phy_register_read(struct rk_hdmirx_dev *hdmirx_dev,
1231 u32 phy_reg, u32 *val)
1232 {
1233 u32 i;
1234 struct device *dev = hdmirx_dev->dev;
1235
1236 hdmirx_dev->cr_read_done = false;
1237 /* clear irq status */
1238 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
1239 /* en irq */
1240 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
1241 PHYCREG_CR_READ_DONE, PHYCREG_CR_READ_DONE);
1242 /* write phy reg addr */
1243 hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
1244 /* config read enable */
1245 hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_READ_P);
1246
1247 for (i = 0; i < WAIT_PHY_REG_TIME; i++) {
1248 usleep_range(200, 210);
1249 if (hdmirx_dev->cr_read_done)
1250 break;
1251 }
1252
1253 if (i == WAIT_PHY_REG_TIME) {
1254 dev_err(dev, "%s wait cr read done failed!\n", __func__);
1255 return -1;
1256 }
1257
1258 /* read phy reg val */
1259 *val = hdmirx_readl(hdmirx_dev, PHYCREG_STATUS);
1260
1261 return 0;
1262 }
1263
hdmirx_phy_register_write(struct rk_hdmirx_dev * hdmirx_dev,u32 phy_reg,u32 val)1264 static int hdmirx_phy_register_write(struct rk_hdmirx_dev *hdmirx_dev,
1265 u32 phy_reg, u32 val)
1266 {
1267 u32 i;
1268 struct device *dev = hdmirx_dev->dev;
1269
1270 hdmirx_dev->cr_write_done = false;
1271 /* clear irq status */
1272 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
1273 /* en irq */
1274 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
1275 PHYCREG_CR_WRITE_DONE, PHYCREG_CR_WRITE_DONE);
1276 /* write phy reg addr */
1277 hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
1278 /* write phy reg val */
1279 hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val);
1280 /* config write enable */
1281 hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P);
1282
1283 for (i = 0; i < WAIT_PHY_REG_TIME; i++) {
1284 usleep_range(200, 210);
1285 if (hdmirx_dev->cr_write_done)
1286 break;
1287 }
1288
1289 if (i == WAIT_PHY_REG_TIME) {
1290 dev_err(dev, "%s wait cr write done failed!\n", __func__);
1291 return -1;
1292 }
1293
1294 return 0;
1295 }
1296
hdmirx_tmds_clk_ratio_config(struct rk_hdmirx_dev * hdmirx_dev)1297 static void hdmirx_tmds_clk_ratio_config(struct rk_hdmirx_dev *hdmirx_dev)
1298 {
1299 u32 val;
1300 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1301
1302 val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1);
1303 v4l2_dbg(3, debug, v4l2_dev, "%s scdc_regbank_st:%#x\n", __func__, val);
1304 hdmirx_dev->tmds_clk_ratio = (val & SCDC_TMDSBITCLKRATIO) > 0;
1305
1306 if (hdmirx_dev->tmds_clk_ratio) {
1307 v4l2_dbg(3, debug, v4l2_dev, "%s HDMITX greater than 3.4Gbps!\n", __func__);
1308 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
1309 TMDS_CLOCK_RATIO, TMDS_CLOCK_RATIO);
1310 } else {
1311 v4l2_dbg(3, debug, v4l2_dev, "%s HDMITX less than 3.4Gbps!\n", __func__);
1312 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
1313 TMDS_CLOCK_RATIO, 0);
1314 }
1315 }
1316
hdmirx_phy_config(struct rk_hdmirx_dev * hdmirx_dev)1317 static void hdmirx_phy_config(struct rk_hdmirx_dev *hdmirx_dev)
1318 {
1319 struct device *dev = hdmirx_dev->dev;
1320
1321 hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
1322 hdmirx_update_bits(hdmirx_dev, SCDC_INT_MASK_N, SCDCTMDSCCFG_CHG,
1323 SCDCTMDSCCFG_CHG);
1324 /* cr_para_clk 24M */
1325 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0));
1326 /* rx data width 40bit valid */
1327 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH);
1328 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET);
1329 usleep_range(100, 110);
1330 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0);
1331 usleep_range(100, 110);
1332 /* select cr para interface */
1333 hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3);
1334
1335 if (wait_reg_bit_status(hdmirx_dev, SYS_GRF_SOC_STATUS1,
1336 HDMIRXPHY_SRAM_INIT_DONE,
1337 HDMIRXPHY_SRAM_INIT_DONE, true, 10))
1338 dev_err(dev, "%s phy SRAM init failed!\n", __func__);
1339
1340 regmap_write(hdmirx_dev->grf, SYS_GRF_SOC_CON1,
1341 (HDMIRXPHY_SRAM_EXT_LD_DONE << 16) | HDMIRXPHY_SRAM_EXT_LD_DONE);
1342 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
1343 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
1344 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
1345 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
1346 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 3);
1347 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 2);
1348 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
1349 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 1);
1350 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
1351 hdmirx_phy_register_write(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, 0);
1352
1353 hdmirx_phy_register_write(hdmirx_dev,
1354 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG,
1355 CDR_SETTING_BOUNDARY_3_DEFAULT);
1356 hdmirx_phy_register_write(hdmirx_dev,
1357 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG,
1358 CDR_SETTING_BOUNDARY_4_DEFAULT);
1359 hdmirx_phy_register_write(hdmirx_dev,
1360 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG,
1361 CDR_SETTING_BOUNDARY_5_DEFAULT);
1362 hdmirx_phy_register_write(hdmirx_dev,
1363 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG,
1364 CDR_SETTING_BOUNDARY_6_DEFAULT);
1365 hdmirx_phy_register_write(hdmirx_dev,
1366 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG,
1367 CDR_SETTING_BOUNDARY_7_DEFAULT);
1368
1369 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0);
1370 if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, PDDQ_ACK, 0, false, 10))
1371 dev_err(dev, "%s wait pddq ack failed!\n", __func__);
1372
1373 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0);
1374 if (wait_reg_bit_status(hdmirx_dev, PHY_STATUS, HDMI_DISABLE_ACK, 0,
1375 false, 50))
1376 dev_err(dev, "%s wait hdmi disable ack failed!\n", __func__);
1377
1378 hdmirx_tmds_clk_ratio_config(hdmirx_dev);
1379 }
1380
hdmirx_controller_init(struct rk_hdmirx_dev * hdmirx_dev)1381 static void hdmirx_controller_init(struct rk_hdmirx_dev *hdmirx_dev)
1382 {
1383 u32 i;
1384 struct device *dev = hdmirx_dev->dev;
1385
1386 hdmirx_dev->timer_base_lock = false;
1387 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
1388 /* en irq */
1389 hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
1390 TIMER_BASE_LOCKED_IRQ, TIMER_BASE_LOCKED_IRQ);
1391 /* write irefclk freq */
1392 hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, IREF_CLK_FREQ_HZ);
1393 for (i = 0; i < WAIT_TIMER_LOCK_TIME; i++) {
1394 usleep_range(200, 210);
1395 if (hdmirx_dev->timer_base_lock)
1396 break;
1397 }
1398
1399 if (i == WAIT_TIMER_LOCK_TIME)
1400 dev_err(dev, "%s wait timer base lock failed!\n", __func__);
1401
1402 hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
1403 VPROC_VSYNC_POL_OVR_VALUE |
1404 VPROC_VSYNC_POL_OVR_EN |
1405 VPROC_HSYNC_POL_OVR_VALUE |
1406 VPROC_HSYNC_POL_OVR_EN,
1407 VPROC_VSYNC_POL_OVR_VALUE |
1408 VPROC_VSYNC_POL_OVR_EN |
1409 VPROC_HSYNC_POL_OVR_VALUE |
1410 VPROC_HSYNC_POL_OVR_EN);
1411 hdmirx_update_bits(hdmirx_dev, VMON_CONTROL,
1412 VMON_SOURCE_SEL_MASK, VMON_SOURCE_SEL_DEFRAMER(0x2));
1413 hdmirx_update_bits(hdmirx_dev, CMU_CONFIG0,
1414 TMDSQPCLK_STABLE_FREQ_MARGIN_MASK |
1415 AUDCLK_STABLE_FREQ_MARGIN_MASK,
1416 TMDSQPCLK_STABLE_FREQ_MARGIN(2) |
1417 AUDCLK_STABLE_FREQ_MARGIN(1));
1418 hdmirx_update_bits(hdmirx_dev, DESCRAND_EN_CONTROL,
1419 SCRAMB_EN_SEL_QST_MASK, SCRAMB_EN_SEL_QST(1));
1420 hdmirx_update_bits(hdmirx_dev, CED_CONFIG,
1421 CED_VIDDATACHECKEN_QST|
1422 CED_DATAISCHECKEN_QST |
1423 CED_GBCHECKEN_QST |
1424 CED_CTRLCHECKEN_QST |
1425 CED_CHLOCKMAXER_QST_MASK,
1426 CED_VIDDATACHECKEN_QST|
1427 // CED_DATAISCHECKEN_QST |
1428 CED_GBCHECKEN_QST |
1429 CED_CTRLCHECKEN_QST |
1430 CED_CHLOCKMAXER_QST(0x10));
1431 }
1432
hdmirx_format_change(struct rk_hdmirx_dev * hdmirx_dev)1433 static void hdmirx_format_change(struct rk_hdmirx_dev *hdmirx_dev)
1434 {
1435 struct v4l2_dv_timings timings;
1436 struct hdmirx_stream *stream = &hdmirx_dev->stream;
1437 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1438 const struct v4l2_event ev_src_chg = {
1439 .type = V4L2_EVENT_SOURCE_CHANGE,
1440 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1441 };
1442
1443 if (hdmirx_try_to_get_timings(hdmirx_dev, &timings, 20)) {
1444 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
1445 &hdmirx_dev->delayed_work_hotplug,
1446 msecs_to_jiffies(1000));
1447 return;
1448 }
1449
1450 if (!v4l2_match_dv_timings(&hdmirx_dev->timings, &timings, 0, false)) {
1451 /* automatically set timing rather than set by userspace */
1452 hdmirx_dev->timings = timings;
1453 v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
1454 "hdmirx_format_change: New format: ",
1455 &timings, false);
1456 }
1457
1458 hdmirx_dev->get_timing = true;
1459 v4l2_dbg(1, debug, v4l2_dev, "%s: queue res_chg_event\n", __func__);
1460 v4l2_event_queue(&stream->vdev, &ev_src_chg);
1461 }
1462
hdmirx_set_ddr_store_fmt(struct rk_hdmirx_dev * hdmirx_dev)1463 static void hdmirx_set_ddr_store_fmt(struct rk_hdmirx_dev *hdmirx_dev)
1464 {
1465 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1466 enum ddr_store_fmt store_fmt;
1467 u32 dma_cfg1;
1468
1469 switch (hdmirx_dev->pix_fmt) {
1470 case HDMIRX_RGB888:
1471 store_fmt = STORE_RGB888;
1472 break;
1473 case HDMIRX_YUV444:
1474 store_fmt = STORE_YUV444_8BIT;
1475 break;
1476 case HDMIRX_YUV422:
1477 store_fmt = STORE_YUV422_8BIT;
1478 break;
1479 case HDMIRX_YUV420:
1480 store_fmt = STORE_YUV420_8BIT;
1481 break;
1482
1483 default:
1484 store_fmt = STORE_RGB888;
1485 break;
1486 }
1487
1488 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
1489 DDR_STORE_FORMAT_MASK, DDR_STORE_FORMAT(store_fmt));
1490 dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
1491 v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
1492 __func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
1493 }
1494
hdmirx_wait_lock_and_get_timing(struct rk_hdmirx_dev * hdmirx_dev)1495 static int hdmirx_wait_lock_and_get_timing(struct rk_hdmirx_dev *hdmirx_dev)
1496 {
1497 u32 i, j = 0;
1498 u32 mu_status, scdc_status, dma_st10, cmu_st;
1499 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1500
1501 for (i = 1; i < WAIT_SIGNAL_LOCK_TIME; i++) {
1502 mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
1503 scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
1504 dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
1505 cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
1506
1507 if ((mu_status & TMDSVALID_STABLE_ST) &&
1508 (dma_st10 & HDMIRX_LOCK) &&
1509 (cmu_st & TMDSQPCLK_LOCKED_ST))
1510 j++;
1511 else
1512 j = 0;
1513
1514 if (j > WAIT_LOCK_STABLE_TIME)
1515 break;
1516
1517 if (i % NO_LOCK_CFG_RETRY_TIME == 0)
1518 hdmirx_phy_config(hdmirx_dev);
1519
1520 if (!tx_5v_power_present(hdmirx_dev)) {
1521 v4l2_err(v4l2_dev, "%s HDMI pull out, return!\n", __func__);
1522 return -1;
1523 }
1524
1525 hdmirx_tmds_clk_ratio_config(hdmirx_dev);
1526 }
1527
1528 if (i == WAIT_SIGNAL_LOCK_TIME) {
1529 v4l2_err(v4l2_dev, "%s signal not lock, tmds_clk_ratio:%d\n",
1530 __func__, hdmirx_dev->tmds_clk_ratio);
1531 v4l2_err(v4l2_dev, "%s mu_st:%#x, scdc_st:%#x, dma_st10:%#x\n",
1532 __func__, mu_status, scdc_status, dma_st10);
1533
1534 return -1;
1535 }
1536
1537 v4l2_info(v4l2_dev, "%s signal lock ok, i:%d!\n", __func__, i);
1538 hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ);
1539
1540 hdmirx_dev->avi_pkt_rcv = false;
1541 hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
1542 hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
1543 PKTDEC_AVIIF_RCV_IRQ, PKTDEC_AVIIF_RCV_IRQ);
1544
1545 for (i = 0; i < WAIT_AVI_PKT_TIME; i++) {
1546 usleep_range(1000, 1100);
1547 if (hdmirx_dev->avi_pkt_rcv) {
1548 v4l2_dbg(1, debug, v4l2_dev,
1549 "%s: avi_pkt_rcv i:%d\n", __func__, i);
1550 break;
1551 }
1552 }
1553
1554 if (i == WAIT_AVI_PKT_TIME) {
1555 v4l2_err(v4l2_dev, "%s wait avi_pkt_rcv failed!\n", __func__);
1556 hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
1557 PKTDEC_AVIIF_RCV_IRQ, 0);
1558 }
1559
1560 hdmirx_reset_dma(hdmirx_dev);
1561 usleep_range(200*1000, 200*1010);
1562 hdmirx_format_change(hdmirx_dev);
1563
1564 return 0;
1565 }
1566
hdmirx_dma_config(struct rk_hdmirx_dev * hdmirx_dev)1567 static void hdmirx_dma_config(struct rk_hdmirx_dev *hdmirx_dev)
1568 {
1569 hdmirx_set_ddr_store_fmt(hdmirx_dev);
1570
1571 /* Note: uv_swap, rb can not swap, doc err*/
1572 if (hdmirx_dev->cur_fmt_fourcc != V4L2_PIX_FMT_NV16)
1573 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, RB_SWAP_EN);
1574 else
1575 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, RB_SWAP_EN, 0);
1576
1577 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
1578 LOCK_FRAME_NUM_MASK,
1579 LOCK_FRAME_NUM(2));
1580 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG1,
1581 UV_WID_MASK |
1582 Y_WID_MASK |
1583 ABANDON_EN,
1584 UV_WID(1) |
1585 Y_WID(2) |
1586 ABANDON_EN);
1587 }
1588
hdmirx_submodule_init(struct rk_hdmirx_dev * hdmirx_dev)1589 static void hdmirx_submodule_init(struct rk_hdmirx_dev *hdmirx_dev)
1590 {
1591 hdmirx_scdc_init(hdmirx_dev);
1592 hdmirx_controller_init(hdmirx_dev);
1593 }
1594
hdmirx_enum_input(struct file * file,void * priv,struct v4l2_input * input)1595 static int hdmirx_enum_input(struct file *file, void *priv,
1596 struct v4l2_input *input)
1597 {
1598 if (input->index > 0)
1599 return -EINVAL;
1600
1601 input->type = V4L2_INPUT_TYPE_CAMERA;
1602 input->std = 0;
1603 strscpy(input->name, "hdmirx", sizeof(input->name));
1604 input->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1605
1606 return 0;
1607 }
1608
fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)1609 static int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
1610 {
1611 /* Note: cbcr plane bpp is 16 bit */
1612 switch (fcc) {
1613 case V4L2_PIX_FMT_NV24:
1614 *xsubs = 1;
1615 *ysubs = 1;
1616 break;
1617 case V4L2_PIX_FMT_NV16:
1618 *xsubs = 2;
1619 *ysubs = 1;
1620 break;
1621 case V4L2_PIX_FMT_NV12:
1622 *xsubs = 2;
1623 *ysubs = 2;
1624 break;
1625 default:
1626 return -EINVAL;
1627 }
1628
1629 return 0;
1630 }
1631
hdmirx_align_bits_per_pixel(const struct hdmirx_output_fmt * fmt,int plane_index)1632 static u32 hdmirx_align_bits_per_pixel(const struct hdmirx_output_fmt *fmt,
1633 int plane_index)
1634 {
1635 u32 bpp = 0;
1636
1637 if (fmt) {
1638 switch (fmt->fourcc) {
1639 case V4L2_PIX_FMT_NV24:
1640 case V4L2_PIX_FMT_NV16:
1641 case V4L2_PIX_FMT_NV12:
1642 case V4L2_PIX_FMT_BGR24:
1643 bpp = fmt->bpp[plane_index];
1644 break;
1645
1646 default:
1647 pr_err("fourcc: %#x is not supported!\n", fmt->fourcc);
1648 break;
1649 }
1650 }
1651
1652 return bpp;
1653 }
1654
1655 static const struct
find_output_fmt(struct hdmirx_stream * stream,u32 pixelfmt)1656 hdmirx_output_fmt *find_output_fmt(struct hdmirx_stream *stream, u32 pixelfmt)
1657 {
1658 const struct hdmirx_output_fmt *fmt;
1659 u32 i;
1660
1661 for (i = 0; i < ARRAY_SIZE(g_out_fmts); i++) {
1662 fmt = &g_out_fmts[i];
1663 if (fmt->fourcc == pixelfmt)
1664 return fmt;
1665 }
1666
1667 return NULL;
1668 }
1669
hdmirx_set_fmt(struct hdmirx_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)1670 static void hdmirx_set_fmt(struct hdmirx_stream *stream,
1671 struct v4l2_pix_format_mplane *pixm,
1672 bool try)
1673 {
1674 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1675 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1676 struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt;
1677 const struct hdmirx_output_fmt *fmt;
1678 unsigned int imagesize = 0, planes;
1679 u32 xsubs = 1, ysubs = 1, i;
1680
1681 memset(&pixm->plane_fmt[0], 0, sizeof(struct v4l2_plane_pix_format));
1682 fmt = find_output_fmt(stream, pixm->pixelformat);
1683 if (!fmt) {
1684 fmt = &g_out_fmts[0];
1685 v4l2_err(v4l2_dev,
1686 "%s: set_fmt:%#x not support, use def_fmt:%x\n",
1687 __func__, pixm->pixelformat, fmt->fourcc);
1688 }
1689
1690 if ((bt->width == 0) || (bt->height == 0))
1691 v4l2_err(v4l2_dev, "%s: err resolution:%#xx%#x!!!\n",
1692 __func__, bt->width, bt->height);
1693
1694 pixm->width = bt->width;
1695 pixm->height = bt->height;
1696 pixm->num_planes = fmt->mplanes;
1697 pixm->field = V4L2_FIELD_NONE;
1698
1699 switch (hdmirx_dev->cur_color_range) {
1700 case HDMIRX_DEFAULT_RANGE:
1701 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
1702 break;
1703 case HDMIRX_LIMIT_RANGE:
1704 pixm->quantization = V4L2_QUANTIZATION_LIM_RANGE;
1705 break;
1706 case HDMIRX_FULL_RANGE:
1707 pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1708 break;
1709
1710 default:
1711 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
1712 break;
1713 }
1714
1715 if (hdmirx_dev->pix_fmt == HDMIRX_RGB888) {
1716 if (hdmirx_dev->cur_color_space == HDMIRX_BT2020_RGB_OR_YCC)
1717 pixm->colorspace = V4L2_COLORSPACE_BT2020;
1718 else if (hdmirx_dev->cur_color_space == HDMIRX_ADOBE_RGB)
1719 pixm->colorspace = V4L2_COLORSPACE_OPRGB;
1720 else
1721 pixm->colorspace = V4L2_COLORSPACE_SRGB;
1722 } else {
1723 switch (hdmirx_dev->cur_color_space) {
1724 case HDMIRX_XVYCC601:
1725 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1726 pixm->ycbcr_enc = V4L2_YCBCR_ENC_XV601;
1727 break;
1728 case HDMIRX_XVYCC709:
1729 pixm->colorspace = V4L2_COLORSPACE_REC709;
1730 pixm->ycbcr_enc = V4L2_YCBCR_ENC_XV709;
1731 break;
1732 case HDMIRX_SYCC601:
1733 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1734 pixm->ycbcr_enc = V4L2_YCBCR_ENC_601;
1735 break;
1736 case HDMIRX_ADOBE_YCC601:
1737 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1738 pixm->ycbcr_enc = V4L2_YCBCR_ENC_601;
1739 break;
1740 case HDMIRX_BT2020_YCC_CONST_LUM:
1741 pixm->colorspace = V4L2_COLORSPACE_BT2020;
1742 pixm->ycbcr_enc = V4L2_YCBCR_ENC_BT2020_CONST_LUM;
1743 break;
1744 case HDMIRX_BT2020_RGB_OR_YCC:
1745 pixm->colorspace = V4L2_COLORSPACE_BT2020;
1746 pixm->ycbcr_enc = V4L2_YCBCR_ENC_BT2020;
1747 break;
1748
1749 default:
1750 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1751 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1752 break;
1753 }
1754 }
1755
1756 /* calculate plane size and image size */
1757 fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
1758 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
1759
1760 for (i = 0; i < planes; i++) {
1761 struct v4l2_plane_pix_format *plane_fmt;
1762 int width, height, bpl, size, bpp;
1763
1764 if (i == 0) {
1765 width = pixm->width;
1766 height = pixm->height;
1767 } else {
1768 width = pixm->width / xsubs;
1769 height = pixm->height / ysubs;
1770 }
1771
1772 bpp = hdmirx_align_bits_per_pixel(fmt, i);
1773 bpl = ALIGN(width * bpp / HDMIRX_STORED_BIT_WIDTH,
1774 MEMORY_ALIGN_ROUND_UP_BYTES);
1775 size = bpl * height;
1776 imagesize += size;
1777
1778 if (fmt->mplanes > i) {
1779 /* Set bpl and size for each mplane */
1780 plane_fmt = pixm->plane_fmt + i;
1781 plane_fmt->bytesperline = bpl;
1782 plane_fmt->sizeimage = size;
1783 }
1784
1785 v4l2_dbg(1, debug, v4l2_dev,
1786 "C-Plane %i size: %d, Total imagesize: %d\n",
1787 i, size, imagesize);
1788 }
1789
1790 /* convert to non-MPLANE format.
1791 * It's important since we want to unify non-MPLANE and MPLANE.
1792 */
1793 if (fmt->mplanes == 1)
1794 pixm->plane_fmt[0].sizeimage = imagesize;
1795
1796 if (!try) {
1797 stream->out_fmt = fmt;
1798 stream->pixm = *pixm;
1799
1800 v4l2_dbg(1, debug, v4l2_dev,
1801 "%s: req(%d, %d), out(%d, %d), fmt:%#x\n", __func__,
1802 pixm->width, pixm->height, stream->pixm.width,
1803 stream->pixm.height, fmt->fourcc);
1804 }
1805 }
1806
hdmirx_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1807 static int hdmirx_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1808 struct v4l2_format *f)
1809 {
1810 struct hdmirx_stream *stream = video_drvdata(file);
1811 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1812 struct v4l2_pix_format *pix = &f->fmt.pix;
1813
1814 if (pix->pixelformat != hdmirx_dev->cur_fmt_fourcc)
1815 return -EINVAL;
1816
1817 hdmirx_set_fmt(stream, &f->fmt.pix_mp, true);
1818
1819 return 0;
1820 }
1821
hdmirx_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)1822 static int hdmirx_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1823 struct v4l2_fmtdesc *f)
1824 {
1825 const struct hdmirx_output_fmt *fmt;
1826
1827 if (f->index >= ARRAY_SIZE(g_out_fmts))
1828 return -EINVAL;
1829
1830 fmt = &g_out_fmts[f->index];
1831 f->pixelformat = fmt->fourcc;
1832
1833 return 0;
1834 }
1835
hdmirx_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)1836 static int hdmirx_s_fmt_vid_cap_mplane(struct file *file,
1837 void *priv, struct v4l2_format *f)
1838 {
1839 struct hdmirx_stream *stream = video_drvdata(file);
1840 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1841 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1842 struct v4l2_pix_format *pix = &f->fmt.pix;
1843
1844 if (vb2_is_busy(&stream->buf_queue)) {
1845 v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
1846 return -EBUSY;
1847 }
1848
1849 if (pix->pixelformat != hdmirx_dev->cur_fmt_fourcc) {
1850 v4l2_err(v4l2_dev, "%s: err, set_fmt:%#x, cur_fmt:%#x!\n",
1851 __func__, pix->pixelformat, hdmirx_dev->cur_fmt_fourcc);
1852 return -EINVAL;
1853 }
1854
1855 hdmirx_set_fmt(stream, &f->fmt.pix_mp, false);
1856
1857 return 0;
1858 }
1859
hdmirx_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1860 static int hdmirx_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1861 struct v4l2_format *f)
1862 {
1863 struct hdmirx_stream *stream = video_drvdata(file);
1864 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1865 struct v4l2_pix_format_mplane pixm;
1866
1867 pixm.pixelformat = hdmirx_dev->cur_fmt_fourcc;
1868 hdmirx_set_fmt(stream, &pixm, false);
1869 f->fmt.pix_mp = stream->pixm;
1870
1871 return 0;
1872 }
1873
hdmirx_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1874 static int hdmirx_querycap(struct file *file, void *priv,
1875 struct v4l2_capability *cap)
1876 {
1877 struct hdmirx_stream *stream = video_drvdata(file);
1878 struct device *dev = stream->hdmirx_dev->dev;
1879
1880 strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
1881 strscpy(cap->card, dev->driver->name, sizeof(cap->card));
1882 snprintf(cap->bus_info, sizeof(cap->bus_info), "%s", dev_name(dev));
1883
1884 return 0;
1885 }
1886
hdmirx_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])1887 static int hdmirx_queue_setup(struct vb2_queue *queue,
1888 unsigned int *num_buffers,
1889 unsigned int *num_planes,
1890 unsigned int sizes[],
1891 struct device *alloc_ctxs[])
1892 {
1893 struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
1894 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
1895 const struct v4l2_pix_format_mplane *pixm = NULL;
1896 const struct hdmirx_output_fmt *out_fmt;
1897 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
1898 u32 i, height;
1899
1900 pixm = &stream->pixm;
1901 out_fmt = stream->out_fmt;
1902
1903 if ((num_planes == NULL) || (out_fmt == NULL)) {
1904 v4l2_err(v4l2_dev, "%s: out_fmt null pointer err!\n", __func__);
1905 return -EINVAL;
1906 }
1907 *num_planes = out_fmt->mplanes;
1908 height = pixm->height;
1909
1910 for (i = 0; i < out_fmt->mplanes; i++) {
1911 const struct v4l2_plane_pix_format *plane_fmt;
1912 int h = height;
1913
1914 plane_fmt = &pixm->plane_fmt[i];
1915 sizes[i] = plane_fmt->sizeimage / height * h;
1916 }
1917
1918 v4l2_dbg(1, debug, v4l2_dev, "%s count %d, size %d\n",
1919 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
1920
1921 return 0;
1922 }
1923
1924 /*
1925 * The vb2_buffer are stored in hdmirx_buffer, in order to unify
1926 * mplane buffer and none-mplane buffer.
1927 */
hdmirx_buf_queue(struct vb2_buffer * vb)1928 static void hdmirx_buf_queue(struct vb2_buffer *vb)
1929 {
1930 struct vb2_v4l2_buffer *vbuf;
1931 struct hdmirx_buffer *hdmirx_buf;
1932 struct vb2_queue *queue;
1933 struct hdmirx_stream *stream;
1934 struct v4l2_pix_format_mplane *pixm;
1935 const struct hdmirx_output_fmt *out_fmt;
1936 unsigned long lock_flags = 0;
1937 int i;
1938
1939 if (vb == NULL) {
1940 pr_err("%s: vb null pointer err!\n", __func__);
1941 return;
1942 }
1943
1944 vbuf = to_vb2_v4l2_buffer(vb);
1945 hdmirx_buf = to_hdmirx_buffer(vbuf);
1946 queue = vb->vb2_queue;
1947 stream = vb2_get_drv_priv(queue);
1948 pixm = &stream->pixm;
1949 out_fmt = stream->out_fmt;
1950
1951 memset(hdmirx_buf->buff_addr, 0, sizeof(hdmirx_buf->buff_addr));
1952 /*
1953 * If mplanes > 1, every c-plane has its own m-plane,
1954 * otherwise, multiple c-planes are in the same m-plane
1955 */
1956 for (i = 0; i < out_fmt->mplanes; i++)
1957 hdmirx_buf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
1958
1959 if (out_fmt->mplanes == 1) {
1960 if (out_fmt->cplanes == 1) {
1961 hdmirx_buf->buff_addr[HDMIRX_PLANE_CBCR] =
1962 hdmirx_buf->buff_addr[HDMIRX_PLANE_Y];
1963 } else {
1964 for (i = 0; i < out_fmt->cplanes - 1; i++)
1965 hdmirx_buf->buff_addr[i + 1] =
1966 hdmirx_buf->buff_addr[i] +
1967 pixm->plane_fmt[i].bytesperline *
1968 pixm->height;
1969 }
1970 }
1971
1972 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1973 list_add_tail(&hdmirx_buf->queue, &stream->buf_head);
1974 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1975 }
1976
return_all_buffers(struct hdmirx_stream * stream,enum vb2_buffer_state state)1977 static void return_all_buffers(struct hdmirx_stream *stream,
1978 enum vb2_buffer_state state)
1979 {
1980 struct hdmirx_buffer *buf;
1981 unsigned long flags;
1982
1983 spin_lock_irqsave(&stream->vbq_lock, flags);
1984 if (stream->curr_buf)
1985 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
1986 if ((stream->next_buf) && (stream->next_buf != stream->curr_buf))
1987 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
1988 stream->curr_buf = NULL;
1989 stream->next_buf = NULL;
1990
1991 while (!list_empty(&stream->buf_head)) {
1992 buf = list_first_entry(&stream->buf_head,
1993 struct hdmirx_buffer, queue);
1994 list_del(&buf->queue);
1995 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1996 vb2_buffer_done(&buf->vb.vb2_buf, state);
1997 spin_lock_irqsave(&stream->vbq_lock, flags);
1998 }
1999 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2000 }
2001
hdmirx_stop_streaming(struct vb2_queue * queue)2002 static void hdmirx_stop_streaming(struct vb2_queue *queue)
2003 {
2004 struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
2005 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
2006 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2007 int ret;
2008
2009 v4l2_info(v4l2_dev, "stream start stopping\n");
2010 mutex_lock(&hdmirx_dev->stream_lock);
2011 stream->stopping = true;
2012
2013 /* wait last irq to return the buffer */
2014 ret = wait_event_timeout(stream->wq_stopped, stream->stopping != true,
2015 msecs_to_jiffies(50));
2016 if (!ret) {
2017 v4l2_err(v4l2_dev, "%s wait last irq timeout, return bufs!\n",
2018 __func__);
2019 stream->stopping = false;
2020 }
2021
2022 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
2023 hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
2024 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
2025 LINE_FLAG_INT_EN |
2026 HDMIRX_DMA_IDLE_INT |
2027 HDMIRX_LOCK_DISABLE_INT |
2028 LAST_FRAME_AXI_UNFINISH_INT_EN |
2029 FIFO_OVERFLOW_INT_EN |
2030 FIFO_UNDERFLOW_INT_EN |
2031 HDMIRX_AXI_ERROR_INT_EN, 0);
2032 return_all_buffers(stream, VB2_BUF_STATE_ERROR);
2033 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, 0);
2034 sip_hdmirx_config(HDMIRX_AUTO_TOUCH_EN, 0, 0, 0);
2035 mutex_unlock(&hdmirx_dev->stream_lock);
2036 v4l2_info(v4l2_dev, "stream stopping finished\n");
2037 }
2038
hdmirx_start_streaming(struct vb2_queue * queue,unsigned int count)2039 static int hdmirx_start_streaming(struct vb2_queue *queue, unsigned int count)
2040 {
2041 struct hdmirx_stream *stream = vb2_get_drv_priv(queue);
2042 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
2043 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2044 unsigned long lock_flags = 0;
2045 struct v4l2_dv_timings timings = hdmirx_dev->timings;
2046 struct v4l2_bt_timings *bt = &timings.bt;
2047 int line_flag;
2048 uint32_t touch_flag;
2049
2050 if (!hdmirx_dev->get_timing) {
2051 v4l2_err(v4l2_dev, "Err, timing is invalid\n");
2052 return 0;
2053 }
2054
2055 if (signal_not_lock(hdmirx_dev)) {
2056 v4l2_err(v4l2_dev, "%s: signal is not locked, retry!\n", __func__);
2057 process_signal_change(hdmirx_dev);
2058 return 0;
2059 }
2060
2061 mutex_lock(&hdmirx_dev->stream_lock);
2062 touch_flag = (hdmirx_dev->bound_cpu << 1) | 0x1;
2063 sip_hdmirx_config(HDMIRX_AUTO_TOUCH_EN, 0, touch_flag, 100);
2064 stream->frame_idx = 0;
2065 stream->line_flag_int_cnt = 0;
2066 stream->curr_buf = NULL;
2067 stream->next_buf = NULL;
2068 stream->irq_stat = 0;
2069 stream->stopping = false;
2070
2071 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
2072 if (!stream->curr_buf) {
2073 if (!list_empty(&stream->buf_head)) {
2074 stream->curr_buf = list_first_entry(&stream->buf_head,
2075 struct hdmirx_buffer, queue);
2076 list_del(&stream->curr_buf->queue);
2077 } else {
2078 stream->curr_buf = NULL;
2079 }
2080 }
2081 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
2082
2083 if (!stream->curr_buf) {
2084 mutex_unlock(&hdmirx_dev->stream_lock);
2085 return -ENOMEM;
2086 }
2087
2088 v4l2_dbg(2, debug, v4l2_dev,
2089 "%s: start_stream cur_buf y_addr:%#x, uv_addr:%#x\n",
2090 __func__, stream->curr_buf->buff_addr[HDMIRX_PLANE_Y],
2091 stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
2092 hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
2093 stream->curr_buf->buff_addr[HDMIRX_PLANE_Y]);
2094 hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
2095 stream->curr_buf->buff_addr[HDMIRX_PLANE_CBCR]);
2096
2097 if (bt->height) {
2098 if (bt->interlaced == V4L2_DV_INTERLACED)
2099 line_flag = bt->height / 4;
2100 else
2101 line_flag = bt->height / 2;
2102 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG7,
2103 LINE_FLAG_NUM_MASK,
2104 LINE_FLAG_NUM(line_flag));
2105 } else {
2106 v4l2_err(v4l2_dev, "height err: %d\n", bt->height);
2107 }
2108
2109 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, HDMIRX_DMA_EN);
2110 hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
2111 hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1);
2112 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
2113 LINE_FLAG_INT_EN |
2114 HDMIRX_DMA_IDLE_INT |
2115 HDMIRX_LOCK_DISABLE_INT |
2116 LAST_FRAME_AXI_UNFINISH_INT_EN |
2117 FIFO_OVERFLOW_INT_EN |
2118 FIFO_UNDERFLOW_INT_EN |
2119 HDMIRX_AXI_ERROR_INT_EN,
2120 LINE_FLAG_INT_EN |
2121 HDMIRX_DMA_IDLE_INT |
2122 HDMIRX_LOCK_DISABLE_INT |
2123 LAST_FRAME_AXI_UNFINISH_INT_EN |
2124 FIFO_OVERFLOW_INT_EN |
2125 FIFO_UNDERFLOW_INT_EN |
2126 HDMIRX_AXI_ERROR_INT_EN);
2127 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, HDMIRX_DMA_EN);
2128 v4l2_dbg(1, debug, v4l2_dev, "%s: enable dma", __func__);
2129 mutex_unlock(&hdmirx_dev->stream_lock);
2130
2131 return 0;
2132 }
2133
hdmirx_set_mute(struct rk_hdmirx_dev * hdmirx_dev,enum mute_type type)2134 static void hdmirx_set_mute(struct rk_hdmirx_dev *hdmirx_dev, enum mute_type type)
2135 {
2136 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2137
2138 switch (type) {
2139 case MUTE_OFF:
2140 if ((stream->curr_buf != NULL || stream->next_buf != NULL) &&
2141 hdmirx_dev->get_timing)
2142 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
2143 HDMIRX_DMA_EN, HDMIRX_DMA_EN);
2144 break;
2145 case MUTE_VIDEO:
2146 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
2147 break;
2148
2149 default:
2150 break;
2151 }
2152 }
2153
hdmirx_get_hdcp_auth_status(struct rk_hdmirx_dev * hdmirx_dev)2154 static int hdmirx_get_hdcp_auth_status(struct rk_hdmirx_dev *hdmirx_dev)
2155 {
2156 u32 val;
2157
2158 hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff);
2159 msleep(200);
2160 val = hdmirx_readl(hdmirx_dev, HDCP_INT_STATUS) & 0x40;
2161
2162 return val ? 1 : 0;
2163 }
2164
hdmirx_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)2165 static long hdmirx_ioctl_default(struct file *file, void *fh,
2166 bool valid_prio, unsigned int cmd, void *arg)
2167 {
2168 struct hdmirx_stream *stream = video_drvdata(file);
2169 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
2170 long ret = 0;
2171 bool hpd;
2172 enum mute_type type;
2173 enum audio_stat stat;
2174
2175 if (!arg)
2176 return -EINVAL;
2177
2178 switch (cmd) {
2179 case RK_HDMIRX_CMD_GET_FPS:
2180 *(int *)arg = hdmirx_dev->get_timing ? hdmirx_dev->fps : 0;
2181 break;
2182 case RK_HDMIRX_CMD_GET_SIGNAL_STABLE_STATUS:
2183 *(int *)arg = hdmirx_dev->get_timing;
2184 break;
2185 case RK_HDMIRX_CMD_SET_HPD:
2186 hpd = *(int *)arg ? true : false;
2187 hdmirx_hpd_ctrl(hdmirx_dev, hpd);
2188 break;
2189 case RK_HDMIRX_CMD_SET_MUTE:
2190 type = *(int *)arg;
2191 hdmirx_set_mute(hdmirx_dev, type);
2192 break;
2193 case RK_HDMIRX_CMD_SOFT_RESET:
2194 hdmirx_reset_all(hdmirx_dev);
2195 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
2196 &hdmirx_dev->delayed_work_hotplug,
2197 msecs_to_jiffies(1000));
2198 break;
2199 case RK_HDMIRX_CMD_GET_HDCP_STATUS:
2200 *(int *)arg = hdmirx_get_hdcp_auth_status(hdmirx_dev);
2201 break;
2202 case RK_HDMIRX_CMD_SET_AUDIO_STATE:
2203 stat = *(enum audio_stat *)arg;
2204 hdmirx_audio_set_state(hdmirx_dev, stat);
2205 break;
2206 case RK_HDMIRX_CMD_RESET_AUDIO_FIFO:
2207 hdmirx_audio_fifo_init(hdmirx_dev);
2208 break;
2209 case RK_HDMIRX_CMD_GET_INPUT_MODE:
2210 *(int *)arg = hdmirx_dev->is_dvi_mode ? MODE_DVI : MODE_HDMI;
2211 break;
2212 case RK_HDMIRX_CMD_GET_COLOR_RANGE:
2213 hdmirx_get_color_range(hdmirx_dev);
2214 *(int *)arg = hdmirx_dev->cur_color_range;
2215 break;
2216 case RK_HDMIRX_CMD_GET_COLOR_SPACE:
2217 hdmirx_get_color_space(hdmirx_dev);
2218 *(int *)arg = hdmirx_dev->cur_color_space;
2219 break;
2220
2221 default:
2222 ret = -EINVAL;
2223 }
2224
2225 return ret;
2226 }
2227
2228 // ---------------------- vb2 queue -------------------------
2229 static struct vb2_ops hdmirx_vb2_ops = {
2230 .queue_setup = hdmirx_queue_setup,
2231 .buf_queue = hdmirx_buf_queue,
2232 .wait_prepare = vb2_ops_wait_prepare,
2233 .wait_finish = vb2_ops_wait_finish,
2234 .stop_streaming = hdmirx_stop_streaming,
2235 .start_streaming = hdmirx_start_streaming,
2236 };
2237
hdmirx_init_vb2_queue(struct vb2_queue * q,struct hdmirx_stream * stream,enum v4l2_buf_type buf_type)2238 static int hdmirx_init_vb2_queue(struct vb2_queue *q,
2239 struct hdmirx_stream *stream,
2240 enum v4l2_buf_type buf_type)
2241 {
2242 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
2243
2244 q->type = buf_type;
2245 q->io_modes = VB2_MMAP | VB2_DMABUF;
2246 q->drv_priv = stream;
2247 q->ops = &hdmirx_vb2_ops;
2248 q->mem_ops = &vb2_dma_contig_memops;
2249 q->buf_struct_size = sizeof(struct hdmirx_buffer);
2250 q->min_buffers_needed = HDMIRX_REQ_BUFS_MIN;
2251 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2252 q->lock = &stream->vlock;
2253 q->dev = hdmirx_dev->dev;
2254 q->allow_cache_hints = 1;
2255 q->bidirectional = 1;
2256 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
2257 q->gfp_flags = GFP_DMA32;
2258 return vb2_queue_init(q);
2259 }
2260
2261 // ---------------------- video device -------------------------
2262 static const struct v4l2_ioctl_ops hdmirx_v4l2_ioctl_ops = {
2263 .vidioc_querycap = hdmirx_querycap,
2264 .vidioc_try_fmt_vid_cap_mplane = hdmirx_try_fmt_vid_cap_mplane,
2265 .vidioc_s_fmt_vid_cap_mplane = hdmirx_s_fmt_vid_cap_mplane,
2266 .vidioc_g_fmt_vid_cap_mplane = hdmirx_g_fmt_vid_cap_mplane,
2267 .vidioc_enum_fmt_vid_cap = hdmirx_enum_fmt_vid_cap_mplane,
2268
2269 .vidioc_s_dv_timings = hdmirx_s_dv_timings,
2270 .vidioc_g_dv_timings = hdmirx_g_dv_timings,
2271 .vidioc_enum_dv_timings = hdmirx_enum_dv_timings,
2272 .vidioc_query_dv_timings = hdmirx_query_dv_timings,
2273 .vidioc_dv_timings_cap = hdmirx_dv_timings_cap,
2274 .vidioc_enum_input = hdmirx_enum_input,
2275 .vidioc_g_edid = hdmirx_get_edid,
2276 .vidioc_s_edid = hdmirx_set_edid,
2277
2278 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2279 .vidioc_querybuf = vb2_ioctl_querybuf,
2280 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2281 .vidioc_qbuf = vb2_ioctl_qbuf,
2282 .vidioc_expbuf = vb2_ioctl_expbuf,
2283 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2284 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
2285 .vidioc_streamon = vb2_ioctl_streamon,
2286 .vidioc_streamoff = vb2_ioctl_streamoff,
2287
2288 .vidioc_log_status = v4l2_ctrl_log_status,
2289 .vidioc_subscribe_event = hdmirx_subscribe_event,
2290 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2291 .vidioc_default = hdmirx_ioctl_default,
2292 };
2293
2294 static const struct v4l2_file_operations hdmirx_fops = {
2295 .owner = THIS_MODULE,
2296 .open = v4l2_fh_open,
2297 .release = vb2_fop_release,
2298 .unlocked_ioctl = video_ioctl2,
2299 .read = vb2_fop_read,
2300 .poll = vb2_fop_poll,
2301 .mmap = vb2_fop_mmap,
2302 };
2303
hdmirx_register_stream_vdev(struct hdmirx_stream * stream)2304 static int hdmirx_register_stream_vdev(struct hdmirx_stream *stream)
2305 {
2306 struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
2307 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2308 struct video_device *vdev = &stream->vdev;
2309 int ret = 0;
2310 char *vdev_name;
2311
2312 vdev_name = HDMIRX_VDEV_NAME;
2313 strscpy(vdev->name, vdev_name, sizeof(vdev->name));
2314 INIT_LIST_HEAD(&stream->buf_head);
2315 spin_lock_init(&stream->vbq_lock);
2316 mutex_init(&stream->vlock);
2317 init_waitqueue_head(&stream->wq_stopped);
2318 stream->curr_buf = NULL;
2319 stream->next_buf = NULL;
2320
2321 vdev->ioctl_ops = &hdmirx_v4l2_ioctl_ops;
2322 vdev->release = video_device_release_empty;
2323 vdev->fops = &hdmirx_fops;
2324 vdev->minor = -1;
2325 vdev->v4l2_dev = v4l2_dev;
2326 vdev->lock = &stream->vlock;
2327 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
2328 V4L2_CAP_STREAMING;
2329 video_set_drvdata(vdev, stream);
2330 vdev->vfl_dir = VFL_DIR_RX;
2331
2332 hdmirx_init_vb2_queue(&stream->buf_queue, stream,
2333 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
2334 vdev->queue = &stream->buf_queue;
2335
2336 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2337 if (ret < 0) {
2338 v4l2_err(v4l2_dev,
2339 "video_register_device failed with error %d\n", ret);
2340 return ret;
2341 }
2342
2343 return 0;
2344 }
2345
process_signal_change(struct rk_hdmirx_dev * hdmirx_dev)2346 static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev)
2347 {
2348 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2349 const struct v4l2_event evt_signal_lost = {
2350 .type = RK_HDMIRX_V4L2_EVENT_SIGNAL_LOST,
2351 };
2352
2353 hdmirx_dev->get_timing = false;
2354 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, 0);
2355 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
2356 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
2357 LINE_FLAG_INT_EN |
2358 HDMIRX_DMA_IDLE_INT |
2359 HDMIRX_LOCK_DISABLE_INT |
2360 LAST_FRAME_AXI_UNFINISH_INT_EN |
2361 FIFO_OVERFLOW_INT_EN |
2362 FIFO_UNDERFLOW_INT_EN |
2363 HDMIRX_AXI_ERROR_INT_EN, 0);
2364 hdmirx_reset_dma(hdmirx_dev);
2365 hdmirx_interrupts_setup(hdmirx_dev, false);
2366 v4l2_event_queue(&stream->vdev, &evt_signal_lost);
2367 if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_stop)
2368 hdmirx_dev->hdcp->hdcp_stop(hdmirx_dev->hdcp);
2369 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
2370 &hdmirx_dev->delayed_work_res_change,
2371 msecs_to_jiffies(1000));
2372 }
2373
avpunit_0_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2374 static void avpunit_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2375 int status, bool *handled)
2376 {
2377 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2378
2379 if (status & (CED_DYN_CNT_CH2_IRQ |
2380 CED_DYN_CNT_CH1_IRQ |
2381 CED_DYN_CNT_CH0_IRQ)) {
2382 v4l2_dbg(2, debug, v4l2_dev, "%s: avp0_st:%#x\n",
2383 __func__, status);
2384 *handled = true;
2385 }
2386
2387 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
2388 hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0);
2389 }
2390
avpunit_1_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2391 static void avpunit_1_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2392 int status, bool *handled)
2393 {
2394 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2395
2396 if (status & (VMON_VMEAS_IRQ | VMON_HMEAS_IRQ)) {
2397 process_signal_change(hdmirx_dev);
2398 v4l2_dbg(2, debug, v4l2_dev, "%s: avp1_st:%#x\n",
2399 __func__, status);
2400 *handled = true;
2401 }
2402
2403 if (status & DEFRAMER_VSYNC_THR_REACHED_IRQ) {
2404 v4l2_info(v4l2_dev, "Vertical Sync threshold reached interrupt %#x", status);
2405 hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
2406 DEFRAMER_VSYNC_THR_REACHED_MASK_N,
2407 0);
2408 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
2409 &hdmirx_dev->delayed_work_audio, HZ / 2);
2410 *handled = true;
2411 }
2412
2413 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff);
2414 hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_FORCE, 0x0);
2415 }
2416
mainunit_0_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2417 static void mainunit_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2418 int status, bool *handled)
2419 {
2420 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2421
2422 v4l2_dbg(2, debug, v4l2_dev, "mu0_st:%#x\n", status);
2423 if (status & TIMER_BASE_LOCKED_IRQ) {
2424 hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
2425 TIMER_BASE_LOCKED_IRQ, 0);
2426 hdmirx_dev->timer_base_lock = true;
2427 *handled = true;
2428 }
2429
2430 if (status & TMDSQPCLK_OFF_CHG) {
2431 process_signal_change(hdmirx_dev);
2432 v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_OFF_CHG\n", __func__);
2433 *handled = true;
2434 }
2435
2436 if (status & TMDSQPCLK_LOCKED_CHG) {
2437 process_signal_change(hdmirx_dev);
2438 v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSQPCLK_LOCKED_CHG\n", __func__);
2439 *handled = true;
2440 }
2441
2442 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
2443 hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0);
2444 }
2445
mainunit_2_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2446 static void mainunit_2_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2447 int status, bool *handled)
2448 {
2449 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2450
2451 v4l2_dbg(2, debug, v4l2_dev, "mu2_st:%#x\n", status);
2452 if (status & PHYCREG_CR_WRITE_DONE) {
2453 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
2454 PHYCREG_CR_WRITE_DONE, 0);
2455 hdmirx_dev->cr_write_done = true;
2456 *handled = true;
2457 }
2458
2459 if (status & PHYCREG_CR_READ_DONE) {
2460 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
2461 PHYCREG_CR_READ_DONE, 0);
2462 hdmirx_dev->cr_read_done = true;
2463 *handled = true;
2464 }
2465
2466 if (status & TMDSVALID_STABLE_CHG) {
2467 process_signal_change(hdmirx_dev);
2468 v4l2_dbg(2, debug, v4l2_dev, "%s: TMDSVALID_STABLE_CHG\n", __func__);
2469 *handled = true;
2470 }
2471
2472 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
2473 hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0);
2474 }
2475
pkt_0_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2476 static void pkt_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2477 int status, bool *handled)
2478 {
2479 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2480
2481 if ((status & PKTDEC_AVIIF_CHG_IRQ)) {
2482 process_signal_change(hdmirx_dev);
2483 v4l2_dbg(2, debug, v4l2_dev, "%s: ptk0_st:%#x\n",
2484 __func__, status);
2485 *handled = true;
2486 }
2487
2488 hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff);
2489 hdmirx_writel(hdmirx_dev, PKT_0_INT_FORCE, 0x0);
2490 }
2491
pkt_2_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2492 static void pkt_2_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2493 int status, bool *handled)
2494 {
2495 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2496
2497 v4l2_dbg(2, debug, v4l2_dev, "%s pk2_st:%#x\n", __func__, status);
2498 if (status & PKTDEC_AVIIF_RCV_IRQ) {
2499 hdmirx_update_bits(hdmirx_dev, PKT_2_INT_MASK_N,
2500 PKTDEC_AVIIF_RCV_IRQ, 0);
2501 hdmirx_dev->avi_pkt_rcv = true;
2502 v4l2_dbg(2, debug, v4l2_dev, "%s: AVIIF_RCV_IRQ\n", __func__);
2503 *handled = true;
2504 }
2505
2506 hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
2507 }
2508
scdc_int_handler(struct rk_hdmirx_dev * hdmirx_dev,int status,bool * handled)2509 static void scdc_int_handler(struct rk_hdmirx_dev *hdmirx_dev,
2510 int status, bool *handled)
2511 {
2512 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2513
2514 v4l2_dbg(2, debug, v4l2_dev, "%s scdc_st:%#x\n", __func__, status);
2515 if (status & SCDCTMDSCCFG_CHG) {
2516 hdmirx_tmds_clk_ratio_config(hdmirx_dev);
2517 *handled = true;
2518 }
2519
2520 hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
2521 }
2522
hdmirx_hdmi_irq_handler(int irq,void * dev_id)2523 static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id)
2524 {
2525 struct rk_hdmirx_dev *hdmirx_dev = dev_id;
2526 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2527 bool handled = false;
2528 u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st, pk0_st;
2529 u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk, pk0_mask;
2530
2531 mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N);
2532 mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N);
2533 pk0_mask = hdmirx_readl(hdmirx_dev, PKT_0_INT_MASK_N);
2534 pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N);
2535 scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N);
2536 mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS);
2537 mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS);
2538 pk0_st = hdmirx_readl(hdmirx_dev, PKT_0_INT_STATUS);
2539 pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS);
2540 scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS);
2541 avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS);
2542 avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS);
2543 avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N);
2544 avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N);
2545 mu0_st &= mu0_mask;
2546 mu2_st &= mu2_mask;
2547 pk0_st &= pk0_mask;
2548 pk2_st &= pk2_mask;
2549 avp1_st &= avp1_msk;
2550 avp0_st &= avp0_msk;
2551 scdc_st &= scdc_mask;
2552
2553 if (avp0_st)
2554 avpunit_0_int_handler(hdmirx_dev, avp0_st, &handled);
2555 if (avp1_st)
2556 avpunit_1_int_handler(hdmirx_dev, avp1_st, &handled);
2557 if (mu0_st)
2558 mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled);
2559 if (mu2_st)
2560 mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled);
2561 if (pk0_st)
2562 pkt_0_int_handler(hdmirx_dev, pk0_st, &handled);
2563 if (pk2_st)
2564 pkt_2_int_handler(hdmirx_dev, pk2_st, &handled);
2565 if (scdc_st)
2566 scdc_int_handler(hdmirx_dev, scdc_st, &handled);
2567
2568 if (!handled) {
2569 v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled!", __func__);
2570 v4l2_dbg(2, debug, v4l2_dev,
2571 "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk0: %#x, pk2:%#x, scdc:%#x\n",
2572 avp0_st, avp1_st, mu0_st, mu2_st, pk0_st, pk2_st, scdc_st);
2573 }
2574
2575 v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__);
2576 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
2577
2578 return handled ? IRQ_HANDLED : IRQ_NONE;
2579 }
2580
hdmirx_vb_done(struct hdmirx_stream * stream,struct vb2_v4l2_buffer * vb_done)2581 static void hdmirx_vb_done(struct hdmirx_stream *stream,
2582 struct vb2_v4l2_buffer *vb_done)
2583 {
2584 const struct hdmirx_output_fmt *fmt = stream->out_fmt;
2585 u32 i;
2586
2587 /* Dequeue a filled buffer */
2588 for (i = 0; i < fmt->mplanes; i++) {
2589 vb2_set_plane_payload(&vb_done->vb2_buf, i,
2590 stream->pixm.plane_fmt[i].sizeimage);
2591 }
2592
2593 vb_done->vb2_buf.timestamp = ktime_get_ns();
2594 vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
2595 }
2596
dma_idle_int_handler(struct rk_hdmirx_dev * hdmirx_dev,bool * handled)2597 static void dma_idle_int_handler(struct rk_hdmirx_dev *hdmirx_dev, bool *handled)
2598 {
2599 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2600 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2601 struct v4l2_dv_timings timings = hdmirx_dev->timings;
2602 struct v4l2_bt_timings *bt = &timings.bt;
2603 struct vb2_v4l2_buffer *vb_done = NULL;
2604
2605 if (!(stream->irq_stat) && !(stream->irq_stat & LINE_FLAG_INT_EN))
2606 v4l2_dbg(1, debug, v4l2_dev,
2607 "%s: last time have no line_flag_irq\n", __func__);
2608
2609 if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
2610 goto DMA_IDLE_OUT;
2611
2612 if ((bt->interlaced != V4L2_DV_INTERLACED) ||
2613 (stream->line_flag_int_cnt % 2 == 0)) {
2614 if (stream->next_buf) {
2615 if (stream->curr_buf)
2616 vb_done = &stream->curr_buf->vb;
2617
2618 if (vb_done) {
2619 vb_done->vb2_buf.timestamp = ktime_get_ns();
2620 vb_done->sequence = stream->frame_idx;
2621 hdmirx_vb_done(stream, vb_done);
2622 stream->frame_idx++;
2623 if (stream->frame_idx == 30)
2624 v4l2_info(v4l2_dev, "rcv frames\n");
2625 }
2626
2627 stream->curr_buf = NULL;
2628 if (stream->next_buf) {
2629 stream->curr_buf = stream->next_buf;
2630 stream->next_buf = NULL;
2631 }
2632 } else {
2633 v4l2_dbg(3, debug, v4l2_dev,
2634 "%s: next_buf NULL, skip vb_done!\n", __func__);
2635 }
2636 }
2637
2638 DMA_IDLE_OUT:
2639 *handled = true;
2640 }
2641
line_flag_int_handler(struct rk_hdmirx_dev * hdmirx_dev,bool * handled)2642 static void line_flag_int_handler(struct rk_hdmirx_dev *hdmirx_dev, bool *handled)
2643 {
2644 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2645 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2646 struct v4l2_dv_timings timings = hdmirx_dev->timings;
2647 struct v4l2_bt_timings *bt = &timings.bt;
2648 u32 dma_cfg6;
2649
2650 stream->line_flag_int_cnt++;
2651 if (!(stream->irq_stat) && !(stream->irq_stat & HDMIRX_DMA_IDLE_INT))
2652 v4l2_dbg(1, debug, v4l2_dev,
2653 "%s: last have no dma_idle_irq\n", __func__);
2654 dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
2655 if (!(dma_cfg6 & HDMIRX_DMA_EN)) {
2656 v4l2_dbg(2, debug, v4l2_dev, "%s: dma not on\n", __func__);
2657 goto LINE_FLAG_OUT;
2658 }
2659
2660 if (stream->line_flag_int_cnt <= FILTER_FRAME_CNT)
2661 goto LINE_FLAG_OUT;
2662
2663 if ((bt->interlaced != V4L2_DV_INTERLACED) ||
2664 (stream->line_flag_int_cnt % 2 == 0)) {
2665 if (!stream->next_buf) {
2666 spin_lock(&stream->vbq_lock);
2667 if (!list_empty(&stream->buf_head)) {
2668 stream->next_buf = list_first_entry(&stream->buf_head,
2669 struct hdmirx_buffer, queue);
2670 list_del(&stream->next_buf->queue);
2671 } else {
2672 stream->next_buf = NULL;
2673 }
2674 spin_unlock(&stream->vbq_lock);
2675
2676 if (stream->next_buf) {
2677 hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
2678 stream->next_buf->buff_addr[HDMIRX_PLANE_Y]);
2679 hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
2680 stream->next_buf->buff_addr[HDMIRX_PLANE_CBCR]);
2681 } else {
2682 v4l2_dbg(3, debug, v4l2_dev,
2683 "%s: No buffer is available\n", __func__);
2684 }
2685 }
2686 } else {
2687 v4l2_dbg(3, debug, v4l2_dev, "%s: interlace:%d, line_flag_int_cnt:%d\n",
2688 __func__, bt->interlaced, stream->line_flag_int_cnt);
2689 }
2690
2691 LINE_FLAG_OUT:
2692 *handled = true;
2693 }
2694
hdmirx_dma_irq_handler(int irq,void * dev_id)2695 static irqreturn_t hdmirx_dma_irq_handler(int irq, void *dev_id)
2696 {
2697 struct rk_hdmirx_dev *hdmirx_dev = dev_id;
2698 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2699 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2700 u32 dma_stat1, dma_stat13;
2701 bool handled = false;
2702
2703 dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1);
2704 dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13);
2705 v4l2_dbg(3, debug, v4l2_dev, "dma_irq st1:%#x, st13:%d\n",
2706 dma_stat1, dma_stat13);
2707
2708 if (dma_stat1 & HDMIRX_DMA_IDLE_INT) {
2709 if (stream->stopping) {
2710 v4l2_dbg(1, debug, v4l2_dev, "%s: stop stream!\n", __func__);
2711 stream->stopping = false;
2712 hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
2713 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
2714 LINE_FLAG_INT_EN |
2715 HDMIRX_DMA_IDLE_INT |
2716 HDMIRX_LOCK_DISABLE_INT |
2717 LAST_FRAME_AXI_UNFINISH_INT_EN |
2718 FIFO_OVERFLOW_INT_EN |
2719 FIFO_UNDERFLOW_INT_EN |
2720 HDMIRX_AXI_ERROR_INT_EN, 0);
2721 wake_up(&stream->wq_stopped);
2722 return IRQ_HANDLED;
2723 }
2724
2725 dma_idle_int_handler(hdmirx_dev, &handled);
2726 }
2727
2728 if (dma_stat1 & LINE_FLAG_INT_EN)
2729 line_flag_int_handler(hdmirx_dev, &handled);
2730
2731 if (!handled)
2732 v4l2_dbg(3, debug, v4l2_dev,
2733 "%s: dma irq not handled, dma_stat1:%#x!\n",
2734 __func__, dma_stat1);
2735
2736 stream->irq_stat = dma_stat1;
2737 hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
2738
2739 return IRQ_HANDLED;
2740 }
2741
hdmirx_audio_interrupts_setup(struct rk_hdmirx_dev * hdmirx_dev,bool en)2742 static void hdmirx_audio_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en)
2743 {
2744 dev_info(hdmirx_dev->dev, "%s: %d", __func__, en);
2745 if (en) {
2746 hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
2747 DEFRAMER_VSYNC_THR_REACHED_MASK_N,
2748 DEFRAMER_VSYNC_THR_REACHED_MASK_N);
2749 } else {
2750 hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
2751 DEFRAMER_VSYNC_THR_REACHED_MASK_N,
2752 0);
2753 }
2754 }
2755
hdmirx_interrupts_setup(struct rk_hdmirx_dev * hdmirx_dev,bool en)2756 static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en)
2757 {
2758 struct v4l2_bt_timings *bt = &hdmirx_dev->timings.bt;
2759
2760 v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev, "%s: %sable\n",
2761 __func__, en ? "en" : "dis");
2762
2763 if (en && bt->pixelclock > 590000000 && hdmirx_dev->pix_fmt != HDMIRX_YUV420) {
2764 hdmirx_update_bits(hdmirx_dev, VMON_CONTROL,
2765 VMON_IRQ_THR_MASK, VMON_IRQ_THR_MASK);
2766 hdmirx_update_bits(hdmirx_dev, VMON_CONTROL2,
2767 VMON_IRQ_VERTICAL_MASK |
2768 VMON_IRQ_HORIZONAL_MASK,
2769 VMON_IRQ_VERTICAL_SEL(0x1f) |
2770 VMON_IRQ_HORIZONAL_SEL(0x1f));
2771 hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0,
2772 VS_REMAPFILTER_EN_QST |
2773 VS_FILTER_ORDER_QST_MASK |
2774 HS_FILTER_ORDER_QST_MASK,
2775 VS_REMAPFILTER_EN_QST |
2776 VS_FILTER_ORDER_QST(0x3) |
2777 HS_FILTER_ORDER_QST(0x0));
2778 } else {
2779 hdmirx_update_bits(hdmirx_dev, VMON_CONTROL,
2780 VMON_IRQ_THR_MASK, 0);
2781 hdmirx_update_bits(hdmirx_dev, VMON_CONTROL2,
2782 VMON_IRQ_VERTICAL_MASK |
2783 VMON_IRQ_HORIZONAL_MASK,
2784 VMON_IRQ_VERTICAL_SEL(0x1f) |
2785 VMON_IRQ_HORIZONAL_SEL(0x0));
2786 hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0,
2787 HS_FILTER_ORDER_QST_MASK,
2788 HS_FILTER_ORDER_QST(0x3));
2789 }
2790
2791 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
2792 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
2793 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
2794 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff);
2795 hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff);
2796
2797 if (en) {
2798 hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N,
2799 TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG,
2800 TMDSQPCLK_OFF_CHG | TMDSQPCLK_LOCKED_CHG);
2801 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
2802 TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG);
2803 hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N,
2804 VMON_VMEAS_IRQ | VMON_HMEAS_IRQ,
2805 VMON_VMEAS_IRQ | VMON_HMEAS_IRQ);
2806 hdmirx_update_bits(hdmirx_dev, PKT_0_INT_MASK_N,
2807 PKTDEC_AVIIF_CHG_MASK_N,
2808 PKTDEC_AVIIF_CHG_MASK_N);
2809 } else {
2810 hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
2811 hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
2812 hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
2813 hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0);
2814 hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0);
2815 }
2816
2817 sip_hdmirx_config(HDMIRX_REG_PRE_FETCH, 0, MAINUNIT_0_INT_MASK_N, 0);
2818 sip_hdmirx_config(HDMIRX_REG_PRE_FETCH, 0, MAINUNIT_2_INT_MASK_N, 0);
2819 sip_hdmirx_config(HDMIRX_REG_PRE_FETCH, 0, AVPUNIT_0_INT_MASK_N, 0);
2820 sip_hdmirx_config(HDMIRX_REG_PRE_FETCH, 0, AVPUNIT_1_INT_MASK_N, 0);
2821 }
2822
hdmirx_plugin(struct rk_hdmirx_dev * hdmirx_dev)2823 static void hdmirx_plugin(struct rk_hdmirx_dev *hdmirx_dev)
2824 {
2825 int ret;
2826
2827 rockchip_set_system_status(SYS_STATUS_HDMIRX);
2828 cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, 0);
2829 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
2830 &hdmirx_dev->delayed_work_heartbeat, msecs_to_jiffies(10));
2831 sip_wdt_config(WDT_START, 0, 0, 0);
2832 hdmirx_set_cpu_limit_freq(hdmirx_dev);
2833 hdmirx_interrupts_setup(hdmirx_dev, false);
2834 hdmirx_submodule_init(hdmirx_dev);
2835 hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
2836 POWERPROVIDED);
2837 if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_start)
2838 hdmirx_dev->hdcp->hdcp_start(hdmirx_dev->hdcp);
2839 hdmirx_hpd_ctrl(hdmirx_dev, true);
2840 hdmirx_phy_config(hdmirx_dev);
2841 hdmirx_audio_setup(hdmirx_dev);
2842 ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev);
2843 if (ret) {
2844 hdmirx_plugout(hdmirx_dev);
2845 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
2846 &hdmirx_dev->delayed_work_hotplug,
2847 msecs_to_jiffies(1000));
2848 return;
2849 }
2850 hdmirx_dma_config(hdmirx_dev);
2851 hdmirx_interrupts_setup(hdmirx_dev, true);
2852 extcon_set_state_sync(hdmirx_dev->extcon, EXTCON_JACK_VIDEO_IN, true);
2853 hdmirx_audio_handle_plugged_change(hdmirx_dev, 1);
2854 }
2855
hdmirx_plugout(struct rk_hdmirx_dev * hdmirx_dev)2856 static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev)
2857 {
2858 hdmirx_audio_handle_plugged_change(hdmirx_dev, 0);
2859 extcon_set_state_sync(hdmirx_dev->extcon, EXTCON_JACK_VIDEO_IN, false);
2860 hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0);
2861 hdmirx_interrupts_setup(hdmirx_dev, false);
2862 hdmirx_hpd_ctrl(hdmirx_dev, false);
2863 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
2864 hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
2865 LINE_FLAG_INT_EN |
2866 HDMIRX_DMA_IDLE_INT |
2867 HDMIRX_LOCK_DISABLE_INT |
2868 LAST_FRAME_AXI_UNFINISH_INT_EN |
2869 FIFO_OVERFLOW_INT_EN |
2870 FIFO_UNDERFLOW_INT_EN |
2871 HDMIRX_AXI_ERROR_INT_EN, 0);
2872 hdmirx_reset_dma(hdmirx_dev);
2873 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
2874 HDMI_DISABLE | PHY_RESET | PHY_PDDQ,
2875 HDMI_DISABLE);
2876 hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
2877 cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
2878 cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
2879 cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, PM_QOS_DEFAULT_VALUE);
2880 hdmirx_cancel_cpu_limit_freq(hdmirx_dev);
2881 cancel_delayed_work(&hdmirx_dev->delayed_work_heartbeat);
2882 flush_work(&hdmirx_dev->work_wdt_config);
2883 sip_wdt_config(WDT_STOP, 0, 0, 0);
2884 rockchip_clear_system_status(SYS_STATUS_HDMIRX);
2885 }
2886
hdmirx_delayed_work_hotplug(struct work_struct * work)2887 static void hdmirx_delayed_work_hotplug(struct work_struct *work)
2888 {
2889 struct delayed_work *dwork = to_delayed_work(work);
2890 struct rk_hdmirx_dev *hdmirx_dev = container_of(dwork,
2891 struct rk_hdmirx_dev, delayed_work_hotplug);
2892 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
2893 struct hdmirx_stream *stream = &hdmirx_dev->stream;
2894 const struct v4l2_event evt_signal_lost = {
2895 .type = RK_HDMIRX_V4L2_EVENT_SIGNAL_LOST,
2896 };
2897 bool plugin;
2898
2899 mutex_lock(&hdmirx_dev->work_lock);
2900 hdmirx_dev->get_timing = false;
2901 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, 0);
2902 v4l2_event_queue(&stream->vdev, &evt_signal_lost);
2903 plugin = tx_5v_power_present(hdmirx_dev);
2904 v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin);
2905 v4l2_dbg(1, debug, v4l2_dev, "%s: plugin:%d\n", __func__, plugin);
2906
2907 if (plugin)
2908 hdmirx_plugin(hdmirx_dev);
2909 else
2910 hdmirx_plugout(hdmirx_dev);
2911
2912 mutex_unlock(&hdmirx_dev->work_lock);
2913 }
2914
hdmirx_audio_ch(struct rk_hdmirx_dev * hdmirx_dev)2915 static u32 hdmirx_audio_ch(struct rk_hdmirx_dev *hdmirx_dev)
2916 {
2917 u32 acr_pb3_0, acr_pb7_4, ch, ca;
2918
2919 hdmirx_readl(hdmirx_dev, PKTDEC_AUDIF_PH2_1);
2920 acr_pb3_0 = hdmirx_readl(hdmirx_dev, PKTDEC_AUDIF_PB3_0);
2921 acr_pb7_4 = hdmirx_readl(hdmirx_dev, PKTDEC_AUDIF_PB7_4);
2922 ca = acr_pb7_4 & 0xff;
2923 ch = ((acr_pb3_0>>8) & 0x07) + 1;
2924 dev_dbg(hdmirx_dev->dev, "%s: acr_pb3_0=%#x; ch=%u; ca=%#x\n",
2925 __func__, acr_pb3_0, ch, ca);
2926 return ch;
2927 }
2928
hdmirx_audio_fs(struct rk_hdmirx_dev * hdmirx_dev)2929 static u32 hdmirx_audio_fs(struct rk_hdmirx_dev *hdmirx_dev)
2930 {
2931 u64 tmds_clk, fs_audio = 0;
2932 u32 acr_cts, acr_n, tmdsqpclk_freq;
2933 u32 acr_pb7_4, acr_pb3_0;
2934
2935 tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
2936 hdmirx_readl(hdmirx_dev, PKTDEC_ACR_PH2_1);
2937 acr_pb7_4 = hdmirx_readl(hdmirx_dev, PKTDEC_ACR_PB3_0);
2938 acr_pb3_0 = hdmirx_readl(hdmirx_dev, PKTDEC_ACR_PB7_4);
2939 acr_cts = __be32_to_cpu(acr_pb7_4) & 0xfffff;
2940 acr_n = (__be32_to_cpu(acr_pb3_0) & 0x0fffff00) >> 8;
2941 tmds_clk = tmdsqpclk_freq * 4 * 1000U;
2942 if (acr_cts != 0) {
2943 fs_audio = div_u64((tmds_clk * acr_n), acr_cts);
2944 fs_audio /= 128;
2945 fs_audio = div_u64(fs_audio + 50, 100);
2946 fs_audio *= 100;
2947 }
2948 dev_dbg(hdmirx_dev->dev, "%s: fs_audio=%llu; acr_cts=%u; acr_n=%u\n",
2949 __func__, fs_audio, acr_cts, acr_n);
2950 return fs_audio;
2951 }
2952
hdmirx_audio_set_ch(struct rk_hdmirx_dev * hdmirx_dev,u32 ch_audio)2953 static void hdmirx_audio_set_ch(struct rk_hdmirx_dev *hdmirx_dev, u32 ch_audio)
2954 {
2955 hdmirx_dev->audio_state.ch_audio = ch_audio;
2956 }
2957
hdmirx_audio_set_fs(struct rk_hdmirx_dev * hdmirx_dev,u32 fs_audio)2958 static void hdmirx_audio_set_fs(struct rk_hdmirx_dev *hdmirx_dev, u32 fs_audio)
2959 {
2960 u32 hdmirx_aud_clkrate_t = fs_audio*128;
2961
2962 dev_dbg(hdmirx_dev->dev, "%s: %u to %u with fs %u\n", __func__,
2963 hdmirx_dev->audio_state.hdmirx_aud_clkrate, hdmirx_aud_clkrate_t,
2964 fs_audio);
2965 clk_set_rate(hdmirx_dev->clks[1].clk, hdmirx_aud_clkrate_t);
2966 hdmirx_dev->audio_state.hdmirx_aud_clkrate = hdmirx_aud_clkrate_t;
2967 hdmirx_dev->audio_state.fs_audio = fs_audio;
2968 }
2969
hdmirx_audio_fifo_init(struct rk_hdmirx_dev * hdmirx_dev)2970 static void hdmirx_audio_fifo_init(struct rk_hdmirx_dev *hdmirx_dev)
2971 {
2972 dev_info(hdmirx_dev->dev, "%s\n", __func__);
2973 hdmirx_writel(hdmirx_dev, AUDIO_FIFO_CONTROL, 1);
2974 usleep_range(200, 210);
2975 hdmirx_writel(hdmirx_dev, AUDIO_FIFO_CONTROL, 0);
2976 }
2977
hdmirx_audio_clk_ppm_inc(struct rk_hdmirx_dev * hdmirx_dev,int ppm)2978 static void hdmirx_audio_clk_ppm_inc(struct rk_hdmirx_dev *hdmirx_dev, int ppm)
2979 {
2980 int delta, rate, inc;
2981
2982 rate = hdmirx_dev->audio_state.hdmirx_aud_clkrate;
2983 if (ppm < 0) {
2984 ppm = -ppm;
2985 inc = -1;
2986 } else
2987 inc = 1;
2988 delta = (int)div64_u64((uint64_t)rate * ppm + 500000, 1000000);
2989 delta *= inc;
2990 rate = hdmirx_dev->audio_state.hdmirx_aud_clkrate + delta;
2991 dev_dbg(hdmirx_dev->dev, "%s: %u to %u(delta:%d)\n",
2992 __func__, hdmirx_dev->audio_state.hdmirx_aud_clkrate, rate, delta);
2993 clk_set_rate(hdmirx_dev->clks[1].clk, rate);
2994 hdmirx_dev->audio_state.hdmirx_aud_clkrate = rate;
2995 }
2996
hdmirx_audio_set_state(struct rk_hdmirx_dev * hdmirx_dev,enum audio_stat stat)2997 static void hdmirx_audio_set_state(struct rk_hdmirx_dev *hdmirx_dev, enum audio_stat stat)
2998 {
2999 switch (stat) {
3000 case AUDIO_OFF:
3001 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_audio);
3002 hdmirx_update_bits(hdmirx_dev, GLOBAL_SWENABLE, AUDIO_ENABLE, 0);
3003 break;
3004 case AUDIO_ON:
3005 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3006 &hdmirx_dev->delayed_work_audio, HZ / 2);
3007 break;
3008 default:
3009 break;
3010 }
3011 }
3012
hdmirx_audio_setup(struct rk_hdmirx_dev * hdmirx_dev)3013 static void hdmirx_audio_setup(struct rk_hdmirx_dev *hdmirx_dev)
3014 {
3015 struct hdmirx_audiostate *as = &hdmirx_dev->audio_state;
3016
3017 as->ctsn_flag = 0;
3018 as->fs_audio = 0;
3019 as->ch_audio = 0;
3020 as->pre_state = 0;
3021 as->init_state = INIT_FIFO_STATE*4;
3022 as->fifo_int = false;
3023 as->audio_enabled = false;
3024 hdmirx_audio_set_fs(hdmirx_dev, 44100);
3025 /* Disable audio domain */
3026 hdmirx_update_bits(hdmirx_dev, GLOBAL_SWENABLE, AUDIO_ENABLE, 0);
3027 /* Configure Vsync interrupt threshold */
3028 hdmirx_update_bits(hdmirx_dev, DEFRAMER_CONFIG0, VS_CNT_THR_QST_MASK, VS_CNT_THR_QST(3));
3029 hdmirx_audio_interrupts_setup(hdmirx_dev, true);
3030 hdmirx_writel(hdmirx_dev, DEFRAMER_VSYNC_CNT_CLEAR, VSYNC_CNT_CLR_P);
3031 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, DEFRAMER_VSYNC_THR_REACHED_CLEAR);
3032 hdmirx_writel(hdmirx_dev, AUDIO_FIFO_THR_PASS, INIT_FIFO_STATE);
3033 hdmirx_writel(hdmirx_dev, AUDIO_FIFO_THR,
3034 AFIFO_THR_LOW_QST(0x20) | AFIFO_THR_HIGH_QST(0x160));
3035 hdmirx_writel(hdmirx_dev, AUDIO_FIFO_MUTE_THR,
3036 AFIFO_THR_MUTE_LOW_QST(0x8) | AFIFO_THR_MUTE_HIGH_QST(0x178));
3037 }
3038
hdmirx_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)3039 static int hdmirx_audio_hw_params(struct device *dev, void *data,
3040 struct hdmi_codec_daifmt *daifmt,
3041 struct hdmi_codec_params *params)
3042 {
3043 dev_dbg(dev, "%s\n", __func__);
3044 return 0;
3045 }
3046
hdmirx_audio_startup(struct device * dev,void * data)3047 static int hdmirx_audio_startup(struct device *dev, void *data)
3048 {
3049 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3050
3051 if (tx_5v_power_present(hdmirx_dev) && hdmirx_dev->audio_present)
3052 return 0;
3053 dev_err(dev, "%s: device is no connected or audio is off\n", __func__);
3054 return -ENODEV;
3055 }
3056
hdmirx_audio_shutdown(struct device * dev,void * data)3057 static void hdmirx_audio_shutdown(struct device *dev, void *data)
3058 {
3059 dev_dbg(dev, "%s\n", __func__);
3060 }
3061
hdmirx_audio_get_dai_id(struct snd_soc_component * comment,struct device_node * endpoint)3062 static int hdmirx_audio_get_dai_id(struct snd_soc_component *comment,
3063 struct device_node *endpoint)
3064 {
3065 dev_dbg(comment->dev, "%s\n", __func__);
3066 return 0;
3067 }
3068
hdmirx_audio_handle_plugged_change(struct rk_hdmirx_dev * hdmirx_dev,bool plugged)3069 static void hdmirx_audio_handle_plugged_change(struct rk_hdmirx_dev *hdmirx_dev, bool plugged)
3070 {
3071 if (hdmirx_dev->plugged_cb && hdmirx_dev->codec_dev)
3072 hdmirx_dev->plugged_cb(hdmirx_dev->codec_dev, plugged);
3073 }
3074
hdmirx_audio_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)3075 static int hdmirx_audio_hook_plugged_cb(struct device *dev, void *data,
3076 hdmi_codec_plugged_cb fn,
3077 struct device *codec_dev)
3078 {
3079 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3080
3081 dev_dbg(dev, "%s\n", __func__);
3082 mutex_lock(&hdmirx_dev->work_lock);
3083 hdmirx_dev->plugged_cb = fn;
3084 hdmirx_dev->codec_dev = codec_dev;
3085 hdmirx_audio_handle_plugged_change(hdmirx_dev, tx_5v_power_present(hdmirx_dev));
3086 mutex_unlock(&hdmirx_dev->work_lock);
3087 return 0;
3088 }
3089
3090 static const struct hdmi_codec_ops hdmirx_audio_codec_ops = {
3091 .hw_params = hdmirx_audio_hw_params,
3092 .audio_startup = hdmirx_audio_startup,
3093 .audio_shutdown = hdmirx_audio_shutdown,
3094 .get_dai_id = hdmirx_audio_get_dai_id,
3095 .hook_plugged_cb = hdmirx_audio_hook_plugged_cb
3096 };
3097
hdmirx_register_audio_device(struct rk_hdmirx_dev * hdmirx_dev)3098 static int hdmirx_register_audio_device(struct rk_hdmirx_dev *hdmirx_dev)
3099 {
3100 struct hdmirx_audiostate *as = &hdmirx_dev->audio_state;
3101 struct hdmi_codec_pdata codec_data = {
3102 .ops = &hdmirx_audio_codec_ops,
3103 .spdif = 1,
3104 .i2s = 1,
3105 .max_i2s_channels = 8,
3106 .data = hdmirx_dev,
3107 };
3108
3109 as->pdev = platform_device_register_data(hdmirx_dev->dev,
3110 HDMI_CODEC_DRV_NAME,
3111 PLATFORM_DEVID_AUTO,
3112 &codec_data,
3113 sizeof(codec_data));
3114
3115 return PTR_ERR_OR_ZERO(as->pdev);
3116 }
3117
hdmirx_unregister_audio_device(void * data)3118 static void hdmirx_unregister_audio_device(void *data)
3119 {
3120 struct rk_hdmirx_dev *hdmirx_dev = data;
3121 struct hdmirx_audiostate *as = &hdmirx_dev->audio_state;
3122
3123 if (as->pdev) {
3124 platform_device_unregister(as->pdev);
3125 as->pdev = NULL;
3126 }
3127 }
3128
hdmirx_unregister_class_device(void * data)3129 static void hdmirx_unregister_class_device(void *data)
3130 {
3131 struct rk_hdmirx_dev *hdmirx_dev = data;
3132 struct device *dev = hdmirx_dev->classdev;
3133
3134 device_unregister(dev);
3135 }
3136
audio_fifo_err(u32 fifo_status)3137 static const char *audio_fifo_err(u32 fifo_status)
3138 {
3139 switch (fifo_status & (AFIFO_UNDERFLOW_ST | AFIFO_OVERFLOW_ST)) {
3140 case AFIFO_UNDERFLOW_ST:
3141 return "underflow";
3142 case AFIFO_OVERFLOW_ST:
3143 return "overflow";
3144 case AFIFO_UNDERFLOW_ST | AFIFO_OVERFLOW_ST:
3145 return "underflow and overflow";
3146 }
3147 return "underflow or overflow";
3148 }
3149
hdmirx_enable_audio_output(struct rk_hdmirx_dev * hdmirx_dev,int ch_audio,int fs_audio,int spdif)3150 static void hdmirx_enable_audio_output(struct rk_hdmirx_dev *hdmirx_dev,
3151 int ch_audio, int fs_audio, int spdif)
3152 {
3153 if (spdif) {
3154 dev_warn(hdmirx_dev->dev, "We don't recommend using spdif\n");
3155 } else {
3156 if (ch_audio > 2) {
3157 hdmirx_update_bits(hdmirx_dev, AUDIO_PROC_CONFIG0,
3158 SPEAKER_ALLOC_OVR_EN | I2S_EN,
3159 SPEAKER_ALLOC_OVR_EN | I2S_EN);
3160 hdmirx_writel(hdmirx_dev, AUDIO_PROC_CONFIG3, 0xffffffff);
3161 } else {
3162 hdmirx_update_bits(hdmirx_dev, AUDIO_PROC_CONFIG0,
3163 SPEAKER_ALLOC_OVR_EN | I2S_EN, I2S_EN);
3164 }
3165 }
3166 }
3167
hdmirx_delayed_work_audio(struct work_struct * work)3168 static void hdmirx_delayed_work_audio(struct work_struct *work)
3169 {
3170 struct delayed_work *dwork = to_delayed_work(work);
3171 struct rk_hdmirx_dev *hdmirx_dev = container_of(dwork,
3172 struct rk_hdmirx_dev,
3173 delayed_work_audio);
3174 struct hdmirx_audiostate *as = &hdmirx_dev->audio_state;
3175 u32 fs_audio, ch_audio;
3176 int cur_state, init_state, pre_state, fifo_status2;
3177 unsigned long delay = 200;
3178
3179 if (!as->audio_enabled) {
3180 dev_info(hdmirx_dev->dev, "%s: enable audio\n", __func__);
3181 hdmirx_update_bits(hdmirx_dev, GLOBAL_SWENABLE, AUDIO_ENABLE, AUDIO_ENABLE);
3182 hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, AUDIO_SWRESETREQ);
3183 as->audio_enabled = true;
3184 }
3185 fs_audio = hdmirx_audio_fs(hdmirx_dev);
3186 ch_audio = hdmirx_audio_ch(hdmirx_dev);
3187 fifo_status2 = hdmirx_readl(hdmirx_dev, AUDIO_FIFO_STATUS2);
3188 if (fifo_status2 & (AFIFO_UNDERFLOW_ST | AFIFO_OVERFLOW_ST)) {
3189 dev_warn(hdmirx_dev->dev, "%s: audio %s %#x, with fs %svalid %d\n",
3190 __func__, audio_fifo_err(fifo_status2), fifo_status2,
3191 is_validfs(fs_audio) ? "" : "in", fs_audio);
3192 if (is_validfs(fs_audio)) {
3193 hdmirx_audio_set_fs(hdmirx_dev, fs_audio);
3194 hdmirx_audio_set_ch(hdmirx_dev, ch_audio);
3195 hdmirx_enable_audio_output(hdmirx_dev, ch_audio, fs_audio, 0);
3196 }
3197 hdmirx_audio_fifo_init(hdmirx_dev);
3198 as->pre_state = 0;
3199 goto exit;
3200 }
3201 cur_state = fifo_status2 & 0xFFFF;
3202 init_state = as->init_state;
3203 pre_state = as->pre_state;
3204 dev_dbg(hdmirx_dev->dev, "%s: HDMI_RX_AUD_FIFO_FILLSTS1:%#x, single offset:%d, total offset:%d\n",
3205 __func__, cur_state, cur_state - pre_state, cur_state - init_state);
3206 if (!is_validfs(fs_audio)) {
3207 v4l2_dbg(1, debug, &hdmirx_dev->v4l2_dev,
3208 "%s: no supported fs(%u), cur_state %d\n",
3209 __func__, fs_audio, cur_state);
3210 delay = 1000;
3211 } else if (abs(fs_audio - as->fs_audio) > 1000 || ch_audio != as->ch_audio) {
3212 dev_info(hdmirx_dev->dev, "%s: restart audio fs(%d -> %d) ch(%d -> %d)\n",
3213 __func__, as->fs_audio, fs_audio, as->ch_audio, ch_audio);
3214 hdmirx_audio_set_fs(hdmirx_dev, fs_audio);
3215 hdmirx_audio_set_ch(hdmirx_dev, ch_audio);
3216 hdmirx_enable_audio_output(hdmirx_dev, ch_audio, fs_audio, 0);
3217 hdmirx_audio_fifo_init(hdmirx_dev);
3218 as->pre_state = 0;
3219 goto exit;
3220 }
3221
3222 if (cur_state != 0) {
3223 if (!hdmirx_dev->audio_present) {
3224 dev_info(hdmirx_dev->dev, "audio on");
3225 hdmirx_audio_handle_plugged_change(hdmirx_dev, 1);
3226 hdmirx_dev->audio_present = true;
3227 }
3228 if (cur_state - init_state > 16 && cur_state - pre_state > 0)
3229 hdmirx_audio_clk_ppm_inc(hdmirx_dev, 10);
3230 else if (cur_state - init_state < -16 && cur_state - pre_state < 0)
3231 hdmirx_audio_clk_ppm_inc(hdmirx_dev, -10);
3232 } else {
3233 if (hdmirx_dev->audio_present) {
3234 dev_info(hdmirx_dev->dev, "audio off");
3235 hdmirx_audio_handle_plugged_change(hdmirx_dev, 0);
3236 hdmirx_dev->audio_present = false;
3237 }
3238 }
3239 as->pre_state = cur_state;
3240 exit:
3241 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3242 &hdmirx_dev->delayed_work_audio,
3243 msecs_to_jiffies(delay));
3244 }
3245
hdmirx_delayed_work_res_change(struct work_struct * work)3246 static void hdmirx_delayed_work_res_change(struct work_struct *work)
3247 {
3248 struct delayed_work *dwork = to_delayed_work(work);
3249 struct rk_hdmirx_dev *hdmirx_dev = container_of(dwork,
3250 struct rk_hdmirx_dev, delayed_work_res_change);
3251 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
3252 bool plugin;
3253 int ret;
3254
3255 mutex_lock(&hdmirx_dev->work_lock);
3256 sip_hdmirx_config(HDMIRX_INFO_NOTIFY, 0, DMA_CONFIG6, 0);
3257 plugin = tx_5v_power_present(hdmirx_dev);
3258 v4l2_dbg(1, debug, v4l2_dev, "%s: plugin:%d\n", __func__, plugin);
3259 if (plugin) {
3260 hdmirx_submodule_init(hdmirx_dev);
3261 hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
3262 POWERPROVIDED);
3263 if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_start)
3264 hdmirx_dev->hdcp->hdcp_start(hdmirx_dev->hdcp);
3265 hdmirx_hpd_ctrl(hdmirx_dev, true);
3266 hdmirx_phy_config(hdmirx_dev);
3267 hdmirx_audio_setup(hdmirx_dev);
3268 ret = hdmirx_wait_lock_and_get_timing(hdmirx_dev);
3269 if (ret) {
3270 hdmirx_plugout(hdmirx_dev);
3271 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3272 &hdmirx_dev->delayed_work_hotplug,
3273 msecs_to_jiffies(1000));
3274 } else {
3275 hdmirx_dma_config(hdmirx_dev);
3276 hdmirx_interrupts_setup(hdmirx_dev, true);
3277 hdmirx_audio_handle_plugged_change(hdmirx_dev, 1);
3278 }
3279 }
3280 mutex_unlock(&hdmirx_dev->work_lock);
3281 }
3282
hdmirx_delayed_work_heartbeat(struct work_struct * work)3283 static void hdmirx_delayed_work_heartbeat(struct work_struct *work)
3284 {
3285 struct delayed_work *dwork = to_delayed_work(work);
3286 struct rk_hdmirx_dev *hdmirx_dev = container_of(dwork,
3287 struct rk_hdmirx_dev, delayed_work_heartbeat);
3288
3289 queue_work_on(hdmirx_dev->wdt_cfg_bound_cpu, system_highpri_wq,
3290 &hdmirx_dev->work_wdt_config);
3291 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3292 &hdmirx_dev->delayed_work_heartbeat, HZ);
3293 }
3294
hdmirx_work_wdt_config(struct work_struct * work)3295 static void hdmirx_work_wdt_config(struct work_struct *work)
3296 {
3297 struct rk_hdmirx_dev *hdmirx_dev = container_of(work,
3298 struct rk_hdmirx_dev, work_wdt_config);
3299 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
3300
3301 sip_wdt_config(WDT_PING, 0, 0, 0);
3302 v4l2_dbg(3, debug, v4l2_dev, "hb\n");
3303 }
3304
hdmirx_5v_det_irq_handler(int irq,void * dev_id)3305 static irqreturn_t hdmirx_5v_det_irq_handler(int irq, void *dev_id)
3306 {
3307 struct rk_hdmirx_dev *hdmirx_dev = dev_id;
3308 u32 val;
3309 u32 dma_cfg6;
3310
3311 dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
3312 if (dma_cfg6 & HDMIRX_DMA_EN) {
3313 hdmirx_update_bits(hdmirx_dev, MAINUNIT_2_INT_MASK_N,
3314 TMDSVALID_STABLE_CHG, TMDSVALID_STABLE_CHG);
3315 hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, TMDSVALID_STABLE_CHG);
3316 }
3317
3318 val = gpiod_get_value(hdmirx_dev->hdmirx_det_gpio);
3319 v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: 5v:%d\n", __func__, val);
3320
3321 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3322 &hdmirx_dev->delayed_work_hotplug, msecs_to_jiffies(10));
3323
3324 return IRQ_HANDLED;
3325 }
3326
3327 static const struct hdmirx_cec_ops hdmirx_cec_ops = {
3328 .write = hdmirx_writel,
3329 .read = hdmirx_readl,
3330 };
3331
hdmirx_parse_dt(struct rk_hdmirx_dev * hdmirx_dev)3332 static int hdmirx_parse_dt(struct rk_hdmirx_dev *hdmirx_dev)
3333 {
3334 struct device *dev = hdmirx_dev->dev;
3335 struct device_node *np = hdmirx_dev->of_node;
3336 int ret;
3337
3338 if (!np) {
3339 dev_err(dev, "missing DT node\n");
3340 return -EINVAL;
3341 }
3342
3343 hdmirx_dev->num_clks = devm_clk_bulk_get_all(dev, &hdmirx_dev->clks);
3344 if (hdmirx_dev->num_clks < 1)
3345 return -ENODEV;
3346
3347 hdmirx_dev->rst_a = devm_reset_control_get(hdmirx_dev->dev, "rst_a");
3348 if (IS_ERR(hdmirx_dev->rst_a)) {
3349 dev_err(dev, "failed to get rst_a control\n");
3350 return PTR_ERR(hdmirx_dev->rst_a);
3351 }
3352
3353 hdmirx_dev->rst_p = devm_reset_control_get(hdmirx_dev->dev, "rst_p");
3354 if (IS_ERR(hdmirx_dev->rst_p)) {
3355 dev_err(dev, "failed to get rst_p control\n");
3356 return PTR_ERR(hdmirx_dev->rst_p);
3357 }
3358
3359 hdmirx_dev->rst_ref = devm_reset_control_get(hdmirx_dev->dev, "rst_ref");
3360 if (IS_ERR(hdmirx_dev->rst_ref)) {
3361 dev_err(dev, "failed to get rst_ref control\n");
3362 return PTR_ERR(hdmirx_dev->rst_ref);
3363 }
3364
3365 hdmirx_dev->rst_biu = devm_reset_control_get(hdmirx_dev->dev, "rst_biu");
3366 if (IS_ERR(hdmirx_dev->rst_biu)) {
3367 dev_err(dev, "failed to get rst_biu control\n");
3368 return PTR_ERR(hdmirx_dev->rst_biu);
3369 }
3370
3371
3372 hdmirx_dev->hdmirx_det_gpio = devm_gpiod_get_optional(dev,
3373 "hdmirx-det", GPIOD_IN);
3374 if (IS_ERR(hdmirx_dev->hdmirx_det_gpio)) {
3375 dev_err(dev, "failed to get hdmirx det gpio\n");
3376 return PTR_ERR(hdmirx_dev->hdmirx_det_gpio);
3377 }
3378
3379 hdmirx_dev->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
3380 if (IS_ERR(hdmirx_dev->grf)) {
3381 dev_err(dev, "failed to get rockchip,grf\n");
3382 return PTR_ERR(hdmirx_dev->grf);
3383 }
3384
3385 hdmirx_dev->vo1_grf = syscon_regmap_lookup_by_phandle(np,
3386 "rockchip,vo1_grf");
3387 if (IS_ERR(hdmirx_dev->vo1_grf)) {
3388 dev_err(dev, "failed to get rockchip,vo1_grf\n");
3389 return PTR_ERR(hdmirx_dev->vo1_grf);
3390 }
3391
3392 if (of_property_read_u32(np, "hpd-trigger-level",
3393 &hdmirx_dev->hpd_trigger_level)) {
3394 hdmirx_dev->hpd_trigger_level = 1;
3395 dev_warn(dev, "failed to get hpd-trigger-level, set high as default\n");
3396 }
3397
3398 if (of_property_read_bool(np, "hdcp1x-enable"))
3399 hdmirx_dev->hdcp_enable = HDCP_1X_ENABLE;
3400
3401 if (of_property_read_bool(np, "hdcp2x-enable"))
3402 hdmirx_dev->hdcp_enable = HDCP_2X_ENABLE;
3403
3404 if (of_property_read_bool(np, "cec-enable"))
3405 hdmirx_dev->cec_enable = true;
3406
3407 ret = of_reserved_mem_device_init(dev);
3408 if (ret)
3409 dev_warn(dev, "No reserved memory for HDMIRX, use default CMA\n");
3410
3411 return 0;
3412 }
3413
hdmirx_disable_all_interrupts(struct rk_hdmirx_dev * hdmirx_dev)3414 static void hdmirx_disable_all_interrupts(struct rk_hdmirx_dev *hdmirx_dev)
3415 {
3416 hdmirx_audio_interrupts_setup(hdmirx_dev, false);
3417 hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
3418 hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0);
3419 hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
3420 hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
3421 hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0);
3422 hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0);
3423 hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0);
3424 hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0);
3425 hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0);
3426 hdmirx_writel(hdmirx_dev, HDCP_INT_MASK_N, 0);
3427 hdmirx_writel(hdmirx_dev, HDCP_1_INT_MASK_N, 0);
3428 hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0);
3429
3430 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_0_INT_CLEAR, 0xffffffff);
3431 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_1_INT_CLEAR, 0xffffffff);
3432 hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff);
3433 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff);
3434 hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff);
3435 hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff);
3436 hdmirx_clear_interrupt(hdmirx_dev, PKT_1_INT_CLEAR, 0xffffffff);
3437 hdmirx_clear_interrupt(hdmirx_dev, PKT_2_INT_CLEAR, 0xffffffff);
3438 hdmirx_clear_interrupt(hdmirx_dev, SCDC_INT_CLEAR, 0xffffffff);
3439 hdmirx_clear_interrupt(hdmirx_dev, HDCP_INT_CLEAR, 0xffffffff);
3440 hdmirx_clear_interrupt(hdmirx_dev, HDCP_1_INT_CLEAR, 0xffffffff);
3441 hdmirx_clear_interrupt(hdmirx_dev, CEC_INT_CLEAR, 0xffffffff);
3442 }
3443
hdmirx_power_on(struct rk_hdmirx_dev * hdmirx_dev)3444 static int hdmirx_power_on(struct rk_hdmirx_dev *hdmirx_dev)
3445 {
3446 pm_runtime_enable(hdmirx_dev->dev);
3447 pm_runtime_get_sync(hdmirx_dev->dev);
3448 hdmirx_dev->power_on = true;
3449
3450 hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0);
3451 regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2,
3452 (HDCP1_GATING_EN | HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) |
3453 ((HDCP1_GATING_EN | HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16));
3454 regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON1,
3455 HDCP1_P0_GPIO_IN_SEL | HDCP1_P0_GPIO_IN_SEL << 16);
3456
3457 /*
3458 * Some interrupts are enabled by default, so we disable
3459 * all interrupts and clear interrupts status first.
3460 */
3461 hdmirx_disable_all_interrupts(hdmirx_dev);
3462
3463 return 0;
3464 }
3465
hdmirx_edid_init_config(struct rk_hdmirx_dev * hdmirx_dev)3466 static void hdmirx_edid_init_config(struct rk_hdmirx_dev *hdmirx_dev)
3467 {
3468 int ret;
3469 struct v4l2_edid def_edid;
3470
3471 /* disable hpd and write edid */
3472 def_edid.pad = 0;
3473 def_edid.start_block = 0;
3474 def_edid.blocks = EDID_NUM_BLOCKS_MAX;
3475 if (hdmirx_dev->edid_version == HDMIRX_EDID_600M)
3476 def_edid.edid = edid_init_data_600M;
3477 else
3478 def_edid.edid = edid_init_data_340M;
3479 ret = hdmirx_write_edid(hdmirx_dev, &def_edid, false);
3480 if (ret)
3481 dev_err(hdmirx_dev->dev, "%s write edid failed!\n", __func__);
3482 }
3483
hdmirx_runtime_suspend(struct device * dev)3484 static int hdmirx_runtime_suspend(struct device *dev)
3485 {
3486 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3487 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
3488
3489 disable_irq(hdmirx_dev->hdmi_irq);
3490 disable_irq(hdmirx_dev->dma_irq);
3491 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_DIS, RK_IRQ_HDMIRX_HDMI, 0);
3492
3493 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_hotplug);
3494 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_res_change);
3495 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_audio);
3496 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_heartbeat);
3497 cancel_delayed_work_sync(&hdmirx_dev->delayed_work_cec);
3498 flush_work(&hdmirx_dev->work_wdt_config);
3499 sip_wdt_config(WDT_STOP, 0, 0, 0);
3500
3501 clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks);
3502
3503 v4l2_dbg(2, debug, v4l2_dev, "%s: suspend!\n", __func__);
3504
3505 return pinctrl_pm_select_sleep_state(dev);
3506 }
3507
hdmirx_runtime_resume(struct device * dev)3508 static int hdmirx_runtime_resume(struct device *dev)
3509 {
3510 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3511 struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
3512 int ret;
3513
3514 v4l2_dbg(2, debug, v4l2_dev, "%s: resume!\n", __func__);
3515 ret = pinctrl_pm_select_default_state(dev);
3516 if (ret < 0)
3517 return ret;
3518
3519 ret = clk_bulk_prepare_enable(hdmirx_dev->num_clks, hdmirx_dev->clks);
3520 if (ret) {
3521 dev_err(dev, "failed to enable hdmirx bulk clks: %d\n", ret);
3522 return ret;
3523 }
3524
3525 reset_control_assert(hdmirx_dev->rst_a);
3526 reset_control_assert(hdmirx_dev->rst_p);
3527 reset_control_assert(hdmirx_dev->rst_ref);
3528 reset_control_assert(hdmirx_dev->rst_biu);
3529 usleep_range(150, 160);
3530 reset_control_deassert(hdmirx_dev->rst_a);
3531 reset_control_deassert(hdmirx_dev->rst_p);
3532 reset_control_deassert(hdmirx_dev->rst_ref);
3533 reset_control_deassert(hdmirx_dev->rst_biu);
3534 usleep_range(150, 160);
3535
3536 hdmirx_edid_init_config(hdmirx_dev);
3537
3538 if (hdmirx_dev->cec && hdmirx_dev->cec->adap)
3539 hdmirx_cec_state_reconfiguration(hdmirx_dev, false);
3540
3541 if (hdmirx_dev->initialized) {
3542 enable_irq(hdmirx_dev->hdmi_irq);
3543 enable_irq(hdmirx_dev->dma_irq);
3544 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
3545 }
3546
3547 regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON2,
3548 (HDCP1_GATING_EN | HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) |
3549 ((HDCP1_GATING_EN | HDMIRX_SDAIN_MSK | HDMIRX_SCLIN_MSK) << 16));
3550 regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON1,
3551 HDCP1_P0_GPIO_IN_SEL | HDCP1_P0_GPIO_IN_SEL << 16);
3552 if (hdmirx_dev->initialized)
3553 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3554 &hdmirx_dev->delayed_work_hotplug,
3555 msecs_to_jiffies(20));
3556 else
3557 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3558 &hdmirx_dev->delayed_work_hotplug,
3559 msecs_to_jiffies(2000));
3560
3561 return 0;
3562 }
3563
3564 static const struct dev_pm_ops rk_hdmirx_pm_ops = {
3565 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
3566 pm_runtime_force_resume)
3567 SET_RUNTIME_PM_OPS(hdmirx_runtime_suspend, hdmirx_runtime_resume, NULL)
3568 };
3569
audio_rate_show(struct device * dev,struct device_attribute * attr,char * buf)3570 static ssize_t audio_rate_show(struct device *dev,
3571 struct device_attribute *attr, char *buf)
3572 {
3573 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3574
3575 return snprintf(buf, PAGE_SIZE, "%d", hdmirx_dev->audio_state.fs_audio);
3576 }
3577
audio_present_show(struct device * dev,struct device_attribute * attr,char * buf)3578 static ssize_t audio_present_show(struct device *dev,
3579 struct device_attribute *attr, char *buf)
3580 {
3581 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3582
3583 return snprintf(buf, PAGE_SIZE, "%d",
3584 tx_5v_power_present(hdmirx_dev) ? hdmirx_dev->audio_present : 0);
3585 }
3586
edid_show(struct device * dev,struct device_attribute * attr,char * buf)3587 static ssize_t edid_show(struct device *dev,
3588 struct device_attribute *attr, char *buf)
3589 {
3590 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3591 int edid = 0;
3592
3593 if (hdmirx_dev)
3594 edid = hdmirx_dev->edid_version;
3595
3596 return snprintf(buf, PAGE_SIZE, "%d\n", edid);
3597 }
3598
edid_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3599 static ssize_t edid_store(struct device *dev,
3600 struct device_attribute *attr,
3601 const char *buf, size_t count)
3602 {
3603 int edid;
3604 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3605
3606 if (!hdmirx_dev)
3607 return -EINVAL;
3608
3609 if (kstrtoint(buf, 10, &edid))
3610 return -EINVAL;
3611
3612 if (edid != HDMIRX_EDID_340M && edid != HDMIRX_EDID_600M)
3613 return count;
3614
3615 if (hdmirx_dev->edid_version != edid) {
3616 disable_irq(hdmirx_dev->hdmi_irq);
3617 disable_irq(hdmirx_dev->dma_irq);
3618 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_DIS, RK_IRQ_HDMIRX_HDMI, 0);
3619
3620 if (tx_5v_power_present(hdmirx_dev))
3621 hdmirx_plugout(hdmirx_dev);
3622 hdmirx_dev->edid_version = edid;
3623 hdmirx_edid_init_config(hdmirx_dev);
3624
3625 enable_irq(hdmirx_dev->hdmi_irq);
3626 enable_irq(hdmirx_dev->dma_irq);
3627 sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
3628 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
3629 &hdmirx_dev->delayed_work_hotplug,
3630 msecs_to_jiffies(1000));
3631 }
3632
3633 return count;
3634 }
3635
status_show(struct device * dev,struct device_attribute * attr,char * buf)3636 static ssize_t status_show(struct device *dev,
3637 struct device_attribute *attr, char *buf)
3638 {
3639 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3640
3641 if (!hdmirx_dev)
3642 return -EINVAL;
3643
3644 return snprintf(buf, PAGE_SIZE, "%s\n",
3645 hdmirx_dev->hpd_on ? "connected" : "disconnected");
3646 }
3647
status_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3648 static ssize_t status_store(struct device *dev,
3649 struct device_attribute *attr,
3650 const char *buf, size_t count)
3651 {
3652 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
3653
3654 if (!hdmirx_dev)
3655 return -EINVAL;
3656
3657 if (sysfs_streq(buf, "on")) {
3658 hdmirx_dev->force_off = false;
3659 if (!tx_5v_power_present(hdmirx_dev))
3660 return count;
3661 hdmirx_hpd_ctrl(hdmirx_dev, true);
3662 } else if (sysfs_streq(buf, "off")) {
3663 hdmirx_dev->force_off = true;
3664 if (!tx_5v_power_present(hdmirx_dev))
3665 return count;
3666 hdmirx_hpd_ctrl(hdmirx_dev, false);
3667 } else {
3668 return -EINVAL;
3669 }
3670
3671 return count;
3672 }
3673
3674 static DEVICE_ATTR_RO(audio_rate);
3675 static DEVICE_ATTR_RO(audio_present);
3676 static DEVICE_ATTR_RW(edid);
3677 static DEVICE_ATTR_RW(status);
3678
3679 static struct attribute *hdmirx_attrs[] = {
3680 &dev_attr_audio_rate.attr,
3681 &dev_attr_audio_present.attr,
3682 &dev_attr_edid.attr,
3683 &dev_attr_status.attr,
3684 NULL
3685 };
3686 ATTRIBUTE_GROUPS(hdmirx);
3687
3688 static const struct hdmirx_reg_table hdmirx_ctrl_table[] = {
3689 {0x00, 0x0c, HDMIRX_ATTR_RO},
3690 {0x10, 0x10, HDMIRX_ATTR_RE},
3691 {0x14, 0x1c, HDMIRX_ATTR_RO},
3692 {0x20, 0x20, HDMIRX_ATTR_WO},
3693 {0x24, 0x28, HDMIRX_ATTR_RW},
3694 {0x40, 0x40, HDMIRX_ATTR_WO},
3695 {0x44, 0x44, HDMIRX_ATTR_RO},
3696 {0x48, 0x48, HDMIRX_ATTR_RW},
3697 {0x50, 0x50, HDMIRX_ATTR_RW},
3698 {0x60, 0x60, HDMIRX_ATTR_RW},
3699 {0x70, 0x70, HDMIRX_ATTR_RE},
3700 {0x74, 0x74, HDMIRX_ATTR_RW},
3701 {0x78, 0x78, HDMIRX_ATTR_RE},
3702 {0x7c, 0x7c, HDMIRX_ATTR_RO},
3703 {0x80, 0x84, HDMIRX_ATTR_RO},
3704 {0xc0, 0xc0, HDMIRX_ATTR_RO},
3705 {0xc4, 0xc4, HDMIRX_ATTR_RE},
3706 {0xc8, 0xc8, HDMIRX_ATTR_RO},
3707 {0xcc, 0xd4, HDMIRX_ATTR_RW},
3708 {0xd8, 0xd8, HDMIRX_ATTR_RO},
3709 {0xe0, 0xe8, HDMIRX_ATTR_RW},
3710 {0xf0, 0xf0, HDMIRX_ATTR_WO},
3711 {0xf4, 0xf4, HDMIRX_ATTR_RO},
3712 {0xf8, 0xf8, HDMIRX_ATTR_RW},
3713 {0x150, 0x150, HDMIRX_ATTR_RO},
3714 {0x160, 0x164, HDMIRX_ATTR_RW},
3715 {0x210, 0x214, HDMIRX_ATTR_RW},
3716 {0x218, 0x218, HDMIRX_ATTR_RO},
3717 {0x220, 0x228, HDMIRX_ATTR_RE},
3718 {0x22c, 0x22c, HDMIRX_ATTR_RW},
3719 {0x230, 0x230, HDMIRX_ATTR_WO},
3720 {0x234, 0x234, HDMIRX_ATTR_RO},
3721 {0x270, 0x274, HDMIRX_ATTR_RW},
3722 {0x278, 0x278, HDMIRX_ATTR_WO},
3723 {0x27c, 0x27c, HDMIRX_ATTR_RO},
3724 {0x290, 0x294, HDMIRX_ATTR_RW},
3725 {0x2a0, 0x2a8, HDMIRX_ATTR_WO},
3726 {0x2ac, 0x2ac, HDMIRX_ATTR_RO},
3727 {0x2b0, 0x2b4, HDMIRX_ATTR_RE},
3728 {0x2b8, 0x2b8, HDMIRX_ATTR_RO},
3729 {0x2bc, 0x2bc, HDMIRX_ATTR_RW},
3730 {0x2c0, 0x2d0, HDMIRX_ATTR_RO},
3731 {0x2d4, 0x2d8, HDMIRX_ATTR_RW},
3732 {0x2e0, 0x2e0, HDMIRX_ATTR_RW},
3733 {0x2e4, 0x2e4, HDMIRX_ATTR_RO},
3734 {0x2f0, 0x2f0, HDMIRX_ATTR_RW},
3735 {0x2f4, 0x2f4, HDMIRX_ATTR_RO},
3736 {0x2f8, 0x2f8, HDMIRX_ATTR_RW},
3737 {0x2fc, 0x2fc, HDMIRX_ATTR_RO},
3738 {0x300, 0x300, HDMIRX_ATTR_RW},
3739 {0x304, 0x304, HDMIRX_ATTR_RO},
3740 /* {0x3f0, 0x410, HDMIRX_ATTR_WO}, */
3741 {0x420, 0x434, HDMIRX_ATTR_RW},
3742 {0x460, 0x460, HDMIRX_ATTR_RW},
3743 /* {0x464, 0x478, HDMIRX_ATTR_WO}, */
3744 {0x480, 0x48c, HDMIRX_ATTR_RW},
3745 {0x490, 0x494, HDMIRX_ATTR_RO},
3746 {0x580, 0x580, HDMIRX_ATTR_RW},
3747 {0x584, 0x584, HDMIRX_ATTR_WO},
3748 {0x588, 0x59c, HDMIRX_ATTR_RO},
3749 {0x5a0, 0x5a4, HDMIRX_ATTR_RE},
3750 {0x5a8, 0x5bc, HDMIRX_ATTR_RO},
3751 {0x5c0, 0x5e0, HDMIRX_ATTR_RW},
3752 {0x700, 0x728, HDMIRX_ATTR_RW},
3753 {0x740, 0x74c, HDMIRX_ATTR_RW},
3754 {0x760, 0x760, HDMIRX_ATTR_RW},
3755 {0x764, 0x764, HDMIRX_ATTR_RO},
3756 {0x768, 0x768, HDMIRX_ATTR_RW},
3757 {0x7c0, 0x7c8, HDMIRX_ATTR_RW},
3758 {0x7cc, 0x7d0, HDMIRX_ATTR_RO},
3759 {0x7d4, 0x7d4, HDMIRX_ATTR_RW},
3760 {0x1580, 0x1598, HDMIRX_ATTR_RO},
3761 {0x2000, 0x2000, HDMIRX_ATTR_WO},
3762 {0x2004, 0x2004, HDMIRX_ATTR_RO},
3763 {0x2008, 0x200c, HDMIRX_ATTR_RW},
3764 {0x2020, 0x2030, HDMIRX_ATTR_RW},
3765 {0x2040, 0x2050, HDMIRX_ATTR_RO},
3766 {0x2060, 0x2068, HDMIRX_ATTR_RW},
3767 {0x4400, 0x4428, HDMIRX_ATTR_RW},
3768 {0x4430, 0x446c, HDMIRX_ATTR_RO},
3769 {0x5000, 0x5000, HDMIRX_ATTR_RO},
3770 {0x5010, 0x5010, HDMIRX_ATTR_RO},
3771 {0x5014, 0x5014, HDMIRX_ATTR_RW},
3772 {0x5020, 0x5020, HDMIRX_ATTR_RO},
3773 {0x5024, 0x5024, HDMIRX_ATTR_RW},
3774 {0x5030, 0x5030, HDMIRX_ATTR_RO},
3775 {0x5034, 0x5034, HDMIRX_ATTR_RW},
3776 {0x5040, 0x5040, HDMIRX_ATTR_RO},
3777 {0x5044, 0x5044, HDMIRX_ATTR_RW},
3778 {0x5050, 0x5050, HDMIRX_ATTR_RO},
3779 {0x5054, 0x5054, HDMIRX_ATTR_RW},
3780 {0x5080, 0x5080, HDMIRX_ATTR_RO},
3781 {0x5084, 0x5084, HDMIRX_ATTR_RW},
3782 {0x5090, 0x5090, HDMIRX_ATTR_RO},
3783 {0x5094, 0x5094, HDMIRX_ATTR_RW},
3784 {0x50a0, 0x50a0, HDMIRX_ATTR_RO},
3785 {0x50a4, 0x50a4, HDMIRX_ATTR_RW},
3786 {0x50c0, 0x50c0, HDMIRX_ATTR_RO},
3787 {0x50c4, 0x50c4, HDMIRX_ATTR_RW},
3788 {0x50d0, 0x50d0, HDMIRX_ATTR_RO},
3789 {0x50d4, 0x50d4, HDMIRX_ATTR_RW},
3790 {0x50e0, 0x50e0, HDMIRX_ATTR_RO},
3791 {0x50e4, 0x50e4, HDMIRX_ATTR_RW},
3792 {0x5100, 0x5100, HDMIRX_ATTR_RO},
3793 {0x5104, 0x5104, HDMIRX_ATTR_RW},
3794 };
3795
hdmirx_ctrl_show(struct seq_file * s,void * v)3796 static int hdmirx_ctrl_show(struct seq_file *s, void *v)
3797 {
3798 struct rk_hdmirx_dev *hdmirx_dev = s->private;
3799 u32 i = 0, j = 0, val = 0;
3800
3801 seq_puts(s, "\n--------------------hdmirx ctrl--------------------");
3802 for (i = 0; i < ARRAY_SIZE(hdmirx_ctrl_table); i++) {
3803 for (j = hdmirx_ctrl_table[i].reg_base;
3804 j <= hdmirx_ctrl_table[i].reg_end; j += 4) {
3805 if (j % 16 == 0)
3806 seq_printf(s, "\n%08x:", j);
3807 if (hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_WO)
3808 seq_puts(s, " WO......");
3809 else if (hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_RE)
3810 seq_puts(s, " Reserved");
3811 else {
3812 val = hdmirx_readl(hdmirx_dev, j);
3813 seq_printf(s, " %08x", val);
3814 }
3815 }
3816 }
3817 seq_puts(s, "\n---------------------------------------------------\n");
3818
3819 return 0;
3820 }
3821
hdmirx_ctrl_open(struct inode * inode,struct file * file)3822 static int hdmirx_ctrl_open(struct inode *inode, struct file *file)
3823 {
3824 return single_open(file, hdmirx_ctrl_show, inode->i_private);
3825 }
3826
3827 static ssize_t
hdmirx_ctrl_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)3828 hdmirx_ctrl_write(struct file *file, const char __user *buf,
3829 size_t count, loff_t *ppos)
3830 {
3831 struct rk_hdmirx_dev *hdmirx_dev =
3832 ((struct seq_file *)file->private_data)->private;
3833 u32 reg, val;
3834 char kbuf[25];
3835 u32 i;
3836 bool write_en = false;
3837
3838 if (copy_from_user(kbuf, buf, count))
3839 return -EFAULT;
3840 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
3841 return -EFAULT;
3842 for (i = 0; i < ARRAY_SIZE(hdmirx_ctrl_table); i++) {
3843 if (reg >= hdmirx_ctrl_table[i].reg_base &&
3844 reg <= hdmirx_ctrl_table[i].reg_end &&
3845 (hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_RW ||
3846 hdmirx_ctrl_table[i].attr == HDMIRX_ATTR_WO)) {
3847 write_en = true;
3848 break;
3849 }
3850 }
3851 if (!write_en)
3852 return count;
3853
3854 dev_info(hdmirx_dev->dev, "/**********hdmi register config******/");
3855 dev_info(hdmirx_dev->dev, "\n reg=%x val=%x\n", reg, val);
3856 hdmirx_writel(hdmirx_dev, reg, val);
3857 return count;
3858 }
3859
3860 static const struct file_operations hdmirx_ctrl_fops = {
3861 .owner = THIS_MODULE,
3862 .open = hdmirx_ctrl_open,
3863 .read = seq_read,
3864 .write = hdmirx_ctrl_write,
3865 .llseek = seq_lseek,
3866 .release = single_release,
3867 };
3868
hdmirx_phy_show(struct seq_file * s,void * v)3869 static int hdmirx_phy_show(struct seq_file *s, void *v)
3870 {
3871 struct rk_hdmirx_dev *hdmirx_dev = s->private;
3872 u32 i = 0, val = 0;
3873
3874 seq_puts(s, "\n--------------------hdmirx phy---------------------\n");
3875 hdmirx_phy_register_read(hdmirx_dev, SUP_DIG_ANA_CREGS_SUP_ANA_NC, &val);
3876 seq_printf(s, "%08x: %08x\n", SUP_DIG_ANA_CREGS_SUP_ANA_NC, val);
3877
3878 for (i = LANE0_DIG_ASIC_RX_OVRD_OUT_0;
3879 i <= LANE3_DIG_ASIC_RX_OVRD_OUT_0; i += 0x100) {
3880 hdmirx_phy_register_read(hdmirx_dev, i, &val);
3881 seq_printf(s, "%08x: %08x\n", i, val);
3882 }
3883 for (i = LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2;
3884 i <= LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2; i += 0x100) {
3885 hdmirx_phy_register_read(hdmirx_dev, i, &val);
3886 seq_printf(s, "%08x: %08x\n", i, val);
3887 }
3888
3889 hdmirx_phy_register_read(hdmirx_dev,
3890 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG, &val);
3891 seq_printf(s, "%08x: %08x\n",
3892 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG, val);
3893 hdmirx_phy_register_read(hdmirx_dev,
3894 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM, &val);
3895 seq_printf(s, "%08x: %08x\n",
3896 HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM, val);
3897
3898 for (i = RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT;
3899 i <= RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT; i += 0x100) {
3900 hdmirx_phy_register_read(hdmirx_dev, i, &val);
3901 seq_printf(s, "%08x: %08x\n", i, val);
3902 }
3903 for (i = RAWLANE0_DIG_AON_FAST_FLAGS;
3904 i <= RAWLANE3_DIG_AON_FAST_FLAGS; i += 0x100) {
3905 hdmirx_phy_register_read(hdmirx_dev, i, &val);
3906 seq_printf(s, "%08x: %08x\n", i, val);
3907 }
3908 seq_puts(s, "---------------------------------------------------\n");
3909
3910 return 0;
3911 }
3912
hdmirx_phy_open(struct inode * inode,struct file * file)3913 static int hdmirx_phy_open(struct inode *inode, struct file *file)
3914 {
3915 return single_open(file, hdmirx_phy_show, inode->i_private);
3916 }
3917
3918 static ssize_t
hdmirx_phy_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)3919 hdmirx_phy_write(struct file *file, const char __user *buf,
3920 size_t count, loff_t *ppos)
3921 {
3922 struct rk_hdmirx_dev *hdmirx_dev =
3923 ((struct seq_file *)file->private_data)->private;
3924 u32 reg, val;
3925 char kbuf[25];
3926
3927 if (copy_from_user(kbuf, buf, count))
3928 return -EFAULT;
3929 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
3930 return -EFAULT;
3931 if (reg > RAWLANE3_DIG_AON_FAST_FLAGS) {
3932 dev_err(hdmirx_dev->dev, "it is no a hdmirx register\n");
3933 return count;
3934 }
3935 dev_info(hdmirx_dev->dev, "/**********hdmi register config******/");
3936 dev_info(hdmirx_dev->dev, "\n reg=%x val=%x\n", reg, val);
3937 hdmirx_phy_register_write(hdmirx_dev, reg, val);
3938 return count;
3939 }
3940
3941 static const struct file_operations hdmirx_phy_fops = {
3942 .owner = THIS_MODULE,
3943 .open = hdmirx_phy_open,
3944 .read = seq_read,
3945 .write = hdmirx_phy_write,
3946 .llseek = seq_lseek,
3947 .release = single_release,
3948 };
3949
hdmirx_status_show(struct seq_file * s,void * v)3950 static int hdmirx_status_show(struct seq_file *s, void *v)
3951 {
3952 struct rk_hdmirx_dev *hdmirx_dev = s->private;
3953 struct v4l2_dv_timings timings = hdmirx_dev->timings;
3954 struct v4l2_bt_timings *bt = &timings.bt;
3955 bool plugin;
3956 u32 htot, vtot, fps;
3957 u32 val;
3958
3959 plugin = tx_5v_power_present(hdmirx_dev);
3960 seq_printf(s, "status: %s\n", plugin ? "plugin" : "plugout");
3961 if (!plugin)
3962 return 0;
3963
3964 val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
3965 seq_puts(s, "Clk-Ch:");
3966 if (val & 0x1)
3967 seq_puts(s, "Lock\t");
3968 else
3969 seq_puts(s, "Unlock\t");
3970 seq_puts(s, "Ch0:");
3971 if (val & 0x2)
3972 seq_puts(s, "Lock\t");
3973 else
3974 seq_puts(s, "Unlock\t");
3975 seq_puts(s, "Ch1:");
3976 if (val & 0x4)
3977 seq_puts(s, "Lock\t");
3978 else
3979 seq_puts(s, "Unlock\t");
3980 seq_puts(s, "Ch2:");
3981 if (val & 0x8)
3982 seq_puts(s, "Lock\n");
3983 else
3984 seq_puts(s, "Unlock\n");
3985
3986 val = hdmirx_readl(hdmirx_dev, 0x598);
3987 if (val & 0x8000)
3988 seq_printf(s, "Ch0-Err:%d\t", (val & 0x7fff));
3989 if (val & 0x80000000)
3990 seq_printf(s, "Ch1-Err:%d\t", (val & 0x7fff0000) >> 16);
3991 val = hdmirx_readl(hdmirx_dev, 0x59c);
3992 if (val & 0x8000)
3993 seq_printf(s, "Ch2-Err:%d", (val & 0x7fff));
3994 seq_puts(s, "\n");
3995
3996 htot = bt->width + bt->hfrontporch + bt->hsync + bt->hbackporch;
3997 if (bt->interlaced) {
3998 vtot = bt->height + bt->vfrontporch + bt->vsync + bt->vbackporch +
3999 bt->il_vfrontporch + bt->il_vsync + bt->il_vbackporch;
4000 vtot /= 2;
4001 } else {
4002 vtot = bt->height + bt->vfrontporch + bt->vsync + bt->vbackporch;
4003 }
4004
4005 fps = (bt->pixelclock + (htot * vtot) / 2) / (htot * vtot);
4006
4007 seq_puts(s, "Color Format: ");
4008 if (hdmirx_dev->pix_fmt == HDMIRX_RGB888)
4009 seq_puts(s, "RGB");
4010 else if (hdmirx_dev->pix_fmt == HDMIRX_YUV422)
4011 seq_puts(s, "YUV422");
4012 else if (hdmirx_dev->pix_fmt == HDMIRX_YUV444)
4013 seq_puts(s, "YUV444");
4014 else if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
4015 seq_puts(s, "YUV420");
4016 else
4017 seq_puts(s, "UNKNOWN");
4018
4019 val = hdmirx_readl(hdmirx_dev, DMA_CONFIG1) & DDR_STORE_FORMAT_MASK;
4020 val = val >> 12;
4021 seq_puts(s, "\t\t\tStore Format: ");
4022 if (val == STORE_RGB888)
4023 seq_puts(s, "RGB\n");
4024 else if (val == STORE_RGBA_ARGB)
4025 seq_puts(s, "RGBA/ARGB\n");
4026 else if (val == STORE_YUV420_8BIT)
4027 seq_puts(s, "YUV420 (8 bit)\n");
4028 else if (val == STORE_YUV420_10BIT)
4029 seq_puts(s, "YUV420 (10 bit)\n");
4030 else if (val == STORE_YUV422_8BIT)
4031 seq_puts(s, "YUV422 (8 bit)\n");
4032 else if (val == STORE_YUV422_10BIT)
4033 seq_puts(s, "YUV422 (10 bit)\n");
4034 else if (val == STORE_YUV444_8BIT)
4035 seq_puts(s, "YUV444 (8 bit)\n");
4036 else if (val == STORE_YUV420_16BIT)
4037 seq_puts(s, "YUV420 (16 bit)\n");
4038 else if (val == STORE_YUV422_16BIT)
4039 seq_puts(s, "YUV422 (16 bit)\n");
4040 else
4041 seq_puts(s, "UNKNOWN\n");
4042
4043 seq_printf(s, "Timing: %ux%u%s%u (%ux%u)",
4044 bt->width, bt->height, bt->interlaced ? "i" : "p",
4045 fps, htot, vtot);
4046
4047 seq_printf(s, "\t\thfp:%d hs:%d hbp:%d vfp:%d vs:%d vbp:%d\n",
4048 bt->hfrontporch, bt->hsync, bt->hbackporch,
4049 bt->vfrontporch, bt->vsync, bt->vbackporch);
4050 seq_printf(s, "Pixel Clk: %llu\n", bt->pixelclock);
4051 seq_printf(s, "Mode: %s\n", hdmirx_dev->is_dvi_mode ? "DVI" : "HDMI");
4052
4053 hdmirx_get_colordepth(hdmirx_dev);
4054 seq_printf(s, "Color Depth: %u bit", hdmirx_dev->color_depth / 3);
4055 seq_puts(s, "\n");
4056
4057 hdmirx_get_color_range(hdmirx_dev);
4058 seq_puts(s, "Color Range: ");
4059 if (hdmirx_dev->cur_color_range == HDMIRX_DEFAULT_RANGE)
4060 seq_puts(s, "DEFAULT\n");
4061 else if (hdmirx_dev->cur_color_range == HDMIRX_FULL_RANGE)
4062 seq_puts(s, "FULL\n");
4063 else
4064 seq_puts(s, "LIMITED\n");
4065
4066 hdmirx_get_color_space(hdmirx_dev);
4067 seq_puts(s, "Color Space: ");
4068 if (hdmirx_dev->cur_color_space < 8)
4069 seq_printf(s, "%s\n", hdmirx_color_space[hdmirx_dev->cur_color_space]);
4070 else
4071 seq_puts(s, "Unknown\n");
4072
4073 return 0;
4074 }
4075
hdmirx_status_open(struct inode * inode,struct file * file)4076 static int hdmirx_status_open(struct inode *inode, struct file *file)
4077 {
4078 return single_open(file, hdmirx_status_show, inode->i_private);
4079 }
4080
4081 static const struct file_operations hdmirx_status_fops = {
4082 .owner = THIS_MODULE,
4083 .open = hdmirx_status_open,
4084 .read = seq_read,
4085 .llseek = seq_lseek,
4086 .release = single_release,
4087 };
4088
hdmirx_register_debugfs(struct device * dev,struct rk_hdmirx_dev * hdmirx_dev)4089 static void hdmirx_register_debugfs(struct device *dev,
4090 struct rk_hdmirx_dev *hdmirx_dev)
4091 {
4092 hdmirx_dev->debugfs_dir = debugfs_create_dir("hdmirx", NULL);
4093 if (IS_ERR(hdmirx_dev->debugfs_dir))
4094 return;
4095
4096 debugfs_create_file("ctrl", 0600, hdmirx_dev->debugfs_dir,
4097 hdmirx_dev, &hdmirx_ctrl_fops);
4098 debugfs_create_file("phy", 0600, hdmirx_dev->debugfs_dir,
4099 hdmirx_dev, &hdmirx_phy_fops);
4100 debugfs_create_file("status", 0600, hdmirx_dev->debugfs_dir,
4101 hdmirx_dev, &hdmirx_status_fops);
4102 }
4103
hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev * hdmirx_dev)4104 static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev)
4105 {
4106 int ret;
4107
4108 if (hdmirx_dev->policy == NULL) {
4109 hdmirx_dev->policy = cpufreq_cpu_get(hdmirx_dev->bound_cpu);
4110 if (!hdmirx_dev->policy) {
4111 dev_err(hdmirx_dev->dev, "%s: cpu%d policy NULL\n",
4112 __func__, hdmirx_dev->bound_cpu);
4113 return -1;
4114 }
4115
4116 ret = freq_qos_add_request(&hdmirx_dev->policy->constraints,
4117 &hdmirx_dev->min_sta_freq_req,
4118 FREQ_QOS_MIN,
4119 FREQ_QOS_MIN_DEFAULT_VALUE);
4120 if (ret < 0) {
4121 dev_err(hdmirx_dev->dev,
4122 "%s: failed to add sta freq constraint\n",
4123 __func__);
4124 freq_qos_remove_request(&hdmirx_dev->min_sta_freq_req);
4125 hdmirx_dev->policy = NULL;
4126 return -1;
4127 }
4128 hdmirx_dev->freq_qos_add = true;
4129 }
4130
4131 if (hdmirx_dev->freq_qos_add)
4132 freq_qos_update_request(&hdmirx_dev->min_sta_freq_req,
4133 hdmirx_dev->cpu_freq_khz);
4134 else
4135 dev_err(hdmirx_dev->dev, "%s freq qos nod add\n", __func__);
4136
4137 return 0;
4138 }
4139
hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev * hdmirx_dev)4140 static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev)
4141 {
4142 if (hdmirx_dev->freq_qos_add)
4143 freq_qos_update_request(&hdmirx_dev->min_sta_freq_req,
4144 FREQ_QOS_MIN_DEFAULT_VALUE);
4145 else
4146 dev_err(hdmirx_dev->dev, "%s freq qos nod add\n", __func__);
4147 }
4148
hdmirx_probe(struct platform_device * pdev)4149 static int hdmirx_probe(struct platform_device *pdev)
4150 {
4151 const struct v4l2_dv_timings timings_def = HDMIRX_DEFAULT_TIMING;
4152 struct device *dev = &pdev->dev;
4153 struct rk_hdmirx_dev *hdmirx_dev;
4154 struct hdmirx_stream *stream;
4155 struct v4l2_device *v4l2_dev;
4156 struct v4l2_ctrl_handler *hdl;
4157 struct resource *res;
4158 int ret, irq, cpu_aff;
4159 struct hdmirx_cec_data cec_data;
4160 struct cpumask cpumask;
4161
4162 hdmirx_dev = devm_kzalloc(dev, sizeof(*hdmirx_dev), GFP_KERNEL);
4163 if (!hdmirx_dev)
4164 return -ENOMEM;
4165
4166 dev_set_drvdata(dev, hdmirx_dev);
4167 hdmirx_dev->dev = dev;
4168 hdmirx_dev->of_node = dev->of_node;
4169 hdmirx_dev->cpu_freq_khz = CPU_LIMIT_FREQ_KHZ;
4170 hdmirx_dev->edid_version = HDMIRX_EDID_340M;
4171 ret = hdmirx_parse_dt(hdmirx_dev);
4172 if (ret)
4173 return ret;
4174
4175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmirx_regs");
4176 hdmirx_dev->regs = devm_ioremap_resource(dev, res);
4177 if (IS_ERR(hdmirx_dev->regs)) {
4178 dev_err(dev, "failed to remap regs resource\n");
4179 return PTR_ERR(hdmirx_dev->regs);
4180 }
4181
4182 if (sip_cpu_logical_map_mpidr(0) == 0)
4183 cpu_aff = sip_cpu_logical_map_mpidr(4); // big cpu0
4184 else
4185 cpu_aff = sip_cpu_logical_map_mpidr(1); // big cpu1
4186
4187 sip_fiq_control(RK_SIP_FIQ_CTRL_SET_AFF, RK_IRQ_HDMIRX_HDMI, cpu_aff);
4188 hdmirx_dev->bound_cpu = (cpu_aff >> 8) & 0xf;
4189 hdmirx_dev->wdt_cfg_bound_cpu = hdmirx_dev->bound_cpu + 1;
4190 dev_info(dev, "%s: cpu_aff:%#x, Bound_cpu:%d, wdt_cfg_bound_cpu:%d\n",
4191 __func__, cpu_aff,
4192 hdmirx_dev->bound_cpu,
4193 hdmirx_dev->wdt_cfg_bound_cpu);
4194 cpu_latency_qos_add_request(&hdmirx_dev->pm_qos, PM_QOS_DEFAULT_VALUE);
4195
4196 mutex_init(&hdmirx_dev->stream_lock);
4197 mutex_init(&hdmirx_dev->work_lock);
4198 spin_lock_init(&hdmirx_dev->rst_lock);
4199 INIT_WORK(&hdmirx_dev->work_wdt_config,
4200 hdmirx_work_wdt_config);
4201 INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_hotplug,
4202 hdmirx_delayed_work_hotplug);
4203 INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_res_change,
4204 hdmirx_delayed_work_res_change);
4205 INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_audio,
4206 hdmirx_delayed_work_audio);
4207 INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_heartbeat,
4208 hdmirx_delayed_work_heartbeat);
4209 INIT_DELAYED_WORK(&hdmirx_dev->delayed_work_cec,
4210 hdmirx_delayed_work_cec);
4211 hdmirx_dev->power_on = false;
4212
4213 ret = hdmirx_power_on(hdmirx_dev);
4214 if (ret)
4215 goto err_work_queues;
4216
4217 hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
4218 hdmirx_dev->timings = timings_def;
4219
4220 irq = platform_get_irq_byname(pdev, "hdmi");
4221 if (irq < 0) {
4222 dev_err(dev, "get hdmi irq failed!\n");
4223 ret = irq;
4224 goto err_work_queues;
4225 }
4226
4227 cpumask_clear(&cpumask);
4228 cpumask_set_cpu(hdmirx_dev->bound_cpu, &cpumask);
4229 irq_set_affinity_hint(irq, &cpumask);
4230 hdmirx_dev->hdmi_irq = irq;
4231 ret = devm_request_irq(dev, irq, hdmirx_hdmi_irq_handler, 0,
4232 RK_HDMIRX_DRVNAME"-hdmi", hdmirx_dev);
4233 if (ret) {
4234 dev_err(dev, "request hdmi irq thread failed! ret:%d\n", ret);
4235 goto err_work_queues;
4236 }
4237
4238 irq = platform_get_irq_byname(pdev, "dma");
4239 if (irq < 0) {
4240 dev_err(dev, "get dma irq failed!\n");
4241 ret = irq;
4242 goto err_work_queues;
4243 }
4244
4245 cpumask_clear(&cpumask);
4246 cpumask_set_cpu(hdmirx_dev->bound_cpu, &cpumask);
4247 irq_set_affinity_hint(irq, &cpumask);
4248 hdmirx_dev->dma_irq = irq;
4249 ret = devm_request_threaded_irq(dev, irq, NULL, hdmirx_dma_irq_handler,
4250 IRQF_ONESHOT, RK_HDMIRX_DRVNAME"-dma", hdmirx_dev);
4251 if (ret) {
4252 dev_err(dev, "request dma irq thread failed! ret:%d\n", ret);
4253 goto err_work_queues;
4254 }
4255
4256 hdmirx_submodule_init(hdmirx_dev);
4257
4258 v4l2_dev = &hdmirx_dev->v4l2_dev;
4259 strscpy(v4l2_dev->name, dev_name(dev), sizeof(v4l2_dev->name));
4260
4261 hdl = &hdmirx_dev->hdl;
4262 v4l2_ctrl_handler_init(hdl, 1);
4263 hdmirx_dev->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl,
4264 NULL, V4L2_CID_DV_RX_POWER_PRESENT,
4265 0, 1, 0, 0);
4266 if (hdl->error) {
4267 dev_err(dev, "v4l2 ctrl handler init failed!\n");
4268 ret = hdl->error;
4269 goto err_work_queues;
4270 }
4271 hdmirx_dev->v4l2_dev.ctrl_handler = hdl;
4272
4273 ret = v4l2_device_register(dev, &hdmirx_dev->v4l2_dev);
4274 if (ret < 0) {
4275 dev_err(dev, "register v4l2 device failed!\n");
4276 goto err_hdl;
4277 }
4278
4279 stream = &hdmirx_dev->stream;
4280 stream->hdmirx_dev = hdmirx_dev;
4281 ret = hdmirx_register_stream_vdev(stream);
4282 if (ret < 0) {
4283 dev_err(dev, "register video device failed!\n");
4284 goto err_unreg_v4l2_dev;
4285 }
4286
4287 ret = hdmirx_register_audio_device(hdmirx_dev);
4288 if (ret) {
4289 dev_err(dev, "register audio_driver failed!\n");
4290 goto err_unreg_video_dev;
4291 }
4292 ret = devm_add_action_or_reset(dev, hdmirx_unregister_audio_device, hdmirx_dev);
4293 if (ret)
4294 goto err_unreg_video_dev;
4295
4296 hdmirx_dev->classdev = device_create_with_groups(hdmirx_class,
4297 dev, MKDEV(0, 0),
4298 hdmirx_dev,
4299 hdmirx_groups,
4300 "hdmirx");
4301 if (IS_ERR(hdmirx_dev->classdev)) {
4302 ret = PTR_ERR(hdmirx_dev->classdev);
4303 goto err_unreg_video_dev;
4304 }
4305 ret = devm_add_action_or_reset(dev, hdmirx_unregister_class_device, hdmirx_dev);
4306 if (ret)
4307 goto err_unreg_video_dev;
4308
4309 hdmirx_dev->extcon = devm_extcon_dev_allocate(dev, hdmirx_extcon_cable);
4310 if (IS_ERR(hdmirx_dev->extcon)) {
4311 ret = PTR_ERR(hdmirx_dev->extcon);
4312 dev_err(&pdev->dev, "allocate extcon failed\n");
4313 goto err_unreg_video_dev;
4314 }
4315
4316 ret = devm_extcon_dev_register(dev, hdmirx_dev->extcon);
4317 if (ret) {
4318 dev_err(&pdev->dev, "failed to register extcon: %d\n", ret);
4319 goto err_unreg_video_dev;
4320 }
4321
4322 irq = gpiod_to_irq(hdmirx_dev->hdmirx_det_gpio);
4323 if (irq < 0) {
4324 dev_err(dev, "failed to get hdmirx-det gpio irq\n");
4325 ret = irq;
4326 goto err_unreg_video_dev;
4327 }
4328
4329 cpumask_clear(&cpumask);
4330 cpumask_set_cpu(hdmirx_dev->bound_cpu, &cpumask);
4331 irq_set_affinity_hint(irq, &cpumask);
4332 hdmirx_dev->det_irq = irq;
4333 ret = devm_request_irq(dev, irq, hdmirx_5v_det_irq_handler,
4334 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
4335 RK_HDMIRX_DRVNAME"-5v", hdmirx_dev);
4336 if (ret) {
4337 dev_err(dev, "request hdmirx-det gpio irq thread failed! ret:%d\n", ret);
4338 goto err_unreg_video_dev;
4339 }
4340
4341 if (hdmirx_dev->cec_enable) {
4342 hdmirx_dev->cec_notifier = cec_notifier_conn_register(dev, NULL, NULL);
4343 if (!hdmirx_dev->cec_notifier) {
4344 ret = -ENOMEM;
4345 goto err_unreg_video_dev;
4346 }
4347
4348 irq = platform_get_irq_byname(pdev, "cec");
4349 if (irq < 0) {
4350 dev_err(dev, "get hdmi cec irq failed!\n");
4351 cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
4352 ret = irq;
4353 goto err_unreg_video_dev;
4354 }
4355 cpumask_clear(&cpumask);
4356 cpumask_set_cpu(hdmirx_dev->bound_cpu, &cpumask);
4357 irq_set_affinity_hint(irq, &cpumask);
4358
4359 cec_data.hdmirx = hdmirx_dev;
4360 cec_data.dev = hdmirx_dev->dev;
4361 cec_data.ops = &hdmirx_cec_ops;
4362 cec_data.irq = irq;
4363 cec_data.edid = edid_init_data_340M;
4364 hdmirx_dev->cec = rk_hdmirx_cec_register(&cec_data);
4365 if (hdmirx_dev->cec && hdmirx_dev->cec->adap)
4366 schedule_delayed_work_on(hdmirx_dev->bound_cpu,
4367 &hdmirx_dev->delayed_work_cec,
4368 msecs_to_jiffies(4000));
4369 }
4370 hdmirx_register_hdcp(dev, hdmirx_dev, hdmirx_dev->hdcp_enable);
4371
4372 hdmirx_register_debugfs(hdmirx_dev->dev, hdmirx_dev);
4373
4374 hdmirx_dev->initialized = true;
4375 dev_info(dev, "%s driver probe ok!\n", dev_name(dev));
4376
4377 return 0;
4378
4379 err_unreg_video_dev:
4380 video_unregister_device(&hdmirx_dev->stream.vdev);
4381 err_unreg_v4l2_dev:
4382 v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
4383 err_hdl:
4384 v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
4385 err_work_queues:
4386 cpu_latency_qos_remove_request(&hdmirx_dev->pm_qos);
4387 cancel_delayed_work(&hdmirx_dev->delayed_work_hotplug);
4388 cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
4389 cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
4390 clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks);
4391 if (hdmirx_dev->power_on)
4392 pm_runtime_put_sync(dev);
4393 pm_runtime_disable(dev);
4394
4395 return ret;
4396 }
4397
hdmirx_remove(struct platform_device * pdev)4398 static int hdmirx_remove(struct platform_device *pdev)
4399 {
4400 struct device *dev = &pdev->dev;
4401 struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
4402
4403 debugfs_remove_recursive(hdmirx_dev->debugfs_dir);
4404
4405 cpu_latency_qos_remove_request(&hdmirx_dev->pm_qos);
4406 cancel_delayed_work(&hdmirx_dev->delayed_work_hotplug);
4407 cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
4408 cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
4409 cancel_delayed_work(&hdmirx_dev->delayed_work_cec);
4410 clk_bulk_disable_unprepare(hdmirx_dev->num_clks, hdmirx_dev->clks);
4411 reset_control_assert(hdmirx_dev->rst_a);
4412 reset_control_assert(hdmirx_dev->rst_p);
4413 reset_control_assert(hdmirx_dev->rst_ref);
4414 reset_control_assert(hdmirx_dev->rst_biu);
4415
4416 if (hdmirx_dev->cec)
4417 rk_hdmirx_cec_unregister(hdmirx_dev->cec);
4418 if (hdmirx_dev->cec_notifier)
4419 cec_notifier_conn_unregister(hdmirx_dev->cec_notifier);
4420
4421 if (hdmirx_dev->hdcp)
4422 rk_hdmirx_hdcp_unregister(hdmirx_dev->hdcp);
4423
4424 video_unregister_device(&hdmirx_dev->stream.vdev);
4425 v4l2_ctrl_handler_free(&hdmirx_dev->hdl);
4426 v4l2_device_unregister(&hdmirx_dev->v4l2_dev);
4427
4428 if (hdmirx_dev->power_on)
4429 pm_runtime_put_sync(dev);
4430 pm_runtime_disable(dev);
4431 of_reserved_mem_device_release(dev);
4432
4433 return 0;
4434 }
4435
4436 static const struct of_device_id hdmirx_id[] = {
4437 { .compatible = "rockchip,hdmirx-ctrler" },
4438 { },
4439 };
4440 MODULE_DEVICE_TABLE(of, hdmirx_id);
4441
4442 static struct platform_driver hdmirx_driver = {
4443 .probe = hdmirx_probe,
4444 .remove = hdmirx_remove,
4445 .driver = {
4446 .name = RK_HDMIRX_DRVNAME,
4447 .of_match_table = hdmirx_id,
4448 .pm = &rk_hdmirx_pm_ops,
4449 }
4450 };
4451
hdmirx_init(void)4452 static int __init hdmirx_init(void)
4453 {
4454 hdmirx_class = class_create(THIS_MODULE, "hdmirx");
4455 if (IS_ERR(hdmirx_class))
4456 return PTR_ERR(hdmirx_class);
4457 return platform_driver_register(&hdmirx_driver);
4458 }
4459 module_init(hdmirx_init);
4460
hdmirx_exit(void)4461 static void __exit hdmirx_exit(void)
4462 {
4463 platform_driver_unregister(&hdmirx_driver);
4464 class_destroy(hdmirx_class);
4465 }
4466 module_exit(hdmirx_exit);
4467
4468 MODULE_DESCRIPTION("Rockchip HDMI Receiver Driver");
4469 MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
4470 MODULE_LICENSE("GPL v2");
4471