1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */ 3 #ifndef _RKCIF_MIPI_CSI2_H_ 4 #define _RKCIF_MIPI_CSI2_H_ 5 6 #include <linux/notifier.h> 7 #include <media/v4l2-device.h> 8 #include <media/v4l2-fwnode.h> 9 #include <media/v4l2-subdev.h> 10 #include <media/v4l2-event.h> 11 #include <linux/rkcif-config.h> 12 13 #define CSI2_ERR_FSFE_MASK (0xff << 8) 14 #define CSI2_ERR_COUNT_ALL_MASK (0xff) 15 16 #define RKCIF_V4L2_EVENT_ELEMS 4 17 18 /* 19 * there must be 5 pads: 1 input pad from sensor, and 20 * the 4 virtual channel output pads 21 */ 22 #define CSI2_SINK_PAD 0 23 #define CSI2_NUM_SINK_PADS 4 24 #define CSI2_NUM_SRC_PADS 11 25 #define CSI2_NUM_PADS 5 26 #define CSI2_NUM_PADS_MAX 12 27 #define CSI2_NUM_PADS_SINGLE_LINK 2 28 #define MAX_CSI2_SENSORS 2 29 30 #define RKCIF_DEFAULT_WIDTH 640 31 #define RKCIF_DEFAULT_HEIGHT 480 32 33 #define CSI_ERRSTR_LEN (256) 34 #define CSI_VCINFO_LEN (12) 35 36 /* 37 * The default maximum bit-rate per lane in Mbps, if the 38 * source subdev does not provide V4L2_CID_LINK_FREQ. 39 */ 40 #define CSI2_DEFAULT_MAX_MBPS 849 41 42 #define IMX_MEDIA_GRP_ID_CSI2 BIT(8) 43 #define CSIHOST_MAX_ERRINT_COUNT 10 44 45 #define DEVICE_NAME "rockchip-mipi-csi2" 46 #define DEVICE_NAME_HW "rockchip-mipi-csi2-hw" 47 48 /* CSI Host Registers Define */ 49 #define CSIHOST_N_LANES 0x04 50 #define CSIHOST_DPHY_SHUTDOWNZ 0x08 51 #define CSIHOST_PHY_RSTZ 0x0c 52 #define CSIHOST_RESETN 0x10 53 #define CSIHOST_PHY_STATE 0x14 54 #define CSIHOST_ERR1 0x20 55 #define CSIHOST_ERR2 0x24 56 #define CSIHOST_MSK1 0x28 57 #define CSIHOST_MSK2 0x2c 58 #define CSIHOST_CONTROL 0x40 59 60 #define CSIHOST_ERR1_PHYERR_SPTSYNCHS 0x0000000f 61 #define CSIHOST_ERR1_ERR_BNDRY_MATCH 0x000000f0 62 #define CSIHOST_ERR1_ERR_SEQ 0x00000f00 63 #define CSIHOST_ERR1_ERR_FRM_DATA 0x0000f000 64 #define CSIHOST_ERR1_ERR_CRC 0x0f000000 65 #define CSIHOST_ERR1_ERR_ECC2 0x10000000 66 #define CSIHOST_ERR1_ERR_CTRL 0x000f0000 67 68 #define CSIHOST_ERR2_PHYERR_ESC 0x0000000f 69 #define CSIHOST_ERR2_PHYERR_SOTHS 0x000000f0 70 #define CSIHOST_ERR2_ECC_CORRECTED 0x00000f00 71 #define CSIHOST_ERR2_ERR_ID 0x0000f000 72 #define CSIHOST_ERR2_PHYERR_CODEHS 0x01000000 73 74 #define SW_CPHY_EN(x) ((x) << 0) 75 #define SW_DSI_EN(x) ((x) << 4) 76 #define SW_DATATYPE_FS(x) ((x) << 8) 77 #define SW_DATATYPE_FE(x) ((x) << 14) 78 #define SW_DATATYPE_LS(x) ((x) << 20) 79 #define SW_DATATYPE_LE(x) ((x) << 26) 80 81 #define RK_MAX_CSI_HW (6) 82 83 /* 84 * add new chip id in tail in time order 85 * by increasing to distinguish csi2 host version 86 */ 87 enum rkcsi2_chip_id { 88 CHIP_PX30_CSI2, 89 CHIP_RK1808_CSI2, 90 CHIP_RK3128_CSI2, 91 CHIP_RK3288_CSI2, 92 CHIP_RV1126_CSI2, 93 CHIP_RK3568_CSI2, 94 CHIP_RK3588_CSI2, 95 CHIP_RV1106_CSI2, 96 CHIP_RK3562_CSI2, 97 }; 98 99 enum csi2_pads { 100 RK_CSI2_PAD_SINK = 0, 101 RK_CSI2X_PAD_SOURCE0, 102 RK_CSI2X_PAD_SOURCE1, 103 RK_CSI2X_PAD_SOURCE2, 104 RK_CSI2X_PAD_SOURCE3 105 }; 106 107 enum csi2_err { 108 RK_CSI2_ERR_SOTSYN = 0x0, 109 RK_CSI2_ERR_FS_FE_MIS, 110 RK_CSI2_ERR_FRM_SEQ_ERR, 111 RK_CSI2_ERR_CRC_ONCE, 112 RK_CSI2_ERR_CRC, 113 RK_CSI2_ERR_ALL, 114 RK_CSI2_ERR_MAX 115 }; 116 117 enum host_type_t { 118 RK_CSI_RXHOST, 119 RK_DSI_RXHOST 120 }; 121 122 struct csi2_match_data { 123 int chip_id; 124 int num_pads; 125 int num_hw; 126 }; 127 128 struct csi2_hw_match_data { 129 int chip_id; 130 }; 131 132 struct csi2_sensor_info { 133 struct v4l2_subdev *sd; 134 struct v4l2_mbus_config mbus; 135 int lanes; 136 }; 137 138 struct csi2_err_stats { 139 unsigned int cnt; 140 }; 141 142 struct csi2_dev { 143 struct device *dev; 144 struct v4l2_subdev sd; 145 struct media_pad pad[CSI2_NUM_PADS_MAX]; 146 struct clk_bulk_data *clks_bulk; 147 int clks_num; 148 struct reset_control *rsts_bulk; 149 150 void __iomem *base; 151 struct v4l2_async_notifier notifier; 152 struct v4l2_fwnode_bus_mipi_csi2 bus; 153 154 /* lock to protect all members below */ 155 struct mutex lock; 156 157 struct v4l2_mbus_framefmt format_mbus; 158 struct v4l2_rect crop; 159 int stream_count; 160 struct v4l2_subdev *src_sd; 161 bool sink_linked[CSI2_NUM_SRC_PADS]; 162 bool is_check_sot_sync; 163 struct csi2_sensor_info sensors[MAX_CSI2_SENSORS]; 164 const struct csi2_match_data *match_data; 165 int num_sensors; 166 atomic_t frm_sync_seq; 167 struct csi2_err_stats err_list[RK_CSI2_ERR_MAX]; 168 struct csi2_hw *csi2_hw[RK_MAX_CSI_HW]; 169 int irq1; 170 int irq2; 171 int dsi_input_en; 172 struct rkcif_csi_info csi_info; 173 const char *dev_name; 174 }; 175 176 struct csi2_hw { 177 struct device *dev; 178 struct clk_bulk_data *clks_bulk; 179 int clks_num; 180 struct reset_control *rsts_bulk; 181 struct csi2_dev *csi2; 182 const struct csi2_hw_match_data *match_data; 183 184 void __iomem *base; 185 186 /* lock to protect all members below */ 187 struct mutex lock; 188 189 int irq1; 190 int irq2; 191 const char *dev_name; 192 }; 193 194 u32 rkcif_csi2_get_sof(struct csi2_dev *csi2_dev); 195 void rkcif_csi2_set_sof(struct csi2_dev *csi2_dev, u32 seq); 196 void rkcif_csi2_event_inc_sof(struct csi2_dev *csi2_dev); 197 int rkcif_csi2_plat_drv_init(void); 198 void rkcif_csi2_plat_drv_exit(void); 199 int rkcif_csi2_hw_plat_drv_init(void); 200 void rkcif_csi2_hw_plat_drv_exit(void); 201 int rkcif_csi2_register_notifier(struct notifier_block *nb); 202 int rkcif_csi2_unregister_notifier(struct notifier_block *nb); 203 void rkcif_csi2_event_reset_pipe(struct csi2_dev *csi2_dev, int reset_src); 204 205 #endif 206