1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip CIF Driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/of.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_platform.h>
16 #include <linux/of_reserved_mem.h>
17 #include <linux/reset.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/regmap.h>
21 #include <media/videobuf2-cma-sg.h>
22 #include <media/videobuf2-dma-contig.h>
23 #include <media/videobuf2-dma-sg.h>
24 #include <media/v4l2-fwnode.h>
25 #include <linux/iommu.h>
26 #include <dt-bindings/soc/rockchip-system-status.h>
27 #include <soc/rockchip/rockchip-system-status.h>
28 #include <linux/io.h>
29 #include <linux/mfd/syscon.h>
30 #include <soc/rockchip/rockchip_iommu.h>
31 #include "common.h"
32
33 static const struct cif_reg px30_cif_regs[] = {
34 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
35 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
36 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
37 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
38 [CIF_REG_DVP_LINE_NUM_ADDR] = CIF_REG(CIF_LINE_NUM_ADDR),
39 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
40 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
41 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
42 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
43 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
44 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
45 [CIF_REG_DVP_SCM_ADDR_Y] = CIF_REG(CIF_SCM_ADDR_Y),
46 [CIF_REG_DVP_SCM_ADDR_U] = CIF_REG(CIF_SCM_ADDR_U),
47 [CIF_REG_DVP_SCM_ADDR_V] = CIF_REG(CIF_SCM_ADDR_V),
48 [CIF_REG_DVP_WB_UP_FILTER] = CIF_REG(CIF_WB_UP_FILTER),
49 [CIF_REG_DVP_WB_LOW_FILTER] = CIF_REG(CIF_WB_LOW_FILTER),
50 [CIF_REG_DVP_WBC_CNT] = CIF_REG(CIF_WBC_CNT),
51 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
52 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
53 [CIF_REG_DVP_SCL_DST] = CIF_REG(CIF_SCL_DST),
54 [CIF_REG_DVP_SCL_FCT] = CIF_REG(CIF_SCL_FCT),
55 [CIF_REG_DVP_SCL_VALID_NUM] = CIF_REG(CIF_SCL_VALID_NUM),
56 [CIF_REG_DVP_LINE_LOOP_CTRL] = CIF_REG(CIF_LINE_LOOP_CTR),
57 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
58 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
59 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
60 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
61 };
62
63 static const char * const px30_cif_clks[] = {
64 "aclk_cif",
65 "hclk_cif",
66 "pclk_cif",
67 "cif_out",
68 };
69
70 static const char * const px30_cif_rsts[] = {
71 "rst_cif_a",
72 "rst_cif_h",
73 "rst_cif_pclkin",
74 };
75
76 static const struct cif_reg rk1808_cif_regs[] = {
77 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
78 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
79 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
80 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
81 [CIF_REG_DVP_DMA_IDLE_REQ] = CIF_REG(CIF_DMA_IDLE_REQ),
82 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
83 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
84 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
85 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
86 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
87 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
88 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
89 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
90 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
91 [CIF_REG_DVP_PATH_SEL] = CIF_REG(CIF_PATH_SEL),
92 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
93 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
94 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
95 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
96 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
97 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
98 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
99 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
100 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
101 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
102 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
103 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
104 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
105 [CIF_REG_MIPI_WATER_LINE] = CIF_REG(CIF_CSI_WATER_LINE),
106 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
107 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
108 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
109 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
110 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
111 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
112 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
113 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
114 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
115 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
116 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
117 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
118 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
119 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
120 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
121 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
122 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
123 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
124 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
125 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
126 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
127 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
128 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
129 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
130 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
131 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
132 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
133 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
134 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
135 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
136 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
137 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
138 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
139 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
140 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
141 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
142 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
143 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
144 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
145 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
146 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
147 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
148 [CIF_REG_MMU_DTE_ADDR] = CIF_REG(CIF_MMU_DTE_ADDR),
149 [CIF_REG_MMU_STATUS] = CIF_REG(CIF_MMU_DTE_ADDR),
150 [CIF_REG_MMU_COMMAND] = CIF_REG(CIF_MMU_COMMAND),
151 [CIF_REG_MMU_PAGE_FAULT_ADDR] = CIF_REG(CIF_MMU_PAGE_FAULT_ADDR),
152 [CIF_REG_MMU_ZAP_ONE_LINE] = CIF_REG(CIF_MMU_ZAP_ONE_LINE),
153 [CIF_REG_MMU_INT_RAWSTAT] = CIF_REG(CIF_MMU_INT_RAWSTAT),
154 [CIF_REG_MMU_INT_CLEAR] = CIF_REG(CIF_MMU_INT_CLEAR),
155 [CIF_REG_MMU_INT_MASK] = CIF_REG(CIF_MMU_INT_MASK),
156 [CIF_REG_MMU_INT_STATUS] = CIF_REG(CIF_MMU_INT_STATUS),
157 [CIF_REG_MMU_AUTO_GATING] = CIF_REG(CIF_MMU_AUTO_GATING),
158 };
159
160 static const char * const rk1808_cif_clks[] = {
161 "aclk_cif",
162 "dclk_cif",
163 "hclk_cif",
164 "sclk_cif_out",
165 /* "pclk_csi2host" */
166 };
167
168 static const char * const rk1808_cif_rsts[] = {
169 "rst_cif_a",
170 "rst_cif_h",
171 "rst_cif_i",
172 "rst_cif_d",
173 "rst_cif_pclkin",
174 };
175
176 static const struct cif_reg rk3128_cif_regs[] = {
177 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
178 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
179 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
180 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
181 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
182 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
183 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
184 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
185 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
186 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
187 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
188 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
189 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
190 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
191 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
192 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
193 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
194 };
195
196 static const char * const rk3128_cif_clks[] = {
197 "aclk_cif",
198 "hclk_cif",
199 "sclk_cif_out",
200 };
201
202 static const char * const rk3128_cif_rsts[] = {
203 "rst_cif",
204 };
205
206 static const struct cif_reg rk3288_cif_regs[] = {
207 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
208 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
209 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
210 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
211 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
212 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
213 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
214 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
215 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
216 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
217 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
218 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
219 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
220 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
221 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
222 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
223 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
224 };
225
226 static const char * const rk3288_cif_clks[] = {
227 "aclk_cif0",
228 "hclk_cif0",
229 "cif0_in",
230 };
231
232 static const char * const rk3288_cif_rsts[] = {
233 "rst_cif",
234 };
235
236 static const struct cif_reg rk3328_cif_regs[] = {
237 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
238 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
239 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
240 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
241 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
242 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
243 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
244 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
245 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
246 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
247 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
248 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
249 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
250 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
251 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
252 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
253 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
254 };
255
256 static const char * const rk3328_cif_clks[] = {
257 "aclk_cif",
258 "hclk_cif",
259 };
260
261 static const char * const rk3328_cif_rsts[] = {
262 "rst_cif_a",
263 "rst_cif_p",
264 "rst_cif_h",
265 };
266
267 static const char * const rk3368_cif_clks[] = {
268 "pclk_cif",
269 "aclk_cif0",
270 "hclk_cif0",
271 "cif0_in",
272 };
273
274 static const char * const rk3368_cif_rsts[] = {
275 "rst_cif",
276 };
277
278 static const struct cif_reg rk3368_cif_regs[] = {
279 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
280 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
281 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
282 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
283 [CIF_REG_DVP_DMA_IDLE_REQ] = CIF_REG(CIF_DMA_IDLE_REQ),
284 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
285 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
286 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
287 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
288 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
289 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
290 [CIF_REG_DVP_CROP] = CIF_REG(CIF_CROP),
291 [CIF_REG_DVP_SCL_CTRL] = CIF_REG(CIF_SCL_CTRL),
292 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(CIF_FIFO_ENTRY),
293 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(CIF_FRAME_STATUS),
294 [CIF_REG_DVP_CUR_DST] = CIF_REG(CIF_CUR_DST),
295 [CIF_REG_DVP_LAST_LINE] = CIF_REG(CIF_LAST_LINE),
296 [CIF_REG_DVP_LAST_PIX] = CIF_REG(CIF_LAST_PIX),
297 };
298
299 static const char * const rv1126_cif_clks[] = {
300 "aclk_cif",
301 "hclk_cif",
302 "dclk_cif",
303 };
304
305 static const char * const rv1126_cif_rsts[] = {
306 "rst_cif_a",
307 "rst_cif_h",
308 "rst_cif_d",
309 "rst_cif_p",
310 "rst_cif_i",
311 "rst_cif_rx_p",
312 };
313
314 static const struct cif_reg rv1126_cif_regs[] = {
315 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
316 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
317 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
318 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
319 [CIF_REG_DVP_MULTI_ID] = CIF_REG(CIF_MULTI_ID),
320 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
321 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
322 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
323 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
324 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
325 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
326 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
327 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
328 [CIF_REG_DVP_CROP] = CIF_REG(RV1126_CIF_CROP),
329 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(RV1126_CIF_FRAME_STATUS),
330 [CIF_REG_DVP_CUR_DST] = CIF_REG(RV1126_CIF_CUR_DST),
331 [CIF_REG_DVP_LAST_LINE] = CIF_REG(RV1126_CIF_LAST_LINE),
332 [CIF_REG_DVP_LAST_PIX] = CIF_REG(RV1126_CIF_LAST_PIX),
333 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(CIF_FRM0_ADDR_Y_ID1),
334 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(CIF_FRM0_ADDR_UV_ID1),
335 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(CIF_FRM1_ADDR_Y_ID1),
336 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(CIF_FRM1_ADDR_UV_ID1),
337 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(CIF_FRM0_ADDR_Y_ID2),
338 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(CIF_FRM0_ADDR_UV_ID2),
339 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(CIF_FRM1_ADDR_Y_ID2),
340 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(CIF_FRM1_ADDR_UV_ID2),
341 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(CIF_FRM0_ADDR_Y_ID3),
342 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(CIF_FRM0_ADDR_UV_ID3),
343 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(CIF_FRM1_ADDR_Y_ID3),
344 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(CIF_FRM1_ADDR_UV_ID3),
345 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
346 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
347 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
348 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
349 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
350 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
351 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
352 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
353 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
354 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
355 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
356 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
357 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
358 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
359 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
360 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
361 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
362 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
363 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
364 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
365 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
366 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
367 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
368 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
369 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
370 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
371 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
372 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
373 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
374 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
375 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
376 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
377 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
378 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
379 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
380 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
381 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
382 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
383 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
384 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
385 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
386 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
387 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
388 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
389 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
390 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
391 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
392 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
393 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
394 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
395 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
396 [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0),
397 [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0),
398 [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0),
399 [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0),
400 [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1),
401 [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1),
402 [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1),
403 [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1),
404 [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2),
405 [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2),
406 [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2),
407 [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2),
408 [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3),
409 [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3),
410 [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3),
411 [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3),
412 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
413 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
414 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_CIFIO_CON),
415 };
416
417 static const char * const rv1126_cif_lite_clks[] = {
418 "aclk_cif_lite",
419 "hclk_cif_lite",
420 "dclk_cif_lite",
421 };
422
423 static const char * const rv1126_cif_lite_rsts[] = {
424 "rst_cif_lite_a",
425 "rst_cif_lite_h",
426 "rst_cif_lite_d",
427 "rst_cif_lite_rx_p",
428 };
429
430 static const struct cif_reg rv1126_cif_lite_regs[] = {
431 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
432 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
433 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
434 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
435 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
436 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
437 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
438 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
439 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
440 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
441 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
442 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
443 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
444 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
445 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
446 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
447 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
448 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
449 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
450 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
451 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
452 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
453 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
454 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
455 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
456 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
457 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
458 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
459 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
460 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
461 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
462 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
463 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
464 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
465 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
466 [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0),
467 [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0),
468 [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0),
469 [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0),
470 [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1),
471 [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1),
472 [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1),
473 [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1),
474 [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2),
475 [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2),
476 [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2),
477 [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2),
478 [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3),
479 [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3),
480 [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3),
481 [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3),
482 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
483 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
484 };
485
486 static const char * const rk3568_cif_clks[] = {
487 "aclk_cif",
488 "hclk_cif",
489 "dclk_cif",
490 "iclk_cif_g",
491 };
492
493 static const char * const rk3568_cif_rsts[] = {
494 "rst_cif_a",
495 "rst_cif_h",
496 "rst_cif_d",
497 "rst_cif_p",
498 "rst_cif_i",
499 };
500
501 static const struct cif_reg rk3568_cif_regs[] = {
502 [CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
503 [CIF_REG_DVP_INTEN] = CIF_REG(CIF_INTEN),
504 [CIF_REG_DVP_INTSTAT] = CIF_REG(CIF_INTSTAT),
505 [CIF_REG_DVP_FOR] = CIF_REG(CIF_FOR),
506 [CIF_REG_DVP_MULTI_ID] = CIF_REG(CIF_MULTI_ID),
507 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(CIF_FRM0_ADDR_Y),
508 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(CIF_FRM0_ADDR_UV),
509 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(CIF_FRM1_ADDR_Y),
510 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(CIF_FRM1_ADDR_UV),
511 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(CIF_VIR_LINE_WIDTH),
512 [CIF_REG_DVP_SET_SIZE] = CIF_REG(CIF_SET_SIZE),
513 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(CIF_LINE_INT_NUM),
514 [CIF_REG_DVP_LINE_CNT] = CIF_REG(CIF_LINE_CNT),
515 [CIF_REG_DVP_CROP] = CIF_REG(RV1126_CIF_CROP),
516 [CIF_REG_DVP_FIFO_ENTRY] = CIF_REG(RK3568_CIF_FIFO_ENTRY),
517 [CIF_REG_DVP_FRAME_STATUS] = CIF_REG(RV1126_CIF_FRAME_STATUS),
518 [CIF_REG_DVP_CUR_DST] = CIF_REG(RV1126_CIF_CUR_DST),
519 [CIF_REG_DVP_LAST_LINE] = CIF_REG(RV1126_CIF_LAST_LINE),
520 [CIF_REG_DVP_LAST_PIX] = CIF_REG(RV1126_CIF_LAST_PIX),
521 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(CIF_FRM0_ADDR_Y_ID1),
522 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(CIF_FRM0_ADDR_UV_ID1),
523 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(CIF_FRM1_ADDR_Y_ID1),
524 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(CIF_FRM1_ADDR_UV_ID1),
525 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(CIF_FRM0_ADDR_Y_ID2),
526 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(CIF_FRM0_ADDR_UV_ID2),
527 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(CIF_FRM1_ADDR_Y_ID2),
528 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(CIF_FRM1_ADDR_UV_ID2),
529 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(CIF_FRM0_ADDR_Y_ID3),
530 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(CIF_FRM0_ADDR_UV_ID3),
531 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(CIF_FRM1_ADDR_Y_ID3),
532 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(CIF_FRM1_ADDR_UV_ID3),
533 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CIF_CSI_ID0_CTRL0),
534 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CIF_CSI_ID0_CTRL1),
535 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CIF_CSI_ID1_CTRL0),
536 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CIF_CSI_ID1_CTRL1),
537 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CIF_CSI_ID2_CTRL0),
538 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CIF_CSI_ID2_CTRL1),
539 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CIF_CSI_ID3_CTRL0),
540 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CIF_CSI_ID3_CTRL1),
541 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CIF_CSI_MIPI_LVDS_CTRL),
542 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID0),
543 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID0),
544 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID0),
545 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID0),
546 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID0),
547 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID0),
548 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID0),
549 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID0),
550 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID1),
551 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID1),
552 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID1),
553 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID1),
554 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID1),
555 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID1),
556 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID1),
557 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID1),
558 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID2),
559 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID2),
560 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID2),
561 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID2),
562 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID2),
563 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID2),
564 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID2),
565 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID2),
566 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_Y_ID3),
567 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_Y_ID3),
568 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM0_ADDR_UV_ID3),
569 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CIF_CSI_FRM1_ADDR_UV_ID3),
570 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_Y_ID3),
571 [CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_Y_ID3),
572 [CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM0_VLW_UV_ID3),
573 [CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3] = CIF_REG(CIF_CSI_FRM1_VLW_UV_ID3),
574 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CIF_CSI_INTEN),
575 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CIF_CSI_INTSTAT),
576 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID0_1),
577 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CIF_CSI_LINE_INT_NUM_ID2_3),
578 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CIF_CSI_LINE_CNT_ID0_1),
579 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CIF_CSI_LINE_CNT_ID2_3),
580 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CIF_CSI_ID0_CROP_START),
581 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CIF_CSI_ID1_CROP_START),
582 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CIF_CSI_ID2_CROP_START),
583 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CIF_CSI_ID3_CROP_START),
584 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CIF_CSI_FRAME_NUM_VC0),
585 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CIF_CSI_FRAME_NUM_VC1),
586 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CIF_CSI_FRAME_NUM_VC2),
587 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CIF_CSI_FRAME_NUM_VC3),
588 [CIF_REG_Y_STAT_CONTROL] = CIF_REG(CIF_Y_STAT_CONTROL),
589 [CIF_REG_Y_STAT_VALUE] = CIF_REG(CIF_Y_STAT_VALUE),
590 [CIF_REG_MMU_DTE_ADDR] = CIF_REG(CIF_MMU_DTE_ADDR),
591 [CIF_REG_MMU_STATUS] = CIF_REG(CIF_MMU_STATUS),
592 [CIF_REG_MMU_COMMAND] = CIF_REG(CIF_MMU_COMMAND),
593 [CIF_REG_MMU_PAGE_FAULT_ADDR] = CIF_REG(CIF_MMU_PAGE_FAULT_ADDR),
594 [CIF_REG_MMU_ZAP_ONE_LINE] = CIF_REG(CIF_MMU_ZAP_ONE_LINE),
595 [CIF_REG_MMU_INT_RAWSTAT] = CIF_REG(CIF_MMU_INT_RAWSTAT),
596 [CIF_REG_MMU_INT_CLEAR] = CIF_REG(CIF_MMU_INT_CLEAR),
597 [CIF_REG_MMU_INT_MASK] = CIF_REG(CIF_MMU_INT_MASK),
598 [CIF_REG_MMU_INT_STATUS] = CIF_REG(CIF_MMU_INT_STATUS),
599 [CIF_REG_MMU_AUTO_GATING] = CIF_REG(CIF_MMU_AUTO_GATING),
600 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_VI_CON0),
601 [CIF_REG_GRF_CIFIO_CON1] = CIF_REG(CIF_GRF_VI_CON1),
602 };
603
604 static const char * const rk3588_cif_clks[] = {
605 "aclk_cif",
606 "hclk_cif",
607 "dclk_cif",
608 "iclk_host0",
609 "iclk_host1",
610 };
611
612 static const char * const rk3588_cif_rsts[] = {
613 "rst_cif_a",
614 "rst_cif_h",
615 "rst_cif_d",
616 "rst_cif_host0",
617 "rst_cif_host1",
618 "rst_cif_host2",
619 "rst_cif_host3",
620 "rst_cif_host4",
621 "rst_cif_host5",
622 };
623
624 static const struct cif_reg rk3588_cif_regs[] = {
625 [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
626 [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
627 [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
628 [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
629 [CIF_REG_DVP_MULTI_ID] = CIF_REG(DVP_MULTI_ID),
630 [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
631 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
632 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
633 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
634 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
635 [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(DVP_FRM0_ADDR_Y_ID1),
636 [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(DVP_FRM0_ADDR_UV_ID1),
637 [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(DVP_FRM1_ADDR_Y_ID1),
638 [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(DVP_FRM1_ADDR_UV_ID1),
639 [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(DVP_FRM0_ADDR_Y_ID2),
640 [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(DVP_FRM0_ADDR_UV_ID2),
641 [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(DVP_FRM1_ADDR_Y_ID2),
642 [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(DVP_FRM1_ADDR_UV_ID2),
643 [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(DVP_FRM0_ADDR_Y_ID3),
644 [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(DVP_FRM0_ADDR_UV_ID3),
645 [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(DVP_FRM1_ADDR_Y_ID3),
646 [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(DVP_FRM1_ADDR_UV_ID3),
647 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
648 [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
649 [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
650 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
651 [CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG(DVP_LINE_INT_NUM_23),
652 [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_INT_NUM_01),
653 [CIF_REG_DVP_LINE_CNT1] = CIF_REG(DVP_LINE_INT_NUM_23),
654
655 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
656 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
657 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
658 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
659 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
660 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
661 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
662 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
663 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
664 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
665 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
666 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
667 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
668 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
669 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
670 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
671 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
672 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
673 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
674 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
675 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
676 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
677 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
678 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
679 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
680 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
681 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
682 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
683 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
684 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
685 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
686 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
687 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
688 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
689 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
690 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
691 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
692 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
693 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
694 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
695 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
696 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
697 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
698 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
699 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
700 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
701 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
702 [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
703
704 [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
705 [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
706 [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
707
708 [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
709 [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
710 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
711 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
712 [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
713 [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
714 [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
715 [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
716 [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
717 [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
718 [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
719 [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
720 [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
721 [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
722 [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
723 [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
724 [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
725 [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
726 [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
727 [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
728 [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
729 [CIF_REG_TOISP1_CTRL] = CIF_REG(TOISP1_CH_CTRL),
730 [CIF_REG_TOISP1_SIZE] = CIF_REG(TOISP1_CROP_SIZE),
731 [CIF_REG_TOISP1_CROP] = CIF_REG(TOISP1_CROP),
732 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
733 };
734
735 static const char * const rv1106_cif_clks[] = {
736 "aclk_cif",
737 "hclk_cif",
738 "dclk_cif",
739 "pclk_cif",
740 "i0clk_cif",
741 "i1clk_cif",
742 "rx0clk_cif",
743 "rx1clk_cif",
744 "isp0clk_cif",
745 "sclk_m0_cif",
746 "sclk_m1_cif",
747 "pclk_vepu_cif",
748 };
749
750 static const char * const rv1106_cif_rsts[] = {
751 "rst_cif_a",
752 "rst_cif_h",
753 "rst_cif_d",
754 "rst_cif_p",
755 "rst_cif_i0",
756 "rst_cif_i1",
757 "rst_cif_rx0",
758 "rst_cif_rx1",
759 "rst_cif_isp0",
760 "rst_cif_pclk_vepu",
761 };
762
763 static const struct cif_reg rv1106_cif_regs[] = {
764 [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
765 [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
766 [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
767 [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
768 [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
769 [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
770 [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
771 [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
772 [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
773 [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
774 [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
775 [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
776 [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
777 [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_CNT_01),
778
779 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
780 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
781 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
782 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
783 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
784 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
785 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
786 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
787 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
788 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
789 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
790 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
791 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
792 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
793 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
794 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
795 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
796 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
797 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
798 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
799 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
800 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
801 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
802 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
803 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
804 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
805 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
806 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
807 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
808 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
809 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
810 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
811 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
812 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
813 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
814 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
815 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
816 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
817 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
818 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
819 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
820 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
821 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
822 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
823 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
824 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
825 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
826 [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
827 [CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
828 [CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
829 [CIF_REG_LVDS_ID2_CTRL0] = CIF_REG(CIF_LVDS0_ID2_CTRL0),
830 [CIF_REG_LVDS_ID3_CTRL0] = CIF_REG(CIF_LVDS0_ID3_CTRL0),
831 [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106),
832 [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106),
833 [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106),
834 [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106),
835 [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106),
836 [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106),
837 [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106),
838 [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106),
839 [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106),
840 [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106),
841 [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106),
842 [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106),
843 [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106),
844 [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106),
845 [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106),
846 [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106),
847 [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
848 [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
849 [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
850
851 [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
852 [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
853 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
854 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
855 [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
856 [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
857 [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
858 [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
859 [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
860 [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
861 [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
862 [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
863 [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
864 [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
865 [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
866 [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
867 [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
868 [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
869
870 [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
871 [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
872 [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
873 [CIF_REG_GRF_CIFIO_CON] = CIF_REG(RV1106_CIF_GRF_VI_CON),
874 [CIF_REG_GRF_CIFIO_VENC] = CIF_REG(RV1106_CIF_GRF_VENC_WRAPPER),
875 };
876
877 static const char * const rk3562_cif_clks[] = {
878 "aclk_cif",
879 "hclk_cif",
880 "dclk_cif",
881 "csirx0_data",
882 "csirx1_data",
883 "csirx2_data",
884 "csirx3_data",
885 };
886
887 static const char * const rk3562_cif_rsts[] = {
888 "rst_cif_a",
889 "rst_cif_h",
890 "rst_cif_d",
891 "rst_cif_i0",
892 "rst_cif_i1",
893 "rst_cif_i2",
894 "rst_cif_i3",
895 };
896
897 static const struct cif_reg rk3562_cif_regs[] = {
898 [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
899 [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
900 [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
901 [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
902 [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
903 [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
904 [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
905 [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
906 [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
907 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
908 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
909 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
910 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
911 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
912 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
913 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
914 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
915 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
916 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
917 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
918 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
919 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
920 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
921 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
922 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
923 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
924 [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
925 [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
926 [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
927 [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
928 [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
929 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
930 [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
931 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
932 [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
933 [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
934 [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
935 [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
936 [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
937 [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
938 [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
939 [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
940 [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
941 [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
942 [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
943 [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
944 [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
945 [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
946
947 [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
948 [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
949 [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
950
951 [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
952 [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
953 [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
954 [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
955 [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
956 [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
957
958 [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
959 [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
960 [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
961 };
962
963 static const struct rkcif_hw_match_data px30_cif_match_data = {
964 .chip_id = CHIP_PX30_CIF,
965 .clks = px30_cif_clks,
966 .clks_num = ARRAY_SIZE(px30_cif_clks),
967 .rsts = px30_cif_rsts,
968 .rsts_num = ARRAY_SIZE(px30_cif_rsts),
969 .cif_regs = px30_cif_regs,
970 };
971
972 static const struct rkcif_hw_match_data rk1808_cif_match_data = {
973 .chip_id = CHIP_RK1808_CIF,
974 .clks = rk1808_cif_clks,
975 .clks_num = ARRAY_SIZE(rk1808_cif_clks),
976 .rsts = rk1808_cif_rsts,
977 .rsts_num = ARRAY_SIZE(rk1808_cif_rsts),
978 .cif_regs = rk1808_cif_regs,
979 };
980
981 static const struct rkcif_hw_match_data rk3128_cif_match_data = {
982 .chip_id = CHIP_RK3128_CIF,
983 .clks = rk3128_cif_clks,
984 .clks_num = ARRAY_SIZE(rk3128_cif_clks),
985 .rsts = rk3128_cif_rsts,
986 .rsts_num = ARRAY_SIZE(rk3128_cif_rsts),
987 .cif_regs = rk3128_cif_regs,
988 };
989
990 static const struct rkcif_hw_match_data rk3288_cif_match_data = {
991 .chip_id = CHIP_RK3288_CIF,
992 .clks = rk3288_cif_clks,
993 .clks_num = ARRAY_SIZE(rk3288_cif_clks),
994 .rsts = rk3288_cif_rsts,
995 .rsts_num = ARRAY_SIZE(rk3288_cif_rsts),
996 .cif_regs = rk3288_cif_regs,
997 };
998
999 static const struct rkcif_hw_match_data rk3328_cif_match_data = {
1000 .chip_id = CHIP_RK3328_CIF,
1001 .clks = rk3328_cif_clks,
1002 .clks_num = ARRAY_SIZE(rk3328_cif_clks),
1003 .rsts = rk3328_cif_rsts,
1004 .rsts_num = ARRAY_SIZE(rk3328_cif_rsts),
1005 .cif_regs = rk3328_cif_regs,
1006 };
1007
1008 static const struct rkcif_hw_match_data rk3368_cif_match_data = {
1009 .chip_id = CHIP_RK3368_CIF,
1010 .clks = rk3368_cif_clks,
1011 .clks_num = ARRAY_SIZE(rk3368_cif_clks),
1012 .rsts = rk3368_cif_rsts,
1013 .rsts_num = ARRAY_SIZE(rk3368_cif_rsts),
1014 .cif_regs = rk3368_cif_regs,
1015 };
1016
1017 static const struct rkcif_hw_match_data rv1126_cif_match_data = {
1018 .chip_id = CHIP_RV1126_CIF,
1019 .clks = rv1126_cif_clks,
1020 .clks_num = ARRAY_SIZE(rv1126_cif_clks),
1021 .rsts = rv1126_cif_rsts,
1022 .rsts_num = ARRAY_SIZE(rv1126_cif_rsts),
1023 .cif_regs = rv1126_cif_regs,
1024 };
1025
1026 static const struct rkcif_hw_match_data rv1126_cif_lite_match_data = {
1027 .chip_id = CHIP_RV1126_CIF_LITE,
1028 .clks = rv1126_cif_lite_clks,
1029 .clks_num = ARRAY_SIZE(rv1126_cif_lite_clks),
1030 .rsts = rv1126_cif_lite_rsts,
1031 .rsts_num = ARRAY_SIZE(rv1126_cif_lite_rsts),
1032 .cif_regs = rv1126_cif_lite_regs,
1033 };
1034
1035 static const struct rkcif_hw_match_data rk3568_cif_match_data = {
1036 .chip_id = CHIP_RK3568_CIF,
1037 .clks = rk3568_cif_clks,
1038 .clks_num = ARRAY_SIZE(rk3568_cif_clks),
1039 .rsts = rk3568_cif_rsts,
1040 .rsts_num = ARRAY_SIZE(rk3568_cif_rsts),
1041 .cif_regs = rk3568_cif_regs,
1042 };
1043
1044 static const struct rkcif_hw_match_data rk3588_cif_match_data = {
1045 .chip_id = CHIP_RK3588_CIF,
1046 .clks = rk3588_cif_clks,
1047 .clks_num = ARRAY_SIZE(rk3588_cif_clks),
1048 .rsts = rk3588_cif_rsts,
1049 .rsts_num = ARRAY_SIZE(rk3588_cif_rsts),
1050 .cif_regs = rk3588_cif_regs,
1051 };
1052
1053 static const struct rkcif_hw_match_data rv1106_cif_match_data = {
1054 .chip_id = CHIP_RV1106_CIF,
1055 .clks = rv1106_cif_clks,
1056 .clks_num = ARRAY_SIZE(rv1106_cif_clks),
1057 .rsts = rv1106_cif_rsts,
1058 .rsts_num = ARRAY_SIZE(rv1106_cif_rsts),
1059 .cif_regs = rv1106_cif_regs,
1060 };
1061
1062 static const struct rkcif_hw_match_data rk3562_cif_match_data = {
1063 .chip_id = CHIP_RK3562_CIF,
1064 .clks = rk3562_cif_clks,
1065 .clks_num = ARRAY_SIZE(rk3562_cif_clks),
1066 .rsts = rk3562_cif_rsts,
1067 .rsts_num = ARRAY_SIZE(rk3562_cif_rsts),
1068 .cif_regs = rk3562_cif_regs,
1069 };
1070
1071 static const struct of_device_id rkcif_plat_of_match[] = {
1072 #ifdef CONFIG_CPU_PX30
1073 {
1074 .compatible = "rockchip,px30-cif",
1075 .data = &px30_cif_match_data,
1076 },
1077 #endif
1078 #ifdef CONFIG_CPU_RK1808
1079 {
1080 .compatible = "rockchip,rk1808-cif",
1081 .data = &rk1808_cif_match_data,
1082 },
1083 #endif
1084 #ifdef CONFIG_CPU_RK312X
1085 {
1086 .compatible = "rockchip,rk3128-cif",
1087 .data = &rk3128_cif_match_data,
1088 },
1089 #endif
1090 #ifdef CONFIG_CPU_RK3288
1091 {
1092 .compatible = "rockchip,rk3288-cif",
1093 .data = &rk3288_cif_match_data,
1094 },
1095 #endif
1096 #ifdef CONFIG_CPU_RK3328
1097 {
1098 .compatible = "rockchip,rk3328-cif",
1099 .data = &rk3328_cif_match_data,
1100 },
1101 #endif
1102 #ifdef CONFIG_CPU_RK3368
1103 {
1104 .compatible = "rockchip,rk3368-cif",
1105 .data = &rk3368_cif_match_data,
1106 },
1107 #endif
1108 #ifdef CONFIG_CPU_RK3568
1109 {
1110 .compatible = "rockchip,rk3568-cif",
1111 .data = &rk3568_cif_match_data,
1112 },
1113 #endif
1114 #ifdef CONFIG_CPU_RK3588
1115 {
1116 .compatible = "rockchip,rk3588-cif",
1117 .data = &rk3588_cif_match_data,
1118 },
1119 #endif
1120 #ifdef CONFIG_CPU_RV1126
1121 {
1122 .compatible = "rockchip,rv1126-cif",
1123 .data = &rv1126_cif_match_data,
1124 },
1125 {
1126 .compatible = "rockchip,rv1126-cif-lite",
1127 .data = &rv1126_cif_lite_match_data,
1128 },
1129 #endif
1130 #ifdef CONFIG_CPU_RV1106
1131 {
1132 .compatible = "rockchip,rv1106-cif",
1133 .data = &rv1106_cif_match_data,
1134 },
1135 #endif
1136 #ifdef CONFIG_CPU_RK3562
1137 {
1138 .compatible = "rockchip,rk3562-cif",
1139 .data = &rk3562_cif_match_data,
1140 },
1141 #endif
1142 {},
1143 };
1144
rkcif_irq_handler(int irq,void * ctx)1145 static irqreturn_t rkcif_irq_handler(int irq, void *ctx)
1146 {
1147 struct device *dev = ctx;
1148 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1149 unsigned int intstat_glb = 0;
1150 u64 irq_start, irq_stop;
1151 int i;
1152
1153 irq_start = ktime_get_ns();
1154 if (cif_hw->chip_id >= CHIP_RK3588_CIF) {
1155 intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
1156 if (intstat_glb)
1157 rkcif_write_register(cif_hw->cif_dev[0], CIF_REG_GLB_INTST, intstat_glb);
1158 }
1159
1160 for (i = 0; i < cif_hw->dev_num; i++) {
1161 if (cif_hw->cif_dev[i]->isr_hdl) {
1162 cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
1163 if (cif_hw->cif_dev[i]->err_state &&
1164 (!work_busy(&cif_hw->cif_dev[i]->err_state_work.work))) {
1165 cif_hw->cif_dev[i]->err_state_work.err_state = cif_hw->cif_dev[i]->err_state;
1166 cif_hw->cif_dev[i]->err_state = 0;
1167 schedule_work(&cif_hw->cif_dev[i]->err_state_work.work);
1168 }
1169 if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb)
1170 rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
1171 }
1172 }
1173 irq_stop = ktime_get_ns();
1174 cif_hw->irq_time = irq_stop - irq_start;
1175 return IRQ_HANDLED;
1176 }
1177
rkcif_disable_sys_clk(struct rkcif_hw * cif_hw)1178 void rkcif_disable_sys_clk(struct rkcif_hw *cif_hw)
1179 {
1180 int i;
1181
1182 for (i = cif_hw->clk_size - 1; i >= 0; i--)
1183 clk_disable_unprepare(cif_hw->clks[i]);
1184 }
1185
rkcif_enable_sys_clk(struct rkcif_hw * cif_hw)1186 int rkcif_enable_sys_clk(struct rkcif_hw *cif_hw)
1187 {
1188 int i, ret = -EINVAL;
1189
1190 for (i = 0; i < cif_hw->clk_size; i++) {
1191 ret = clk_prepare_enable(cif_hw->clks[i]);
1192
1193 if (ret < 0)
1194 goto err;
1195 }
1196
1197 write_cif_reg_and(cif_hw->base_addr, CIF_CSI_INTEN, 0x0);
1198 return 0;
1199
1200 err:
1201 for (--i; i >= 0; --i)
1202 clk_disable_unprepare(cif_hw->clks[i]);
1203
1204 return ret;
1205 }
1206
rkcif_iommu_cleanup(struct rkcif_hw * cif_hw)1207 static void rkcif_iommu_cleanup(struct rkcif_hw *cif_hw)
1208 {
1209 if (cif_hw->iommu_en)
1210 rockchip_iommu_disable(cif_hw->dev);
1211 }
1212
rkcif_iommu_enable(struct rkcif_hw * cif_hw)1213 static void rkcif_iommu_enable(struct rkcif_hw *cif_hw)
1214 {
1215 if (cif_hw->iommu_en)
1216 rockchip_iommu_enable(cif_hw->dev);
1217 }
1218
is_iommu_enable(struct device * dev)1219 static inline bool is_iommu_enable(struct device *dev)
1220 {
1221 struct device_node *iommu;
1222
1223 iommu = of_parse_phandle(dev->of_node, "iommus", 0);
1224 if (!iommu) {
1225 dev_info(dev, "no iommu attached, using non-iommu buffers\n");
1226 return false;
1227 } else if (!of_device_is_available(iommu)) {
1228 dev_info(dev, "iommu is disabled, using non-iommu buffers\n");
1229 of_node_put(iommu);
1230 return false;
1231 }
1232 of_node_put(iommu);
1233
1234 return true;
1235 }
1236
rkcif_hw_soft_reset(struct rkcif_hw * cif_hw,bool is_rst_iommu)1237 void rkcif_hw_soft_reset(struct rkcif_hw *cif_hw, bool is_rst_iommu)
1238 {
1239 unsigned int i;
1240
1241 if (cif_hw->iommu_en && is_rst_iommu)
1242 rkcif_iommu_cleanup(cif_hw);
1243
1244 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
1245 if (cif_hw->cif_rst[i])
1246 reset_control_assert(cif_hw->cif_rst[i]);
1247 udelay(5);
1248 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
1249 if (cif_hw->cif_rst[i])
1250 reset_control_deassert(cif_hw->cif_rst[i]);
1251
1252 if (cif_hw->iommu_en && is_rst_iommu)
1253 rkcif_iommu_enable(cif_hw);
1254 }
1255
rkcif_get_efuse_value(struct device_node * np,char * porp_name,u8 * value)1256 static int rkcif_get_efuse_value(struct device_node *np, char *porp_name,
1257 u8 *value)
1258 {
1259 struct nvmem_cell *cell;
1260 unsigned char *buf;
1261 size_t len;
1262
1263 cell = of_nvmem_cell_get(np, porp_name);
1264 if (IS_ERR(cell))
1265 return PTR_ERR(cell);
1266
1267 buf = (unsigned char *)nvmem_cell_read(cell, &len);
1268
1269 nvmem_cell_put(cell);
1270
1271 if (IS_ERR(buf))
1272 return PTR_ERR(buf);
1273
1274 *value = buf[0];
1275
1276 kfree(buf);
1277
1278 return 0;
1279 }
1280
rkcif_get_speciand_package_number(struct device_node * np)1281 static int rkcif_get_speciand_package_number(struct device_node *np)
1282 {
1283 u8 spec = 0, package = 0, low = 0, high = 0;
1284
1285 if (rkcif_get_efuse_value(np, "specification", &spec))
1286 return -EINVAL;
1287 if (rkcif_get_efuse_value(np, "package_low", &low))
1288 return -EINVAL;
1289 if (rkcif_get_efuse_value(np, "package_high", &high))
1290 return -EINVAL;
1291
1292 package = ((high & 0x1) << 3) | low;
1293
1294 /* RK3588S */
1295 if (spec == 0x13)
1296 return package;
1297
1298 return -EINVAL;
1299 }
1300
rkcif_plat_hw_probe(struct platform_device * pdev)1301 static int rkcif_plat_hw_probe(struct platform_device *pdev)
1302 {
1303 const struct of_device_id *match;
1304 struct device_node *node = pdev->dev.of_node;
1305 struct device *dev = &pdev->dev;
1306 struct device_node *np = dev->of_node;
1307 struct rkcif_hw *cif_hw;
1308 struct rkcif_device *cif_dev;
1309 const struct rkcif_hw_match_data *data;
1310 struct resource *res;
1311 int i, ret, irq;
1312 bool is_mem_reserved = false;
1313 struct notifier_block *notifier;
1314 int package = 0;
1315
1316 match = of_match_node(rkcif_plat_of_match, node);
1317 if (IS_ERR(match))
1318 return PTR_ERR(match);
1319 data = match->data;
1320
1321 cif_hw = devm_kzalloc(dev, sizeof(*cif_hw), GFP_KERNEL);
1322 if (!cif_hw)
1323 return -ENOMEM;
1324
1325 dev_set_drvdata(dev, cif_hw);
1326 cif_hw->dev = dev;
1327
1328 package = rkcif_get_speciand_package_number(node);
1329 if (package == 0x2) {
1330 cif_hw->is_rk3588s2 = true;
1331 dev_info(dev, "attach rk3588s2\n");
1332 } else {
1333 cif_hw->is_rk3588s2 = false;
1334 }
1335 irq = platform_get_irq(pdev, 0);
1336 if (irq < 0)
1337 return irq;
1338
1339 ret = devm_request_irq(dev, irq, rkcif_irq_handler,
1340 IRQF_SHARED,
1341 dev_driver_string(dev), dev);
1342 if (ret < 0) {
1343 dev_err(dev, "request irq failed: %d\n", ret);
1344 return ret;
1345 }
1346
1347 cif_hw->irq = irq;
1348 cif_hw->match_data = data;
1349 cif_hw->chip_id = data->chip_id;
1350 if (data->chip_id >= CHIP_RK1808_CIF) {
1351 res = platform_get_resource_byname(pdev,
1352 IORESOURCE_MEM,
1353 "cif_regs");
1354 cif_hw->base_addr = devm_ioremap_resource(dev, res);
1355 if (PTR_ERR(cif_hw->base_addr) == -EBUSY) {
1356 resource_size_t offset = res->start;
1357 resource_size_t size = resource_size(res);
1358
1359 cif_hw->base_addr = devm_ioremap(dev, offset, size);
1360 if (IS_ERR(cif_hw->base_addr)) {
1361 dev_err(dev, "ioremap failed\n");
1362 return PTR_ERR(cif_hw->base_addr);
1363 }
1364 }
1365 } else {
1366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367 cif_hw->base_addr = devm_ioremap_resource(dev, res);
1368 if (IS_ERR(cif_hw->base_addr))
1369 return PTR_ERR(cif_hw->base_addr);
1370 }
1371
1372 if (of_property_read_bool(np, "rockchip,android-usb-camerahal-enable")) {
1373 dev_info(dev, "config cif adapt to android usb camera hal!\n");
1374 cif_hw->adapt_to_usbcamerahal = true;
1375 }
1376
1377 cif_hw->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1378 if (IS_ERR(cif_hw->grf))
1379 dev_warn(dev, "unable to get rockchip,grf\n");
1380
1381 if (data->clks_num > RKCIF_MAX_BUS_CLK ||
1382 data->rsts_num > RKCIF_MAX_RESET) {
1383 dev_err(dev, "out of range: clks(%d %d) rsts(%d %d)\n",
1384 data->clks_num, RKCIF_MAX_BUS_CLK,
1385 data->rsts_num, RKCIF_MAX_RESET);
1386 return -EINVAL;
1387 }
1388
1389 for (i = 0; i < data->clks_num; i++) {
1390 struct clk *clk = devm_clk_get(dev, data->clks[i]);
1391
1392 if (IS_ERR(clk)) {
1393 dev_err(dev, "failed to get %s\n", data->clks[i]);
1394 return PTR_ERR(clk);
1395 }
1396 cif_hw->clks[i] = clk;
1397 }
1398 cif_hw->clk_size = data->clks_num;
1399
1400 for (i = 0; i < data->rsts_num; i++) {
1401 struct reset_control *rst = NULL;
1402
1403 if (data->rsts[i])
1404 rst = devm_reset_control_get(dev, data->rsts[i]);
1405 if (IS_ERR(rst)) {
1406 cif_hw->cif_rst[i] = NULL;
1407 dev_err(dev, "failed to get %s\n", data->rsts[i]);
1408 } else {
1409 cif_hw->cif_rst[i] = rst;
1410 }
1411 }
1412
1413 cif_hw->cif_regs = data->cif_regs;
1414
1415 cif_hw->is_dma_sg_ops = true;
1416 cif_hw->is_dma_contig = true;
1417 mutex_init(&cif_hw->dev_lock);
1418 spin_lock_init(&cif_hw->group_lock);
1419 atomic_set(&cif_hw->power_cnt, 0);
1420
1421 cif_hw->iommu_en = is_iommu_enable(dev);
1422 ret = of_reserved_mem_device_init(dev);
1423 if (ret) {
1424 is_mem_reserved = false;
1425 dev_info(dev, "No reserved memory region assign to CIF\n");
1426 }
1427 if (cif_hw->iommu_en && !is_mem_reserved)
1428 cif_hw->is_dma_contig = false;
1429 cif_hw->mem_ops = &vb2_cma_sg_memops;
1430
1431 if (data->chip_id < CHIP_RK1808_CIF) {
1432 cif_dev = devm_kzalloc(dev, sizeof(*cif_dev), GFP_KERNEL);
1433 if (!cif_dev)
1434 return -ENOMEM;
1435
1436 cif_dev->dev = dev;
1437 cif_dev->hw_dev = cif_hw;
1438 cif_dev->chip_id = cif_hw->chip_id;
1439 cif_hw->cif_dev[0] = cif_dev;
1440 cif_hw->dev_num = 1;
1441 ret = rkcif_plat_init(cif_dev, node, RKCIF_DVP);
1442 if (ret)
1443 return ret;
1444 }
1445
1446 mutex_init(&cif_hw->dev_lock);
1447
1448 pm_runtime_enable(&pdev->dev);
1449
1450 if (data->chip_id >= CHIP_RK1808_CIF &&
1451 data->chip_id != CHIP_RV1126_CIF_LITE) {
1452 platform_driver_register(&rkcif_plat_drv);
1453 platform_driver_register(&rkcif_subdev_driver);
1454 }
1455
1456 notifier = &cif_hw->reset_notifier;
1457 notifier->priority = 1;
1458 notifier->notifier_call = rkcif_reset_notifier;
1459 rkcif_csi2_register_notifier(notifier);
1460
1461 return 0;
1462 }
1463
rkcif_plat_remove(struct platform_device * pdev)1464 static int rkcif_plat_remove(struct platform_device *pdev)
1465 {
1466 struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
1467
1468 pm_runtime_disable(&pdev->dev);
1469 if (cif_hw->iommu_en)
1470 rkcif_iommu_cleanup(cif_hw);
1471
1472 mutex_destroy(&cif_hw->dev_lock);
1473 if (cif_hw->chip_id < CHIP_RK1808_CIF)
1474 rkcif_plat_uninit(cif_hw->cif_dev[0]);
1475
1476 rkcif_csi2_unregister_notifier(&cif_hw->reset_notifier);
1477
1478 return 0;
1479 }
1480
rkcif_hw_shutdown(struct platform_device * pdev)1481 static void rkcif_hw_shutdown(struct platform_device *pdev)
1482 {
1483 struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
1484 struct rkcif_device *cif_dev = NULL;
1485 int i = 0;
1486
1487 if (pm_runtime_get_if_in_use(&pdev->dev) <= 0)
1488 return;
1489
1490 if (cif_hw->chip_id == CHIP_RK3588_CIF ||
1491 cif_hw->chip_id == CHIP_RV1106_CIF ||
1492 cif_hw->chip_id == CHIP_RK3562_CIF) {
1493 write_cif_reg(cif_hw->base_addr, 0, 0);
1494 } else {
1495 for (i = 0; i < cif_hw->dev_num; i++) {
1496 cif_dev = cif_hw->cif_dev[i];
1497 if (atomic_read(&cif_dev->pipe.stream_cnt)) {
1498 if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
1499 rkcif_write_register(cif_dev,
1500 CIF_REG_MIPI_LVDS_CTRL,
1501 0);
1502 else
1503 rkcif_write_register(cif_dev,
1504 CIF_REG_DVP_CTRL,
1505 0);
1506 }
1507 }
1508 }
1509 if (cif_hw->irq > 0)
1510 disable_irq(cif_hw->irq);
1511 pm_runtime_put(&pdev->dev);
1512 }
1513
rkcif_runtime_suspend(struct device * dev)1514 static int __maybe_unused rkcif_runtime_suspend(struct device *dev)
1515 {
1516 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1517
1518 if (atomic_dec_return(&cif_hw->power_cnt))
1519 return 0;
1520 rkcif_disable_sys_clk(cif_hw);
1521
1522 return pinctrl_pm_select_sleep_state(dev);
1523 }
1524
rkcif_runtime_resume(struct device * dev)1525 static int __maybe_unused rkcif_runtime_resume(struct device *dev)
1526 {
1527 struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1528 int ret;
1529
1530 if (atomic_inc_return(&cif_hw->power_cnt) > 1)
1531 return 0;
1532 ret = pinctrl_pm_select_default_state(dev);
1533 if (ret < 0)
1534 return ret;
1535 rkcif_enable_sys_clk(cif_hw);
1536 rkcif_hw_soft_reset(cif_hw, true);
1537
1538 return 0;
1539 }
1540
1541 static const struct dev_pm_ops rkcif_plat_pm_ops = {
1542 SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
1543 };
1544
1545 static struct platform_driver rkcif_hw_plat_drv = {
1546 .driver = {
1547 .name = RKCIF_HW_DRIVER_NAME,
1548 .of_match_table = of_match_ptr(rkcif_plat_of_match),
1549 .pm = &rkcif_plat_pm_ops,
1550 },
1551 .probe = rkcif_plat_hw_probe,
1552 .remove = rkcif_plat_remove,
1553 .shutdown = rkcif_hw_shutdown,
1554 };
1555
rk_cif_plat_drv_init(void)1556 int rk_cif_plat_drv_init(void)
1557 {
1558 int ret;
1559
1560 ret = platform_driver_register(&rkcif_hw_plat_drv);
1561 if (ret)
1562 return ret;
1563 rkcif_csi2_hw_plat_drv_init();
1564 return rkcif_csi2_plat_drv_init();
1565 }
1566
rk_cif_plat_drv_exit(void)1567 static void __exit rk_cif_plat_drv_exit(void)
1568 {
1569 platform_driver_unregister(&rkcif_hw_plat_drv);
1570 rkcif_csi2_plat_drv_exit();
1571 rkcif_csi2_hw_plat_drv_exit();
1572 }
1573
1574 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1575 subsys_initcall(rk_cif_plat_drv_init);
1576 #else
1577 #if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
1578 module_init(rk_cif_plat_drv_init);
1579 #endif
1580 #endif
1581 module_exit(rk_cif_plat_drv_exit);
1582
1583 MODULE_AUTHOR("Rockchip Camera/ISP team");
1584 MODULE_DESCRIPTION("Rockchip CIF platform driver");
1585 MODULE_LICENSE("GPL v2");
1586