1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc5336 driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 */
8
9 //#define DEBUG
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/version.h>
21 #include <linux/rk-camera-module.h>
22 #include <linux/rk-preisp.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
29
30 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
31
32 #ifndef V4L2_CID_DIGITAL_GAIN
33 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34 #endif
35
36 #define SC5336_LANES 2
37 #define SC5336_BITS_PER_SAMPLE 10
38 #define SC5336_LINK_FREQ 432000000
39
40 #define PIXEL_RATE_WITH_315M_10BIT (SC5336_LINK_FREQ * 2 * \
41 SC5336_LANES / SC5336_BITS_PER_SAMPLE)
42 #define SC5336_XVCLK_FREQ 24000000
43
44 #define CHIP_ID 0xce50
45 #define SC5336_REG_CHIP_ID 0x3107
46
47 #define SC5336_REG_CTRL_MODE 0x0100
48 #define SC5336_MODE_SW_STANDBY 0x0
49 #define SC5336_MODE_STREAMING BIT(0)
50
51 #define SC5336_REG_EXPOSURE_H 0x3e00
52 #define SC5336_REG_EXPOSURE_M 0x3e01
53 #define SC5336_REG_EXPOSURE_L 0x3e02
54 #define SC5336_EXPOSURE_MIN 1
55 #define SC5336_EXPOSURE_STEP 1
56 #define SC5336_VTS_MAX 0x7fff
57
58 #define SC5336_REG_DIG_GAIN 0x3e06
59 #define SC5336_REG_DIG_FINE_GAIN 0x3e07
60 #define SC5336_REG_ANA_GAIN 0x3e09
61 #define SC5336_GAIN_MIN 0x0020
62 #define SC5336_GAIN_MAX (32 * 15 * 32) //32*15*32
63 #define SC5336_GAIN_STEP 1
64 #define SC5336_GAIN_DEFAULT 0x120
65
66
67 #define SC5336_REG_GROUP_HOLD 0x3812
68 #define SC5336_GROUP_HOLD_START 0x00
69 #define SC5336_GROUP_HOLD_END 0x30
70
71 #define SC5336_REG_TEST_PATTERN 0x4501
72
73 #define SC5336_REG_VTS_H 0x320e
74 #define SC5336_REG_VTS_L 0x320f
75
76 #define SC5336_FLIP_MIRROR_REG 0x3221
77
78 #define SC5336_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
79 #define SC5336_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
80 #define SC5336_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
81
82 #define SC5336_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
83 #define SC5336_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
84
85 #define SC5336_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
86 #define SC5336_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
87
88 #define REG_DELAY 0xFFFE
89 #define REG_NULL 0xFFFF
90
91 #define SC5336_REG_VALUE_08BIT 1
92 #define SC5336_REG_VALUE_16BIT 2
93 #define SC5336_REG_VALUE_24BIT 3
94
95 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
96 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
97 #define SC5336_NAME "sc5336"
98
99 static const char * const sc5336_supply_names[] = {
100 "avdd", /* Analog power */
101 "dovdd", /* Digital I/O power */
102 "dvdd", /* Digital core power */
103 };
104
105 #define SC5336_NUM_SUPPLIES ARRAY_SIZE(sc5336_supply_names)
106
107 struct regval {
108 u16 addr;
109 u8 val;
110 };
111
112 struct sc5336_mode {
113 u32 bus_fmt;
114 u32 width;
115 u32 height;
116 struct v4l2_fract max_fps;
117 u32 hts_def;
118 u32 vts_def;
119 u32 exp_def;
120 const struct regval *reg_list;
121 u32 hdr_mode;
122 u32 vc[PAD_MAX];
123 };
124
125 struct sc5336 {
126 struct i2c_client *client;
127 struct clk *xvclk;
128 struct gpio_desc *reset_gpio;
129 struct gpio_desc *pwdn_gpio;
130 struct regulator_bulk_data supplies[SC5336_NUM_SUPPLIES];
131
132 struct pinctrl *pinctrl;
133 struct pinctrl_state *pins_default;
134 struct pinctrl_state *pins_sleep;
135
136 struct v4l2_subdev subdev;
137 struct media_pad pad;
138 struct v4l2_ctrl_handler ctrl_handler;
139 struct v4l2_ctrl *exposure;
140 struct v4l2_ctrl *anal_gain;
141 struct v4l2_ctrl *digi_gain;
142 struct v4l2_ctrl *hblank;
143 struct v4l2_ctrl *vblank;
144 struct v4l2_ctrl *test_pattern;
145 struct mutex mutex;
146 bool streaming;
147 bool power_on;
148 const struct sc5336_mode *cur_mode;
149 struct v4l2_fract cur_fps;
150 u32 module_index;
151 const char *module_facing;
152 const char *module_name;
153 const char *len_name;
154 u32 cur_vts;
155 bool is_thunderboot;
156 bool is_first_streamoff;
157 };
158
159 #define to_sc5336(sd) container_of(sd, struct sc5336, subdev)
160
161 /*
162 * Xclk 24Mhz
163 */
164 static const struct regval sc5336_global_regs[] = {
165 {REG_NULL, 0x00},
166 };
167
168 /*
169 * Xclk 24Mhz
170 * max_framerate 30fps
171 * mipi_datarate per lane 864Mbps, 2lane
172 */
173 static const struct regval sc5336_linear_10_2880x1620_regs[] = {
174 {0x0103, 0x01},
175 {0x36e9, 0x80},
176 {0x37f9, 0x80},
177 {0x301f, 0x1a},
178 {0x320e, 0x07},
179 {0x320f, 0x08},
180 {0x3213, 0x04},
181 {0x3241, 0x00},
182 {0x3243, 0x01},
183 {0x3248, 0x02},
184 {0x3249, 0x0b},
185 {0x3253, 0x10},
186 {0x3258, 0x0c},
187 {0x3301, 0x0a},
188 {0x3305, 0x00},
189 {0x3306, 0x58},
190 {0x3308, 0x08},
191 {0x3309, 0xb0},
192 {0x330a, 0x00},
193 {0x330b, 0xc8},
194 {0x3314, 0x14},
195 {0x331f, 0xa1},
196 {0x3321, 0x10},
197 {0x3327, 0x14},
198 {0x3328, 0x0b},
199 {0x3329, 0x0e},
200 {0x3333, 0x10},
201 {0x3334, 0x40},
202 {0x3356, 0x10},
203 {0x3364, 0x5e},
204 {0x338f, 0x80},
205 {0x3390, 0x09},
206 {0x3391, 0x0b},
207 {0x3392, 0x0f},
208 {0x3393, 0x10},
209 {0x3394, 0x16},
210 {0x3395, 0x98},
211 {0x3396, 0x08},
212 {0x3397, 0x09},
213 {0x3398, 0x0f},
214 {0x3399, 0x0a},
215 {0x339a, 0x18},
216 {0x339b, 0x60},
217 {0x339c, 0xff},
218 {0x33ad, 0x0c},
219 {0x33ae, 0x5c},
220 {0x33af, 0x52},
221 {0x33b1, 0xa0},
222 {0x33b2, 0x38},
223 {0x33b3, 0x18},
224 {0x33f8, 0x00},
225 {0x33f9, 0x60},
226 {0x33fa, 0x00},
227 {0x33fb, 0x80},
228 {0x33fc, 0x0b},
229 {0x33fd, 0x1f},
230 {0x349f, 0x03},
231 {0x34a6, 0x0b},
232 {0x34a7, 0x1f},
233 {0x34a8, 0x08},
234 {0x34a9, 0x08},
235 {0x34aa, 0x00},
236 {0x34ab, 0xd0},
237 {0x34ac, 0x00},
238 {0x34ad, 0xf0},
239 {0x34f8, 0x3f},
240 {0x34f9, 0x08},
241 {0x3630, 0xc0},
242 {0x3631, 0x83},
243 {0x3632, 0x54},
244 {0x3633, 0x33},
245 {0x3638, 0xcf},
246 {0x363f, 0xc0},
247 {0x3641, 0x20},
248 {0x3670, 0x56},
249 {0x3674, 0xc0},
250 {0x3675, 0xa0},
251 {0x3676, 0xa0},
252 {0x3677, 0x83},
253 {0x3678, 0x86},
254 {0x3679, 0x8a},
255 {0x367c, 0x08},
256 {0x367d, 0x0f},
257 {0x367e, 0x08},
258 {0x367f, 0x0f},
259 {0x3696, 0x23},
260 {0x3697, 0x33},
261 {0x3698, 0x34},
262 {0x36a0, 0x09},
263 {0x36a1, 0x0f},
264 {0x36b0, 0x85},
265 {0x36b1, 0x8a},
266 {0x36b2, 0x95},
267 {0x36b3, 0xa6},
268 {0x36b4, 0x09},
269 {0x36b5, 0x0b},
270 {0x36b6, 0x0f},
271 {0x36ea, 0x0c},
272 {0x36eb, 0x0c},
273 {0x36ec, 0x0c},
274 {0x36ed, 0xb6},
275 {0x370f, 0x01},
276 {0x3721, 0x6c},
277 {0x3722, 0x89},
278 {0x3724, 0x21},
279 {0x3725, 0xb4},
280 {0x3727, 0x14},
281 {0x3771, 0x89},
282 {0x3772, 0x89},
283 {0x3773, 0xc5},
284 {0x377a, 0x0b},
285 {0x377b, 0x1f},
286 {0x37fa, 0x0c},
287 {0x37fb, 0x24},
288 {0x37fc, 0x01},
289 {0x37fd, 0x36},
290 {0x3901, 0x00},
291 {0x3904, 0x04},
292 {0x3905, 0x8c},
293 {0x391d, 0x04},
294 {0x391f, 0x49},
295 {0x3926, 0x21},
296 {0x3933, 0x80},
297 {0x3934, 0x0a},
298 {0x3935, 0x00},
299 {0x3936, 0xff},
300 {0x3937, 0x75},
301 {0x3938, 0x74},
302 {0x393c, 0x1e},
303 {0x39dc, 0x02},
304 {0x3e00, 0x00},
305 {0x3e01, 0x70},
306 {0x3e02, 0x00},
307 {0x3e09, 0x00},
308 {0x440d, 0x10},
309 {0x440e, 0x02},
310 {0x450d, 0x18},
311 {0x4819, 0x0b},
312 {0x481b, 0x06},
313 {0x481d, 0x17},
314 {0x481f, 0x05},
315 {0x4821, 0x0b},
316 {0x4823, 0x06},
317 {0x4825, 0x05},
318 {0x4827, 0x05},
319 {0x4829, 0x09},
320 {0x5780, 0x66},
321 {0x5787, 0x08},
322 {0x5788, 0x03},
323 {0x5789, 0x00},
324 {0x578a, 0x08},
325 {0x578b, 0x03},
326 {0x578c, 0x00},
327 {0x578d, 0x40},
328 {0x5790, 0x08},
329 {0x5791, 0x04},
330 {0x5792, 0x01},
331 {0x5793, 0x08},
332 {0x5794, 0x04},
333 {0x5795, 0x01},
334 {0x5799, 0x46},
335 {0x57aa, 0x2a},
336 {0x5ae0, 0xfe},
337 {0x5ae1, 0x40},
338 {0x5ae2, 0x38},
339 {0x5ae3, 0x30},
340 {0x5ae4, 0x0c},
341 {0x5ae5, 0x38},
342 {0x5ae6, 0x30},
343 {0x5ae7, 0x28},
344 {0x5ae8, 0x3f},
345 {0x5ae9, 0x34},
346 {0x5aea, 0x2c},
347 {0x5aeb, 0x3f},
348 {0x5aec, 0x34},
349 {0x5aed, 0x2c},
350 {0x36e9, 0x20},
351 {0x37f9, 0x20},
352 {REG_NULL, 0x00},
353 };
354
355 static const struct sc5336_mode supported_modes[] = {
356 {
357 .width = 2880,
358 .height = 1620,
359 .max_fps = {
360 .numerator = 10000,
361 .denominator = 300000,
362 },
363 .exp_def = 0x0080 * 4,
364 .hts_def = 0x0654 * 2,
365 .vts_def = 0x0708,
366 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
367 .reg_list = sc5336_linear_10_2880x1620_regs,
368 .hdr_mode = NO_HDR,
369 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
370 }
371 };
372
373 static const s64 link_freq_menu_items[] = {
374 SC5336_LINK_FREQ
375 };
376
377 static const char * const sc5336_test_pattern_menu[] = {
378 "Disabled",
379 "Vertical Gray Bar Type 1",
380 };
381
382 /* Write registers up to 4 at a time */
sc5336_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)383 static int sc5336_write_reg(struct i2c_client *client, u16 reg,
384 u32 len, u32 val)
385 {
386 u32 buf_i, val_i;
387 u8 buf[6];
388 u8 *val_p;
389 __be32 val_be;
390
391 if (len > 4)
392 return -EINVAL;
393
394 buf[0] = reg >> 8;
395 buf[1] = reg & 0xff;
396
397 val_be = cpu_to_be32(val);
398 val_p = (u8 *)&val_be;
399 buf_i = 2;
400 val_i = 4 - len;
401
402 while (val_i < 4)
403 buf[buf_i++] = val_p[val_i++];
404
405 if (i2c_master_send(client, buf, len + 2) != len + 2)
406 return -EIO;
407 return 0;
408 }
409
sc5336_write_array(struct i2c_client * client,const struct regval * regs)410 static int sc5336_write_array(struct i2c_client *client,
411 const struct regval *regs)
412 {
413 u32 i;
414 int ret = 0;
415
416 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
417 ret = sc5336_write_reg(client, regs[i].addr,
418 SC5336_REG_VALUE_08BIT, regs[i].val);
419
420 return ret;
421 }
422
423 /* Read registers up to 4 at a time */
sc5336_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)424 static int sc5336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
425 u32 *val)
426 {
427 struct i2c_msg msgs[2];
428 u8 *data_be_p;
429 __be32 data_be = 0;
430 __be16 reg_addr_be = cpu_to_be16(reg);
431 int ret;
432
433 if (len > 4 || !len)
434 return -EINVAL;
435
436 data_be_p = (u8 *)&data_be;
437 /* Write register address */
438 msgs[0].addr = client->addr;
439 msgs[0].flags = 0;
440 msgs[0].len = 2;
441 msgs[0].buf = (u8 *)®_addr_be;
442
443 /* Read data from register */
444 msgs[1].addr = client->addr;
445 msgs[1].flags = I2C_M_RD;
446 msgs[1].len = len;
447 msgs[1].buf = &data_be_p[4 - len];
448
449 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
450 if (ret != ARRAY_SIZE(msgs))
451 return -EIO;
452
453 *val = be32_to_cpu(data_be);
454
455 return 0;
456 }
457
sc5336_set_gain_reg(struct sc5336 * sc5336,u32 gain)458 static int sc5336_set_gain_reg(struct sc5336 *sc5336, u32 gain)
459 {
460 u32 coarse_again = 0, coarse_dgian = 0, fine_dgian = 0;
461 u32 gain_factor;
462 int ret = 0;
463
464 if (gain < 32)
465 gain = 32;
466 else if (gain > SC5336_GAIN_MAX)
467 gain = SC5336_GAIN_MAX;
468
469 gain_factor = gain * 1000 / 32;
470 if (gain_factor < 2000) {
471 coarse_again = 0x00;
472 coarse_dgian = 0x00;
473 fine_dgian = gain_factor * 128 / 1000;
474 } else if (gain_factor < 4000) {
475 coarse_again = 0x08;
476 coarse_dgian = 0x00;
477 fine_dgian = gain_factor * 128 / 2000;
478 } else if (gain_factor < 8000) {
479 coarse_again = 0x09;
480 coarse_dgian = 0x00;
481 fine_dgian = gain_factor * 128 / 4000;
482 } else if (gain_factor < 16000) {
483 coarse_again = 0x0b;
484 coarse_dgian = 0x00;
485 fine_dgian = gain_factor * 128 / 8000;
486 } else if (gain_factor < 32000) {
487 coarse_again = 0x0f;
488 coarse_dgian = 0x00;
489 fine_dgian = gain_factor * 128 / 16000;
490 } else if (gain_factor < 32000 * 2) {
491 coarse_again = 0x1f;
492 coarse_dgian = 0x00;
493 fine_dgian = gain_factor * 128 / 32000;
494 } else if (gain_factor < 32000 * 4) {
495 //open dgain begin max digital gain 4X
496 coarse_again = 0x1f;
497 coarse_dgian = 0x01;
498 fine_dgian = gain_factor * 128 / 32000 / 2;
499 } else if (gain_factor < 32000 * 8) {
500 coarse_again = 0x1f;
501 coarse_dgian = 0x03;
502 fine_dgian = gain_factor * 128 / 32000 / 4;
503 } else if (gain_factor < 32000 * 15) {
504 coarse_again = 0x1f;
505 coarse_dgian = 0x07;
506 fine_dgian = gain_factor * 128 / 32000 / 8;
507 } else {
508 coarse_again = 0x1f;
509 coarse_dgian = 0x07;
510 fine_dgian = 0xf0;
511 }
512
513 ret = sc5336_write_reg(sc5336->client,
514 SC5336_REG_DIG_GAIN,
515 SC5336_REG_VALUE_08BIT,
516 coarse_dgian);
517 ret |= sc5336_write_reg(sc5336->client,
518 SC5336_REG_DIG_FINE_GAIN,
519 SC5336_REG_VALUE_08BIT,
520 fine_dgian);
521 ret |= sc5336_write_reg(sc5336->client,
522 SC5336_REG_ANA_GAIN,
523 SC5336_REG_VALUE_08BIT,
524 coarse_again);
525
526 return ret;
527 }
528
sc5336_get_reso_dist(const struct sc5336_mode * mode,struct v4l2_mbus_framefmt * framefmt)529 static int sc5336_get_reso_dist(const struct sc5336_mode *mode,
530 struct v4l2_mbus_framefmt *framefmt)
531 {
532 return abs(mode->width - framefmt->width) +
533 abs(mode->height - framefmt->height);
534 }
535
536 static const struct sc5336_mode *
sc5336_find_best_fit(struct v4l2_subdev_format * fmt)537 sc5336_find_best_fit(struct v4l2_subdev_format *fmt)
538 {
539 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
540 int dist;
541 int cur_best_fit = 0;
542 int cur_best_fit_dist = -1;
543 unsigned int i;
544
545 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
546 dist = sc5336_get_reso_dist(&supported_modes[i], framefmt);
547 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
548 cur_best_fit_dist = dist;
549 cur_best_fit = i;
550 }
551 }
552
553 return &supported_modes[cur_best_fit];
554 }
555
sc5336_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)556 static int sc5336_set_fmt(struct v4l2_subdev *sd,
557 struct v4l2_subdev_pad_config *cfg,
558 struct v4l2_subdev_format *fmt)
559 {
560 struct sc5336 *sc5336 = to_sc5336(sd);
561 const struct sc5336_mode *mode;
562 s64 h_blank, vblank_def;
563
564 mutex_lock(&sc5336->mutex);
565
566 mode = sc5336_find_best_fit(fmt);
567 fmt->format.code = mode->bus_fmt;
568 fmt->format.width = mode->width;
569 fmt->format.height = mode->height;
570 fmt->format.field = V4L2_FIELD_NONE;
571 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
572 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
573 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
574 #else
575 mutex_unlock(&sc5336->mutex);
576 return -ENOTTY;
577 #endif
578 } else {
579 sc5336->cur_mode = mode;
580 h_blank = mode->hts_def - mode->width;
581 __v4l2_ctrl_modify_range(sc5336->hblank, h_blank,
582 h_blank, 1, h_blank);
583 vblank_def = mode->vts_def - mode->height;
584 __v4l2_ctrl_modify_range(sc5336->vblank, vblank_def,
585 SC5336_VTS_MAX - mode->height,
586 1, vblank_def);
587 sc5336->cur_fps = mode->max_fps;
588 }
589
590 mutex_unlock(&sc5336->mutex);
591
592 return 0;
593 }
594
sc5336_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)595 static int sc5336_get_fmt(struct v4l2_subdev *sd,
596 struct v4l2_subdev_pad_config *cfg,
597 struct v4l2_subdev_format *fmt)
598 {
599 struct sc5336 *sc5336 = to_sc5336(sd);
600 const struct sc5336_mode *mode = sc5336->cur_mode;
601
602 mutex_lock(&sc5336->mutex);
603 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
604 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
605 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
606 #else
607 mutex_unlock(&sc5336->mutex);
608 return -ENOTTY;
609 #endif
610 } else {
611 fmt->format.width = mode->width;
612 fmt->format.height = mode->height;
613 fmt->format.code = mode->bus_fmt;
614 fmt->format.field = V4L2_FIELD_NONE;
615 /* format info: width/height/data type/virctual channel */
616 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
617 fmt->reserved[0] = mode->vc[fmt->pad];
618 else
619 fmt->reserved[0] = mode->vc[PAD0];
620 }
621 mutex_unlock(&sc5336->mutex);
622
623 return 0;
624 }
625
sc5336_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)626 static int sc5336_enum_mbus_code(struct v4l2_subdev *sd,
627 struct v4l2_subdev_pad_config *cfg,
628 struct v4l2_subdev_mbus_code_enum *code)
629 {
630 struct sc5336 *sc5336 = to_sc5336(sd);
631
632 if (code->index != 0)
633 return -EINVAL;
634 code->code = sc5336->cur_mode->bus_fmt;
635
636 return 0;
637 }
638
sc5336_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)639 static int sc5336_enum_frame_sizes(struct v4l2_subdev *sd,
640 struct v4l2_subdev_pad_config *cfg,
641 struct v4l2_subdev_frame_size_enum *fse)
642 {
643 if (fse->index >= ARRAY_SIZE(supported_modes))
644 return -EINVAL;
645
646 if (fse->code != supported_modes[0].bus_fmt)
647 return -EINVAL;
648
649 fse->min_width = supported_modes[fse->index].width;
650 fse->max_width = supported_modes[fse->index].width;
651 fse->max_height = supported_modes[fse->index].height;
652 fse->min_height = supported_modes[fse->index].height;
653
654 return 0;
655 }
656
sc5336_enable_test_pattern(struct sc5336 * sc5336,u32 pattern)657 static int sc5336_enable_test_pattern(struct sc5336 *sc5336, u32 pattern)
658 {
659 int ret = 0;
660
661 if (pattern) {
662 ret |= sc5336_write_reg(sc5336->client, 0x4501, SC5336_REG_VALUE_08BIT, 0xac);
663 ret |= sc5336_write_reg(sc5336->client, 0x3902, SC5336_REG_VALUE_08BIT, 0x80);
664 ret |= sc5336_write_reg(sc5336->client, 0x3e07, SC5336_REG_VALUE_08BIT, 0x40);
665 } else {
666 ret |= sc5336_write_reg(sc5336->client, 0x4501, SC5336_REG_VALUE_08BIT, 0xa4);
667 ret |= sc5336_write_reg(sc5336->client, 0x3902, SC5336_REG_VALUE_08BIT, 0xc0);
668 ret |= sc5336_write_reg(sc5336->client, 0x3e07, SC5336_REG_VALUE_08BIT, 0x80);
669 }
670
671 return ret;
672 }
673
sc5336_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)674 static int sc5336_g_frame_interval(struct v4l2_subdev *sd,
675 struct v4l2_subdev_frame_interval *fi)
676 {
677 struct sc5336 *sc5336 = to_sc5336(sd);
678 const struct sc5336_mode *mode = sc5336->cur_mode;
679
680 if (sc5336->streaming)
681 fi->interval = sc5336->cur_fps;
682 else
683 fi->interval = mode->max_fps;
684
685 return 0;
686 }
687
sc5336_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)688 static int sc5336_g_mbus_config(struct v4l2_subdev *sd,
689 unsigned int pad_id,
690 struct v4l2_mbus_config *config)
691 {
692 struct sc5336 *sc5336 = to_sc5336(sd);
693 const struct sc5336_mode *mode = sc5336->cur_mode;
694 u32 val = 1 << (SC5336_LANES - 1) |
695 V4L2_MBUS_CSI2_CHANNEL_0 |
696 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
697
698 if (mode->hdr_mode != NO_HDR)
699 val |= V4L2_MBUS_CSI2_CHANNEL_1;
700 if (mode->hdr_mode == HDR_X3)
701 val |= V4L2_MBUS_CSI2_CHANNEL_2;
702
703 config->type = V4L2_MBUS_CSI2_DPHY;
704 config->flags = val;
705
706 return 0;
707 }
708
sc5336_get_module_inf(struct sc5336 * sc5336,struct rkmodule_inf * inf)709 static void sc5336_get_module_inf(struct sc5336 *sc5336,
710 struct rkmodule_inf *inf)
711 {
712 memset(inf, 0, sizeof(*inf));
713 strscpy(inf->base.sensor, SC5336_NAME, sizeof(inf->base.sensor));
714 strscpy(inf->base.module, sc5336->module_name,
715 sizeof(inf->base.module));
716 strscpy(inf->base.lens, sc5336->len_name, sizeof(inf->base.lens));
717 }
718
sc5336_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)719 static long sc5336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
720 {
721 struct sc5336 *sc5336 = to_sc5336(sd);
722 struct rkmodule_hdr_cfg *hdr;
723 u32 i, h, w;
724 long ret = 0;
725 u32 stream = 0;
726
727 switch (cmd) {
728 case RKMODULE_GET_MODULE_INFO:
729 sc5336_get_module_inf(sc5336, (struct rkmodule_inf *)arg);
730 break;
731 case RKMODULE_GET_HDR_CFG:
732 hdr = (struct rkmodule_hdr_cfg *)arg;
733 hdr->esp.mode = HDR_NORMAL_VC;
734 hdr->hdr_mode = sc5336->cur_mode->hdr_mode;
735 break;
736 case RKMODULE_SET_HDR_CFG:
737 hdr = (struct rkmodule_hdr_cfg *)arg;
738 w = sc5336->cur_mode->width;
739 h = sc5336->cur_mode->height;
740 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
741 if (w == supported_modes[i].width &&
742 h == supported_modes[i].height &&
743 supported_modes[i].hdr_mode == hdr->hdr_mode) {
744 sc5336->cur_mode = &supported_modes[i];
745 break;
746 }
747 }
748 if (i == ARRAY_SIZE(supported_modes)) {
749 dev_err(&sc5336->client->dev,
750 "not find hdr mode:%d %dx%d config\n",
751 hdr->hdr_mode, w, h);
752 ret = -EINVAL;
753 } else {
754 w = sc5336->cur_mode->hts_def - sc5336->cur_mode->width;
755 h = sc5336->cur_mode->vts_def - sc5336->cur_mode->height;
756 __v4l2_ctrl_modify_range(sc5336->hblank, w, w, 1, w);
757 __v4l2_ctrl_modify_range(sc5336->vblank, h,
758 SC5336_VTS_MAX - sc5336->cur_mode->height, 1, h);
759 }
760 break;
761 case PREISP_CMD_SET_HDRAE_EXP:
762 break;
763 case RKMODULE_SET_QUICK_STREAM:
764
765 stream = *((u32 *)arg);
766
767 if (stream)
768 ret = sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE,
769 SC5336_REG_VALUE_08BIT, SC5336_MODE_STREAMING);
770 else
771 ret = sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE,
772 SC5336_REG_VALUE_08BIT, SC5336_MODE_SW_STANDBY);
773 break;
774 default:
775 ret = -ENOIOCTLCMD;
776 break;
777 }
778
779 return ret;
780 }
781
782 #ifdef CONFIG_COMPAT
sc5336_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)783 static long sc5336_compat_ioctl32(struct v4l2_subdev *sd,
784 unsigned int cmd, unsigned long arg)
785 {
786 void __user *up = compat_ptr(arg);
787 struct rkmodule_inf *inf;
788 struct rkmodule_hdr_cfg *hdr;
789 struct preisp_hdrae_exp_s *hdrae;
790 long ret;
791 u32 stream = 0;
792
793 switch (cmd) {
794 case RKMODULE_GET_MODULE_INFO:
795 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
796 if (!inf) {
797 ret = -ENOMEM;
798 return ret;
799 }
800
801 ret = sc5336_ioctl(sd, cmd, inf);
802 if (!ret) {
803 if (copy_to_user(up, inf, sizeof(*inf)))
804 ret = -EFAULT;
805 }
806 kfree(inf);
807 break;
808 case RKMODULE_GET_HDR_CFG:
809 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
810 if (!hdr) {
811 ret = -ENOMEM;
812 return ret;
813 }
814
815 ret = sc5336_ioctl(sd, cmd, hdr);
816 if (!ret) {
817 if (copy_to_user(up, hdr, sizeof(*hdr)))
818 ret = -EFAULT;
819 }
820 kfree(hdr);
821 break;
822 case RKMODULE_SET_HDR_CFG:
823 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
824 if (!hdr) {
825 ret = -ENOMEM;
826 return ret;
827 }
828
829 ret = copy_from_user(hdr, up, sizeof(*hdr));
830 if (!ret)
831 ret = sc5336_ioctl(sd, cmd, hdr);
832 else
833 ret = -EFAULT;
834 kfree(hdr);
835 break;
836 case PREISP_CMD_SET_HDRAE_EXP:
837 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
838 if (!hdrae) {
839 ret = -ENOMEM;
840 return ret;
841 }
842
843 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
844 if (!ret)
845 ret = sc5336_ioctl(sd, cmd, hdrae);
846 else
847 ret = -EFAULT;
848 kfree(hdrae);
849 break;
850 case RKMODULE_SET_QUICK_STREAM:
851 ret = copy_from_user(&stream, up, sizeof(u32));
852 if (!ret)
853 ret = sc5336_ioctl(sd, cmd, &stream);
854 else
855 ret = -EFAULT;
856 break;
857 default:
858 ret = -ENOIOCTLCMD;
859 break;
860 }
861
862 return ret;
863 }
864 #endif
865
__sc5336_start_stream(struct sc5336 * sc5336)866 static int __sc5336_start_stream(struct sc5336 *sc5336)
867 {
868 int ret;
869
870 if (!sc5336->is_thunderboot) {
871 ret = sc5336_write_array(sc5336->client, sc5336->cur_mode->reg_list);
872 if (ret)
873 return ret;
874
875 /* In case these controls are set before streaming */
876 ret = __v4l2_ctrl_handler_setup(&sc5336->ctrl_handler);
877 if (ret)
878 return ret;
879 }
880
881 return sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE,
882 SC5336_REG_VALUE_08BIT, SC5336_MODE_STREAMING);
883 }
884
__sc5336_stop_stream(struct sc5336 * sc5336)885 static int __sc5336_stop_stream(struct sc5336 *sc5336)
886 {
887 if (sc5336->is_thunderboot) {
888 sc5336->is_first_streamoff = true;
889 pm_runtime_put(&sc5336->client->dev);
890 }
891 return sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE,
892 SC5336_REG_VALUE_08BIT, SC5336_MODE_SW_STANDBY);
893 }
894
895 static int __sc5336_power_on(struct sc5336 *sc5336);
sc5336_s_stream(struct v4l2_subdev * sd,int on)896 static int sc5336_s_stream(struct v4l2_subdev *sd, int on)
897 {
898 struct sc5336 *sc5336 = to_sc5336(sd);
899 struct i2c_client *client = sc5336->client;
900 int ret = 0;
901
902 mutex_lock(&sc5336->mutex);
903 on = !!on;
904 if (on == sc5336->streaming)
905 goto unlock_and_return;
906
907 if (on) {
908 if (sc5336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
909 sc5336->is_thunderboot = false;
910 __sc5336_power_on(sc5336);
911 }
912
913 ret = pm_runtime_get_sync(&client->dev);
914 if (ret < 0) {
915 pm_runtime_put_noidle(&client->dev);
916 goto unlock_and_return;
917 }
918
919 ret = __sc5336_start_stream(sc5336);
920 if (ret) {
921 v4l2_err(sd, "start stream failed while write regs\n");
922 pm_runtime_put(&client->dev);
923 goto unlock_and_return;
924 }
925 } else {
926 __sc5336_stop_stream(sc5336);
927 pm_runtime_put(&client->dev);
928 }
929
930 sc5336->streaming = on;
931
932 unlock_and_return:
933 mutex_unlock(&sc5336->mutex);
934
935 return ret;
936 }
937
sc5336_s_power(struct v4l2_subdev * sd,int on)938 static int sc5336_s_power(struct v4l2_subdev *sd, int on)
939 {
940 struct sc5336 *sc5336 = to_sc5336(sd);
941 struct i2c_client *client = sc5336->client;
942 int ret = 0;
943
944 mutex_lock(&sc5336->mutex);
945
946 /* If the power state is not modified - no work to do. */
947 if (sc5336->power_on == !!on)
948 goto unlock_and_return;
949
950 if (on) {
951 ret = pm_runtime_get_sync(&client->dev);
952 if (ret < 0) {
953 pm_runtime_put_noidle(&client->dev);
954 goto unlock_and_return;
955 }
956
957 if (!sc5336->is_thunderboot) {
958 ret = sc5336_write_array(sc5336->client, sc5336_global_regs);
959 if (ret) {
960 v4l2_err(sd, "could not set init registers\n");
961 pm_runtime_put_noidle(&client->dev);
962 goto unlock_and_return;
963 }
964 }
965
966 sc5336->power_on = true;
967 } else {
968 pm_runtime_put(&client->dev);
969 sc5336->power_on = false;
970 }
971
972 unlock_and_return:
973 mutex_unlock(&sc5336->mutex);
974
975 return ret;
976 }
977
978 /* Calculate the delay in us by clock rate and clock cycles */
sc5336_cal_delay(u32 cycles)979 static inline u32 sc5336_cal_delay(u32 cycles)
980 {
981 return DIV_ROUND_UP(cycles, SC5336_XVCLK_FREQ / 1000 / 1000);
982 }
983
__sc5336_power_on(struct sc5336 * sc5336)984 static int __sc5336_power_on(struct sc5336 *sc5336)
985 {
986 int ret;
987 u32 delay_us;
988 struct device *dev = &sc5336->client->dev;
989
990 if (!IS_ERR_OR_NULL(sc5336->pins_default)) {
991 ret = pinctrl_select_state(sc5336->pinctrl,
992 sc5336->pins_default);
993 if (ret < 0)
994 dev_err(dev, "could not set pins\n");
995 }
996 ret = clk_set_rate(sc5336->xvclk, SC5336_XVCLK_FREQ);
997 if (ret < 0)
998 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
999 if (clk_get_rate(sc5336->xvclk) != SC5336_XVCLK_FREQ)
1000 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1001 ret = clk_prepare_enable(sc5336->xvclk);
1002 if (ret < 0) {
1003 dev_err(dev, "Failed to enable xvclk\n");
1004 return ret;
1005 }
1006 if (sc5336->is_thunderboot)
1007 return 0;
1008
1009 if (!IS_ERR(sc5336->reset_gpio))
1010 gpiod_set_value_cansleep(sc5336->reset_gpio, 0);
1011
1012 ret = regulator_bulk_enable(SC5336_NUM_SUPPLIES, sc5336->supplies);
1013 if (ret < 0) {
1014 dev_err(dev, "Failed to enable regulators\n");
1015 goto disable_clk;
1016 }
1017
1018 if (!IS_ERR(sc5336->reset_gpio))
1019 gpiod_set_value_cansleep(sc5336->reset_gpio, 1);
1020
1021 usleep_range(500, 1000);
1022 if (!IS_ERR(sc5336->pwdn_gpio))
1023 gpiod_set_value_cansleep(sc5336->pwdn_gpio, 1);
1024
1025 if (!IS_ERR(sc5336->reset_gpio))
1026 usleep_range(6000, 8000);
1027 else
1028 usleep_range(12000, 16000);
1029
1030 /* 8192 cycles prior to first SCCB transaction */
1031 delay_us = sc5336_cal_delay(8192);
1032 usleep_range(delay_us, delay_us * 2);
1033
1034 return 0;
1035
1036 disable_clk:
1037 clk_disable_unprepare(sc5336->xvclk);
1038
1039 return ret;
1040 }
1041
__sc5336_power_off(struct sc5336 * sc5336)1042 static void __sc5336_power_off(struct sc5336 *sc5336)
1043 {
1044 int ret;
1045 struct device *dev = &sc5336->client->dev;
1046
1047 clk_disable_unprepare(sc5336->xvclk);
1048 if (sc5336->is_thunderboot) {
1049 if (sc5336->is_first_streamoff) {
1050 sc5336->is_thunderboot = false;
1051 sc5336->is_first_streamoff = false;
1052 } else {
1053 return;
1054 }
1055 }
1056
1057 if (!IS_ERR(sc5336->pwdn_gpio))
1058 gpiod_set_value_cansleep(sc5336->pwdn_gpio, 0);
1059 if (!IS_ERR(sc5336->reset_gpio))
1060 gpiod_set_value_cansleep(sc5336->reset_gpio, 0);
1061 if (!IS_ERR_OR_NULL(sc5336->pins_sleep)) {
1062 ret = pinctrl_select_state(sc5336->pinctrl,
1063 sc5336->pins_sleep);
1064 if (ret < 0)
1065 dev_dbg(dev, "could not set pins\n");
1066 }
1067 regulator_bulk_disable(SC5336_NUM_SUPPLIES, sc5336->supplies);
1068 }
1069
sc5336_runtime_resume(struct device * dev)1070 static int sc5336_runtime_resume(struct device *dev)
1071 {
1072 struct i2c_client *client = to_i2c_client(dev);
1073 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1074 struct sc5336 *sc5336 = to_sc5336(sd);
1075
1076 return __sc5336_power_on(sc5336);
1077 }
1078
sc5336_runtime_suspend(struct device * dev)1079 static int sc5336_runtime_suspend(struct device *dev)
1080 {
1081 struct i2c_client *client = to_i2c_client(dev);
1082 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1083 struct sc5336 *sc5336 = to_sc5336(sd);
1084
1085 __sc5336_power_off(sc5336);
1086
1087 return 0;
1088 }
1089
1090 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc5336_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1091 static int sc5336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1092 {
1093 struct sc5336 *sc5336 = to_sc5336(sd);
1094 struct v4l2_mbus_framefmt *try_fmt =
1095 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1096 const struct sc5336_mode *def_mode = &supported_modes[0];
1097
1098 mutex_lock(&sc5336->mutex);
1099 /* Initialize try_fmt */
1100 try_fmt->width = def_mode->width;
1101 try_fmt->height = def_mode->height;
1102 try_fmt->code = def_mode->bus_fmt;
1103 try_fmt->field = V4L2_FIELD_NONE;
1104
1105 mutex_unlock(&sc5336->mutex);
1106 /* No crop or compose */
1107
1108 return 0;
1109 }
1110 #endif
1111
sc5336_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1112 static int sc5336_enum_frame_interval(struct v4l2_subdev *sd,
1113 struct v4l2_subdev_pad_config *cfg,
1114 struct v4l2_subdev_frame_interval_enum *fie)
1115 {
1116 if (fie->index >= ARRAY_SIZE(supported_modes))
1117 return -EINVAL;
1118
1119 fie->code = supported_modes[fie->index].bus_fmt;
1120 fie->width = supported_modes[fie->index].width;
1121 fie->height = supported_modes[fie->index].height;
1122 fie->interval = supported_modes[fie->index].max_fps;
1123 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1124 return 0;
1125 }
1126
1127 static const struct dev_pm_ops sc5336_pm_ops = {
1128 SET_RUNTIME_PM_OPS(sc5336_runtime_suspend,
1129 sc5336_runtime_resume, NULL)
1130 };
1131
1132 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1133 static const struct v4l2_subdev_internal_ops sc5336_internal_ops = {
1134 .open = sc5336_open,
1135 };
1136 #endif
1137
1138 static const struct v4l2_subdev_core_ops sc5336_core_ops = {
1139 .s_power = sc5336_s_power,
1140 .ioctl = sc5336_ioctl,
1141 #ifdef CONFIG_COMPAT
1142 .compat_ioctl32 = sc5336_compat_ioctl32,
1143 #endif
1144 };
1145
1146 static const struct v4l2_subdev_video_ops sc5336_video_ops = {
1147 .s_stream = sc5336_s_stream,
1148 .g_frame_interval = sc5336_g_frame_interval,
1149 };
1150
1151 static const struct v4l2_subdev_pad_ops sc5336_pad_ops = {
1152 .enum_mbus_code = sc5336_enum_mbus_code,
1153 .enum_frame_size = sc5336_enum_frame_sizes,
1154 .enum_frame_interval = sc5336_enum_frame_interval,
1155 .get_fmt = sc5336_get_fmt,
1156 .set_fmt = sc5336_set_fmt,
1157 .get_mbus_config = sc5336_g_mbus_config,
1158 };
1159
1160 static const struct v4l2_subdev_ops sc5336_subdev_ops = {
1161 .core = &sc5336_core_ops,
1162 .video = &sc5336_video_ops,
1163 .pad = &sc5336_pad_ops,
1164 };
1165
sc5336_modify_fps_info(struct sc5336 * sc5336)1166 static void sc5336_modify_fps_info(struct sc5336 *sc5336)
1167 {
1168 const struct sc5336_mode *mode = sc5336->cur_mode;
1169
1170 sc5336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1171 sc5336->cur_vts;
1172 }
1173
sc5336_set_ctrl(struct v4l2_ctrl * ctrl)1174 static int sc5336_set_ctrl(struct v4l2_ctrl *ctrl)
1175 {
1176 struct sc5336 *sc5336 = container_of(ctrl->handler,
1177 struct sc5336, ctrl_handler);
1178 struct i2c_client *client = sc5336->client;
1179 s64 max;
1180 int ret = 0;
1181 u32 val = 0;
1182
1183 /* Propagate change of current control to all related controls */
1184 switch (ctrl->id) {
1185 case V4L2_CID_VBLANK:
1186 /* Update max exposure while meeting expected vblanking */
1187 max = sc5336->cur_mode->height + ctrl->val - 8;
1188 __v4l2_ctrl_modify_range(sc5336->exposure,
1189 sc5336->exposure->minimum, max,
1190 sc5336->exposure->step,
1191 sc5336->exposure->default_value);
1192 break;
1193 }
1194
1195 if (!pm_runtime_get_if_in_use(&client->dev))
1196 return 0;
1197
1198 switch (ctrl->id) {
1199 case V4L2_CID_EXPOSURE:
1200 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1201 if (sc5336->cur_mode->hdr_mode == NO_HDR) {
1202 val = ctrl->val;
1203 /* 4 least significant bits of expsoure are fractional part */
1204 ret = sc5336_write_reg(sc5336->client,
1205 SC5336_REG_EXPOSURE_H,
1206 SC5336_REG_VALUE_08BIT,
1207 SC5336_FETCH_EXP_H(val));
1208 ret |= sc5336_write_reg(sc5336->client,
1209 SC5336_REG_EXPOSURE_M,
1210 SC5336_REG_VALUE_08BIT,
1211 SC5336_FETCH_EXP_M(val));
1212 ret |= sc5336_write_reg(sc5336->client,
1213 SC5336_REG_EXPOSURE_L,
1214 SC5336_REG_VALUE_08BIT,
1215 SC5336_FETCH_EXP_L(val));
1216 }
1217 break;
1218 case V4L2_CID_ANALOGUE_GAIN:
1219 dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1220 if (sc5336->cur_mode->hdr_mode == NO_HDR)
1221 ret = sc5336_set_gain_reg(sc5336, ctrl->val);
1222 break;
1223 case V4L2_CID_VBLANK:
1224 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1225 ret = sc5336_write_reg(sc5336->client,
1226 SC5336_REG_VTS_H,
1227 SC5336_REG_VALUE_08BIT,
1228 (ctrl->val + sc5336->cur_mode->height)
1229 >> 8);
1230 ret |= sc5336_write_reg(sc5336->client,
1231 SC5336_REG_VTS_L,
1232 SC5336_REG_VALUE_08BIT,
1233 (ctrl->val + sc5336->cur_mode->height)
1234 & 0xff);
1235 sc5336->cur_vts = ctrl->val + sc5336->cur_mode->height;
1236 if (sc5336->cur_vts != sc5336->cur_mode->vts_def)
1237 sc5336_modify_fps_info(sc5336);
1238 break;
1239 case V4L2_CID_TEST_PATTERN:
1240 ret = sc5336_enable_test_pattern(sc5336, ctrl->val);
1241 break;
1242 case V4L2_CID_HFLIP:
1243 ret = sc5336_read_reg(sc5336->client, SC5336_FLIP_MIRROR_REG,
1244 SC5336_REG_VALUE_08BIT, &val);
1245 ret |= sc5336_write_reg(sc5336->client, SC5336_FLIP_MIRROR_REG,
1246 SC5336_REG_VALUE_08BIT,
1247 SC5336_FETCH_MIRROR(val, ctrl->val));
1248 break;
1249 case V4L2_CID_VFLIP:
1250 ret = sc5336_read_reg(sc5336->client, SC5336_FLIP_MIRROR_REG,
1251 SC5336_REG_VALUE_08BIT, &val);
1252 ret |= sc5336_write_reg(sc5336->client, SC5336_FLIP_MIRROR_REG,
1253 SC5336_REG_VALUE_08BIT,
1254 SC5336_FETCH_FLIP(val, ctrl->val));
1255 break;
1256 default:
1257 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1258 __func__, ctrl->id, ctrl->val);
1259 break;
1260 }
1261
1262 pm_runtime_put(&client->dev);
1263
1264 return ret;
1265 }
1266
1267 static const struct v4l2_ctrl_ops sc5336_ctrl_ops = {
1268 .s_ctrl = sc5336_set_ctrl,
1269 };
1270
sc5336_initialize_controls(struct sc5336 * sc5336)1271 static int sc5336_initialize_controls(struct sc5336 *sc5336)
1272 {
1273 const struct sc5336_mode *mode;
1274 struct v4l2_ctrl_handler *handler;
1275 struct v4l2_ctrl *ctrl;
1276 s64 exposure_max, vblank_def;
1277 u32 h_blank;
1278 int ret;
1279
1280 handler = &sc5336->ctrl_handler;
1281 mode = sc5336->cur_mode;
1282 ret = v4l2_ctrl_handler_init(handler, 9);
1283 if (ret)
1284 return ret;
1285 handler->lock = &sc5336->mutex;
1286
1287 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1288 0, 0, link_freq_menu_items);
1289 if (ctrl)
1290 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1291
1292 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1293 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT);
1294
1295 h_blank = mode->hts_def - mode->width;
1296 sc5336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1297 h_blank, h_blank, 1, h_blank);
1298 if (sc5336->hblank)
1299 sc5336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1300 vblank_def = mode->vts_def - mode->height;
1301 sc5336->vblank = v4l2_ctrl_new_std(handler, &sc5336_ctrl_ops,
1302 V4L2_CID_VBLANK, vblank_def,
1303 SC5336_VTS_MAX - mode->height,
1304 1, vblank_def);
1305 sc5336->cur_fps = mode->max_fps;
1306 exposure_max = mode->vts_def - 8;
1307 sc5336->exposure = v4l2_ctrl_new_std(handler, &sc5336_ctrl_ops,
1308 V4L2_CID_EXPOSURE, SC5336_EXPOSURE_MIN,
1309 exposure_max, SC5336_EXPOSURE_STEP,
1310 mode->exp_def);
1311 sc5336->anal_gain = v4l2_ctrl_new_std(handler, &sc5336_ctrl_ops,
1312 V4L2_CID_ANALOGUE_GAIN, SC5336_GAIN_MIN,
1313 SC5336_GAIN_MAX, SC5336_GAIN_STEP,
1314 SC5336_GAIN_DEFAULT);
1315 sc5336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1316 &sc5336_ctrl_ops,
1317 V4L2_CID_TEST_PATTERN,
1318 ARRAY_SIZE(sc5336_test_pattern_menu) - 1,
1319 0, 0, sc5336_test_pattern_menu);
1320 v4l2_ctrl_new_std(handler, &sc5336_ctrl_ops,
1321 V4L2_CID_HFLIP, 0, 1, 1, 0);
1322 v4l2_ctrl_new_std(handler, &sc5336_ctrl_ops,
1323 V4L2_CID_VFLIP, 0, 1, 1, 0);
1324 if (handler->error) {
1325 ret = handler->error;
1326 dev_err(&sc5336->client->dev,
1327 "Failed to init controls(%d)\n", ret);
1328 goto err_free_handler;
1329 }
1330
1331 sc5336->subdev.ctrl_handler = handler;
1332
1333 return 0;
1334
1335 err_free_handler:
1336 v4l2_ctrl_handler_free(handler);
1337
1338 return ret;
1339 }
1340
sc5336_check_sensor_id(struct sc5336 * sc5336,struct i2c_client * client)1341 static int sc5336_check_sensor_id(struct sc5336 *sc5336,
1342 struct i2c_client *client)
1343 {
1344 struct device *dev = &sc5336->client->dev;
1345 u32 id = 0;
1346 int ret;
1347
1348 if (sc5336->is_thunderboot) {
1349 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1350 return 0;
1351 }
1352
1353 ret = sc5336_read_reg(client, SC5336_REG_CHIP_ID,
1354 SC5336_REG_VALUE_16BIT, &id);
1355 if (id != CHIP_ID) {
1356 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1357 return -ENODEV;
1358 }
1359
1360 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1361
1362 return 0;
1363 }
1364
sc5336_configure_regulators(struct sc5336 * sc5336)1365 static int sc5336_configure_regulators(struct sc5336 *sc5336)
1366 {
1367 unsigned int i;
1368
1369 for (i = 0; i < SC5336_NUM_SUPPLIES; i++)
1370 sc5336->supplies[i].supply = sc5336_supply_names[i];
1371
1372 return devm_regulator_bulk_get(&sc5336->client->dev,
1373 SC5336_NUM_SUPPLIES,
1374 sc5336->supplies);
1375 }
1376
sc5336_probe(struct i2c_client * client,const struct i2c_device_id * id)1377 static int sc5336_probe(struct i2c_client *client,
1378 const struct i2c_device_id *id)
1379 {
1380 struct device *dev = &client->dev;
1381 struct device_node *node = dev->of_node;
1382 struct sc5336 *sc5336;
1383 struct v4l2_subdev *sd;
1384 char facing[2];
1385 int ret;
1386
1387 dev_info(dev, "driver version: %02x.%02x.%02x",
1388 DRIVER_VERSION >> 16,
1389 (DRIVER_VERSION & 0xff00) >> 8,
1390 DRIVER_VERSION & 0x00ff);
1391
1392 sc5336 = devm_kzalloc(dev, sizeof(*sc5336), GFP_KERNEL);
1393 if (!sc5336)
1394 return -ENOMEM;
1395
1396 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1397 &sc5336->module_index);
1398 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1399 &sc5336->module_facing);
1400 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1401 &sc5336->module_name);
1402 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1403 &sc5336->len_name);
1404 if (ret) {
1405 dev_err(dev, "could not get module information!\n");
1406 return -EINVAL;
1407 }
1408
1409 sc5336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1410 sc5336->client = client;
1411 sc5336->cur_mode = &supported_modes[0];
1412
1413 sc5336->xvclk = devm_clk_get(dev, "xvclk");
1414 if (IS_ERR(sc5336->xvclk)) {
1415 dev_err(dev, "Failed to get xvclk\n");
1416 return -EINVAL;
1417 }
1418
1419 if (sc5336->is_thunderboot) {
1420 sc5336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1421 if (IS_ERR(sc5336->reset_gpio))
1422 dev_warn(dev, "Failed to get reset-gpios\n");
1423
1424 sc5336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1425 if (IS_ERR(sc5336->pwdn_gpio))
1426 dev_warn(dev, "Failed to get pwdn-gpios\n");
1427 } else {
1428 sc5336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1429 if (IS_ERR(sc5336->reset_gpio))
1430 dev_warn(dev, "Failed to get reset-gpios\n");
1431
1432 sc5336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1433 if (IS_ERR(sc5336->pwdn_gpio))
1434 dev_warn(dev, "Failed to get pwdn-gpios\n");
1435 }
1436 sc5336->pinctrl = devm_pinctrl_get(dev);
1437 if (!IS_ERR(sc5336->pinctrl)) {
1438 sc5336->pins_default =
1439 pinctrl_lookup_state(sc5336->pinctrl,
1440 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1441 if (IS_ERR(sc5336->pins_default))
1442 dev_err(dev, "could not get default pinstate\n");
1443
1444 sc5336->pins_sleep =
1445 pinctrl_lookup_state(sc5336->pinctrl,
1446 OF_CAMERA_PINCTRL_STATE_SLEEP);
1447 if (IS_ERR(sc5336->pins_sleep))
1448 dev_err(dev, "could not get sleep pinstate\n");
1449 } else {
1450 dev_err(dev, "no pinctrl\n");
1451 }
1452
1453 ret = sc5336_configure_regulators(sc5336);
1454 if (ret) {
1455 dev_err(dev, "Failed to get power regulators\n");
1456 return ret;
1457 }
1458
1459 mutex_init(&sc5336->mutex);
1460
1461 sd = &sc5336->subdev;
1462 v4l2_i2c_subdev_init(sd, client, &sc5336_subdev_ops);
1463 ret = sc5336_initialize_controls(sc5336);
1464 if (ret)
1465 goto err_destroy_mutex;
1466
1467 ret = __sc5336_power_on(sc5336);
1468 if (ret)
1469 goto err_free_handler;
1470
1471 ret = sc5336_check_sensor_id(sc5336, client);
1472 if (ret)
1473 goto err_power_off;
1474
1475 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1476 sd->internal_ops = &sc5336_internal_ops;
1477 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1478 V4L2_SUBDEV_FL_HAS_EVENTS;
1479 #endif
1480 #if defined(CONFIG_MEDIA_CONTROLLER)
1481 sc5336->pad.flags = MEDIA_PAD_FL_SOURCE;
1482 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1483 ret = media_entity_pads_init(&sd->entity, 1, &sc5336->pad);
1484 if (ret < 0)
1485 goto err_power_off;
1486 #endif
1487
1488 memset(facing, 0, sizeof(facing));
1489 if (strcmp(sc5336->module_facing, "back") == 0)
1490 facing[0] = 'b';
1491 else
1492 facing[0] = 'f';
1493
1494 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1495 sc5336->module_index, facing,
1496 SC5336_NAME, dev_name(sd->dev));
1497 ret = v4l2_async_register_subdev_sensor_common(sd);
1498 if (ret) {
1499 dev_err(dev, "v4l2 async register subdev failed\n");
1500 goto err_clean_entity;
1501 }
1502
1503 pm_runtime_set_active(dev);
1504 pm_runtime_enable(dev);
1505 if (sc5336->is_thunderboot)
1506 pm_runtime_get_sync(dev);
1507 else
1508 pm_runtime_idle(dev);
1509
1510 return 0;
1511
1512 err_clean_entity:
1513 #if defined(CONFIG_MEDIA_CONTROLLER)
1514 media_entity_cleanup(&sd->entity);
1515 #endif
1516 err_power_off:
1517 __sc5336_power_off(sc5336);
1518 err_free_handler:
1519 v4l2_ctrl_handler_free(&sc5336->ctrl_handler);
1520 err_destroy_mutex:
1521 mutex_destroy(&sc5336->mutex);
1522
1523 return ret;
1524 }
1525
sc5336_remove(struct i2c_client * client)1526 static int sc5336_remove(struct i2c_client *client)
1527 {
1528 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1529 struct sc5336 *sc5336 = to_sc5336(sd);
1530
1531 v4l2_async_unregister_subdev(sd);
1532 #if defined(CONFIG_MEDIA_CONTROLLER)
1533 media_entity_cleanup(&sd->entity);
1534 #endif
1535 v4l2_ctrl_handler_free(&sc5336->ctrl_handler);
1536 mutex_destroy(&sc5336->mutex);
1537
1538 pm_runtime_disable(&client->dev);
1539 if (!pm_runtime_status_suspended(&client->dev))
1540 __sc5336_power_off(sc5336);
1541 pm_runtime_set_suspended(&client->dev);
1542
1543 return 0;
1544 }
1545
1546 #if IS_ENABLED(CONFIG_OF)
1547 static const struct of_device_id sc5336_of_match[] = {
1548 { .compatible = "smartsens,sc5336" },
1549 {},
1550 };
1551 MODULE_DEVICE_TABLE(of, sc5336_of_match);
1552 #endif
1553
1554 static const struct i2c_device_id sc5336_match_id[] = {
1555 { "smartsens,sc5336", 0 },
1556 { },
1557 };
1558
1559 static struct i2c_driver sc5336_i2c_driver = {
1560 .driver = {
1561 .name = SC5336_NAME,
1562 .pm = &sc5336_pm_ops,
1563 .of_match_table = of_match_ptr(sc5336_of_match),
1564 },
1565 .probe = &sc5336_probe,
1566 .remove = &sc5336_remove,
1567 .id_table = sc5336_match_id,
1568 };
1569
sensor_mod_init(void)1570 static int __init sensor_mod_init(void)
1571 {
1572 return i2c_add_driver(&sc5336_i2c_driver);
1573 }
1574
sensor_mod_exit(void)1575 static void __exit sensor_mod_exit(void)
1576 {
1577 i2c_del_driver(&sc5336_i2c_driver);
1578 }
1579
1580 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1581 subsys_initcall(sensor_mod_init);
1582 #else
1583 device_initcall_sync(sensor_mod_init);
1584 #endif
1585 module_exit(sensor_mod_exit);
1586
1587 MODULE_DESCRIPTION("smartsens sc5336 sensor driver");
1588 MODULE_LICENSE("GPL");
1589