1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sc530ai driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun * V0.0X01.0X01 fix set vflip/hflip failed bug.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun //#define DEBUG
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun #include <linux/of_graph.h>
21*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
22*4882a593Smuzhiyun #include <linux/sysfs.h>
23*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun #include <linux/version.h>
26*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
27*4882a593Smuzhiyun #include <linux/rk-preisp.h>
28*4882a593Smuzhiyun #include <media/media-entity.h>
29*4882a593Smuzhiyun #include <media/v4l2-common.h>
30*4882a593Smuzhiyun #include <media/v4l2-async.h>
31*4882a593Smuzhiyun #include <media/v4l2-device.h>
32*4882a593Smuzhiyun #include <media/v4l2-event.h>
33*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
34*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
35*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
36*4882a593Smuzhiyun #include <media/v4l2-image-sizes.h>
37*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
38*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
39*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
40*4882a593Smuzhiyun #include <stdarg.h>
41*4882a593Smuzhiyun #include <linux/linkage.h>
42*4882a593Smuzhiyun #include <linux/types.h>
43*4882a593Smuzhiyun #include <linux/printk.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
46*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
49*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define SC530AI_LINK_FREQ_396M 198000000 // 396Mbps
53*4882a593Smuzhiyun #define SC530AI_LINK_FREQ_792M 396000000 // 792Mbps
54*4882a593Smuzhiyun #define SC530AI_LINK_FREQ_792M_2LANE 396000000 // 792Mbps
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define SC530AI_LINEAR_PIXEL_RATES (SC530AI_LINK_FREQ_396M / 10 * 2 * 4)
57*4882a593Smuzhiyun #define SC530AI_HDR_PIXEL_RATES (SC530AI_LINK_FREQ_792M / 10 * 2 * 4)
58*4882a593Smuzhiyun #define SC530AI_MAX_PIXEL_RATE (SC530AI_LINK_FREQ_792M / 10 * 2 * 4)
59*4882a593Smuzhiyun #define SC530AI_LINEAR_PIXEL_RATES_2LAN (SC530AI_LINK_FREQ_792M / 10 * 2 * 2)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define SC530AI_XVCLK_FREQ 27000000
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define SC530AI_CHIP_ID 0x8e39
64*4882a593Smuzhiyun #define SC530AI_REG_CHIP_ID 0x3107
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define SC530AI_REG_CTRL_MODE 0x0100
67*4882a593Smuzhiyun #define SC530AI_MODE_SW_STANDBY 0x0
68*4882a593Smuzhiyun #define SC530AI_MODE_STREAMING BIT(0)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define SC530AI_REG_EXPOSURE_H 0x3e00
71*4882a593Smuzhiyun #define SC530AI_REG_EXPOSURE_M 0x3e01
72*4882a593Smuzhiyun #define SC530AI_REG_EXPOSURE_L 0x3e02
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define SC530AI_EXPOSURE_MIN 2
75*4882a593Smuzhiyun #define SC530AI_EXPOSURE_STEP 1
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define SC530AI_REG_DIG_GAIN 0x3e06
78*4882a593Smuzhiyun #define SC530AI_REG_DIG_FINE_GAIN 0x3e07
79*4882a593Smuzhiyun #define SC530AI_REG_ANA_GAIN 0x3e09
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define SC530AI_GAIN_MIN 0x20
82*4882a593Smuzhiyun #define SC530AI_GAIN_MAX (32 * 326)
83*4882a593Smuzhiyun #define SC530AI_GAIN_STEP 1
84*4882a593Smuzhiyun #define SC530AI_GAIN_DEFAULT 0x20
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define SC530AI_REG_VTS_H 0x320e
87*4882a593Smuzhiyun #define SC530AI_REG_VTS_L 0x320f
88*4882a593Smuzhiyun #define SC530AI_VTS_MAX 0x7fff
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define SC530AI_SOFTWARE_RESET_REG 0x0103
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun // short frame exposure
93*4882a593Smuzhiyun #define SC530AI_REG_SHORT_EXPOSURE_H 0x3e22
94*4882a593Smuzhiyun #define SC530AI_REG_SHORT_EXPOSURE_M 0x3e04
95*4882a593Smuzhiyun #define SC530AI_REG_SHORT_EXPOSURE_L 0x3e05
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define SC530AI_REG_MAX_SHORT_EXP_H 0x3e23
98*4882a593Smuzhiyun #define SC530AI_REG_MAX_SHORT_EXP_L 0x3e24
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define SC530AI_HDR_EXPOSURE_MIN 5 // Half line exposure time
101*4882a593Smuzhiyun #define SC530AI_HDR_EXPOSURE_STEP 4 // Half line exposure time
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define SC530AI_MAX_SHORT_EXPOSURE 608
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun // short frame gain
106*4882a593Smuzhiyun #define SC530AI_REG_SDIG_GAIN 0x3e10
107*4882a593Smuzhiyun #define SC530AI_REG_SDIG_FINE_GAIN 0x3e11
108*4882a593Smuzhiyun #define SC530AI_REG_SANA_GAIN 0x3e13
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun //group hold
111*4882a593Smuzhiyun #define SC530AI_GROUP_UPDATE_ADDRESS 0x3812
112*4882a593Smuzhiyun #define SC530AI_GROUP_UPDATE_START_DATA 0x00
113*4882a593Smuzhiyun #define SC530AI_GROUP_UPDATE_LAUNCH 0x30
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define SC530AI_FLIP_MIRROR_REG 0x3221
116*4882a593Smuzhiyun #define SC530AI_FLIP_MASK 0x60
117*4882a593Smuzhiyun #define SC530AI_MIRROR_MASK 0x06
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define REG_NULL 0xFFFF
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define SC530AI_REG_VALUE_08BIT 1
122*4882a593Smuzhiyun #define SC530AI_REG_VALUE_16BIT 2
123*4882a593Smuzhiyun #define SC530AI_REG_VALUE_24BIT 3
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
126*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
127*4882a593Smuzhiyun #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define SC530AI_NAME "sc530ai"
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define SC530AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
132*4882a593Smuzhiyun #define SC530AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
133*4882a593Smuzhiyun #define SC530AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const char * const sc530ai_supply_names[] = {
136*4882a593Smuzhiyun "avdd", /* Analog power */
137*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
138*4882a593Smuzhiyun "dvdd", /* Digital core power */
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define sc530ai_NUM_SUPPLIES ARRAY_SIZE(sc530ai_supply_names)
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun struct regval {
144*4882a593Smuzhiyun u16 addr;
145*4882a593Smuzhiyun u8 val;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun struct sc530ai_mode {
149*4882a593Smuzhiyun u32 bus_fmt;
150*4882a593Smuzhiyun u32 width;
151*4882a593Smuzhiyun u32 height;
152*4882a593Smuzhiyun struct v4l2_fract max_fps;
153*4882a593Smuzhiyun u32 hts_def;
154*4882a593Smuzhiyun u32 vts_def;
155*4882a593Smuzhiyun u32 exp_def;
156*4882a593Smuzhiyun u32 mipi_freq_idx;
157*4882a593Smuzhiyun u32 bpp;
158*4882a593Smuzhiyun const struct regval *reg_list;
159*4882a593Smuzhiyun u32 hdr_mode;
160*4882a593Smuzhiyun u32 vc[PAD_MAX];
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct sc530ai {
164*4882a593Smuzhiyun struct i2c_client *client;
165*4882a593Smuzhiyun struct clk *xvclk;
166*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
167*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
168*4882a593Smuzhiyun struct regulator_bulk_data supplies[sc530ai_NUM_SUPPLIES];
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun struct pinctrl *pinctrl;
171*4882a593Smuzhiyun struct pinctrl_state *pins_default;
172*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
173*4882a593Smuzhiyun struct v4l2_fract cur_fps;
174*4882a593Smuzhiyun u32 cur_vts;
175*4882a593Smuzhiyun struct v4l2_subdev subdev;
176*4882a593Smuzhiyun struct media_pad pad;
177*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
178*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
179*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
180*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
181*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
182*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
183*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
184*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
185*4882a593Smuzhiyun struct mutex mutex;
186*4882a593Smuzhiyun bool streaming;
187*4882a593Smuzhiyun bool power_on;
188*4882a593Smuzhiyun const struct sc530ai_mode *support_modes;
189*4882a593Smuzhiyun const struct sc530ai_mode *cur_mode;
190*4882a593Smuzhiyun u32 support_modes_num;
191*4882a593Smuzhiyun unsigned int lane_num;
192*4882a593Smuzhiyun u32 module_index;
193*4882a593Smuzhiyun const char *module_facing;
194*4882a593Smuzhiyun const char *module_name;
195*4882a593Smuzhiyun const char *len_name;
196*4882a593Smuzhiyun bool has_init_exp;
197*4882a593Smuzhiyun struct preisp_hdrae_exp_s init_hdrae_exp;
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun #define to_sc530ai(sd) container_of(sd, struct sc530ai, subdev)
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun * Xclk 24Mhz
204*4882a593Smuzhiyun * max_framerate 30fps
205*4882a593Smuzhiyun * mipi_datarate per lane 1008Mbps, 4lane
206*4882a593Smuzhiyun */
207*4882a593Smuzhiyun static const struct regval sc530ai_linear_10_30fps_2880x1620_4lane_regs[] = {
208*4882a593Smuzhiyun {0x0103, 0x01},
209*4882a593Smuzhiyun {0x0100, 0x00},
210*4882a593Smuzhiyun {0x36e9, 0x80},
211*4882a593Smuzhiyun {0x37f9, 0x80},
212*4882a593Smuzhiyun {0x301f, 0x01},
213*4882a593Smuzhiyun {0x3250, 0x40},
214*4882a593Smuzhiyun {0x3251, 0x98},
215*4882a593Smuzhiyun {0x3253, 0x0c},
216*4882a593Smuzhiyun {0x325f, 0x20},
217*4882a593Smuzhiyun {0x3301, 0x08},
218*4882a593Smuzhiyun {0x3304, 0x50},
219*4882a593Smuzhiyun {0x3306, 0x78},
220*4882a593Smuzhiyun {0x3308, 0x14},
221*4882a593Smuzhiyun {0x3309, 0x70},
222*4882a593Smuzhiyun {0x330a, 0x00},
223*4882a593Smuzhiyun {0x330b, 0xd8},
224*4882a593Smuzhiyun {0x330d, 0x10},
225*4882a593Smuzhiyun {0x331e, 0x41},
226*4882a593Smuzhiyun {0x331f, 0x61},
227*4882a593Smuzhiyun {0x3333, 0x10},
228*4882a593Smuzhiyun {0x335d, 0x60},
229*4882a593Smuzhiyun {0x335e, 0x06},
230*4882a593Smuzhiyun {0x335f, 0x08},
231*4882a593Smuzhiyun {0x3364, 0x56},
232*4882a593Smuzhiyun {0x3366, 0x01},
233*4882a593Smuzhiyun {0x337c, 0x02},
234*4882a593Smuzhiyun {0x337d, 0x0a},
235*4882a593Smuzhiyun {0x3390, 0x01},
236*4882a593Smuzhiyun {0x3391, 0x03},
237*4882a593Smuzhiyun {0x3392, 0x07},
238*4882a593Smuzhiyun {0x3393, 0x08},
239*4882a593Smuzhiyun {0x3394, 0x08},
240*4882a593Smuzhiyun {0x3395, 0x08},
241*4882a593Smuzhiyun {0x3396, 0x40},
242*4882a593Smuzhiyun {0x3397, 0x48},
243*4882a593Smuzhiyun {0x3398, 0x4b},
244*4882a593Smuzhiyun {0x3399, 0x08},
245*4882a593Smuzhiyun {0x339a, 0x08},
246*4882a593Smuzhiyun {0x339b, 0x08},
247*4882a593Smuzhiyun {0x339c, 0x1d},
248*4882a593Smuzhiyun {0x33a2, 0x04},
249*4882a593Smuzhiyun {0x33ae, 0x30},
250*4882a593Smuzhiyun {0x33af, 0x50},
251*4882a593Smuzhiyun {0x33b1, 0x80},
252*4882a593Smuzhiyun {0x33b2, 0x48},
253*4882a593Smuzhiyun {0x33b3, 0x30},
254*4882a593Smuzhiyun {0x349f, 0x02},
255*4882a593Smuzhiyun {0x34a6, 0x48},
256*4882a593Smuzhiyun {0x34a7, 0x49},
257*4882a593Smuzhiyun {0x34a8, 0x40},
258*4882a593Smuzhiyun {0x34a9, 0x30},
259*4882a593Smuzhiyun {0x34f8, 0x4b},
260*4882a593Smuzhiyun {0x34f9, 0x30},
261*4882a593Smuzhiyun {0x3632, 0x48},
262*4882a593Smuzhiyun {0x3633, 0x32},
263*4882a593Smuzhiyun {0x3637, 0x29},
264*4882a593Smuzhiyun {0x3638, 0xc1},
265*4882a593Smuzhiyun {0x363b, 0x20},
266*4882a593Smuzhiyun {0x363d, 0x02},
267*4882a593Smuzhiyun {0x3670, 0x09},
268*4882a593Smuzhiyun {0x3674, 0x8b},
269*4882a593Smuzhiyun {0x3675, 0xc6},
270*4882a593Smuzhiyun {0x3676, 0x8b},
271*4882a593Smuzhiyun {0x367c, 0x40},
272*4882a593Smuzhiyun {0x367d, 0x48},
273*4882a593Smuzhiyun {0x3690, 0x32},
274*4882a593Smuzhiyun {0x3691, 0x43},
275*4882a593Smuzhiyun {0x3692, 0x33},
276*4882a593Smuzhiyun {0x3693, 0x40},
277*4882a593Smuzhiyun {0x3694, 0x4b},
278*4882a593Smuzhiyun {0x3698, 0x85},
279*4882a593Smuzhiyun {0x3699, 0x8f},
280*4882a593Smuzhiyun {0x369a, 0xa0},
281*4882a593Smuzhiyun {0x369b, 0xc3},
282*4882a593Smuzhiyun {0x36a2, 0x49},
283*4882a593Smuzhiyun {0x36a3, 0x4b},
284*4882a593Smuzhiyun {0x36a4, 0x4f},
285*4882a593Smuzhiyun {0x36d0, 0x01},
286*4882a593Smuzhiyun {0x36ec, 0x13},
287*4882a593Smuzhiyun {0x370f, 0x01},
288*4882a593Smuzhiyun {0x3722, 0x00},
289*4882a593Smuzhiyun {0x3728, 0x10},
290*4882a593Smuzhiyun {0x37b0, 0x03},
291*4882a593Smuzhiyun {0x37b1, 0x03},
292*4882a593Smuzhiyun {0x37b2, 0x83},
293*4882a593Smuzhiyun {0x37b3, 0x48},
294*4882a593Smuzhiyun {0x37b4, 0x49},
295*4882a593Smuzhiyun {0x37fb, 0x25},
296*4882a593Smuzhiyun {0x37fc, 0x01},
297*4882a593Smuzhiyun {0x3901, 0x00},
298*4882a593Smuzhiyun {0x3902, 0xc5},
299*4882a593Smuzhiyun {0x3904, 0x08},
300*4882a593Smuzhiyun {0x3905, 0x8c},
301*4882a593Smuzhiyun {0x3909, 0x00},
302*4882a593Smuzhiyun {0x391d, 0x04},
303*4882a593Smuzhiyun {0x391f, 0x44},
304*4882a593Smuzhiyun {0x3926, 0x21},
305*4882a593Smuzhiyun {0x3929, 0x18},
306*4882a593Smuzhiyun {0x3933, 0x81},
307*4882a593Smuzhiyun {0x3934, 0x81},
308*4882a593Smuzhiyun {0x3937, 0x69},
309*4882a593Smuzhiyun {0x3939, 0x00},
310*4882a593Smuzhiyun {0x393a, 0x00},
311*4882a593Smuzhiyun {0x39dc, 0x02},
312*4882a593Smuzhiyun {0x3e01, 0xcd},
313*4882a593Smuzhiyun {0x3e02, 0xa0},
314*4882a593Smuzhiyun {0x440e, 0x02},
315*4882a593Smuzhiyun {0x4509, 0x20},
316*4882a593Smuzhiyun {0x4800, 0x04},
317*4882a593Smuzhiyun {0x4837, 0x28},
318*4882a593Smuzhiyun {0x5010, 0x10},
319*4882a593Smuzhiyun {0x5799, 0x06},
320*4882a593Smuzhiyun {0x57ad, 0x00},
321*4882a593Smuzhiyun {0x5ae0, 0xfe},
322*4882a593Smuzhiyun {0x5ae1, 0x40},
323*4882a593Smuzhiyun {0x5ae2, 0x30},
324*4882a593Smuzhiyun {0x5ae3, 0x2a},
325*4882a593Smuzhiyun {0x5ae4, 0x24},
326*4882a593Smuzhiyun {0x5ae5, 0x30},
327*4882a593Smuzhiyun {0x5ae6, 0x2a},
328*4882a593Smuzhiyun {0x5ae7, 0x24},
329*4882a593Smuzhiyun {0x5ae8, 0x3c},
330*4882a593Smuzhiyun {0x5ae9, 0x30},
331*4882a593Smuzhiyun {0x5aea, 0x28},
332*4882a593Smuzhiyun {0x5aeb, 0x3c},
333*4882a593Smuzhiyun {0x5aec, 0x30},
334*4882a593Smuzhiyun {0x5aed, 0x28},
335*4882a593Smuzhiyun {0x5aee, 0xfe},
336*4882a593Smuzhiyun {0x5aef, 0x40},
337*4882a593Smuzhiyun {0x5af4, 0x30},
338*4882a593Smuzhiyun {0x5af5, 0x2a},
339*4882a593Smuzhiyun {0x5af6, 0x24},
340*4882a593Smuzhiyun {0x5af7, 0x30},
341*4882a593Smuzhiyun {0x5af8, 0x2a},
342*4882a593Smuzhiyun {0x5af9, 0x24},
343*4882a593Smuzhiyun {0x5afa, 0x3c},
344*4882a593Smuzhiyun {0x5afb, 0x30},
345*4882a593Smuzhiyun {0x5afc, 0x28},
346*4882a593Smuzhiyun {0x5afd, 0x3c},
347*4882a593Smuzhiyun {0x5afe, 0x30},
348*4882a593Smuzhiyun {0x5aff, 0x28},
349*4882a593Smuzhiyun {0x36e9, 0x44},
350*4882a593Smuzhiyun {0x37f9, 0x34},
351*4882a593Smuzhiyun //{0x0100, 0x01},
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun {REG_NULL, 0x00},
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun static const struct regval sc530ai_hdr_10_30fps_2880x1620_4lane_regs[] = {
357*4882a593Smuzhiyun {0x0103, 0x01},
358*4882a593Smuzhiyun {0x0100, 0x00},
359*4882a593Smuzhiyun {0x36e9, 0x80},
360*4882a593Smuzhiyun {0x37f9, 0x80},
361*4882a593Smuzhiyun {0x301f, 0x03},
362*4882a593Smuzhiyun {0x320e, 0x0c},
363*4882a593Smuzhiyun {0x320f, 0xe4},
364*4882a593Smuzhiyun {0x3250, 0xff},
365*4882a593Smuzhiyun {0x3251, 0x98},
366*4882a593Smuzhiyun {0x3253, 0x0c},
367*4882a593Smuzhiyun {0x325f, 0x20},
368*4882a593Smuzhiyun {0x3281, 0x01},
369*4882a593Smuzhiyun {0x3301, 0x08},
370*4882a593Smuzhiyun {0x3304, 0x58},
371*4882a593Smuzhiyun {0x3306, 0xa0},
372*4882a593Smuzhiyun {0x3308, 0x14},
373*4882a593Smuzhiyun {0x3309, 0x50},
374*4882a593Smuzhiyun {0x330a, 0x01},
375*4882a593Smuzhiyun {0x330b, 0x10},
376*4882a593Smuzhiyun {0x330d, 0x10},
377*4882a593Smuzhiyun {0x331e, 0x49},
378*4882a593Smuzhiyun {0x331f, 0x41},
379*4882a593Smuzhiyun {0x3333, 0x10},
380*4882a593Smuzhiyun {0x335d, 0x60},
381*4882a593Smuzhiyun {0x335e, 0x06},
382*4882a593Smuzhiyun {0x335f, 0x08},
383*4882a593Smuzhiyun {0x3364, 0x56},
384*4882a593Smuzhiyun {0x3366, 0x01},
385*4882a593Smuzhiyun {0x337c, 0x02},
386*4882a593Smuzhiyun {0x337d, 0x0a},
387*4882a593Smuzhiyun {0x3390, 0x01},
388*4882a593Smuzhiyun {0x3391, 0x03},
389*4882a593Smuzhiyun {0x3392, 0x07},
390*4882a593Smuzhiyun {0x3393, 0x08},
391*4882a593Smuzhiyun {0x3394, 0x08},
392*4882a593Smuzhiyun {0x3395, 0x08},
393*4882a593Smuzhiyun {0x3396, 0x48},
394*4882a593Smuzhiyun {0x3397, 0x4b},
395*4882a593Smuzhiyun {0x3398, 0x4f},
396*4882a593Smuzhiyun {0x3399, 0x0a},
397*4882a593Smuzhiyun {0x339a, 0x0a},
398*4882a593Smuzhiyun {0x339b, 0x10},
399*4882a593Smuzhiyun {0x339c, 0x22},
400*4882a593Smuzhiyun {0x33a2, 0x04},
401*4882a593Smuzhiyun {0x33ad, 0x24},
402*4882a593Smuzhiyun {0x33ae, 0x38},
403*4882a593Smuzhiyun {0x33af, 0x38},
404*4882a593Smuzhiyun {0x33b1, 0x80},
405*4882a593Smuzhiyun {0x33b2, 0x48},
406*4882a593Smuzhiyun {0x33b3, 0x30},
407*4882a593Smuzhiyun {0x349f, 0x02},
408*4882a593Smuzhiyun {0x34a6, 0x48},
409*4882a593Smuzhiyun {0x34a7, 0x4b},
410*4882a593Smuzhiyun {0x34a8, 0x20},
411*4882a593Smuzhiyun {0x34a9, 0x18},
412*4882a593Smuzhiyun {0x34f8, 0x5f},
413*4882a593Smuzhiyun {0x34f9, 0x04},
414*4882a593Smuzhiyun {0x3632, 0x48},
415*4882a593Smuzhiyun {0x3633, 0x32},
416*4882a593Smuzhiyun {0x3637, 0x29},
417*4882a593Smuzhiyun {0x3638, 0xc1},
418*4882a593Smuzhiyun {0x363b, 0x20},
419*4882a593Smuzhiyun {0x363d, 0x02},
420*4882a593Smuzhiyun {0x3670, 0x09},
421*4882a593Smuzhiyun {0x3674, 0x88},
422*4882a593Smuzhiyun {0x3675, 0x88},
423*4882a593Smuzhiyun {0x3676, 0x88},
424*4882a593Smuzhiyun {0x367c, 0x40},
425*4882a593Smuzhiyun {0x367d, 0x48},
426*4882a593Smuzhiyun {0x3690, 0x33},
427*4882a593Smuzhiyun {0x3691, 0x34},
428*4882a593Smuzhiyun {0x3692, 0x55},
429*4882a593Smuzhiyun {0x3693, 0x4b},
430*4882a593Smuzhiyun {0x3694, 0x4f},
431*4882a593Smuzhiyun {0x3698, 0x85},
432*4882a593Smuzhiyun {0x3699, 0x8f},
433*4882a593Smuzhiyun {0x369a, 0xa0},
434*4882a593Smuzhiyun {0x369b, 0xc3},
435*4882a593Smuzhiyun {0x36a2, 0x49},
436*4882a593Smuzhiyun {0x36a3, 0x4b},
437*4882a593Smuzhiyun {0x36a4, 0x4f},
438*4882a593Smuzhiyun {0x36d0, 0x01},
439*4882a593Smuzhiyun {0x370f, 0x01},
440*4882a593Smuzhiyun {0x3722, 0x00},
441*4882a593Smuzhiyun {0x3728, 0x10},
442*4882a593Smuzhiyun {0x37b0, 0x03},
443*4882a593Smuzhiyun {0x37b1, 0x03},
444*4882a593Smuzhiyun {0x37b2, 0x83},
445*4882a593Smuzhiyun {0x37b3, 0x48},
446*4882a593Smuzhiyun {0x37b4, 0x4f},
447*4882a593Smuzhiyun {0x3901, 0x00},
448*4882a593Smuzhiyun {0x3902, 0xc5},
449*4882a593Smuzhiyun {0x3904, 0x08},
450*4882a593Smuzhiyun {0x3905, 0x8d},
451*4882a593Smuzhiyun {0x3909, 0x00},
452*4882a593Smuzhiyun {0x391d, 0x04},
453*4882a593Smuzhiyun {0x3926, 0x21},
454*4882a593Smuzhiyun {0x3929, 0x18},
455*4882a593Smuzhiyun {0x3933, 0x83},
456*4882a593Smuzhiyun {0x3934, 0x02},
457*4882a593Smuzhiyun {0x3937, 0x71},
458*4882a593Smuzhiyun {0x3939, 0x00},
459*4882a593Smuzhiyun {0x393a, 0x00},
460*4882a593Smuzhiyun {0x39dc, 0x02},
461*4882a593Smuzhiyun {0x3c0f, 0x00},
462*4882a593Smuzhiyun {0x3e00, 0x01},
463*4882a593Smuzhiyun {0x3e01, 0x82},
464*4882a593Smuzhiyun {0x3e02, 0x00},
465*4882a593Smuzhiyun {0x3e04, 0x18},
466*4882a593Smuzhiyun {0x3e05, 0x20},
467*4882a593Smuzhiyun {0x3e23, 0x00},
468*4882a593Smuzhiyun {0x3e24, 0xc8},
469*4882a593Smuzhiyun {0x440e, 0x02},
470*4882a593Smuzhiyun {0x4509, 0x20},
471*4882a593Smuzhiyun {0x4800, 0x04},
472*4882a593Smuzhiyun {0x4816, 0x11},
473*4882a593Smuzhiyun {0x5010, 0x10},
474*4882a593Smuzhiyun {0x5799, 0x06},
475*4882a593Smuzhiyun {0x57ad, 0x00},
476*4882a593Smuzhiyun {0x5ae0, 0xfe},
477*4882a593Smuzhiyun {0x5ae1, 0x40},
478*4882a593Smuzhiyun {0x5ae2, 0x30},
479*4882a593Smuzhiyun {0x5ae3, 0x2a},
480*4882a593Smuzhiyun {0x5ae4, 0x24},
481*4882a593Smuzhiyun {0x5ae5, 0x30},
482*4882a593Smuzhiyun {0x5ae6, 0x2a},
483*4882a593Smuzhiyun {0x5ae7, 0x24},
484*4882a593Smuzhiyun {0x5ae8, 0x3c},
485*4882a593Smuzhiyun {0x5ae9, 0x30},
486*4882a593Smuzhiyun {0x5aea, 0x28},
487*4882a593Smuzhiyun {0x5aeb, 0x3c},
488*4882a593Smuzhiyun {0x5aec, 0x30},
489*4882a593Smuzhiyun {0x5aed, 0x28},
490*4882a593Smuzhiyun {0x5aee, 0xfe},
491*4882a593Smuzhiyun {0x5aef, 0x40},
492*4882a593Smuzhiyun {0x5af4, 0x30},
493*4882a593Smuzhiyun {0x5af5, 0x2a},
494*4882a593Smuzhiyun {0x5af6, 0x24},
495*4882a593Smuzhiyun {0x5af7, 0x30},
496*4882a593Smuzhiyun {0x5af8, 0x2a},
497*4882a593Smuzhiyun {0x5af9, 0x24},
498*4882a593Smuzhiyun {0x5afa, 0x3c},
499*4882a593Smuzhiyun {0x5afb, 0x30},
500*4882a593Smuzhiyun {0x5afc, 0x28},
501*4882a593Smuzhiyun {0x5afd, 0x3c},
502*4882a593Smuzhiyun {0x5afe, 0x30},
503*4882a593Smuzhiyun {0x5aff, 0x28},
504*4882a593Smuzhiyun {0x36e9, 0x44},
505*4882a593Smuzhiyun {0x37f9, 0x44},
506*4882a593Smuzhiyun //{0x0100, 0x01},
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun {REG_NULL, 0x00},
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /*
512*4882a593Smuzhiyun * Xclk 24Mhz
513*4882a593Smuzhiyun * max_framerate 30fps
514*4882a593Smuzhiyun * mipi_datarate per lane 1008Mbps, 2lane
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun static const struct regval sc530ai_10_30fps_2880x1620_2lane_regs[] = {
517*4882a593Smuzhiyun {0x0103, 0x01},
518*4882a593Smuzhiyun {0x0100, 0x00},
519*4882a593Smuzhiyun {0x36e9, 0x80},
520*4882a593Smuzhiyun {0x37f9, 0x80},
521*4882a593Smuzhiyun {0x3018, 0x32},
522*4882a593Smuzhiyun {0x3019, 0x0c},
523*4882a593Smuzhiyun {0x301f, 0x18},
524*4882a593Smuzhiyun {0x3250, 0x40},
525*4882a593Smuzhiyun {0x3251, 0x98},
526*4882a593Smuzhiyun {0x3253, 0x0c},
527*4882a593Smuzhiyun {0x325f, 0x20},
528*4882a593Smuzhiyun {0x3301, 0x08},
529*4882a593Smuzhiyun {0x3304, 0x50},
530*4882a593Smuzhiyun {0x3306, 0x78},
531*4882a593Smuzhiyun {0x3308, 0x14},
532*4882a593Smuzhiyun {0x3309, 0x70},
533*4882a593Smuzhiyun {0x330a, 0x00},
534*4882a593Smuzhiyun {0x330b, 0xd8},
535*4882a593Smuzhiyun {0x330d, 0x10},
536*4882a593Smuzhiyun {0x331e, 0x41},
537*4882a593Smuzhiyun {0x331f, 0x61},
538*4882a593Smuzhiyun {0x3333, 0x10},
539*4882a593Smuzhiyun {0x335d, 0x60},
540*4882a593Smuzhiyun {0x335e, 0x06},
541*4882a593Smuzhiyun {0x335f, 0x08},
542*4882a593Smuzhiyun {0x3364, 0x56},
543*4882a593Smuzhiyun {0x3366, 0x01},
544*4882a593Smuzhiyun {0x337c, 0x02},
545*4882a593Smuzhiyun {0x337d, 0x0a},
546*4882a593Smuzhiyun {0x3390, 0x01},
547*4882a593Smuzhiyun {0x3391, 0x03},
548*4882a593Smuzhiyun {0x3392, 0x07},
549*4882a593Smuzhiyun {0x3393, 0x08},
550*4882a593Smuzhiyun {0x3394, 0x08},
551*4882a593Smuzhiyun {0x3395, 0x08},
552*4882a593Smuzhiyun {0x3396, 0x40},
553*4882a593Smuzhiyun {0x3397, 0x48},
554*4882a593Smuzhiyun {0x3398, 0x4b},
555*4882a593Smuzhiyun {0x3399, 0x08},
556*4882a593Smuzhiyun {0x339a, 0x08},
557*4882a593Smuzhiyun {0x339b, 0x08},
558*4882a593Smuzhiyun {0x339c, 0x1d},
559*4882a593Smuzhiyun {0x33a2, 0x04},
560*4882a593Smuzhiyun {0x33ae, 0x30},
561*4882a593Smuzhiyun {0x33af, 0x50},
562*4882a593Smuzhiyun {0x33b1, 0x80},
563*4882a593Smuzhiyun {0x33b2, 0x80},
564*4882a593Smuzhiyun {0x33b3, 0x40},
565*4882a593Smuzhiyun {0x349f, 0x02},
566*4882a593Smuzhiyun {0x34a6, 0x48},
567*4882a593Smuzhiyun {0x34a7, 0x49},
568*4882a593Smuzhiyun {0x34a8, 0x40},
569*4882a593Smuzhiyun {0x34a9, 0x30},
570*4882a593Smuzhiyun {0x34f8, 0x4b},
571*4882a593Smuzhiyun {0x34f9, 0x30},
572*4882a593Smuzhiyun {0x3632, 0x48},
573*4882a593Smuzhiyun {0x3633, 0x32},
574*4882a593Smuzhiyun {0x3637, 0x2b},
575*4882a593Smuzhiyun {0x3638, 0xc1},
576*4882a593Smuzhiyun {0x363b, 0x20},
577*4882a593Smuzhiyun {0x363d, 0x02},
578*4882a593Smuzhiyun {0x3670, 0x09},
579*4882a593Smuzhiyun {0x3674, 0x8b},
580*4882a593Smuzhiyun {0x3675, 0xc6},
581*4882a593Smuzhiyun {0x3676, 0x8b},
582*4882a593Smuzhiyun {0x367c, 0x40},
583*4882a593Smuzhiyun {0x367d, 0x48},
584*4882a593Smuzhiyun {0x3690, 0x32},
585*4882a593Smuzhiyun {0x3691, 0x32},
586*4882a593Smuzhiyun {0x3692, 0x33},
587*4882a593Smuzhiyun {0x3693, 0x40},
588*4882a593Smuzhiyun {0x3694, 0x4b},
589*4882a593Smuzhiyun {0x3698, 0x85},
590*4882a593Smuzhiyun {0x3699, 0x8f},
591*4882a593Smuzhiyun {0x369a, 0xa0},
592*4882a593Smuzhiyun {0x369b, 0xc3},
593*4882a593Smuzhiyun {0x36a2, 0x49},
594*4882a593Smuzhiyun {0x36a3, 0x4b},
595*4882a593Smuzhiyun {0x36a4, 0x4f},
596*4882a593Smuzhiyun {0x36d0, 0x01},
597*4882a593Smuzhiyun {0x36ec, 0x03},
598*4882a593Smuzhiyun {0x370f, 0x01},
599*4882a593Smuzhiyun {0x3722, 0x00},
600*4882a593Smuzhiyun {0x3728, 0x10},
601*4882a593Smuzhiyun {0x37b0, 0x03},
602*4882a593Smuzhiyun {0x37b1, 0x03},
603*4882a593Smuzhiyun {0x37b2, 0x83},
604*4882a593Smuzhiyun {0x37b3, 0x48},
605*4882a593Smuzhiyun {0x37b4, 0x49},
606*4882a593Smuzhiyun {0x37fb, 0x25},
607*4882a593Smuzhiyun {0x37fc, 0x01},
608*4882a593Smuzhiyun {0x3901, 0x00},
609*4882a593Smuzhiyun {0x3902, 0xc5},
610*4882a593Smuzhiyun {0x3904, 0x08},
611*4882a593Smuzhiyun {0x3905, 0x8c},
612*4882a593Smuzhiyun {0x3909, 0x00},
613*4882a593Smuzhiyun {0x391d, 0x04},
614*4882a593Smuzhiyun {0x391f, 0x44},
615*4882a593Smuzhiyun {0x3926, 0x21},
616*4882a593Smuzhiyun {0x3929, 0x18},
617*4882a593Smuzhiyun {0x3933, 0x81},
618*4882a593Smuzhiyun {0x3934, 0x81},
619*4882a593Smuzhiyun {0x3937, 0x69},
620*4882a593Smuzhiyun {0x3939, 0x00},
621*4882a593Smuzhiyun {0x393a, 0x00},
622*4882a593Smuzhiyun {0x39dc, 0x02},
623*4882a593Smuzhiyun {0x3e01, 0xcd},
624*4882a593Smuzhiyun {0x3e02, 0xa0},
625*4882a593Smuzhiyun {0x440e, 0x02},
626*4882a593Smuzhiyun {0x4509, 0x20},
627*4882a593Smuzhiyun {0x4800, 0x04},
628*4882a593Smuzhiyun {0x4837, 0x14},
629*4882a593Smuzhiyun {0x5010, 0x10},
630*4882a593Smuzhiyun {0x5799, 0x06},
631*4882a593Smuzhiyun {0x57ad, 0x00},
632*4882a593Smuzhiyun {0x5ae0, 0xfe},
633*4882a593Smuzhiyun {0x5ae1, 0x40},
634*4882a593Smuzhiyun {0x5ae2, 0x30},
635*4882a593Smuzhiyun {0x5ae3, 0x2a},
636*4882a593Smuzhiyun {0x5ae4, 0x24},
637*4882a593Smuzhiyun {0x5ae5, 0x30},
638*4882a593Smuzhiyun {0x5ae6, 0x2a},
639*4882a593Smuzhiyun {0x5ae7, 0x24},
640*4882a593Smuzhiyun {0x5ae8, 0x3c},
641*4882a593Smuzhiyun {0x5ae9, 0x30},
642*4882a593Smuzhiyun {0x5aea, 0x28},
643*4882a593Smuzhiyun {0x5aeb, 0x3c},
644*4882a593Smuzhiyun {0x5aec, 0x30},
645*4882a593Smuzhiyun {0x5aed, 0x28},
646*4882a593Smuzhiyun {0x5aee, 0xfe},
647*4882a593Smuzhiyun {0x5aef, 0x40},
648*4882a593Smuzhiyun {0x5af4, 0x30},
649*4882a593Smuzhiyun {0x5af5, 0x2a},
650*4882a593Smuzhiyun {0x5af6, 0x24},
651*4882a593Smuzhiyun {0x5af7, 0x30},
652*4882a593Smuzhiyun {0x5af8, 0x2a},
653*4882a593Smuzhiyun {0x5af9, 0x24},
654*4882a593Smuzhiyun {0x5afa, 0x3c},
655*4882a593Smuzhiyun {0x5afb, 0x30},
656*4882a593Smuzhiyun {0x5afc, 0x28},
657*4882a593Smuzhiyun {0x5afd, 0x3c},
658*4882a593Smuzhiyun {0x5afe, 0x30},
659*4882a593Smuzhiyun {0x5aff, 0x28},
660*4882a593Smuzhiyun {0x36e9, 0x44},
661*4882a593Smuzhiyun {0x37f9, 0x34},
662*4882a593Smuzhiyun // {0x0100, 0x01},
663*4882a593Smuzhiyun {REG_NULL, 0x00},
664*4882a593Smuzhiyun };
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun static const struct sc530ai_mode supported_modes_4lane[] = {
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun .width = 2880,
669*4882a593Smuzhiyun .height = 1620,
670*4882a593Smuzhiyun .max_fps = {
671*4882a593Smuzhiyun .numerator = 10000,
672*4882a593Smuzhiyun .denominator = 300000,
673*4882a593Smuzhiyun },
674*4882a593Smuzhiyun .exp_def = 0xcda / 2,
675*4882a593Smuzhiyun .hts_def = 0xb40,
676*4882a593Smuzhiyun .vts_def = 0x0672,
677*4882a593Smuzhiyun .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
678*4882a593Smuzhiyun .reg_list = sc530ai_linear_10_30fps_2880x1620_4lane_regs,
679*4882a593Smuzhiyun .mipi_freq_idx = 0,
680*4882a593Smuzhiyun .bpp = 10,
681*4882a593Smuzhiyun .hdr_mode = NO_HDR,
682*4882a593Smuzhiyun .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
683*4882a593Smuzhiyun },
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun .width = 2880,
686*4882a593Smuzhiyun .height = 1620,
687*4882a593Smuzhiyun .max_fps = {
688*4882a593Smuzhiyun .numerator = 10000,
689*4882a593Smuzhiyun .denominator = 300000,
690*4882a593Smuzhiyun },
691*4882a593Smuzhiyun .exp_def = 0x1820 / 2,
692*4882a593Smuzhiyun .hts_def = 0xb40,
693*4882a593Smuzhiyun .vts_def = 0x0ce4,
694*4882a593Smuzhiyun .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
695*4882a593Smuzhiyun .reg_list = sc530ai_hdr_10_30fps_2880x1620_4lane_regs,
696*4882a593Smuzhiyun .mipi_freq_idx = 1,
697*4882a593Smuzhiyun .bpp = 10,
698*4882a593Smuzhiyun .hdr_mode = HDR_X2,
699*4882a593Smuzhiyun .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
700*4882a593Smuzhiyun .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
701*4882a593Smuzhiyun .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
702*4882a593Smuzhiyun .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
703*4882a593Smuzhiyun },
704*4882a593Smuzhiyun };
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun static const struct sc530ai_mode supported_modes_2lane[] = {
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun .width = 2880,
709*4882a593Smuzhiyun .height = 1620,
710*4882a593Smuzhiyun .max_fps = {
711*4882a593Smuzhiyun .numerator = 10000,
712*4882a593Smuzhiyun .denominator = 300000,
713*4882a593Smuzhiyun },
714*4882a593Smuzhiyun .exp_def = 0xcda / 2,
715*4882a593Smuzhiyun .hts_def = 0xb40,
716*4882a593Smuzhiyun .vts_def = 0x0672,
717*4882a593Smuzhiyun .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
718*4882a593Smuzhiyun .reg_list = sc530ai_10_30fps_2880x1620_2lane_regs,
719*4882a593Smuzhiyun .mipi_freq_idx = 2,
720*4882a593Smuzhiyun .bpp = 10,
721*4882a593Smuzhiyun .hdr_mode = NO_HDR,
722*4882a593Smuzhiyun .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
723*4882a593Smuzhiyun },
724*4882a593Smuzhiyun };
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun static const s64 link_freq_items[] = {
727*4882a593Smuzhiyun SC530AI_LINK_FREQ_396M,
728*4882a593Smuzhiyun SC530AI_LINK_FREQ_792M,
729*4882a593Smuzhiyun SC530AI_LINK_FREQ_792M_2LANE,
730*4882a593Smuzhiyun };
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun /* Write registers up to 4 at a time */
sc530ai_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)733*4882a593Smuzhiyun static int sc530ai_write_reg(struct i2c_client *client, u16 reg,
734*4882a593Smuzhiyun u32 len, u32 val)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun u32 buf_i, val_i;
737*4882a593Smuzhiyun u8 buf[6];
738*4882a593Smuzhiyun u8 *val_p;
739*4882a593Smuzhiyun __be32 val_be;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun if (len > 4)
742*4882a593Smuzhiyun return -EINVAL;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun buf[0] = reg >> 8;
745*4882a593Smuzhiyun buf[1] = reg & 0xff;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun val_be = cpu_to_be32(val);
748*4882a593Smuzhiyun val_p = (u8 *)&val_be;
749*4882a593Smuzhiyun buf_i = 2;
750*4882a593Smuzhiyun val_i = 4 - len;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun while (val_i < 4)
753*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
756*4882a593Smuzhiyun return -EIO;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun return 0;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
sc530ai_write_array(struct i2c_client * client,const struct regval * regs)761*4882a593Smuzhiyun static int sc530ai_write_array(struct i2c_client *client,
762*4882a593Smuzhiyun const struct regval *regs)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun u32 i;
765*4882a593Smuzhiyun int ret = 0;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
768*4882a593Smuzhiyun ret = sc530ai_write_reg(client, regs[i].addr,
769*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT, regs[i].val);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun return ret;
772*4882a593Smuzhiyun }
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun /* Read registers up to 4 at a time */
sc530ai_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)775*4882a593Smuzhiyun static int sc530ai_read_reg(struct i2c_client *client,
776*4882a593Smuzhiyun u16 reg, unsigned int len, u32 *val)
777*4882a593Smuzhiyun {
778*4882a593Smuzhiyun struct i2c_msg msgs[2];
779*4882a593Smuzhiyun u8 *data_be_p;
780*4882a593Smuzhiyun __be32 data_be = 0;
781*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
782*4882a593Smuzhiyun int ret;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun if (len > 4 || !len)
785*4882a593Smuzhiyun return -EINVAL;
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
788*4882a593Smuzhiyun /* Write register address */
789*4882a593Smuzhiyun msgs[0].addr = client->addr;
790*4882a593Smuzhiyun msgs[0].flags = 0;
791*4882a593Smuzhiyun msgs[0].len = 2;
792*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun /* Read data from register */
795*4882a593Smuzhiyun msgs[1].addr = client->addr;
796*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
797*4882a593Smuzhiyun msgs[1].len = len;
798*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
801*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
802*4882a593Smuzhiyun return -EIO;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun return 0;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun
sc530ai_get_reso_dist(const struct sc530ai_mode * mode,struct v4l2_mbus_framefmt * framefmt)809*4882a593Smuzhiyun static int sc530ai_get_reso_dist(const struct sc530ai_mode *mode,
810*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
811*4882a593Smuzhiyun {
812*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
813*4882a593Smuzhiyun abs(mode->height - framefmt->height);
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun static const struct sc530ai_mode *
sc530ai_find_best_fit(struct sc530ai * sc530ai,struct v4l2_subdev_format * fmt)817*4882a593Smuzhiyun sc530ai_find_best_fit(struct sc530ai *sc530ai, struct v4l2_subdev_format *fmt)
818*4882a593Smuzhiyun {
819*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
820*4882a593Smuzhiyun int dist;
821*4882a593Smuzhiyun int cur_best_fit = 0;
822*4882a593Smuzhiyun int cur_best_fit_dist = -1;
823*4882a593Smuzhiyun unsigned int i;
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun for (i = 0; i < sc530ai->support_modes_num; i++) {
826*4882a593Smuzhiyun dist = sc530ai_get_reso_dist(&sc530ai->support_modes[i], framefmt);
827*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
828*4882a593Smuzhiyun cur_best_fit_dist = dist;
829*4882a593Smuzhiyun cur_best_fit = i;
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun return &sc530ai->support_modes[cur_best_fit];
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
sc530ai_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)836*4882a593Smuzhiyun static int sc530ai_set_fmt(struct v4l2_subdev *sd,
837*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
838*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
839*4882a593Smuzhiyun {
840*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
841*4882a593Smuzhiyun const struct sc530ai_mode *mode;
842*4882a593Smuzhiyun s64 h_blank, vblank_def;
843*4882a593Smuzhiyun u64 pixel_rate = 0;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun mutex_lock(&sc530ai->mutex);
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun mode = sc530ai_find_best_fit(sc530ai, fmt);
848*4882a593Smuzhiyun fmt->format.code = mode->bus_fmt;
849*4882a593Smuzhiyun fmt->format.width = mode->width;
850*4882a593Smuzhiyun fmt->format.height = mode->height;
851*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
852*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
853*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
854*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
855*4882a593Smuzhiyun #else
856*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
857*4882a593Smuzhiyun return -ENOTTY;
858*4882a593Smuzhiyun #endif
859*4882a593Smuzhiyun } else {
860*4882a593Smuzhiyun sc530ai->cur_mode = mode;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
863*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc530ai->hblank, h_blank,
864*4882a593Smuzhiyun h_blank, 1, h_blank);
865*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
866*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc530ai->vblank, vblank_def,
867*4882a593Smuzhiyun SC530AI_VTS_MAX - mode->height,
868*4882a593Smuzhiyun 1, vblank_def);
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(sc530ai->link_freq, mode->mipi_freq_idx);
871*4882a593Smuzhiyun pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
872*4882a593Smuzhiyun mode->bpp * 2 * sc530ai->lane_num;
873*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl_int64(sc530ai->pixel_rate, pixel_rate);
874*4882a593Smuzhiyun sc530ai->cur_vts = mode->vts_def;
875*4882a593Smuzhiyun sc530ai->cur_fps = mode->max_fps;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun return 0;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
sc530ai_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)883*4882a593Smuzhiyun static int sc530ai_get_fmt(struct v4l2_subdev *sd,
884*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
885*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
886*4882a593Smuzhiyun {
887*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
888*4882a593Smuzhiyun const struct sc530ai_mode *mode = sc530ai->cur_mode;
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun mutex_lock(&sc530ai->mutex);
891*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
892*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
893*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
894*4882a593Smuzhiyun #else
895*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
896*4882a593Smuzhiyun return -ENOTTY;
897*4882a593Smuzhiyun #endif
898*4882a593Smuzhiyun } else {
899*4882a593Smuzhiyun fmt->format.width = mode->width;
900*4882a593Smuzhiyun fmt->format.height = mode->height;
901*4882a593Smuzhiyun fmt->format.code = mode->bus_fmt;
902*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
903*4882a593Smuzhiyun /* format info: width/height/data type/virctual channel */
904*4882a593Smuzhiyun if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
905*4882a593Smuzhiyun fmt->reserved[0] = mode->vc[fmt->pad];
906*4882a593Smuzhiyun else
907*4882a593Smuzhiyun fmt->reserved[0] = mode->vc[PAD0];
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun return 0;
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun
sc530ai_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)914*4882a593Smuzhiyun static int sc530ai_enum_mbus_code(struct v4l2_subdev *sd,
915*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
916*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
917*4882a593Smuzhiyun {
918*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun if (code->index != 0)
921*4882a593Smuzhiyun return -EINVAL;
922*4882a593Smuzhiyun code->code = sc530ai->cur_mode->bus_fmt;
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun return 0;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun
sc530ai_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)927*4882a593Smuzhiyun static int sc530ai_enum_frame_sizes(struct v4l2_subdev *sd,
928*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
929*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun if (fse->index >= sc530ai->support_modes_num)
934*4882a593Smuzhiyun return -EINVAL;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun if (fse->code != sc530ai->support_modes[fse->index].bus_fmt)
937*4882a593Smuzhiyun return -EINVAL;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun fse->min_width = sc530ai->support_modes[fse->index].width;
940*4882a593Smuzhiyun fse->max_width = sc530ai->support_modes[fse->index].width;
941*4882a593Smuzhiyun fse->max_height = sc530ai->support_modes[fse->index].height;
942*4882a593Smuzhiyun fse->min_height = sc530ai->support_modes[fse->index].height;
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun return 0;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
sc530ai_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)947*4882a593Smuzhiyun static int sc530ai_g_frame_interval(struct v4l2_subdev *sd,
948*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
949*4882a593Smuzhiyun {
950*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
951*4882a593Smuzhiyun const struct sc530ai_mode *mode = sc530ai->cur_mode;
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun if (sc530ai->streaming)
954*4882a593Smuzhiyun fi->interval = sc530ai->cur_fps;
955*4882a593Smuzhiyun else
956*4882a593Smuzhiyun fi->interval = mode->max_fps;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun return 0;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun
sc530ai_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)961*4882a593Smuzhiyun static int sc530ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
962*4882a593Smuzhiyun struct v4l2_mbus_config *config)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
965*4882a593Smuzhiyun const struct sc530ai_mode *mode = sc530ai->cur_mode;
966*4882a593Smuzhiyun u32 val = 1 << (sc530ai->lane_num - 1) |
967*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
968*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun if (mode->hdr_mode != NO_HDR)
971*4882a593Smuzhiyun val |= V4L2_MBUS_CSI2_CHANNEL_1;
972*4882a593Smuzhiyun if (mode->hdr_mode == HDR_X3)
973*4882a593Smuzhiyun val |= V4L2_MBUS_CSI2_CHANNEL_2;
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2_DPHY;
976*4882a593Smuzhiyun config->flags = val;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun return 0;
979*4882a593Smuzhiyun }
980*4882a593Smuzhiyun
sc530ai_get_module_inf(struct sc530ai * sc530ai,struct rkmodule_inf * inf)981*4882a593Smuzhiyun static void sc530ai_get_module_inf(struct sc530ai *sc530ai,
982*4882a593Smuzhiyun struct rkmodule_inf *inf)
983*4882a593Smuzhiyun {
984*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
985*4882a593Smuzhiyun strscpy(inf->base.sensor, SC530AI_NAME, sizeof(inf->base.sensor));
986*4882a593Smuzhiyun strscpy(inf->base.module, sc530ai->module_name,
987*4882a593Smuzhiyun sizeof(inf->base.module));
988*4882a593Smuzhiyun strscpy(inf->base.lens, sc530ai->len_name, sizeof(inf->base.lens));
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
sc530ai_get_gain_reg(u32 total_gain,u32 * again,u32 * dgain,u32 * dgain_fine)991*4882a593Smuzhiyun static void sc530ai_get_gain_reg(u32 total_gain, u32 *again, u32 *dgain,
992*4882a593Smuzhiyun u32 *dgain_fine)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun u32 gain_factor = 0;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun if (total_gain < SC530AI_GAIN_MIN)
997*4882a593Smuzhiyun total_gain = SC530AI_GAIN_MIN;
998*4882a593Smuzhiyun else if (total_gain > SC530AI_GAIN_MAX)
999*4882a593Smuzhiyun total_gain = SC530AI_GAIN_MAX;
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun gain_factor = total_gain * 1000 / 32;
1002*4882a593Smuzhiyun if (gain_factor < 2000) { /* 1 - 2x gain */
1003*4882a593Smuzhiyun *again = 0x00;
1004*4882a593Smuzhiyun *dgain = 0x00;
1005*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 1000;
1006*4882a593Smuzhiyun } else if (gain_factor < 2550) { /* 2x - 2.55x gain */
1007*4882a593Smuzhiyun *again = 0x01;
1008*4882a593Smuzhiyun *dgain = 0x00;
1009*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 2000;
1010*4882a593Smuzhiyun } else if (gain_factor < 2550 * 2) { /* 2.55x - 5.1x gain */
1011*4882a593Smuzhiyun *again = 0x40;
1012*4882a593Smuzhiyun *dgain = 0x00;
1013*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 2550;
1014*4882a593Smuzhiyun } else if (gain_factor < 2550 * 4) { /* 5.1x - 10.2x gain */
1015*4882a593Smuzhiyun *again = 0x48;
1016*4882a593Smuzhiyun *dgain = 0x00;
1017*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 5110;
1018*4882a593Smuzhiyun } else if (gain_factor < 2550 * 8) { /* 10.2x - 20.4x gain */
1019*4882a593Smuzhiyun *again = 0x49;
1020*4882a593Smuzhiyun *dgain = 0x00;
1021*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 10200;
1022*4882a593Smuzhiyun } else if (gain_factor < 2550 * 16) { /* 20.4x - 40.8x gain */
1023*4882a593Smuzhiyun *again = 0x4B;
1024*4882a593Smuzhiyun *dgain = 0x00;
1025*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 20400;
1026*4882a593Smuzhiyun } else if (gain_factor < 2550 * 32) { /* 40.8x - 81.6x gain */
1027*4882a593Smuzhiyun *again = 0x4f;
1028*4882a593Smuzhiyun *dgain = 0x00;
1029*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 40800;
1030*4882a593Smuzhiyun } else if (gain_factor < 2550 * 64) { /* 81.6x - 163.2x gain */
1031*4882a593Smuzhiyun *again = 0x5f;
1032*4882a593Smuzhiyun *dgain = 0x00;
1033*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 40800 / 2;
1034*4882a593Smuzhiyun } else if (gain_factor < 2550 * 128) { /* 163.2x - 326.4x gain */
1035*4882a593Smuzhiyun *again = 0x5f;
1036*4882a593Smuzhiyun *dgain = 0x01;
1037*4882a593Smuzhiyun *dgain_fine = gain_factor * 128 / 40800 / 4;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun
sc530ai_set_hdrae(struct sc530ai * sc530ai,struct preisp_hdrae_exp_s * ae)1041*4882a593Smuzhiyun static int sc530ai_set_hdrae(struct sc530ai *sc530ai,
1042*4882a593Smuzhiyun struct preisp_hdrae_exp_s *ae)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun int ret = 0;
1045*4882a593Smuzhiyun u32 l_exp_time, m_exp_time, s_exp_time;
1046*4882a593Smuzhiyun u32 l_t_gain, m_t_gain, s_t_gain;
1047*4882a593Smuzhiyun u32 l_again = 0, l_dgain = 0, l_dgain_fine = 0;
1048*4882a593Smuzhiyun u32 s_again = 0, s_dgain = 0, s_dgain_fine = 0;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun if (!sc530ai->has_init_exp && !sc530ai->streaming) {
1051*4882a593Smuzhiyun sc530ai->init_hdrae_exp = *ae;
1052*4882a593Smuzhiyun sc530ai->has_init_exp = true;
1053*4882a593Smuzhiyun dev_dbg(&sc530ai->client->dev,
1054*4882a593Smuzhiyun "sc530ai don't stream, record exp for hdr!\n");
1055*4882a593Smuzhiyun return ret;
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun l_exp_time = ae->long_exp_reg;
1059*4882a593Smuzhiyun m_exp_time = ae->middle_exp_reg;
1060*4882a593Smuzhiyun s_exp_time = ae->short_exp_reg;
1061*4882a593Smuzhiyun l_t_gain = ae->long_gain_reg;
1062*4882a593Smuzhiyun m_t_gain = ae->middle_gain_reg;
1063*4882a593Smuzhiyun s_t_gain = ae->short_gain_reg;
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun if (sc530ai->cur_mode->hdr_mode == HDR_X2) {
1066*4882a593Smuzhiyun //2 stagger
1067*4882a593Smuzhiyun l_t_gain = m_t_gain;
1068*4882a593Smuzhiyun l_exp_time = m_exp_time;
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun l_exp_time = l_exp_time << 1;
1072*4882a593Smuzhiyun s_exp_time = s_exp_time << 1;
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun // set exposure reg
1075*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1076*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_H,
1077*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1078*4882a593Smuzhiyun SC530AI_FETCH_EXP_H(l_exp_time));
1079*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1080*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_M,
1081*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1082*4882a593Smuzhiyun SC530AI_FETCH_EXP_M(l_exp_time));
1083*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1084*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_L,
1085*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1086*4882a593Smuzhiyun SC530AI_FETCH_EXP_L(l_exp_time));
1087*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1088*4882a593Smuzhiyun SC530AI_REG_SHORT_EXPOSURE_H,
1089*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1090*4882a593Smuzhiyun SC530AI_FETCH_EXP_H(s_exp_time));
1091*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1092*4882a593Smuzhiyun SC530AI_REG_SHORT_EXPOSURE_M,
1093*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1094*4882a593Smuzhiyun SC530AI_FETCH_EXP_M(s_exp_time));
1095*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1096*4882a593Smuzhiyun SC530AI_REG_SHORT_EXPOSURE_L,
1097*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1098*4882a593Smuzhiyun SC530AI_FETCH_EXP_L(s_exp_time));
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun // set gain reg
1101*4882a593Smuzhiyun sc530ai_get_gain_reg(l_t_gain, &l_again, &l_dgain, &l_dgain_fine);
1102*4882a593Smuzhiyun sc530ai_get_gain_reg(s_t_gain, &s_again, &s_dgain, &s_dgain_fine);
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1105*4882a593Smuzhiyun SC530AI_REG_DIG_GAIN,
1106*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1107*4882a593Smuzhiyun l_dgain);
1108*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1109*4882a593Smuzhiyun SC530AI_REG_DIG_FINE_GAIN,
1110*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1111*4882a593Smuzhiyun l_dgain_fine);
1112*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1113*4882a593Smuzhiyun SC530AI_REG_ANA_GAIN,
1114*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1115*4882a593Smuzhiyun l_again);
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1118*4882a593Smuzhiyun SC530AI_REG_SDIG_GAIN,
1119*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1120*4882a593Smuzhiyun s_dgain);
1121*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1122*4882a593Smuzhiyun SC530AI_REG_SDIG_FINE_GAIN,
1123*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1124*4882a593Smuzhiyun s_dgain_fine);
1125*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1126*4882a593Smuzhiyun SC530AI_REG_SANA_GAIN,
1127*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1128*4882a593Smuzhiyun s_again);
1129*4882a593Smuzhiyun return ret;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
sc530ai_get_channel_info(struct sc530ai * sc530ai,struct rkmodule_channel_info * ch_info)1132*4882a593Smuzhiyun static int sc530ai_get_channel_info(struct sc530ai *sc530ai, struct rkmodule_channel_info *ch_info)
1133*4882a593Smuzhiyun {
1134*4882a593Smuzhiyun if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1135*4882a593Smuzhiyun return -EINVAL;
1136*4882a593Smuzhiyun ch_info->vc = sc530ai->cur_mode->vc[ch_info->index];
1137*4882a593Smuzhiyun ch_info->width = sc530ai->cur_mode->width;
1138*4882a593Smuzhiyun ch_info->height = sc530ai->cur_mode->height;
1139*4882a593Smuzhiyun ch_info->bus_fmt = sc530ai->cur_mode->bus_fmt;
1140*4882a593Smuzhiyun return 0;
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun
sc530ai_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1143*4882a593Smuzhiyun static long sc530ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1146*4882a593Smuzhiyun struct rkmodule_hdr_cfg *hdr;
1147*4882a593Smuzhiyun const struct sc530ai_mode *mode;
1148*4882a593Smuzhiyun struct rkmodule_channel_info *ch_info;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun long ret = 0;
1151*4882a593Smuzhiyun u32 i, h = 0, w;
1152*4882a593Smuzhiyun u32 stream = 0;
1153*4882a593Smuzhiyun int pixel_rate = 0;
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun switch (cmd) {
1156*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1157*4882a593Smuzhiyun sc530ai_get_module_inf(sc530ai, (struct rkmodule_inf *)arg);
1158*4882a593Smuzhiyun break;
1159*4882a593Smuzhiyun case RKMODULE_GET_HDR_CFG:
1160*4882a593Smuzhiyun hdr = (struct rkmodule_hdr_cfg *)arg;
1161*4882a593Smuzhiyun hdr->esp.mode = HDR_NORMAL_VC;
1162*4882a593Smuzhiyun hdr->hdr_mode = sc530ai->cur_mode->hdr_mode;
1163*4882a593Smuzhiyun break;
1164*4882a593Smuzhiyun case RKMODULE_SET_HDR_CFG:
1165*4882a593Smuzhiyun hdr = (struct rkmodule_hdr_cfg *)arg;
1166*4882a593Smuzhiyun w = sc530ai->cur_mode->width;
1167*4882a593Smuzhiyun h = sc530ai->cur_mode->height;
1168*4882a593Smuzhiyun for (i = 0; i < sc530ai->support_modes_num; i++) {
1169*4882a593Smuzhiyun if (w == sc530ai->support_modes[i].width &&
1170*4882a593Smuzhiyun h == sc530ai->support_modes[i].height &&
1171*4882a593Smuzhiyun sc530ai->support_modes[i].hdr_mode == hdr->hdr_mode) {
1172*4882a593Smuzhiyun sc530ai->cur_mode = &sc530ai->support_modes[i];
1173*4882a593Smuzhiyun break;
1174*4882a593Smuzhiyun }
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun if (i == sc530ai->support_modes_num) {
1177*4882a593Smuzhiyun dev_err(&sc530ai->client->dev,
1178*4882a593Smuzhiyun "not find hdr mode:%d %dx%d config\n",
1179*4882a593Smuzhiyun hdr->hdr_mode, w, h);
1180*4882a593Smuzhiyun ret = -EINVAL;
1181*4882a593Smuzhiyun } else {
1182*4882a593Smuzhiyun mode = sc530ai->cur_mode;
1183*4882a593Smuzhiyun w = sc530ai->cur_mode->hts_def -
1184*4882a593Smuzhiyun sc530ai->cur_mode->width;
1185*4882a593Smuzhiyun h = sc530ai->cur_mode->vts_def -
1186*4882a593Smuzhiyun sc530ai->cur_mode->height;
1187*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc530ai->hblank, w, w, 1, w);
1188*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc530ai->vblank, h,
1189*4882a593Smuzhiyun SC530AI_VTS_MAX -
1190*4882a593Smuzhiyun sc530ai->cur_mode->height,
1191*4882a593Smuzhiyun 1, h);
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(sc530ai->link_freq,
1194*4882a593Smuzhiyun mode->mipi_freq_idx);
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun pixel_rate = (int)link_freq_items[mode->mipi_freq_idx]
1197*4882a593Smuzhiyun / mode->bpp * 2 * sc530ai->lane_num;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl_int64(sc530ai->pixel_rate,
1200*4882a593Smuzhiyun pixel_rate);
1201*4882a593Smuzhiyun sc530ai->cur_vts = mode->vts_def;
1202*4882a593Smuzhiyun sc530ai->cur_fps = mode->max_fps;
1203*4882a593Smuzhiyun dev_info(&sc530ai->client->dev, "sensor mode: %d\n",
1204*4882a593Smuzhiyun sc530ai->cur_mode->hdr_mode);
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun break;
1207*4882a593Smuzhiyun case PREISP_CMD_SET_HDRAE_EXP:
1208*4882a593Smuzhiyun if (sc530ai->cur_mode->hdr_mode == HDR_X2)
1209*4882a593Smuzhiyun ret = sc530ai_set_hdrae(sc530ai, arg);
1210*4882a593Smuzhiyun break;
1211*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1212*4882a593Smuzhiyun stream = *((u32 *)arg);
1213*4882a593Smuzhiyun if (stream)
1214*4882a593Smuzhiyun ret = sc530ai_write_reg(sc530ai->client,
1215*4882a593Smuzhiyun SC530AI_REG_CTRL_MODE,
1216*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1217*4882a593Smuzhiyun SC530AI_MODE_STREAMING);
1218*4882a593Smuzhiyun else
1219*4882a593Smuzhiyun ret = sc530ai_write_reg(sc530ai->client,
1220*4882a593Smuzhiyun SC530AI_REG_CTRL_MODE,
1221*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1222*4882a593Smuzhiyun SC530AI_MODE_SW_STANDBY);
1223*4882a593Smuzhiyun break;
1224*4882a593Smuzhiyun case RKMODULE_GET_CHANNEL_INFO:
1225*4882a593Smuzhiyun ch_info = (struct rkmodule_channel_info *)arg;
1226*4882a593Smuzhiyun ret = sc530ai_get_channel_info(sc530ai, ch_info);
1227*4882a593Smuzhiyun break;
1228*4882a593Smuzhiyun default:
1229*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1230*4882a593Smuzhiyun break;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun return ret;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
sc530ai_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1237*4882a593Smuzhiyun static long sc530ai_compat_ioctl32(struct v4l2_subdev *sd,
1238*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
1241*4882a593Smuzhiyun struct rkmodule_inf *inf;
1242*4882a593Smuzhiyun struct rkmodule_hdr_cfg *hdr;
1243*4882a593Smuzhiyun struct preisp_hdrae_exp_s *hdrae;
1244*4882a593Smuzhiyun struct rkmodule_channel_info *ch_info;
1245*4882a593Smuzhiyun long ret = 0;
1246*4882a593Smuzhiyun u32 stream = 0;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun switch (cmd) {
1249*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1250*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1251*4882a593Smuzhiyun if (!inf) {
1252*4882a593Smuzhiyun ret = -ENOMEM;
1253*4882a593Smuzhiyun return ret;
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, inf);
1257*4882a593Smuzhiyun if (!ret) {
1258*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
1259*4882a593Smuzhiyun if (ret)
1260*4882a593Smuzhiyun return -EFAULT;
1261*4882a593Smuzhiyun }
1262*4882a593Smuzhiyun kfree(inf);
1263*4882a593Smuzhiyun break;
1264*4882a593Smuzhiyun case RKMODULE_GET_HDR_CFG:
1265*4882a593Smuzhiyun hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1266*4882a593Smuzhiyun if (!hdr) {
1267*4882a593Smuzhiyun ret = -ENOMEM;
1268*4882a593Smuzhiyun return ret;
1269*4882a593Smuzhiyun }
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, hdr);
1272*4882a593Smuzhiyun if (!ret) {
1273*4882a593Smuzhiyun ret = copy_to_user(up, hdr, sizeof(*hdr));
1274*4882a593Smuzhiyun if (ret)
1275*4882a593Smuzhiyun return -EFAULT;
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun kfree(hdr);
1278*4882a593Smuzhiyun break;
1279*4882a593Smuzhiyun case RKMODULE_SET_HDR_CFG:
1280*4882a593Smuzhiyun hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1281*4882a593Smuzhiyun if (!hdr) {
1282*4882a593Smuzhiyun ret = -ENOMEM;
1283*4882a593Smuzhiyun return ret;
1284*4882a593Smuzhiyun }
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun if (copy_from_user(hdr, up, sizeof(*hdr))) {
1287*4882a593Smuzhiyun kfree(hdr);
1288*4882a593Smuzhiyun return -EFAULT;
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, hdr);
1292*4882a593Smuzhiyun kfree(hdr);
1293*4882a593Smuzhiyun break;
1294*4882a593Smuzhiyun case PREISP_CMD_SET_HDRAE_EXP:
1295*4882a593Smuzhiyun hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1296*4882a593Smuzhiyun if (!hdrae) {
1297*4882a593Smuzhiyun ret = -ENOMEM;
1298*4882a593Smuzhiyun return ret;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1302*4882a593Smuzhiyun kfree(hdrae);
1303*4882a593Smuzhiyun return -EFAULT;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, hdrae);
1307*4882a593Smuzhiyun kfree(hdrae);
1308*4882a593Smuzhiyun break;
1309*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1310*4882a593Smuzhiyun if (copy_from_user(&stream, up, sizeof(u32)))
1311*4882a593Smuzhiyun return -EFAULT;
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, &stream);
1314*4882a593Smuzhiyun break;
1315*4882a593Smuzhiyun case RKMODULE_GET_CHANNEL_INFO:
1316*4882a593Smuzhiyun ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1317*4882a593Smuzhiyun if (!ch_info) {
1318*4882a593Smuzhiyun ret = -ENOMEM;
1319*4882a593Smuzhiyun return ret;
1320*4882a593Smuzhiyun }
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun ret = sc530ai_ioctl(sd, cmd, ch_info);
1323*4882a593Smuzhiyun if (!ret) {
1324*4882a593Smuzhiyun ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1325*4882a593Smuzhiyun if (ret)
1326*4882a593Smuzhiyun ret = -EFAULT;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun kfree(ch_info);
1329*4882a593Smuzhiyun break;
1330*4882a593Smuzhiyun default:
1331*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1332*4882a593Smuzhiyun break;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun return ret;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun #endif
1338*4882a593Smuzhiyun
__sc530ai_start_stream(struct sc530ai * sc530ai)1339*4882a593Smuzhiyun static int __sc530ai_start_stream(struct sc530ai *sc530ai)
1340*4882a593Smuzhiyun {
1341*4882a593Smuzhiyun int ret;
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun ret = sc530ai_write_array(sc530ai->client, sc530ai->cur_mode->reg_list);
1344*4882a593Smuzhiyun if (ret)
1345*4882a593Smuzhiyun return ret;
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun /* In case these controls are set before streaming */
1348*4882a593Smuzhiyun ret = __v4l2_ctrl_handler_setup(&sc530ai->ctrl_handler);
1349*4882a593Smuzhiyun if (ret)
1350*4882a593Smuzhiyun return ret;
1351*4882a593Smuzhiyun if (sc530ai->has_init_exp && sc530ai->cur_mode->hdr_mode != NO_HDR) {
1352*4882a593Smuzhiyun ret = sc530ai_ioctl(&sc530ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
1353*4882a593Smuzhiyun &sc530ai->init_hdrae_exp);
1354*4882a593Smuzhiyun if (ret) {
1355*4882a593Smuzhiyun dev_err(&sc530ai->client->dev,
1356*4882a593Smuzhiyun "init exp fail in hdr mode\n");
1357*4882a593Smuzhiyun return ret;
1358*4882a593Smuzhiyun }
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun return sc530ai_write_reg(sc530ai->client, SC530AI_REG_CTRL_MODE,
1361*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1362*4882a593Smuzhiyun SC530AI_MODE_STREAMING);
1363*4882a593Smuzhiyun }
1364*4882a593Smuzhiyun
__sc530ai_stop_stream(struct sc530ai * sc530ai)1365*4882a593Smuzhiyun static int __sc530ai_stop_stream(struct sc530ai *sc530ai)
1366*4882a593Smuzhiyun {
1367*4882a593Smuzhiyun sc530ai->has_init_exp = false;
1368*4882a593Smuzhiyun return sc530ai_write_reg(sc530ai->client, SC530AI_REG_CTRL_MODE,
1369*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1370*4882a593Smuzhiyun SC530AI_MODE_SW_STANDBY);
1371*4882a593Smuzhiyun }
1372*4882a593Smuzhiyun
sc530ai_s_stream(struct v4l2_subdev * sd,int on)1373*4882a593Smuzhiyun static int sc530ai_s_stream(struct v4l2_subdev *sd, int on)
1374*4882a593Smuzhiyun {
1375*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1376*4882a593Smuzhiyun struct i2c_client *client = sc530ai->client;
1377*4882a593Smuzhiyun int ret = 0;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun mutex_lock(&sc530ai->mutex);
1380*4882a593Smuzhiyun on = !!on;
1381*4882a593Smuzhiyun if (on == sc530ai->streaming)
1382*4882a593Smuzhiyun goto unlock_and_return;
1383*4882a593Smuzhiyun if (on) {
1384*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1385*4882a593Smuzhiyun if (ret < 0) {
1386*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1387*4882a593Smuzhiyun goto unlock_and_return;
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun ret = __sc530ai_start_stream(sc530ai);
1390*4882a593Smuzhiyun if (ret) {
1391*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
1392*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1393*4882a593Smuzhiyun goto unlock_and_return;
1394*4882a593Smuzhiyun }
1395*4882a593Smuzhiyun } else {
1396*4882a593Smuzhiyun __sc530ai_stop_stream(sc530ai);
1397*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun sc530ai->streaming = on;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun unlock_and_return:
1403*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun return ret;
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun
sc530ai_s_power(struct v4l2_subdev * sd,int on)1408*4882a593Smuzhiyun static int sc530ai_s_power(struct v4l2_subdev *sd, int on)
1409*4882a593Smuzhiyun {
1410*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1411*4882a593Smuzhiyun struct i2c_client *client = sc530ai->client;
1412*4882a593Smuzhiyun int ret = 0;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun mutex_lock(&sc530ai->mutex);
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
1417*4882a593Smuzhiyun if (sc530ai->power_on == !!on)
1418*4882a593Smuzhiyun goto unlock_and_return;
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun if (on) {
1421*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1422*4882a593Smuzhiyun if (ret < 0) {
1423*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1424*4882a593Smuzhiyun goto unlock_and_return;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1428*4882a593Smuzhiyun SC530AI_SOFTWARE_RESET_REG,
1429*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1430*4882a593Smuzhiyun 0x01);
1431*4882a593Smuzhiyun usleep_range(100, 200);
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun sc530ai->power_on = true;
1434*4882a593Smuzhiyun } else {
1435*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1436*4882a593Smuzhiyun sc530ai->power_on = false;
1437*4882a593Smuzhiyun }
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun unlock_and_return:
1440*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun return ret;
1443*4882a593Smuzhiyun }
1444*4882a593Smuzhiyun
__sc530ai_power_on(struct sc530ai * sc530ai)1445*4882a593Smuzhiyun static int __sc530ai_power_on(struct sc530ai *sc530ai)
1446*4882a593Smuzhiyun {
1447*4882a593Smuzhiyun int ret;
1448*4882a593Smuzhiyun struct device *dev = &sc530ai->client->dev;
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(sc530ai->pins_default)) {
1451*4882a593Smuzhiyun ret = pinctrl_select_state(sc530ai->pinctrl,
1452*4882a593Smuzhiyun sc530ai->pins_default);
1453*4882a593Smuzhiyun if (ret < 0)
1454*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun ret = clk_set_rate(sc530ai->xvclk, SC530AI_XVCLK_FREQ);
1457*4882a593Smuzhiyun if (ret < 0)
1458*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
1459*4882a593Smuzhiyun if (clk_get_rate(sc530ai->xvclk) != SC530AI_XVCLK_FREQ)
1460*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1461*4882a593Smuzhiyun ret = clk_prepare_enable(sc530ai->xvclk);
1462*4882a593Smuzhiyun if (ret < 0) {
1463*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
1464*4882a593Smuzhiyun return ret;
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun if (!IS_ERR(sc530ai->reset_gpio))
1467*4882a593Smuzhiyun gpiod_set_value_cansleep(sc530ai->reset_gpio, 0);
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun ret = regulator_bulk_enable(sc530ai_NUM_SUPPLIES, sc530ai->supplies);
1470*4882a593Smuzhiyun if (ret < 0) {
1471*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
1472*4882a593Smuzhiyun goto disable_clk;
1473*4882a593Smuzhiyun }
1474*4882a593Smuzhiyun
1475*4882a593Smuzhiyun if (!IS_ERR(sc530ai->reset_gpio))
1476*4882a593Smuzhiyun gpiod_set_value_cansleep(sc530ai->reset_gpio, 1);
1477*4882a593Smuzhiyun
1478*4882a593Smuzhiyun usleep_range(500, 1000);
1479*4882a593Smuzhiyun if (!IS_ERR(sc530ai->pwdn_gpio))
1480*4882a593Smuzhiyun gpiod_set_value_cansleep(sc530ai->pwdn_gpio, 1);
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun usleep_range(4000, 5000);
1483*4882a593Smuzhiyun return 0;
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun disable_clk:
1486*4882a593Smuzhiyun clk_disable_unprepare(sc530ai->xvclk);
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun return ret;
1489*4882a593Smuzhiyun }
1490*4882a593Smuzhiyun
__sc530ai_power_off(struct sc530ai * sc530ai)1491*4882a593Smuzhiyun static void __sc530ai_power_off(struct sc530ai *sc530ai)
1492*4882a593Smuzhiyun {
1493*4882a593Smuzhiyun int ret;
1494*4882a593Smuzhiyun struct device *dev = &sc530ai->client->dev;
1495*4882a593Smuzhiyun
1496*4882a593Smuzhiyun if (!IS_ERR(sc530ai->pwdn_gpio))
1497*4882a593Smuzhiyun gpiod_set_value_cansleep(sc530ai->pwdn_gpio, 0);
1498*4882a593Smuzhiyun clk_disable_unprepare(sc530ai->xvclk);
1499*4882a593Smuzhiyun if (!IS_ERR(sc530ai->reset_gpio))
1500*4882a593Smuzhiyun gpiod_set_value_cansleep(sc530ai->reset_gpio, 0);
1501*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(sc530ai->pins_sleep)) {
1502*4882a593Smuzhiyun ret = pinctrl_select_state(sc530ai->pinctrl,
1503*4882a593Smuzhiyun sc530ai->pins_sleep);
1504*4882a593Smuzhiyun if (ret < 0)
1505*4882a593Smuzhiyun dev_dbg(dev, "could not set pins\n");
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun regulator_bulk_disable(sc530ai_NUM_SUPPLIES, sc530ai->supplies);
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun
sc530ai_runtime_resume(struct device * dev)1510*4882a593Smuzhiyun static int __maybe_unused sc530ai_runtime_resume(struct device *dev)
1511*4882a593Smuzhiyun {
1512*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1513*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1514*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun return __sc530ai_power_on(sc530ai);
1517*4882a593Smuzhiyun }
1518*4882a593Smuzhiyun
sc530ai_runtime_suspend(struct device * dev)1519*4882a593Smuzhiyun static int __maybe_unused sc530ai_runtime_suspend(struct device *dev)
1520*4882a593Smuzhiyun {
1521*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1522*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1523*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun __sc530ai_power_off(sc530ai);
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun return 0;
1528*4882a593Smuzhiyun }
1529*4882a593Smuzhiyun
1530*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc530ai_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1531*4882a593Smuzhiyun static int sc530ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1532*4882a593Smuzhiyun {
1533*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1534*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
1535*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
1536*4882a593Smuzhiyun const struct sc530ai_mode *def_mode = &sc530ai->support_modes[0];
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun mutex_lock(&sc530ai->mutex);
1539*4882a593Smuzhiyun /* Initialize try_fmt */
1540*4882a593Smuzhiyun try_fmt->width = def_mode->width;
1541*4882a593Smuzhiyun try_fmt->height = def_mode->height;
1542*4882a593Smuzhiyun try_fmt->code = def_mode->bus_fmt;
1543*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun mutex_unlock(&sc530ai->mutex);
1546*4882a593Smuzhiyun /* No crop or compose */
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun return 0;
1549*4882a593Smuzhiyun }
1550*4882a593Smuzhiyun #endif
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun #define DST_WIDTH 2880
1553*4882a593Smuzhiyun #define DST_HEIGHT 1616
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun /*
1556*4882a593Smuzhiyun * The resolution of the driver configuration needs to be exactly
1557*4882a593Smuzhiyun * the same as the current output resolution of the sensor,
1558*4882a593Smuzhiyun * the input width of the isp needs to be 16 aligned,
1559*4882a593Smuzhiyun * the input height of the isp needs to be 8 aligned.
1560*4882a593Smuzhiyun * Can be cropped to standard resolution by this function,
1561*4882a593Smuzhiyun * otherwise it will crop out strange resolution according
1562*4882a593Smuzhiyun * to the alignment rules.
1563*4882a593Smuzhiyun */
sc530ai_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1564*4882a593Smuzhiyun static int sc530ai_get_selection(struct v4l2_subdev *sd,
1565*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1566*4882a593Smuzhiyun struct v4l2_subdev_selection *sel)
1567*4882a593Smuzhiyun {
1568*4882a593Smuzhiyun if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1569*4882a593Smuzhiyun sel->r.left = 0;
1570*4882a593Smuzhiyun sel->r.width = DST_WIDTH;
1571*4882a593Smuzhiyun sel->r.top = 2;
1572*4882a593Smuzhiyun sel->r.height = DST_HEIGHT;
1573*4882a593Smuzhiyun return 0;
1574*4882a593Smuzhiyun }
1575*4882a593Smuzhiyun return -EINVAL;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
sc530ai_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1578*4882a593Smuzhiyun static int sc530ai_enum_frame_interval(struct v4l2_subdev *sd,
1579*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1580*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
1581*4882a593Smuzhiyun {
1582*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun if (fie->index >= sc530ai->support_modes_num)
1585*4882a593Smuzhiyun return -EINVAL;
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun fie->code = sc530ai->support_modes[fie->index].bus_fmt;
1588*4882a593Smuzhiyun fie->width = sc530ai->support_modes[fie->index].width;
1589*4882a593Smuzhiyun fie->height = sc530ai->support_modes[fie->index].height;
1590*4882a593Smuzhiyun fie->interval = sc530ai->support_modes[fie->index].max_fps;
1591*4882a593Smuzhiyun fie->reserved[0] = sc530ai->support_modes[fie->index].hdr_mode;
1592*4882a593Smuzhiyun return 0;
1593*4882a593Smuzhiyun }
1594*4882a593Smuzhiyun
1595*4882a593Smuzhiyun static const struct dev_pm_ops sc530ai_pm_ops = {
1596*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(sc530ai_runtime_suspend,
1597*4882a593Smuzhiyun sc530ai_runtime_resume, NULL)
1598*4882a593Smuzhiyun };
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1601*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops sc530ai_internal_ops = {
1602*4882a593Smuzhiyun .open = sc530ai_open,
1603*4882a593Smuzhiyun };
1604*4882a593Smuzhiyun #endif
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops sc530ai_core_ops = {
1607*4882a593Smuzhiyun .s_power = sc530ai_s_power,
1608*4882a593Smuzhiyun .ioctl = sc530ai_ioctl,
1609*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1610*4882a593Smuzhiyun .compat_ioctl32 = sc530ai_compat_ioctl32,
1611*4882a593Smuzhiyun #endif
1612*4882a593Smuzhiyun };
1613*4882a593Smuzhiyun
1614*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops sc530ai_video_ops = {
1615*4882a593Smuzhiyun .s_stream = sc530ai_s_stream,
1616*4882a593Smuzhiyun .g_frame_interval = sc530ai_g_frame_interval,
1617*4882a593Smuzhiyun };
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops sc530ai_pad_ops = {
1620*4882a593Smuzhiyun .enum_mbus_code = sc530ai_enum_mbus_code,
1621*4882a593Smuzhiyun .enum_frame_size = sc530ai_enum_frame_sizes,
1622*4882a593Smuzhiyun .enum_frame_interval = sc530ai_enum_frame_interval,
1623*4882a593Smuzhiyun .get_fmt = sc530ai_get_fmt,
1624*4882a593Smuzhiyun .set_fmt = sc530ai_set_fmt,
1625*4882a593Smuzhiyun .get_selection = sc530ai_get_selection,
1626*4882a593Smuzhiyun .get_mbus_config = sc530ai_g_mbus_config,
1627*4882a593Smuzhiyun };
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun static const struct v4l2_subdev_ops sc530ai_subdev_ops = {
1630*4882a593Smuzhiyun .core = &sc530ai_core_ops,
1631*4882a593Smuzhiyun .video = &sc530ai_video_ops,
1632*4882a593Smuzhiyun .pad = &sc530ai_pad_ops,
1633*4882a593Smuzhiyun };
1634*4882a593Smuzhiyun
sc530ai_modify_fps_info(struct sc530ai * sc5330ai)1635*4882a593Smuzhiyun static void sc530ai_modify_fps_info(struct sc530ai *sc5330ai)
1636*4882a593Smuzhiyun {
1637*4882a593Smuzhiyun const struct sc530ai_mode *mode = sc5330ai->cur_mode;
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun sc5330ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1640*4882a593Smuzhiyun sc5330ai->cur_vts;
1641*4882a593Smuzhiyun }
1642*4882a593Smuzhiyun
sc530ai_set_ctrl(struct v4l2_ctrl * ctrl)1643*4882a593Smuzhiyun static int sc530ai_set_ctrl(struct v4l2_ctrl *ctrl)
1644*4882a593Smuzhiyun {
1645*4882a593Smuzhiyun struct sc530ai *sc530ai = container_of(ctrl->handler,
1646*4882a593Smuzhiyun struct sc530ai, ctrl_handler);
1647*4882a593Smuzhiyun struct i2c_client *client = sc530ai->client;
1648*4882a593Smuzhiyun s64 max;
1649*4882a593Smuzhiyun u32 again = 0, dgain = 0, dgain_fine = 0;
1650*4882a593Smuzhiyun int ret = 0;
1651*4882a593Smuzhiyun u32 val = 0, vts = 0;
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
1654*4882a593Smuzhiyun switch (ctrl->id) {
1655*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1656*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1657*4882a593Smuzhiyun max = sc530ai->cur_mode->height + ctrl->val - 5;
1658*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc530ai->exposure,
1659*4882a593Smuzhiyun sc530ai->exposure->minimum, max,
1660*4882a593Smuzhiyun sc530ai->exposure->step,
1661*4882a593Smuzhiyun sc530ai->exposure->default_value);
1662*4882a593Smuzhiyun break;
1663*4882a593Smuzhiyun }
1664*4882a593Smuzhiyun
1665*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1666*4882a593Smuzhiyun return 0;
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun switch (ctrl->id) {
1669*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1670*4882a593Smuzhiyun if (sc530ai->cur_mode->hdr_mode != NO_HDR)
1671*4882a593Smuzhiyun goto ctrl_end;
1672*4882a593Smuzhiyun val = ctrl->val << 1;
1673*4882a593Smuzhiyun ret = sc530ai_write_reg(sc530ai->client,
1674*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_H,
1675*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1676*4882a593Smuzhiyun SC530AI_FETCH_EXP_H(val));
1677*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1678*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_M,
1679*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1680*4882a593Smuzhiyun SC530AI_FETCH_EXP_M(val));
1681*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1682*4882a593Smuzhiyun SC530AI_REG_EXPOSURE_L,
1683*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1684*4882a593Smuzhiyun SC530AI_FETCH_EXP_L(val));
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun dev_dbg(&client->dev, "set exposure 0x%x\n", val);
1687*4882a593Smuzhiyun break;
1688*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1689*4882a593Smuzhiyun if (sc530ai->cur_mode->hdr_mode != NO_HDR)
1690*4882a593Smuzhiyun goto ctrl_end;
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun sc530ai_get_gain_reg(ctrl->val, &again, &dgain, &dgain_fine);
1693*4882a593Smuzhiyun ret = sc530ai_write_reg(sc530ai->client,
1694*4882a593Smuzhiyun SC530AI_REG_DIG_GAIN,
1695*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1696*4882a593Smuzhiyun dgain);
1697*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1698*4882a593Smuzhiyun SC530AI_REG_DIG_FINE_GAIN,
1699*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1700*4882a593Smuzhiyun dgain_fine);
1701*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1702*4882a593Smuzhiyun SC530AI_REG_ANA_GAIN,
1703*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1704*4882a593Smuzhiyun again);
1705*4882a593Smuzhiyun dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1706*4882a593Smuzhiyun break;
1707*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1708*4882a593Smuzhiyun vts = ctrl->val + sc530ai->cur_mode->height;
1709*4882a593Smuzhiyun ret = sc530ai_write_reg(sc530ai->client,
1710*4882a593Smuzhiyun SC530AI_REG_VTS_H,
1711*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1712*4882a593Smuzhiyun (vts >> 8) & 0x7f);
1713*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1714*4882a593Smuzhiyun SC530AI_REG_VTS_L,
1715*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1716*4882a593Smuzhiyun vts & 0xff);
1717*4882a593Smuzhiyun if (!ret)
1718*4882a593Smuzhiyun sc530ai->cur_vts = vts;
1719*4882a593Smuzhiyun sc530ai_modify_fps_info(sc530ai);
1720*4882a593Smuzhiyun dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1721*4882a593Smuzhiyun break;
1722*4882a593Smuzhiyun case V4L2_CID_HFLIP:
1723*4882a593Smuzhiyun ret = sc530ai_read_reg(sc530ai->client, SC530AI_FLIP_MIRROR_REG,
1724*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT, &val);
1725*4882a593Smuzhiyun if (ret)
1726*4882a593Smuzhiyun break;
1727*4882a593Smuzhiyun
1728*4882a593Smuzhiyun if (ctrl->val)
1729*4882a593Smuzhiyun val |= SC530AI_MIRROR_MASK;
1730*4882a593Smuzhiyun else
1731*4882a593Smuzhiyun val &= ~SC530AI_MIRROR_MASK;
1732*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1733*4882a593Smuzhiyun SC530AI_FLIP_MIRROR_REG,
1734*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT, val);
1735*4882a593Smuzhiyun break;
1736*4882a593Smuzhiyun case V4L2_CID_VFLIP:
1737*4882a593Smuzhiyun ret = sc530ai_read_reg(sc530ai->client,
1738*4882a593Smuzhiyun SC530AI_FLIP_MIRROR_REG,
1739*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT, &val);
1740*4882a593Smuzhiyun if (ret)
1741*4882a593Smuzhiyun break;
1742*4882a593Smuzhiyun
1743*4882a593Smuzhiyun if (ctrl->val)
1744*4882a593Smuzhiyun val |= SC530AI_FLIP_MASK;
1745*4882a593Smuzhiyun else
1746*4882a593Smuzhiyun val &= ~SC530AI_FLIP_MASK;
1747*4882a593Smuzhiyun ret |= sc530ai_write_reg(sc530ai->client,
1748*4882a593Smuzhiyun SC530AI_FLIP_MIRROR_REG,
1749*4882a593Smuzhiyun SC530AI_REG_VALUE_08BIT,
1750*4882a593Smuzhiyun val);
1751*4882a593Smuzhiyun break;
1752*4882a593Smuzhiyun default:
1753*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1754*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
1755*4882a593Smuzhiyun break;
1756*4882a593Smuzhiyun }
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun ctrl_end:
1759*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun return ret;
1762*4882a593Smuzhiyun }
1763*4882a593Smuzhiyun
1764*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sc530ai_ctrl_ops = {
1765*4882a593Smuzhiyun .s_ctrl = sc530ai_set_ctrl,
1766*4882a593Smuzhiyun };
1767*4882a593Smuzhiyun
sc530ai_parse_of(struct sc530ai * sc530ai)1768*4882a593Smuzhiyun static int sc530ai_parse_of(struct sc530ai *sc530ai)
1769*4882a593Smuzhiyun {
1770*4882a593Smuzhiyun struct device *dev = &sc530ai->client->dev;
1771*4882a593Smuzhiyun struct device_node *endpoint;
1772*4882a593Smuzhiyun struct fwnode_handle *fwnode;
1773*4882a593Smuzhiyun int rval;
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1776*4882a593Smuzhiyun if (!endpoint) {
1777*4882a593Smuzhiyun dev_err(dev, "Failed to get endpoint\n");
1778*4882a593Smuzhiyun return -EINVAL;
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun fwnode = of_fwnode_handle(endpoint);
1781*4882a593Smuzhiyun rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1782*4882a593Smuzhiyun if (rval <= 0) {
1783*4882a593Smuzhiyun dev_err(dev, " Get mipi lane num failed!\n");
1784*4882a593Smuzhiyun return -EINVAL;
1785*4882a593Smuzhiyun }
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun sc530ai->lane_num = rval;
1788*4882a593Smuzhiyun dev_info(dev, "lane_num = %d\n", sc530ai->lane_num);
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun if (sc530ai->lane_num == 2) {
1791*4882a593Smuzhiyun sc530ai->support_modes = supported_modes_2lane;
1792*4882a593Smuzhiyun sc530ai->support_modes_num = ARRAY_SIZE(supported_modes_2lane);
1793*4882a593Smuzhiyun } else if (sc530ai->lane_num == 4) {
1794*4882a593Smuzhiyun sc530ai->support_modes = supported_modes_4lane;
1795*4882a593Smuzhiyun sc530ai->support_modes_num = ARRAY_SIZE(supported_modes_4lane);
1796*4882a593Smuzhiyun }
1797*4882a593Smuzhiyun
1798*4882a593Smuzhiyun sc530ai->cur_mode = &sc530ai->support_modes[0];
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun return 0;
1801*4882a593Smuzhiyun }
1802*4882a593Smuzhiyun
sc530ai_initialize_controls(struct sc530ai * sc530ai)1803*4882a593Smuzhiyun static int sc530ai_initialize_controls(struct sc530ai *sc530ai)
1804*4882a593Smuzhiyun {
1805*4882a593Smuzhiyun const struct sc530ai_mode *mode;
1806*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1807*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1808*4882a593Smuzhiyun u64 dst_pixel_rate = 0;
1809*4882a593Smuzhiyun u32 h_blank;
1810*4882a593Smuzhiyun int ret;
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun handler = &sc530ai->ctrl_handler;
1813*4882a593Smuzhiyun mode = sc530ai->cur_mode;
1814*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 8);
1815*4882a593Smuzhiyun if (ret)
1816*4882a593Smuzhiyun return ret;
1817*4882a593Smuzhiyun handler->lock = &sc530ai->mutex;
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun sc530ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1820*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
1821*4882a593Smuzhiyun ARRAY_SIZE(link_freq_items) - 1, 0,
1822*4882a593Smuzhiyun link_freq_items);
1823*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(sc530ai->link_freq, mode->mipi_freq_idx);
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun if (mode->mipi_freq_idx == 0)
1826*4882a593Smuzhiyun dst_pixel_rate = SC530AI_LINEAR_PIXEL_RATES;
1827*4882a593Smuzhiyun else if (mode->mipi_freq_idx == 1)
1828*4882a593Smuzhiyun dst_pixel_rate = SC530AI_HDR_PIXEL_RATES;
1829*4882a593Smuzhiyun else if (mode->mipi_freq_idx == 2)
1830*4882a593Smuzhiyun dst_pixel_rate = SC530AI_LINEAR_PIXEL_RATES_2LAN;
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun sc530ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1833*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE, 0,
1834*4882a593Smuzhiyun SC530AI_MAX_PIXEL_RATE,
1835*4882a593Smuzhiyun 1, dst_pixel_rate);
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1838*4882a593Smuzhiyun sc530ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1839*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1840*4882a593Smuzhiyun if (sc530ai->hblank)
1841*4882a593Smuzhiyun sc530ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1844*4882a593Smuzhiyun sc530ai->vblank = v4l2_ctrl_new_std(handler, &sc530ai_ctrl_ops,
1845*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1846*4882a593Smuzhiyun SC530AI_VTS_MAX - mode->height,
1847*4882a593Smuzhiyun 1, vblank_def);
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun exposure_max = mode->vts_def - 5;
1850*4882a593Smuzhiyun sc530ai->exposure = v4l2_ctrl_new_std(handler, &sc530ai_ctrl_ops,
1851*4882a593Smuzhiyun V4L2_CID_EXPOSURE,
1852*4882a593Smuzhiyun SC530AI_EXPOSURE_MIN,
1853*4882a593Smuzhiyun exposure_max,
1854*4882a593Smuzhiyun SC530AI_EXPOSURE_STEP,
1855*4882a593Smuzhiyun mode->exp_def);
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun sc530ai->anal_gain = v4l2_ctrl_new_std(handler, &sc530ai_ctrl_ops,
1858*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN,
1859*4882a593Smuzhiyun SC530AI_GAIN_MIN,
1860*4882a593Smuzhiyun SC530AI_GAIN_MAX,
1861*4882a593Smuzhiyun SC530AI_GAIN_STEP,
1862*4882a593Smuzhiyun SC530AI_GAIN_DEFAULT);
1863*4882a593Smuzhiyun
1864*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, &sc530ai_ctrl_ops,
1865*4882a593Smuzhiyun V4L2_CID_HFLIP, 0, 1, 1, 0);
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, &sc530ai_ctrl_ops,
1868*4882a593Smuzhiyun V4L2_CID_VFLIP, 0, 1, 1, 0);
1869*4882a593Smuzhiyun
1870*4882a593Smuzhiyun if (handler->error) {
1871*4882a593Smuzhiyun ret = handler->error;
1872*4882a593Smuzhiyun dev_err(&sc530ai->client->dev,
1873*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1874*4882a593Smuzhiyun goto err_free_handler;
1875*4882a593Smuzhiyun }
1876*4882a593Smuzhiyun sc530ai->subdev.ctrl_handler = handler;
1877*4882a593Smuzhiyun sc530ai->has_init_exp = false;
1878*4882a593Smuzhiyun sc530ai->cur_vts = mode->vts_def;
1879*4882a593Smuzhiyun sc530ai->cur_fps = mode->max_fps;
1880*4882a593Smuzhiyun
1881*4882a593Smuzhiyun return 0;
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun err_free_handler:
1884*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1885*4882a593Smuzhiyun return ret;
1886*4882a593Smuzhiyun }
1887*4882a593Smuzhiyun
sc530ai_check_sensor_id(struct sc530ai * sc530ai,struct i2c_client * client)1888*4882a593Smuzhiyun static int sc530ai_check_sensor_id(struct sc530ai *sc530ai,
1889*4882a593Smuzhiyun struct i2c_client *client)
1890*4882a593Smuzhiyun {
1891*4882a593Smuzhiyun struct device *dev = &sc530ai->client->dev;
1892*4882a593Smuzhiyun u32 id = 0;
1893*4882a593Smuzhiyun int ret;
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun ret = sc530ai_read_reg(client, SC530AI_REG_CHIP_ID,
1896*4882a593Smuzhiyun SC530AI_REG_VALUE_16BIT, &id);
1897*4882a593Smuzhiyun if (id != SC530AI_CHIP_ID) {
1898*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1899*4882a593Smuzhiyun return -ENODEV;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun
1902*4882a593Smuzhiyun dev_info(dev, "Detected SC%06x sensor\n", SC530AI_CHIP_ID);
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun return 0;
1905*4882a593Smuzhiyun }
1906*4882a593Smuzhiyun
sc530ai_configure_regulators(struct sc530ai * sc530ai)1907*4882a593Smuzhiyun static int sc530ai_configure_regulators(struct sc530ai *sc530ai)
1908*4882a593Smuzhiyun {
1909*4882a593Smuzhiyun unsigned int i;
1910*4882a593Smuzhiyun
1911*4882a593Smuzhiyun for (i = 0; i < sc530ai_NUM_SUPPLIES; i++)
1912*4882a593Smuzhiyun sc530ai->supplies[i].supply = sc530ai_supply_names[i];
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun return devm_regulator_bulk_get(&sc530ai->client->dev,
1915*4882a593Smuzhiyun sc530ai_NUM_SUPPLIES,
1916*4882a593Smuzhiyun sc530ai->supplies);
1917*4882a593Smuzhiyun }
1918*4882a593Smuzhiyun
sc530ai_probe(struct i2c_client * client,const struct i2c_device_id * id)1919*4882a593Smuzhiyun static int sc530ai_probe(struct i2c_client *client,
1920*4882a593Smuzhiyun const struct i2c_device_id *id)
1921*4882a593Smuzhiyun {
1922*4882a593Smuzhiyun struct device *dev = &client->dev;
1923*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1924*4882a593Smuzhiyun struct sc530ai *sc530ai;
1925*4882a593Smuzhiyun struct v4l2_subdev *sd;
1926*4882a593Smuzhiyun char facing[2];
1927*4882a593Smuzhiyun int ret;
1928*4882a593Smuzhiyun u32 hdr_mode = 0;
1929*4882a593Smuzhiyun
1930*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1931*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1932*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1933*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun sc530ai = devm_kzalloc(dev, sizeof(*sc530ai), GFP_KERNEL);
1936*4882a593Smuzhiyun if (!sc530ai)
1937*4882a593Smuzhiyun return -ENOMEM;
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1940*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1941*4882a593Smuzhiyun &sc530ai->module_index);
1942*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1943*4882a593Smuzhiyun &sc530ai->module_facing);
1944*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1945*4882a593Smuzhiyun &sc530ai->module_name);
1946*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1947*4882a593Smuzhiyun &sc530ai->len_name);
1948*4882a593Smuzhiyun if (ret) {
1949*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1950*4882a593Smuzhiyun return -EINVAL;
1951*4882a593Smuzhiyun }
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun sc530ai->client = client;
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun ret = sc530ai_parse_of(sc530ai);
1956*4882a593Smuzhiyun if (ret)
1957*4882a593Smuzhiyun return -EINVAL;
1958*4882a593Smuzhiyun
1959*4882a593Smuzhiyun sc530ai->xvclk = devm_clk_get(dev, "xvclk");
1960*4882a593Smuzhiyun if (IS_ERR(sc530ai->xvclk)) {
1961*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1962*4882a593Smuzhiyun return -EINVAL;
1963*4882a593Smuzhiyun }
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun sc530ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1966*4882a593Smuzhiyun if (IS_ERR(sc530ai->reset_gpio))
1967*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun sc530ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1970*4882a593Smuzhiyun if (IS_ERR(sc530ai->pwdn_gpio))
1971*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1972*4882a593Smuzhiyun
1973*4882a593Smuzhiyun sc530ai->pinctrl = devm_pinctrl_get(dev);
1974*4882a593Smuzhiyun if (!IS_ERR(sc530ai->pinctrl)) {
1975*4882a593Smuzhiyun sc530ai->pins_default =
1976*4882a593Smuzhiyun pinctrl_lookup_state(sc530ai->pinctrl,
1977*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
1978*4882a593Smuzhiyun if (IS_ERR(sc530ai->pins_default))
1979*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun sc530ai->pins_sleep =
1982*4882a593Smuzhiyun pinctrl_lookup_state(sc530ai->pinctrl,
1983*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
1984*4882a593Smuzhiyun if (IS_ERR(sc530ai->pins_sleep))
1985*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1986*4882a593Smuzhiyun } else {
1987*4882a593Smuzhiyun dev_err(dev, "no pinctrl\n");
1988*4882a593Smuzhiyun }
1989*4882a593Smuzhiyun
1990*4882a593Smuzhiyun ret = sc530ai_configure_regulators(sc530ai);
1991*4882a593Smuzhiyun if (ret) {
1992*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1993*4882a593Smuzhiyun return ret;
1994*4882a593Smuzhiyun }
1995*4882a593Smuzhiyun
1996*4882a593Smuzhiyun mutex_init(&sc530ai->mutex);
1997*4882a593Smuzhiyun
1998*4882a593Smuzhiyun sd = &sc530ai->subdev;
1999*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &sc530ai_subdev_ops);
2000*4882a593Smuzhiyun ret = sc530ai_initialize_controls(sc530ai);
2001*4882a593Smuzhiyun if (ret)
2002*4882a593Smuzhiyun goto err_destroy_mutex;
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun ret = __sc530ai_power_on(sc530ai);
2005*4882a593Smuzhiyun if (ret)
2006*4882a593Smuzhiyun goto err_free_handler;
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun ret = sc530ai_check_sensor_id(sc530ai, client);
2009*4882a593Smuzhiyun if (ret)
2010*4882a593Smuzhiyun goto err_power_off;
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2013*4882a593Smuzhiyun sd->internal_ops = &sc530ai_internal_ops;
2014*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2015*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
2016*4882a593Smuzhiyun #endif
2017*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
2018*4882a593Smuzhiyun sc530ai->pad.flags = MEDIA_PAD_FL_SOURCE;
2019*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2020*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &sc530ai->pad);
2021*4882a593Smuzhiyun if (ret < 0)
2022*4882a593Smuzhiyun goto err_power_off;
2023*4882a593Smuzhiyun #endif
2024*4882a593Smuzhiyun
2025*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
2026*4882a593Smuzhiyun if (strcmp(sc530ai->module_facing, "back") == 0)
2027*4882a593Smuzhiyun facing[0] = 'b';
2028*4882a593Smuzhiyun else
2029*4882a593Smuzhiyun facing[0] = 'f';
2030*4882a593Smuzhiyun
2031*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2032*4882a593Smuzhiyun sc530ai->module_index, facing,
2033*4882a593Smuzhiyun SC530AI_NAME, dev_name(sd->dev));
2034*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
2035*4882a593Smuzhiyun if (ret) {
2036*4882a593Smuzhiyun dev_err(&sc530ai->client->dev,
2037*4882a593Smuzhiyun "v4l2 async register subdev failed\n");
2038*4882a593Smuzhiyun goto err_clean_entity;
2039*4882a593Smuzhiyun }
2040*4882a593Smuzhiyun
2041*4882a593Smuzhiyun pm_runtime_set_active(dev);
2042*4882a593Smuzhiyun pm_runtime_enable(dev);
2043*4882a593Smuzhiyun pm_runtime_idle(dev);
2044*4882a593Smuzhiyun
2045*4882a593Smuzhiyun return 0;
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun err_clean_entity:
2048*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
2049*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
2050*4882a593Smuzhiyun #endif
2051*4882a593Smuzhiyun err_power_off:
2052*4882a593Smuzhiyun __sc530ai_power_off(sc530ai);
2053*4882a593Smuzhiyun err_free_handler:
2054*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc530ai->ctrl_handler);
2055*4882a593Smuzhiyun err_destroy_mutex:
2056*4882a593Smuzhiyun mutex_destroy(&sc530ai->mutex);
2057*4882a593Smuzhiyun
2058*4882a593Smuzhiyun return ret;
2059*4882a593Smuzhiyun }
2060*4882a593Smuzhiyun
sc530ai_remove(struct i2c_client * client)2061*4882a593Smuzhiyun static int sc530ai_remove(struct i2c_client *client)
2062*4882a593Smuzhiyun {
2063*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
2064*4882a593Smuzhiyun struct sc530ai *sc530ai = to_sc530ai(sd);
2065*4882a593Smuzhiyun
2066*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
2067*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
2068*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
2069*4882a593Smuzhiyun #endif
2070*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc530ai->ctrl_handler);
2071*4882a593Smuzhiyun mutex_destroy(&sc530ai->mutex);
2072*4882a593Smuzhiyun
2073*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
2074*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
2075*4882a593Smuzhiyun __sc530ai_power_off(sc530ai);
2076*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
2077*4882a593Smuzhiyun
2078*4882a593Smuzhiyun return 0;
2079*4882a593Smuzhiyun }
2080*4882a593Smuzhiyun
2081*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
2082*4882a593Smuzhiyun static const struct of_device_id sc530ai_of_match[] = {
2083*4882a593Smuzhiyun { .compatible = "smartsens,sc530ai" },
2084*4882a593Smuzhiyun { },
2085*4882a593Smuzhiyun };
2086*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sc530ai_of_match);
2087*4882a593Smuzhiyun #endif
2088*4882a593Smuzhiyun
2089*4882a593Smuzhiyun static const struct i2c_device_id sc530ai_match_id[] = {
2090*4882a593Smuzhiyun { "smartsens,sc530ai", 0 },
2091*4882a593Smuzhiyun { },
2092*4882a593Smuzhiyun };
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun static struct i2c_driver sc530ai_i2c_driver = {
2095*4882a593Smuzhiyun .driver = {
2096*4882a593Smuzhiyun .name = SC530AI_NAME,
2097*4882a593Smuzhiyun .pm = &sc530ai_pm_ops,
2098*4882a593Smuzhiyun .of_match_table = of_match_ptr(sc530ai_of_match),
2099*4882a593Smuzhiyun },
2100*4882a593Smuzhiyun .probe = &sc530ai_probe,
2101*4882a593Smuzhiyun .remove = &sc530ai_remove,
2102*4882a593Smuzhiyun .id_table = sc530ai_match_id,
2103*4882a593Smuzhiyun };
2104*4882a593Smuzhiyun
sensor_mod_init(void)2105*4882a593Smuzhiyun static int __init sensor_mod_init(void)
2106*4882a593Smuzhiyun {
2107*4882a593Smuzhiyun return i2c_add_driver(&sc530ai_i2c_driver);
2108*4882a593Smuzhiyun }
2109*4882a593Smuzhiyun
sensor_mod_exit(void)2110*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
2111*4882a593Smuzhiyun {
2112*4882a593Smuzhiyun i2c_del_driver(&sc530ai_i2c_driver);
2113*4882a593Smuzhiyun }
2114*4882a593Smuzhiyun
2115*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
2116*4882a593Smuzhiyun module_exit(sensor_mod_exit);
2117*4882a593Smuzhiyun
2118*4882a593Smuzhiyun MODULE_DESCRIPTION("smartsens sc530ai sensor driver");
2119*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2120