1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc501ai driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/version.h>
21 #include <linux/rk-camera-module.h>
22 #include <linux/rk-preisp.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
29
30 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
31
32 #ifndef V4L2_CID_DIGITAL_GAIN
33 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34 #endif
35
36 #define SC501AI_LANES 2
37
38 #define SC501AI_LINK_FREQ_396M 396000000 // 792Mbps
39
40 #define SC501AI_PIXEL_RATE_396M_10BIT (SC501AI_LINK_FREQ_396M * 2 * SC501AI_LANES / 10)
41
42 #define SC501AI_XVCLK_FREQ 27000000
43
44 #define SC501AI_CHIP_ID 0xce1f
45 #define SC501AI_REG_CHIP_ID 0x3107
46
47 #define SC501AI_REG_CTRL_MODE 0x0100
48 #define SC501AI_MODE_SW_STANDBY 0x0
49 #define SC501AI_MODE_STREAMING BIT(0)
50
51 #define SC501AI_REG_EXPOSURE_H 0x3e00
52 #define SC501AI_REG_EXPOSURE_M 0x3e01
53 #define SC501AI_REG_EXPOSURE_L 0x3e02
54
55 #define SC501AI_EXPOSURE_MIN 3
56 #define SC501AI_EXPOSURE_STEP 1
57
58 #define SC501AI_REG_DIG_GAIN 0x3e06
59 #define SC501AI_REG_DIG_FINE_GAIN 0x3e07
60 #define SC501AI_REG_ANA_GAIN 0x3e08
61 #define SC501AI_REG_ANA_FINE_GAIN 0x3e09
62
63 #define SC501AI_GAIN_MIN 0x40
64 #define SC501AI_GAIN_MAX 0xc000
65 #define SC501AI_GAIN_STEP 1
66 #define SC501AI_GAIN_DEFAULT 0x40
67
68 #define SC501AI_REG_VTS_H 0x320e
69 #define SC501AI_REG_VTS_L 0x320f
70 #define SC501AI_VTS_MAX 0x7fff
71
72 #define SC501AI_FLIP_MIRROR_REG 0x3221
73 #define SC501AI_FLIP_MASK 0x60
74 #define SC501AI_MIRROR_MASK 0x06
75
76 #define REG_NULL 0xFFFF
77
78 #define SC501AI_REG_VALUE_08BIT 1
79 #define SC501AI_REG_VALUE_16BIT 2
80 #define SC501AI_REG_VALUE_24BIT 3
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84
85 #define SC501AI_NAME "sc501ai"
86
87 #define SC501AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
88 #define SC501AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
89 #define SC501AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
90
91 static const char * const sc501ai_supply_names[] = {
92 "avdd", /* Analog power */
93 "dovdd", /* Digital I/O power */
94 "dvdd", /* Digital core power */
95 };
96
97 #define sc501ai_NUM_SUPPLIES ARRAY_SIZE(sc501ai_supply_names)
98
99 struct regval {
100 u16 addr;
101 u8 val;
102 };
103
104 struct sc501ai_mode {
105 u32 bus_fmt;
106 u32 width;
107 u32 height;
108 struct v4l2_fract max_fps;
109 u32 hts_def;
110 u32 vts_def;
111 u32 exp_def;
112 u32 mipi_freq_idx;
113 u32 bpp;
114 const struct regval *reg_list;
115 u32 vc[PAD_MAX];
116 };
117
118 struct sc501ai {
119 struct i2c_client *client;
120 struct clk *xvclk;
121 struct gpio_desc *reset_gpio;
122 struct gpio_desc *pwdn_gpio;
123 struct regulator_bulk_data supplies[sc501ai_NUM_SUPPLIES];
124
125 struct pinctrl *pinctrl;
126 struct pinctrl_state *pins_default;
127 struct pinctrl_state *pins_sleep;
128
129 struct v4l2_subdev subdev;
130 struct media_pad pad;
131 struct v4l2_ctrl_handler ctrl_handler;
132 struct v4l2_ctrl *exposure;
133 struct v4l2_ctrl *anal_gain;
134 struct v4l2_ctrl *digi_gain;
135 struct v4l2_ctrl *hblank;
136 struct v4l2_ctrl *vblank;
137 struct v4l2_fract cur_fps;
138 struct mutex mutex;
139 bool streaming;
140 bool power_on;
141 const struct sc501ai_mode *cur_mode;
142 u32 module_index;
143 const char *module_facing;
144 const char *module_name;
145 const char *len_name;
146 bool has_init_exp;
147 u32 cur_vts;
148 bool is_thunderboot;
149 bool is_first_streamoff;
150 };
151
152 #define to_sc501ai(sd) container_of(sd, struct sc501ai, subdev)
153
154 /*
155 * Xclk 27Mhz
156 * max_framerate 30fps
157 * mipi_datarate per lane 792Mbps, 2lane
158 */
159 static const struct regval sc501ai_linear_10_2880x1616_regs[] = {
160 {0x0103, 0x01},
161 {0x0100, 0x00},
162 {0x36e9, 0x80},
163 {0x36f9, 0x80},
164 {0x3018, 0x32},
165 {0x3019, 0x0c},
166 {0x301f, 0x0b},
167 {0x3203, 0x02},
168 {0x3207, 0x59},
169 {0x320b, 0x50},
170 {0x3253, 0x0a},
171 {0x3301, 0x0a},
172 {0x3302, 0x18},
173 {0x3303, 0x10},
174 {0x3304, 0x60},
175 {0x3306, 0x60},
176 {0x3308, 0x10},
177 {0x3309, 0x70},
178 {0x330a, 0x00},
179 {0x330b, 0xf0},
180 {0x330d, 0x18},
181 {0x330e, 0x20},
182 {0x330f, 0x02},
183 {0x3310, 0x02},
184 {0x331c, 0x04},
185 {0x331e, 0x51},
186 {0x331f, 0x61},
187 {0x3320, 0x09},
188 {0x3333, 0x10},
189 {0x334c, 0x08},
190 {0x3356, 0x09},
191 {0x3364, 0x17},
192 {0x336d, 0x03},
193 {0x3390, 0x08},
194 {0x3391, 0x18},
195 {0x3392, 0x38},
196 {0x3393, 0x0a},
197 {0x3394, 0x20},
198 {0x3395, 0x20},
199 {0x3396, 0x08},
200 {0x3397, 0x18},
201 {0x3398, 0x38},
202 {0x3399, 0x0a},
203 {0x339a, 0x20},
204 {0x339b, 0x20},
205 {0x339c, 0x20},
206 {0x33ac, 0x10},
207 {0x33ae, 0x10},
208 {0x33af, 0x19},
209 {0x360f, 0x01},
210 {0x3622, 0x03},
211 {0x363a, 0x1f},
212 {0x363c, 0x40},
213 {0x3651, 0x7d},
214 {0x3670, 0x0a},
215 {0x3671, 0x07},
216 {0x3672, 0x17},
217 {0x3673, 0x1e},
218 {0x3674, 0x82},
219 {0x3675, 0x64},
220 {0x3676, 0x66},
221 {0x367a, 0x48},
222 {0x367b, 0x78},
223 {0x367c, 0x58},
224 {0x367d, 0x78},
225 {0x3690, 0x34},
226 {0x3691, 0x34},
227 {0x3692, 0x54},
228 {0x369c, 0x48},
229 {0x369d, 0x78},
230 {0x36ec, 0x0a},
231 {0x3904, 0x04},
232 {0x3908, 0x41},
233 {0x391d, 0x04},
234 {0x39c2, 0x30},
235 {0x3e01, 0xcd},
236 {0x3e02, 0xc0},
237 {0x3e16, 0x00},
238 {0x3e17, 0x80},
239 {0x4500, 0x88},
240 {0x4509, 0x20},
241 {0x4837, 0x14},
242 {0x5799, 0x00},
243 {0x59e0, 0x60},
244 {0x59e1, 0x08},
245 {0x59e2, 0x3f},
246 {0x59e3, 0x18},
247 {0x59e4, 0x18},
248 {0x59e5, 0x3f},
249 {0x59e7, 0x02},
250 {0x59e8, 0x38},
251 {0x59e9, 0x20},
252 {0x59ea, 0x0c},
253 {0x59ec, 0x08},
254 {0x59ed, 0x02},
255 {0x59ee, 0xa0},
256 {0x59ef, 0x08},
257 {0x59f4, 0x18},
258 {0x59f5, 0x10},
259 {0x59f6, 0x0c},
260 {0x59f9, 0x02},
261 {0x59fa, 0x18},
262 {0x59fb, 0x10},
263 {0x59fc, 0x0c},
264 {0x59ff, 0x02},
265 {0x36e9, 0x1c},
266 {0x36f9, 0x24},
267 {REG_NULL, 0x00},
268 };
269
270 static const struct sc501ai_mode supported_modes[] = {
271 {
272 .width = 2880,
273 .height = 1616,
274 .max_fps = {
275 .numerator = 10000,
276 .denominator = 300000,
277 },
278 .exp_def = 0x80,
279 .hts_def = 0xc80,
280 .vts_def = 0x0672,
281 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
282 .reg_list = sc501ai_linear_10_2880x1616_regs,
283 .mipi_freq_idx = 0,
284 .bpp = 10,
285 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
286 },
287 };
288
289 static const s64 link_freq_menu_items[] = {
290 SC501AI_LINK_FREQ_396M
291 };
292
293 /* Write registers up to 4 at a time */
sc501ai_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)294 static int sc501ai_write_reg(struct i2c_client *client, u16 reg,
295 u32 len, u32 val)
296 {
297 u32 buf_i, val_i;
298 u8 buf[6];
299 u8 *val_p;
300 __be32 val_be;
301
302 if (len > 4)
303 return -EINVAL;
304
305 buf[0] = reg >> 8;
306 buf[1] = reg & 0xff;
307
308 val_be = cpu_to_be32(val);
309 val_p = (u8 *)&val_be;
310 buf_i = 2;
311 val_i = 4 - len;
312
313 while (val_i < 4)
314 buf[buf_i++] = val_p[val_i++];
315
316 if (i2c_master_send(client, buf, len + 2) != len + 2)
317 return -EIO;
318
319 return 0;
320 }
321
sc501ai_write_array(struct i2c_client * client,const struct regval * regs)322 static int sc501ai_write_array(struct i2c_client *client,
323 const struct regval *regs)
324 {
325 u32 i;
326 int ret = 0;
327
328 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
329 ret = sc501ai_write_reg(client, regs[i].addr,
330 SC501AI_REG_VALUE_08BIT, regs[i].val);
331
332 return ret;
333 }
334
335 /* Read registers up to 4 at a time */
sc501ai_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)336 static int sc501ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
337 u32 *val)
338 {
339 struct i2c_msg msgs[2];
340 u8 *data_be_p;
341 __be32 data_be = 0;
342 __be16 reg_addr_be = cpu_to_be16(reg);
343 int ret;
344
345 if (len > 4 || !len)
346 return -EINVAL;
347
348 data_be_p = (u8 *)&data_be;
349 /* Write register address */
350 msgs[0].addr = client->addr;
351 msgs[0].flags = 0;
352 msgs[0].len = 2;
353 msgs[0].buf = (u8 *)®_addr_be;
354
355 /* Read data from register */
356 msgs[1].addr = client->addr;
357 msgs[1].flags = I2C_M_RD;
358 msgs[1].len = len;
359 msgs[1].buf = &data_be_p[4 - len];
360
361 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
362 if (ret != ARRAY_SIZE(msgs))
363 return -EIO;
364
365 *val = be32_to_cpu(data_be);
366
367 return 0;
368 }
369
sc501ai_get_reso_dist(const struct sc501ai_mode * mode,struct v4l2_mbus_framefmt * framefmt)370 static int sc501ai_get_reso_dist(const struct sc501ai_mode *mode,
371 struct v4l2_mbus_framefmt *framefmt)
372 {
373 return abs(mode->width - framefmt->width) +
374 abs(mode->height - framefmt->height);
375 }
376
377 static const struct sc501ai_mode *
sc501ai_find_best_fit(struct v4l2_subdev_format * fmt)378 sc501ai_find_best_fit(struct v4l2_subdev_format *fmt)
379 {
380 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
381 int dist;
382 int cur_best_fit = 0;
383 int cur_best_fit_dist = -1;
384 unsigned int i;
385
386 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
387 dist = sc501ai_get_reso_dist(&supported_modes[i], framefmt);
388 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
389 cur_best_fit_dist = dist;
390 cur_best_fit = i;
391 }
392 }
393
394 return &supported_modes[cur_best_fit];
395 }
396
sc501ai_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)397 static int sc501ai_set_fmt(struct v4l2_subdev *sd,
398 struct v4l2_subdev_pad_config *cfg,
399 struct v4l2_subdev_format *fmt)
400 {
401 struct sc501ai *sc501ai = to_sc501ai(sd);
402 const struct sc501ai_mode *mode;
403 s64 h_blank, vblank_def;
404
405 mutex_lock(&sc501ai->mutex);
406
407 mode = sc501ai_find_best_fit(fmt);
408 fmt->format.code = mode->bus_fmt;
409 fmt->format.width = mode->width;
410 fmt->format.height = mode->height;
411 fmt->format.field = V4L2_FIELD_NONE;
412 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
413 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
414 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
415 #else
416 mutex_unlock(&sc501ai->mutex);
417 return -ENOTTY;
418 #endif
419 } else {
420 sc501ai->cur_mode = mode;
421 h_blank = mode->hts_def - mode->width;
422 __v4l2_ctrl_modify_range(sc501ai->hblank, h_blank,
423 h_blank, 1, h_blank);
424 vblank_def = mode->vts_def - mode->height;
425 __v4l2_ctrl_modify_range(sc501ai->vblank, vblank_def,
426 SC501AI_VTS_MAX - mode->height,
427 1, vblank_def);
428 sc501ai->cur_fps = mode->max_fps;
429 }
430
431 mutex_unlock(&sc501ai->mutex);
432
433 return 0;
434 }
435
sc501ai_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)436 static int sc501ai_get_fmt(struct v4l2_subdev *sd,
437 struct v4l2_subdev_pad_config *cfg,
438 struct v4l2_subdev_format *fmt)
439 {
440 struct sc501ai *sc501ai = to_sc501ai(sd);
441 const struct sc501ai_mode *mode = sc501ai->cur_mode;
442
443 mutex_lock(&sc501ai->mutex);
444 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
445 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
446 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
447 #else
448 mutex_unlock(&sc501ai->mutex);
449 return -ENOTTY;
450 #endif
451 } else {
452 fmt->format.width = mode->width;
453 fmt->format.height = mode->height;
454 fmt->format.code = mode->bus_fmt;
455 fmt->format.field = V4L2_FIELD_NONE;
456 /* format info: width/height/data type/virctual channel */
457 fmt->reserved[0] = mode->vc[PAD0];
458 }
459 mutex_unlock(&sc501ai->mutex);
460
461 return 0;
462 }
463
sc501ai_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)464 static int sc501ai_enum_mbus_code(struct v4l2_subdev *sd,
465 struct v4l2_subdev_pad_config *cfg,
466 struct v4l2_subdev_mbus_code_enum *code)
467 {
468 struct sc501ai *sc501ai = to_sc501ai(sd);
469
470 if (code->index != 0)
471 return -EINVAL;
472 code->code = sc501ai->cur_mode->bus_fmt;
473
474 return 0;
475 }
476
sc501ai_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)477 static int sc501ai_enum_frame_sizes(struct v4l2_subdev *sd,
478 struct v4l2_subdev_pad_config *cfg,
479 struct v4l2_subdev_frame_size_enum *fse)
480 {
481 if (fse->index >= ARRAY_SIZE(supported_modes))
482 return -EINVAL;
483
484 if (fse->code != supported_modes[0].bus_fmt)
485 return -EINVAL;
486
487 fse->min_width = supported_modes[fse->index].width;
488 fse->max_width = supported_modes[fse->index].width;
489 fse->max_height = supported_modes[fse->index].height;
490 fse->min_height = supported_modes[fse->index].height;
491
492 return 0;
493 }
494
sc501ai_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)495 static int sc501ai_g_frame_interval(struct v4l2_subdev *sd,
496 struct v4l2_subdev_frame_interval *fi)
497 {
498 struct sc501ai *sc501ai = to_sc501ai(sd);
499 const struct sc501ai_mode *mode = sc501ai->cur_mode;
500
501 if (sc501ai->streaming)
502 fi->interval = sc501ai->cur_fps;
503 else
504 fi->interval = mode->max_fps;
505
506 return 0;
507 }
508
sc501ai_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)509 static int sc501ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
510 struct v4l2_mbus_config *config)
511 {
512 u32 val = 1 << (SC501AI_LANES - 1) |
513 V4L2_MBUS_CSI2_CHANNEL_0 |
514 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
515
516 config->type = V4L2_MBUS_CSI2_DPHY;
517 config->flags = val;
518
519 return 0;
520 }
521
sc501ai_get_module_inf(struct sc501ai * sc501ai,struct rkmodule_inf * inf)522 static void sc501ai_get_module_inf(struct sc501ai *sc501ai,
523 struct rkmodule_inf *inf)
524 {
525 memset(inf, 0, sizeof(*inf));
526 strscpy(inf->base.sensor, SC501AI_NAME, sizeof(inf->base.sensor));
527 strscpy(inf->base.module, sc501ai->module_name,
528 sizeof(inf->base.module));
529 strscpy(inf->base.lens, sc501ai->len_name, sizeof(inf->base.lens));
530 }
531
sc501ai_get_gain_reg(u32 total_gain,u32 * again,u32 * again_fine,u32 * dgain,u32 * dgain_fine)532 static int sc501ai_get_gain_reg(u32 total_gain, u32 *again, u32 *again_fine,
533 u32 *dgain, u32 *dgain_fine)
534 {
535 int ret = 0;
536 u32 step = 0;
537
538 if (total_gain <= 0x60) { /* 1 - 1.5x gain */
539 step = total_gain - 0x40;
540
541 *again = 0x03;
542 *again_fine = step + 0x40;
543 *dgain = 0x00;
544 *dgain_fine = 0x80;
545 } else if (total_gain <= 0xc0) { /* 1.5x - 3x gain */
546 step = (total_gain - 0x60) * 64 / 0x60 - 1;
547
548 *again = 0x23;
549 *again_fine = step + 0x40;
550 *dgain = 0x00;
551 *dgain_fine = 0x80;
552 } else if (total_gain <= 0x180) { /* 3x - 6x gain */
553 step = (total_gain - 0xc0) * 64 / 0xc0 - 1;
554
555 *again = 0x27;
556 *again_fine = step + 0x40;
557 *dgain = 0x00;
558 *dgain_fine = 0x80;
559 } else if (total_gain <= 0x300) { /* 6x - 12x gain */
560 step = (total_gain - 0x180) * 64 / 0x180 - 1;
561
562 *again = 0x2f;
563 *again_fine = step + 0x40;
564 *dgain = 0x00;
565 *dgain_fine = 0x80;
566 } else if (total_gain <= 0x600) { /* 12x - 24x gain */
567 step = (total_gain - 0x300) * 64 / 0x300 - 1;
568
569 *again = 0x3f;
570 *again_fine = step + 0x40;
571 *dgain = 0x00;
572 *dgain_fine = 0x80;
573 } else if (total_gain <= 0xc00) { /* 24x - 48x gain */
574 step = (total_gain - 0x600) * 128 / 0x600 - 1;
575
576 *again = 0x3f;
577 *again_fine = 0x7f;
578 *dgain = 0x00;
579 *dgain_fine = 0x80 + step;
580 } else if (total_gain <= 0x1800) { /* 48x - 96x gain */
581 step = (total_gain - 0xc00) * 128 / 0xc00 - 1;
582
583 *again = 0x3f;
584 *again_fine = 0x7f;
585 *dgain = 0x01;
586 *dgain_fine = 0x80 + step;
587 } else if (total_gain <= 0x3000) { /* 96x - 192x gain */
588 step = (total_gain - 0x1800) * 128 / 0x1800 - 1;
589
590 *again = 0x3f;
591 *again_fine = 0x7f;
592 *dgain = 0x03;
593 *dgain_fine = 0x80 + step;
594 } else if (total_gain <= 0x6000) { /* 192x - 384x gain */
595 step = (total_gain - 0x3000) * 128 / 0x3000 - 1;
596
597 *again = 0x3f;
598 *again_fine = 0x7f;
599 *dgain = 0x07;
600 *dgain_fine = 0x80 + step;
601 } else if (total_gain <= 0xc000) { /* 384x - 768x gain */
602 step = (total_gain - 0x6000) * 128 / 0x6000 - 1;
603
604 *again = 0x3f;
605 *again_fine = 0x7f;
606 *dgain = 0x0f;
607 *dgain_fine = 0x80 + step;
608 }
609 return ret;
610 }
611
sc501ai_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)612 static long sc501ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
613 {
614 struct sc501ai *sc501ai = to_sc501ai(sd);
615
616 long ret = 0;
617 u32 stream = 0;
618
619 switch (cmd) {
620 case RKMODULE_GET_MODULE_INFO:
621 sc501ai_get_module_inf(sc501ai, (struct rkmodule_inf *)arg);
622 break;
623 case RKMODULE_SET_QUICK_STREAM:
624 stream = *((u32 *)arg);
625 if (stream)
626 ret = sc501ai_write_reg(sc501ai->client, SC501AI_REG_CTRL_MODE,
627 SC501AI_REG_VALUE_08BIT, SC501AI_MODE_STREAMING);
628 else
629 ret = sc501ai_write_reg(sc501ai->client, SC501AI_REG_CTRL_MODE,
630 SC501AI_REG_VALUE_08BIT, SC501AI_MODE_SW_STANDBY);
631 break;
632 default:
633 ret = -ENOIOCTLCMD;
634 break;
635 }
636
637 return ret;
638 }
639
640 #ifdef CONFIG_COMPAT
sc501ai_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)641 static long sc501ai_compat_ioctl32(struct v4l2_subdev *sd,
642 unsigned int cmd, unsigned long arg)
643 {
644 void __user *up = compat_ptr(arg);
645 struct rkmodule_inf *inf;
646 long ret = 0;
647 u32 stream = 0;
648
649 switch (cmd) {
650 case RKMODULE_GET_MODULE_INFO:
651 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
652 if (!inf) {
653 ret = -ENOMEM;
654 return ret;
655 }
656
657 ret = sc501ai_ioctl(sd, cmd, inf);
658 if (!ret) {
659 ret = copy_to_user(up, inf, sizeof(*inf));
660 if (ret)
661 ret = -EFAULT;
662 }
663 kfree(inf);
664 break;
665 case RKMODULE_SET_QUICK_STREAM:
666 if (copy_from_user(&stream, up, sizeof(u32)))
667 return -EFAULT;
668
669 ret = sc501ai_ioctl(sd, cmd, &stream);
670 break;
671 default:
672 ret = -ENOIOCTLCMD;
673 break;
674 }
675
676 return ret;
677 }
678 #endif
679
__sc501ai_start_stream(struct sc501ai * sc501ai)680 static int __sc501ai_start_stream(struct sc501ai *sc501ai)
681 {
682 int ret;
683
684 if (!sc501ai->is_thunderboot) {
685 ret = sc501ai_write_array(sc501ai->client, sc501ai->cur_mode->reg_list);
686 if (ret)
687 return ret;
688
689 /* In case these controls are set before streaming */
690 ret = __v4l2_ctrl_handler_setup(&sc501ai->ctrl_handler);
691 if (ret)
692 return ret;
693 }
694
695 return sc501ai_write_reg(sc501ai->client, SC501AI_REG_CTRL_MODE,
696 SC501AI_REG_VALUE_08BIT, SC501AI_MODE_STREAMING);
697 }
698
__sc501ai_stop_stream(struct sc501ai * sc501ai)699 static int __sc501ai_stop_stream(struct sc501ai *sc501ai)
700 {
701 sc501ai->has_init_exp = false;
702 if (sc501ai->is_thunderboot) {
703 sc501ai->is_first_streamoff = true;
704 pm_runtime_put(&sc501ai->client->dev);
705 }
706 return sc501ai_write_reg(sc501ai->client, SC501AI_REG_CTRL_MODE,
707 SC501AI_REG_VALUE_08BIT, SC501AI_MODE_SW_STANDBY);
708 }
709
710 static int __sc501ai_power_on(struct sc501ai *sc501ai);
sc501ai_s_stream(struct v4l2_subdev * sd,int on)711 static int sc501ai_s_stream(struct v4l2_subdev *sd, int on)
712 {
713 struct sc501ai *sc501ai = to_sc501ai(sd);
714 struct i2c_client *client = sc501ai->client;
715 int ret = 0;
716
717 mutex_lock(&sc501ai->mutex);
718 on = !!on;
719 if (on == sc501ai->streaming)
720 goto unlock_and_return;
721
722 if (on) {
723 if (sc501ai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
724 sc501ai->is_thunderboot = false;
725 __sc501ai_power_on(sc501ai);
726 }
727 ret = pm_runtime_get_sync(&client->dev);
728 if (ret < 0) {
729 pm_runtime_put_noidle(&client->dev);
730 goto unlock_and_return;
731 }
732
733 ret = __sc501ai_start_stream(sc501ai);
734 if (ret) {
735 v4l2_err(sd, "start stream failed while write regs\n");
736 pm_runtime_put(&client->dev);
737 goto unlock_and_return;
738 }
739 } else {
740 __sc501ai_stop_stream(sc501ai);
741 pm_runtime_put(&client->dev);
742 }
743
744 sc501ai->streaming = on;
745
746 unlock_and_return:
747 mutex_unlock(&sc501ai->mutex);
748
749 return ret;
750 }
751
sc501ai_s_power(struct v4l2_subdev * sd,int on)752 static int sc501ai_s_power(struct v4l2_subdev *sd, int on)
753 {
754 struct sc501ai *sc501ai = to_sc501ai(sd);
755 struct i2c_client *client = sc501ai->client;
756 int ret = 0;
757
758 mutex_lock(&sc501ai->mutex);
759
760 /* If the power state is not modified - no work to do. */
761 if (sc501ai->power_on == !!on)
762 goto unlock_and_return;
763
764 if (on) {
765 ret = pm_runtime_get_sync(&client->dev);
766 if (ret < 0) {
767 pm_runtime_put_noidle(&client->dev);
768 goto unlock_and_return;
769 }
770
771 sc501ai->power_on = true;
772 } else {
773 pm_runtime_put(&client->dev);
774 sc501ai->power_on = false;
775 }
776
777 unlock_and_return:
778 mutex_unlock(&sc501ai->mutex);
779
780 return ret;
781 }
782
__sc501ai_power_on(struct sc501ai * sc501ai)783 static int __sc501ai_power_on(struct sc501ai *sc501ai)
784 {
785 int ret;
786 struct device *dev = &sc501ai->client->dev;
787
788 if (!IS_ERR_OR_NULL(sc501ai->pins_default)) {
789 ret = pinctrl_select_state(sc501ai->pinctrl,
790 sc501ai->pins_default);
791 if (ret < 0)
792 dev_err(dev, "could not set pins\n");
793 }
794 ret = clk_set_rate(sc501ai->xvclk, SC501AI_XVCLK_FREQ);
795 if (ret < 0)
796 dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
797 if (clk_get_rate(sc501ai->xvclk) != SC501AI_XVCLK_FREQ)
798 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
799 ret = clk_prepare_enable(sc501ai->xvclk);
800 if (ret < 0) {
801 dev_err(dev, "Failed to enable xvclk\n");
802 return ret;
803 }
804
805 if (sc501ai->is_thunderboot)
806 return 0;
807
808 if (!IS_ERR(sc501ai->reset_gpio))
809 gpiod_set_value_cansleep(sc501ai->reset_gpio, 0);
810
811 ret = regulator_bulk_enable(sc501ai_NUM_SUPPLIES, sc501ai->supplies);
812 if (ret < 0) {
813 dev_err(dev, "Failed to enable regulators\n");
814 goto disable_clk;
815 }
816
817 if (!IS_ERR(sc501ai->reset_gpio))
818 gpiod_set_value_cansleep(sc501ai->reset_gpio, 1);
819
820 usleep_range(500, 1000);
821 if (!IS_ERR(sc501ai->pwdn_gpio))
822 gpiod_set_value_cansleep(sc501ai->pwdn_gpio, 1);
823
824 usleep_range(4000, 5000);
825 return 0;
826
827 disable_clk:
828 clk_disable_unprepare(sc501ai->xvclk);
829
830 return ret;
831 }
832
__sc501ai_power_off(struct sc501ai * sc501ai)833 static void __sc501ai_power_off(struct sc501ai *sc501ai)
834 {
835 int ret;
836 struct device *dev = &sc501ai->client->dev;
837
838 clk_disable_unprepare(sc501ai->xvclk);
839 if (sc501ai->is_thunderboot) {
840 if (sc501ai->is_first_streamoff) {
841 sc501ai->is_thunderboot = false;
842 sc501ai->is_first_streamoff = false;
843 } else {
844 return;
845 }
846 }
847
848 if (!IS_ERR(sc501ai->pwdn_gpio))
849 gpiod_set_value_cansleep(sc501ai->pwdn_gpio, 0);
850 clk_disable_unprepare(sc501ai->xvclk);
851 if (!IS_ERR(sc501ai->reset_gpio))
852 gpiod_set_value_cansleep(sc501ai->reset_gpio, 0);
853 if (!IS_ERR_OR_NULL(sc501ai->pins_sleep)) {
854 ret = pinctrl_select_state(sc501ai->pinctrl,
855 sc501ai->pins_sleep);
856 if (ret < 0)
857 dev_dbg(dev, "could not set pins\n");
858 }
859 regulator_bulk_disable(sc501ai_NUM_SUPPLIES, sc501ai->supplies);
860 }
861
sc501ai_runtime_resume(struct device * dev)862 static int sc501ai_runtime_resume(struct device *dev)
863 {
864 struct i2c_client *client = to_i2c_client(dev);
865 struct v4l2_subdev *sd = i2c_get_clientdata(client);
866 struct sc501ai *sc501ai = to_sc501ai(sd);
867
868 return __sc501ai_power_on(sc501ai);
869 }
870
sc501ai_runtime_suspend(struct device * dev)871 static int sc501ai_runtime_suspend(struct device *dev)
872 {
873 struct i2c_client *client = to_i2c_client(dev);
874 struct v4l2_subdev *sd = i2c_get_clientdata(client);
875 struct sc501ai *sc501ai = to_sc501ai(sd);
876
877 __sc501ai_power_off(sc501ai);
878
879 return 0;
880 }
881
882 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc501ai_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)883 static int sc501ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
884 {
885 struct sc501ai *sc501ai = to_sc501ai(sd);
886 struct v4l2_mbus_framefmt *try_fmt =
887 v4l2_subdev_get_try_format(sd, fh->pad, 0);
888 const struct sc501ai_mode *def_mode = &supported_modes[0];
889
890 mutex_lock(&sc501ai->mutex);
891 /* Initialize try_fmt */
892 try_fmt->width = def_mode->width;
893 try_fmt->height = def_mode->height;
894 try_fmt->code = def_mode->bus_fmt;
895 try_fmt->field = V4L2_FIELD_NONE;
896
897 mutex_unlock(&sc501ai->mutex);
898 /* No crop or compose */
899
900 return 0;
901 }
902 #endif
903
sc501ai_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)904 static int sc501ai_enum_frame_interval(struct v4l2_subdev *sd,
905 struct v4l2_subdev_pad_config *cfg,
906 struct v4l2_subdev_frame_interval_enum *fie)
907 {
908 if (fie->index >= ARRAY_SIZE(supported_modes))
909 return -EINVAL;
910
911 fie->code = supported_modes[fie->index].bus_fmt;
912 fie->width = supported_modes[fie->index].width;
913 fie->height = supported_modes[fie->index].height;
914 fie->interval = supported_modes[fie->index].max_fps;
915 fie->reserved[0] = NO_HDR;
916 return 0;
917 }
918
919 static const struct dev_pm_ops sc501ai_pm_ops = {
920 SET_RUNTIME_PM_OPS(sc501ai_runtime_suspend,
921 sc501ai_runtime_resume, NULL)
922 };
923
924 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
925 static const struct v4l2_subdev_internal_ops sc501ai_internal_ops = {
926 .open = sc501ai_open,
927 };
928 #endif
929
930 static const struct v4l2_subdev_core_ops sc501ai_core_ops = {
931 .s_power = sc501ai_s_power,
932 .ioctl = sc501ai_ioctl,
933 #ifdef CONFIG_COMPAT
934 .compat_ioctl32 = sc501ai_compat_ioctl32,
935 #endif
936 };
937
938 static const struct v4l2_subdev_video_ops sc501ai_video_ops = {
939 .s_stream = sc501ai_s_stream,
940 .g_frame_interval = sc501ai_g_frame_interval,
941 };
942
943 static const struct v4l2_subdev_pad_ops sc501ai_pad_ops = {
944 .enum_mbus_code = sc501ai_enum_mbus_code,
945 .enum_frame_size = sc501ai_enum_frame_sizes,
946 .enum_frame_interval = sc501ai_enum_frame_interval,
947 .get_fmt = sc501ai_get_fmt,
948 .set_fmt = sc501ai_set_fmt,
949 .get_mbus_config = sc501ai_g_mbus_config,
950 };
951
952 static const struct v4l2_subdev_ops sc501ai_subdev_ops = {
953 .core = &sc501ai_core_ops,
954 .video = &sc501ai_video_ops,
955 .pad = &sc501ai_pad_ops,
956 };
957
sc501ai_modify_fps_info(struct sc501ai * sc501ai)958 static void sc501ai_modify_fps_info(struct sc501ai *sc501ai)
959 {
960 const struct sc501ai_mode *mode = sc501ai->cur_mode;
961
962 sc501ai->cur_fps.denominator = mode->max_fps.denominator * sc501ai->cur_vts /
963 mode->vts_def;
964 }
sc501ai_set_ctrl(struct v4l2_ctrl * ctrl)965 static int sc501ai_set_ctrl(struct v4l2_ctrl *ctrl)
966 {
967 struct sc501ai *sc501ai = container_of(ctrl->handler,
968 struct sc501ai, ctrl_handler);
969 struct i2c_client *client = sc501ai->client;
970 s64 max;
971 u32 again = 0, again_fine = 0, dgain = 0, dgain_fine = 0;
972 int ret = 0;
973 u32 val = 0, vts = 0;
974 u64 delay_time = 0;
975 u32 cur_fps = 0;
976 u32 def_fps = 0;
977 u32 denominator = 0;
978 u32 numerator = 0;
979
980 /* Propagate change of current control to all related controls */
981 switch (ctrl->id) {
982 case V4L2_CID_VBLANK:
983 /* Update max exposure while meeting expected vblanking */
984 max = sc501ai->cur_mode->height + ctrl->val - 10;
985 __v4l2_ctrl_modify_range(sc501ai->exposure,
986 sc501ai->exposure->minimum, max,
987 sc501ai->exposure->step,
988 sc501ai->exposure->default_value);
989 break;
990 }
991
992 if (!pm_runtime_get_if_in_use(&client->dev))
993 return 0;
994
995 switch (ctrl->id) {
996 case V4L2_CID_EXPOSURE:
997 val = ctrl->val << 1;
998 ret = sc501ai_write_reg(sc501ai->client,
999 SC501AI_REG_EXPOSURE_H,
1000 SC501AI_REG_VALUE_08BIT,
1001 SC501AI_FETCH_EXP_H(val));
1002 ret |= sc501ai_write_reg(sc501ai->client,
1003 SC501AI_REG_EXPOSURE_M,
1004 SC501AI_REG_VALUE_08BIT,
1005 SC501AI_FETCH_EXP_M(val));
1006 ret |= sc501ai_write_reg(sc501ai->client,
1007 SC501AI_REG_EXPOSURE_L,
1008 SC501AI_REG_VALUE_08BIT,
1009 SC501AI_FETCH_EXP_L(val));
1010
1011 dev_dbg(&client->dev, "set exposure 0x%x\n", val);
1012 break;
1013 case V4L2_CID_ANALOGUE_GAIN:
1014 sc501ai_get_gain_reg(ctrl->val, &again, &again_fine, &dgain, &dgain_fine);
1015 ret = sc501ai_write_reg(sc501ai->client,
1016 SC501AI_REG_DIG_GAIN,
1017 SC501AI_REG_VALUE_08BIT,
1018 dgain);
1019 ret |= sc501ai_write_reg(sc501ai->client,
1020 SC501AI_REG_DIG_FINE_GAIN,
1021 SC501AI_REG_VALUE_08BIT,
1022 dgain_fine);
1023 ret |= sc501ai_write_reg(sc501ai->client,
1024 SC501AI_REG_ANA_GAIN,
1025 SC501AI_REG_VALUE_08BIT,
1026 again);
1027 ret |= sc501ai_write_reg(sc501ai->client,
1028 SC501AI_REG_ANA_FINE_GAIN,
1029 SC501AI_REG_VALUE_08BIT,
1030 again_fine);
1031
1032 dev_dbg(&sc501ai->client->dev,
1033 "total_gain:%d again 0x%x, again_fine 0x%x, dgain 0x%x, dgain_fine 0x%x\n",
1034 ctrl->val, again, again_fine, dgain, dgain_fine);
1035 break;
1036 case V4L2_CID_VBLANK:
1037 vts = ctrl->val + sc501ai->cur_mode->height;
1038 ret = sc501ai_write_reg(sc501ai->client,
1039 SC501AI_REG_VTS_H,
1040 SC501AI_REG_VALUE_08BIT,
1041 (vts >> 8) & 0x7f);
1042 ret |= sc501ai_write_reg(sc501ai->client,
1043 SC501AI_REG_VTS_L,
1044 SC501AI_REG_VALUE_08BIT,
1045 vts & 0xff);
1046 sc501ai->cur_vts = vts;
1047 sc501ai_modify_fps_info(sc501ai);
1048 break;
1049 case V4L2_CID_HFLIP:
1050 ret = sc501ai_read_reg(sc501ai->client, SC501AI_FLIP_MIRROR_REG,
1051 SC501AI_REG_VALUE_08BIT, &val);
1052 if (ret)
1053 break;
1054 if (ctrl->val)
1055 val |= SC501AI_MIRROR_MASK;
1056 else
1057 val &= ~SC501AI_MIRROR_MASK;
1058 ret |= sc501ai_write_reg(sc501ai->client, SC501AI_FLIP_MIRROR_REG,
1059 SC501AI_REG_VALUE_08BIT, val);
1060 break;
1061 case V4L2_CID_VFLIP:
1062 ret = sc501ai_read_reg(sc501ai->client,
1063 SC501AI_FLIP_MIRROR_REG,
1064 SC501AI_REG_VALUE_08BIT, &val);
1065 if (ret)
1066 break;
1067 denominator = sc501ai->cur_mode->max_fps.denominator;
1068 numerator = sc501ai->cur_mode->max_fps.numerator;
1069 def_fps = denominator / numerator;
1070 cur_fps = def_fps * sc501ai->cur_mode->vts_def / sc501ai->cur_vts;
1071 if (cur_fps > 25) {
1072 vts = def_fps * sc501ai->cur_mode->vts_def / 25;
1073 ret = sc501ai_write_reg(sc501ai->client,
1074 SC501AI_REG_VTS_H,
1075 SC501AI_REG_VALUE_08BIT,
1076 (vts >> 8) & 0x7f);
1077 ret |= sc501ai_write_reg(sc501ai->client,
1078 SC501AI_REG_VTS_L,
1079 SC501AI_REG_VALUE_08BIT,
1080 vts & 0xff);
1081 delay_time = 1000000 / 25;//one frame interval
1082 delay_time *= 2;
1083 usleep_range(delay_time, delay_time + 1000);
1084 }
1085
1086 if (ctrl->val)
1087 val |= SC501AI_FLIP_MASK;
1088 else
1089 val &= ~SC501AI_FLIP_MASK;
1090
1091 ret |= sc501ai_write_reg(sc501ai->client,
1092 SC501AI_FLIP_MIRROR_REG,
1093 SC501AI_REG_VALUE_08BIT,
1094 val);
1095 if (cur_fps > 25) {
1096 usleep_range(delay_time, delay_time + 1000);
1097 vts = sc501ai->cur_vts;
1098 ret = sc501ai_write_reg(sc501ai->client,
1099 SC501AI_REG_VTS_H,
1100 SC501AI_REG_VALUE_08BIT,
1101 (vts >> 8) & 0x7f);
1102 ret |= sc501ai_write_reg(sc501ai->client,
1103 SC501AI_REG_VTS_L,
1104 SC501AI_REG_VALUE_08BIT,
1105 vts & 0xff);
1106 }
1107 break;
1108 default:
1109 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1110 __func__, ctrl->id, ctrl->val);
1111 break;
1112 }
1113
1114 pm_runtime_put(&client->dev);
1115
1116 return ret;
1117 }
1118
1119 static const struct v4l2_ctrl_ops sc501ai_ctrl_ops = {
1120 .s_ctrl = sc501ai_set_ctrl,
1121 };
1122
sc501ai_initialize_controls(struct sc501ai * sc501ai)1123 static int sc501ai_initialize_controls(struct sc501ai *sc501ai)
1124 {
1125 const struct sc501ai_mode *mode;
1126 struct v4l2_ctrl_handler *handler;
1127 struct v4l2_ctrl *ctrl;
1128 s64 exposure_max, vblank_def;
1129 u32 h_blank;
1130 int ret;
1131
1132 handler = &sc501ai->ctrl_handler;
1133 mode = sc501ai->cur_mode;
1134 ret = v4l2_ctrl_handler_init(handler, 8);
1135 if (ret)
1136 return ret;
1137 handler->lock = &sc501ai->mutex;
1138 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1139 0, 0, link_freq_menu_items);
1140 if (ctrl)
1141 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1142 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1143 0, SC501AI_PIXEL_RATE_396M_10BIT, 1, SC501AI_PIXEL_RATE_396M_10BIT);
1144 h_blank = mode->hts_def - mode->width;
1145
1146 sc501ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1147 h_blank, h_blank, 1, h_blank);
1148 if (sc501ai->hblank)
1149 sc501ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1150 vblank_def = mode->vts_def - mode->height;
1151 sc501ai->cur_vts = mode->vts_def;
1152
1153 sc501ai->vblank = v4l2_ctrl_new_std(handler, &sc501ai_ctrl_ops,
1154 V4L2_CID_VBLANK, vblank_def,
1155 SC501AI_VTS_MAX - mode->height,
1156 1, vblank_def);
1157 exposure_max = mode->vts_def - 10;
1158 sc501ai->exposure = v4l2_ctrl_new_std(handler, &sc501ai_ctrl_ops,
1159 V4L2_CID_EXPOSURE, SC501AI_EXPOSURE_MIN,
1160 exposure_max, SC501AI_EXPOSURE_STEP,
1161 mode->exp_def);
1162 sc501ai->anal_gain = v4l2_ctrl_new_std(handler, &sc501ai_ctrl_ops,
1163 V4L2_CID_ANALOGUE_GAIN, SC501AI_GAIN_MIN,
1164 SC501AI_GAIN_MAX, SC501AI_GAIN_STEP,
1165 SC501AI_GAIN_DEFAULT);
1166
1167 v4l2_ctrl_new_std(handler, &sc501ai_ctrl_ops,
1168 V4L2_CID_HFLIP, 0, 1, 1, 0);
1169
1170 v4l2_ctrl_new_std(handler, &sc501ai_ctrl_ops,
1171 V4L2_CID_VFLIP, 0, 1, 1, 0);
1172 if (handler->error) {
1173 ret = handler->error;
1174 dev_err(&sc501ai->client->dev,
1175 "Failed to init controls(%d)\n", ret);
1176 goto err_free_handler;
1177 }
1178 sc501ai->subdev.ctrl_handler = handler;
1179 sc501ai->has_init_exp = false;
1180 sc501ai->cur_fps = mode->max_fps;
1181
1182 return 0;
1183
1184 err_free_handler:
1185 v4l2_ctrl_handler_free(handler);
1186 return ret;
1187 }
1188
sc501ai_check_sensor_id(struct sc501ai * sc501ai,struct i2c_client * client)1189 static int sc501ai_check_sensor_id(struct sc501ai *sc501ai,
1190 struct i2c_client *client)
1191 {
1192 struct device *dev = &sc501ai->client->dev;
1193 u32 id = 0;
1194 int ret;
1195
1196 if (sc501ai->is_thunderboot) {
1197 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1198 return 0;
1199 }
1200
1201 ret = sc501ai_read_reg(client, SC501AI_REG_CHIP_ID,
1202 SC501AI_REG_VALUE_16BIT, &id);
1203 if (id != SC501AI_CHIP_ID) {
1204 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1205 return -ENODEV;
1206 }
1207
1208 dev_info(dev, "Detected SC%06x sensor\n", SC501AI_CHIP_ID);
1209
1210 return 0;
1211 }
1212
sc501ai_configure_regulators(struct sc501ai * sc501ai)1213 static int sc501ai_configure_regulators(struct sc501ai *sc501ai)
1214 {
1215 unsigned int i;
1216
1217 for (i = 0; i < sc501ai_NUM_SUPPLIES; i++)
1218 sc501ai->supplies[i].supply = sc501ai_supply_names[i];
1219
1220 return devm_regulator_bulk_get(&sc501ai->client->dev,
1221 sc501ai_NUM_SUPPLIES,
1222 sc501ai->supplies);
1223 }
1224
sc501ai_probe(struct i2c_client * client,const struct i2c_device_id * id)1225 static int sc501ai_probe(struct i2c_client *client,
1226 const struct i2c_device_id *id)
1227 {
1228 struct device *dev = &client->dev;
1229 struct device_node *node = dev->of_node;
1230 struct sc501ai *sc501ai;
1231 struct v4l2_subdev *sd;
1232 char facing[2];
1233 int ret;
1234
1235 dev_info(dev, "driver version: %02x.%02x.%02x",
1236 DRIVER_VERSION >> 16,
1237 (DRIVER_VERSION & 0xff00) >> 8,
1238 DRIVER_VERSION & 0x00ff);
1239
1240 sc501ai = devm_kzalloc(dev, sizeof(*sc501ai), GFP_KERNEL);
1241 if (!sc501ai)
1242 return -ENOMEM;
1243
1244 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1245 &sc501ai->module_index);
1246 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1247 &sc501ai->module_facing);
1248 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1249 &sc501ai->module_name);
1250 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1251 &sc501ai->len_name);
1252 if (ret) {
1253 dev_err(dev, "could not get module information!\n");
1254 return -EINVAL;
1255 }
1256
1257 sc501ai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1258
1259 sc501ai->client = client;
1260 sc501ai->cur_mode = &supported_modes[0];
1261
1262 sc501ai->xvclk = devm_clk_get(dev, "xvclk");
1263 if (IS_ERR(sc501ai->xvclk)) {
1264 dev_err(dev, "Failed to get xvclk\n");
1265 return -EINVAL;
1266 }
1267
1268 if (sc501ai->is_thunderboot) {
1269 sc501ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1270 if (IS_ERR(sc501ai->reset_gpio))
1271 dev_warn(dev, "Failed to get reset-gpios\n");
1272
1273 sc501ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1274 if (IS_ERR(sc501ai->pwdn_gpio))
1275 dev_warn(dev, "Failed to get pwdn-gpios\n");
1276 } else {
1277 sc501ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1278 if (IS_ERR(sc501ai->reset_gpio))
1279 dev_warn(dev, "Failed to get reset-gpios\n");
1280
1281 sc501ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1282 if (IS_ERR(sc501ai->pwdn_gpio))
1283 dev_warn(dev, "Failed to get pwdn-gpios\n");
1284 }
1285
1286 sc501ai->pinctrl = devm_pinctrl_get(dev);
1287 if (!IS_ERR(sc501ai->pinctrl)) {
1288 sc501ai->pins_default =
1289 pinctrl_lookup_state(sc501ai->pinctrl,
1290 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1291 if (IS_ERR(sc501ai->pins_default))
1292 dev_err(dev, "could not get default pinstate\n");
1293
1294 sc501ai->pins_sleep =
1295 pinctrl_lookup_state(sc501ai->pinctrl,
1296 OF_CAMERA_PINCTRL_STATE_SLEEP);
1297 if (IS_ERR(sc501ai->pins_sleep))
1298 dev_err(dev, "could not get sleep pinstate\n");
1299 } else {
1300 dev_err(dev, "no pinctrl\n");
1301 }
1302
1303 ret = sc501ai_configure_regulators(sc501ai);
1304 if (ret) {
1305 dev_err(dev, "Failed to get power regulators\n");
1306 return ret;
1307 }
1308
1309 mutex_init(&sc501ai->mutex);
1310
1311 sd = &sc501ai->subdev;
1312 v4l2_i2c_subdev_init(sd, client, &sc501ai_subdev_ops);
1313 ret = sc501ai_initialize_controls(sc501ai);
1314 if (ret)
1315 goto err_destroy_mutex;
1316
1317 ret = __sc501ai_power_on(sc501ai);
1318 if (ret)
1319 goto err_free_handler;
1320
1321 ret = sc501ai_check_sensor_id(sc501ai, client);
1322 if (ret)
1323 goto err_power_off;
1324
1325 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1326 sd->internal_ops = &sc501ai_internal_ops;
1327 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1328 V4L2_SUBDEV_FL_HAS_EVENTS;
1329 #endif
1330 #if defined(CONFIG_MEDIA_CONTROLLER)
1331 sc501ai->pad.flags = MEDIA_PAD_FL_SOURCE;
1332 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1333 ret = media_entity_pads_init(&sd->entity, 1, &sc501ai->pad);
1334 if (ret < 0)
1335 goto err_power_off;
1336 #endif
1337
1338 memset(facing, 0, sizeof(facing));
1339 if (strcmp(sc501ai->module_facing, "back") == 0)
1340 facing[0] = 'b';
1341 else
1342 facing[0] = 'f';
1343
1344 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1345 sc501ai->module_index, facing,
1346 SC501AI_NAME, dev_name(sd->dev));
1347 ret = v4l2_async_register_subdev_sensor_common(sd);
1348 if (ret) {
1349 dev_err(dev, "v4l2 async register subdev failed\n");
1350 goto err_clean_entity;
1351 }
1352
1353 pm_runtime_set_active(dev);
1354 pm_runtime_enable(dev);
1355 if (sc501ai->is_thunderboot)
1356 pm_runtime_get_sync(dev);
1357 else
1358 pm_runtime_idle(dev);
1359
1360 return 0;
1361
1362 err_clean_entity:
1363 #if defined(CONFIG_MEDIA_CONTROLLER)
1364 media_entity_cleanup(&sd->entity);
1365 #endif
1366 err_power_off:
1367 __sc501ai_power_off(sc501ai);
1368 err_free_handler:
1369 v4l2_ctrl_handler_free(&sc501ai->ctrl_handler);
1370 err_destroy_mutex:
1371 mutex_destroy(&sc501ai->mutex);
1372
1373 return ret;
1374 }
1375
sc501ai_remove(struct i2c_client * client)1376 static int sc501ai_remove(struct i2c_client *client)
1377 {
1378 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1379 struct sc501ai *sc501ai = to_sc501ai(sd);
1380
1381 v4l2_async_unregister_subdev(sd);
1382 #if defined(CONFIG_MEDIA_CONTROLLER)
1383 media_entity_cleanup(&sd->entity);
1384 #endif
1385 v4l2_ctrl_handler_free(&sc501ai->ctrl_handler);
1386 mutex_destroy(&sc501ai->mutex);
1387
1388 pm_runtime_disable(&client->dev);
1389 if (!pm_runtime_status_suspended(&client->dev))
1390 __sc501ai_power_off(sc501ai);
1391 pm_runtime_set_suspended(&client->dev);
1392
1393 return 0;
1394 }
1395
1396 #if IS_ENABLED(CONFIG_OF)
1397 static const struct of_device_id sc501ai_of_match[] = {
1398 { .compatible = "smartsens,sc501ai" },
1399 {},
1400 };
1401 MODULE_DEVICE_TABLE(of, sc501ai_of_match);
1402 #endif
1403
1404 static const struct i2c_device_id sc501ai_match_id[] = {
1405 { "smartsens,sc501ai", 0 },
1406 { },
1407 };
1408
1409 static struct i2c_driver sc501ai_i2c_driver = {
1410 .driver = {
1411 .name = SC501AI_NAME,
1412 .pm = &sc501ai_pm_ops,
1413 .of_match_table = of_match_ptr(sc501ai_of_match),
1414 },
1415 .probe = &sc501ai_probe,
1416 .remove = &sc501ai_remove,
1417 .id_table = sc501ai_match_id,
1418 };
1419
sensor_mod_init(void)1420 static int __init sensor_mod_init(void)
1421 {
1422 return i2c_add_driver(&sc501ai_i2c_driver);
1423 }
1424
sensor_mod_exit(void)1425 static void __exit sensor_mod_exit(void)
1426 {
1427 i2c_del_driver(&sc501ai_i2c_driver);
1428 }
1429
1430 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1431 subsys_initcall(sensor_mod_init);
1432 #else
1433 device_initcall_sync(sensor_mod_init);
1434 #endif
1435 module_exit(sensor_mod_exit);
1436
1437 MODULE_DESCRIPTION("smartsens sc501ai sensor driver");
1438 MODULE_LICENSE("GPL");
1439