1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc4336 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 * V0.0X01.0X02 support fastboot
9 */
10
11 //#define DEBUG
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/slab.h>
22 #include <linux/version.h>
23 #include <linux/rk-camera-module.h>
24 #include <linux/rk-preisp.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
29 #include <linux/pinctrl/consumer.h>
30 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define SC4336_LANES 2
39 #define SC4336_BITS_PER_SAMPLE 10
40 #define SC4336_LINK_FREQ_315 315000000
41
42 #define PIXEL_RATE_WITH_315M_10BIT (SC4336_LINK_FREQ_315 * 2 * \
43 SC4336_LANES / SC4336_BITS_PER_SAMPLE)
44 #define SC4336_XVCLK_FREQ 24000000
45
46 #define CHIP_ID 0xdc42
47 #define SC4336_REG_CHIP_ID 0x3107
48
49 #define SC4336_REG_CTRL_MODE 0x0100
50 #define SC4336_MODE_SW_STANDBY 0x0
51 #define SC4336_MODE_STREAMING BIT(0)
52
53 #define SC4336_REG_EXPOSURE_H 0x3e00
54 #define SC4336_REG_EXPOSURE_M 0x3e01
55 #define SC4336_REG_EXPOSURE_L 0x3e02
56 #define SC4336_EXPOSURE_MIN 1
57 #define SC4336_EXPOSURE_STEP 1
58 #define SC4336_VTS_MAX 0x7fff
59
60 #define SC4336_REG_DIG_GAIN 0x3e06
61 #define SC4336_REG_DIG_FINE_GAIN 0x3e07
62 #define SC4336_REG_ANA_GAIN 0x3e09
63 #define SC4336_GAIN_MIN 0x0020
64 #define SC4336_GAIN_MAX (32 * 15 * 32) //32*15*32
65 #define SC4336_GAIN_STEP 1
66 #define SC4336_GAIN_DEFAULT 0x20
67
68
69 #define SC4336_REG_GROUP_HOLD 0x3812
70 #define SC4336_GROUP_HOLD_START 0x00
71 #define SC4336_GROUP_HOLD_END 0x30
72
73 #define SC4336_REG_TEST_PATTERN 0x4501
74 #define SC4336_TEST_PATTERN_BIT_MASK BIT(3)
75
76 #define SC4336_REG_VTS_H 0x320e
77 #define SC4336_REG_VTS_L 0x320f
78
79 #define SC4336_FLIP_MIRROR_REG 0x3221
80
81 #define SC4336_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
82 #define SC4336_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
83 #define SC4336_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
84
85 #define SC4336_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
86 #define SC4336_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
87
88 #define SC4336_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
89 #define SC4336_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
90
91 #define REG_DELAY 0xFFFE
92 #define REG_NULL 0xFFFF
93
94 #define SC4336_REG_VALUE_08BIT 1
95 #define SC4336_REG_VALUE_16BIT 2
96 #define SC4336_REG_VALUE_24BIT 3
97
98 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
99 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
100 #define SC4336_NAME "sc4336"
101
102 static const char * const sc4336_supply_names[] = {
103 "avdd", /* Analog power */
104 "dovdd", /* Digital I/O power */
105 "dvdd", /* Digital core power */
106 };
107
108 #define SC4336_NUM_SUPPLIES ARRAY_SIZE(sc4336_supply_names)
109
110 struct regval {
111 u16 addr;
112 u8 val;
113 };
114
115 struct sc4336_mode {
116 u32 bus_fmt;
117 u32 width;
118 u32 height;
119 struct v4l2_fract max_fps;
120 u32 hts_def;
121 u32 vts_def;
122 u32 exp_def;
123 const struct regval *reg_list;
124 u32 hdr_mode;
125 u32 vc[PAD_MAX];
126 };
127
128 struct sc4336 {
129 struct i2c_client *client;
130 struct clk *xvclk;
131 struct gpio_desc *reset_gpio;
132 struct gpio_desc *pwdn_gpio;
133 struct regulator_bulk_data supplies[SC4336_NUM_SUPPLIES];
134
135 struct pinctrl *pinctrl;
136 struct pinctrl_state *pins_default;
137 struct pinctrl_state *pins_sleep;
138
139 struct v4l2_subdev subdev;
140 struct media_pad pad;
141 struct v4l2_ctrl_handler ctrl_handler;
142 struct v4l2_ctrl *exposure;
143 struct v4l2_ctrl *anal_gain;
144 struct v4l2_ctrl *digi_gain;
145 struct v4l2_ctrl *hblank;
146 struct v4l2_ctrl *vblank;
147 struct v4l2_ctrl *test_pattern;
148 struct mutex mutex;
149 bool streaming;
150 bool power_on;
151 const struct sc4336_mode *cur_mode;
152 struct v4l2_fract cur_fps;
153 u32 module_index;
154 const char *module_facing;
155 const char *module_name;
156 const char *len_name;
157 u32 cur_vts;
158 bool is_thunderboot;
159 bool is_first_streamoff;
160 };
161
162 #define to_sc4336(sd) container_of(sd, struct sc4336, subdev)
163
164 /*
165 * Xclk 24Mhz
166 */
167 static const struct regval sc4336_global_regs[] = {
168 {REG_NULL, 0x00},
169 };
170
171 /*
172 * Xclk 24Mhz
173 * max_framerate 30fps
174 * mipi_datarate per lane 630Mbps, 2lane
175 */
176 static const struct regval sc4336_linear_10_2560x1440_regs[] = {
177 {0x0103, 0x01},
178 {0x36e9, 0x80},
179 {0x37f9, 0x80},
180 {0x301f, 0x03},
181 {0x30b8, 0x44},
182 {0x3253, 0x10},
183 {0x3301, 0x0a},
184 {0x3302, 0xff},
185 {0x3305, 0x00},
186 {0x3306, 0x90},
187 {0x3308, 0x08},
188 {0x330a, 0x01},
189 {0x330b, 0xb0},
190 {0x330d, 0xf0},
191 {0x3333, 0x10},
192 {0x335e, 0x06},
193 {0x335f, 0x0a},
194 {0x3364, 0x5e},
195 {0x337d, 0x0e},
196 {0x338f, 0x20},
197 {0x3390, 0x08},
198 {0x3391, 0x09},
199 {0x3392, 0x0f},
200 {0x3393, 0x18},
201 {0x3394, 0x60},
202 {0x3395, 0xff},
203 {0x3396, 0x08},
204 {0x3397, 0x09},
205 {0x3398, 0x0f},
206 {0x3399, 0x0a},
207 {0x339a, 0x18},
208 {0x339b, 0x60},
209 {0x339c, 0xff},
210 {0x33a2, 0x04},
211 {0x33ad, 0x0c},
212 {0x33b2, 0x40},
213 {0x33b3, 0x30},
214 {0x33f8, 0x00},
215 {0x33f9, 0xa0},
216 {0x33fa, 0x00},
217 {0x33fb, 0xe0},
218 {0x33fc, 0x09},
219 {0x33fd, 0x1f},
220 {0x349f, 0x03},
221 {0x34a6, 0x09},
222 {0x34a7, 0x1f},
223 {0x34a8, 0x28},
224 {0x34a9, 0x28},
225 {0x34aa, 0x01},
226 {0x34ab, 0xd0},
227 {0x34ac, 0x02},
228 {0x34ad, 0x10},
229 {0x34f8, 0x1f},
230 {0x34f9, 0x20},
231 {0x3630, 0xc0},
232 {0x3631, 0x84},
233 {0x3633, 0x44},
234 {0x3637, 0x4c},
235 {0x3641, 0x38},
236 {0x3670, 0x56},
237 {0x3674, 0xc0},
238 {0x3675, 0xa0},
239 {0x3676, 0xa0},
240 {0x3677, 0x84},
241 {0x3678, 0x88},
242 {0x3679, 0x8d},
243 {0x367c, 0x09},
244 {0x367d, 0x0b},
245 {0x367e, 0x08},
246 {0x367f, 0x0f},
247 {0x3696, 0x44},
248 {0x3697, 0x54},
249 {0x3698, 0x54},
250 {0x36a0, 0x0f},
251 {0x36a1, 0x1f},
252 {0x36b0, 0x81},
253 {0x36b1, 0x83},
254 {0x36b2, 0x85},
255 {0x36b3, 0x8b},
256 {0x36b4, 0x09},
257 {0x36b5, 0x0b},
258 {0x36b6, 0x0f},
259 {0x36ea, 0x07},
260 {0x36eb, 0x04},
261 {0x36ec, 0x0c},
262 {0x36ed, 0xaa},
263 {0x370f, 0x01},
264 {0x3722, 0x09},
265 {0x3724, 0x21},
266 {0x3771, 0x09},
267 {0x3772, 0x05},
268 {0x3773, 0x05},
269 {0x377a, 0x0f},
270 {0x377b, 0x1f},
271 {0x37fa, 0x07},
272 {0x37fb, 0x31},
273 {0x37fc, 0x11},
274 {0x37fd, 0x16},
275 {0x3905, 0x8c},
276 {0x391d, 0x04},
277 {0x3926, 0x21},
278 {0x3933, 0x80},
279 {0x3934, 0x03},
280 {0x3935, 0x00},
281 {0x3936, 0x08},
282 {0x3937, 0x74},
283 {0x3938, 0x6f},
284 {0x3939, 0x00},
285 {0x393a, 0x00},
286 {0x39dc, 0x02},
287 {0x3e00, 0x00},
288 {0x3e01, 0x5d},
289 {0x3e02, 0x40},
290 {0x440e, 0x02},
291 {0x4509, 0x28},
292 {0x450d, 0x32},
293 {0x5000, 0x06},
294 {0x5799, 0x46},
295 {0x579a, 0x77},
296 {0x57d9, 0x46},
297 {0x57da, 0x77},
298 {0x5ae0, 0xfe},
299 {0x5ae1, 0x40},
300 {0x5ae2, 0x38},
301 {0x5ae3, 0x30},
302 {0x5ae4, 0x28},
303 {0x5ae5, 0x38},
304 {0x5ae6, 0x30},
305 {0x5ae7, 0x28},
306 {0x5ae8, 0x3f},
307 {0x5ae9, 0x34},
308 {0x5aea, 0x2c},
309 {0x5aeb, 0x3f},
310 {0x5aec, 0x34},
311 {0x5aed, 0x2c},
312 {0x36e9, 0x53},
313 {0x37f9, 0x23},
314 {0x320e, 0x07},
315 {0x320f, 0x08},
316 {REG_NULL, 0x00},
317 };
318
319 static const struct sc4336_mode supported_modes[] = {
320 {
321 .width = 2560,
322 .height = 1440,
323 .max_fps = {
324 .numerator = 10000,
325 .denominator = 250000,
326 },
327 .exp_def = 0x0080,
328 .hts_def = 0x0578 * 2,
329 .vts_def = 0x0708,
330 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
331 .reg_list = sc4336_linear_10_2560x1440_regs,
332 .hdr_mode = NO_HDR,
333 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
334 }
335 };
336
337 static const s64 link_freq_menu_items[] = {
338 SC4336_LINK_FREQ_315
339 };
340
341 static const char * const sc4336_test_pattern_menu[] = {
342 "Disabled",
343 "Vertical Color Bar Type 1",
344 "Vertical Color Bar Type 2",
345 "Vertical Color Bar Type 3",
346 "Vertical Color Bar Type 4"
347 };
348
349 /* Write registers up to 4 at a time */
sc4336_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)350 static int sc4336_write_reg(struct i2c_client *client, u16 reg,
351 u32 len, u32 val)
352 {
353 u32 buf_i, val_i;
354 u8 buf[6];
355 u8 *val_p;
356 __be32 val_be;
357
358 if (len > 4)
359 return -EINVAL;
360
361 buf[0] = reg >> 8;
362 buf[1] = reg & 0xff;
363
364 val_be = cpu_to_be32(val);
365 val_p = (u8 *)&val_be;
366 buf_i = 2;
367 val_i = 4 - len;
368
369 while (val_i < 4)
370 buf[buf_i++] = val_p[val_i++];
371
372 if (i2c_master_send(client, buf, len + 2) != len + 2)
373 return -EIO;
374 return 0;
375 }
376
sc4336_write_array(struct i2c_client * client,const struct regval * regs)377 static int sc4336_write_array(struct i2c_client *client,
378 const struct regval *regs)
379 {
380 u32 i;
381 int ret = 0;
382
383 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
384 ret = sc4336_write_reg(client, regs[i].addr,
385 SC4336_REG_VALUE_08BIT, regs[i].val);
386
387 return ret;
388 }
389
390 /* Read registers up to 4 at a time */
sc4336_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)391 static int sc4336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
392 u32 *val)
393 {
394 struct i2c_msg msgs[2];
395 u8 *data_be_p;
396 __be32 data_be = 0;
397 __be16 reg_addr_be = cpu_to_be16(reg);
398 int ret;
399
400 if (len > 4 || !len)
401 return -EINVAL;
402
403 data_be_p = (u8 *)&data_be;
404 /* Write register address */
405 msgs[0].addr = client->addr;
406 msgs[0].flags = 0;
407 msgs[0].len = 2;
408 msgs[0].buf = (u8 *)®_addr_be;
409
410 /* Read data from register */
411 msgs[1].addr = client->addr;
412 msgs[1].flags = I2C_M_RD;
413 msgs[1].len = len;
414 msgs[1].buf = &data_be_p[4 - len];
415
416 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
417 if (ret != ARRAY_SIZE(msgs))
418 return -EIO;
419
420 *val = be32_to_cpu(data_be);
421
422 return 0;
423 }
424
sc4336_set_gain_reg(struct sc4336 * sc4336,u32 gain)425 static int sc4336_set_gain_reg(struct sc4336 *sc4336, u32 gain)
426 {
427 u32 coarse_again = 0, coarse_dgian = 0, fine_dgian = 0;
428 u32 gain_factor;
429 int ret = 0;
430
431 if (gain < 32)
432 gain = 32;
433 else if (gain > SC4336_GAIN_MAX)
434 gain = SC4336_GAIN_MAX;
435
436 gain_factor = gain * 1000 / 32;
437 if (gain_factor < 2000) {
438 coarse_again = 0x00;
439 coarse_dgian = 0x00;
440 fine_dgian = gain_factor * 128 / 1000;
441 } else if (gain_factor < 4000) {
442 coarse_again = 0x08;
443 coarse_dgian = 0x00;
444 fine_dgian = gain_factor * 128 / 2000;
445 } else if (gain_factor < 8000) {
446 coarse_again = 0x09;
447 coarse_dgian = 0x00;
448 fine_dgian = gain_factor * 128 / 4000;
449 } else if (gain_factor < 16000) {
450 coarse_again = 0x0b;
451 coarse_dgian = 0x00;
452 fine_dgian = gain_factor * 128 / 8000;
453 } else if (gain_factor < 32000) {
454 coarse_again = 0x0f;
455 coarse_dgian = 0x00;
456 fine_dgian = gain_factor * 128 / 16000;
457 } else if (gain_factor < 32000 * 2) {
458 coarse_again = 0x1f;
459 coarse_dgian = 0x00;
460 fine_dgian = gain_factor * 128 / 32000;
461 } else if (gain_factor < 32000 * 4) {
462 //open dgain begin max digital gain 4X
463 coarse_again = 0x1f;
464 coarse_dgian = 0x01;
465 fine_dgian = gain_factor * 128 / 32000 / 2;
466 } else if (gain_factor < 32000 * 8) {
467 coarse_again = 0x1f;
468 coarse_dgian = 0x03;
469 fine_dgian = gain_factor * 128 / 32000 / 4;
470 } else if (gain_factor < 32000 * 15) {
471 coarse_again = 0x1f;
472 coarse_dgian = 0x07;
473 fine_dgian = gain_factor * 128 / 32000 / 8;
474 } else {
475 coarse_again = 0x1f;
476 coarse_dgian = 0x07;
477 fine_dgian = 0xf0;
478 }
479
480 ret = sc4336_write_reg(sc4336->client,
481 SC4336_REG_DIG_GAIN,
482 SC4336_REG_VALUE_08BIT,
483 coarse_dgian);
484 ret |= sc4336_write_reg(sc4336->client,
485 SC4336_REG_DIG_FINE_GAIN,
486 SC4336_REG_VALUE_08BIT,
487 fine_dgian);
488 ret |= sc4336_write_reg(sc4336->client,
489 SC4336_REG_ANA_GAIN,
490 SC4336_REG_VALUE_08BIT,
491 coarse_again);
492
493 return ret;
494 }
495
sc4336_get_reso_dist(const struct sc4336_mode * mode,struct v4l2_mbus_framefmt * framefmt)496 static int sc4336_get_reso_dist(const struct sc4336_mode *mode,
497 struct v4l2_mbus_framefmt *framefmt)
498 {
499 return abs(mode->width - framefmt->width) +
500 abs(mode->height - framefmt->height);
501 }
502
503 static const struct sc4336_mode *
sc4336_find_best_fit(struct v4l2_subdev_format * fmt)504 sc4336_find_best_fit(struct v4l2_subdev_format *fmt)
505 {
506 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
507 int dist;
508 int cur_best_fit = 0;
509 int cur_best_fit_dist = -1;
510 unsigned int i;
511
512 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
513 dist = sc4336_get_reso_dist(&supported_modes[i], framefmt);
514 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
515 cur_best_fit_dist = dist;
516 cur_best_fit = i;
517 }
518 }
519
520 return &supported_modes[cur_best_fit];
521 }
522
sc4336_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)523 static int sc4336_set_fmt(struct v4l2_subdev *sd,
524 struct v4l2_subdev_pad_config *cfg,
525 struct v4l2_subdev_format *fmt)
526 {
527 struct sc4336 *sc4336 = to_sc4336(sd);
528 const struct sc4336_mode *mode;
529 s64 h_blank, vblank_def;
530
531 mutex_lock(&sc4336->mutex);
532
533 mode = sc4336_find_best_fit(fmt);
534 fmt->format.code = mode->bus_fmt;
535 fmt->format.width = mode->width;
536 fmt->format.height = mode->height;
537 fmt->format.field = V4L2_FIELD_NONE;
538 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
539 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
540 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
541 #else
542 mutex_unlock(&sc4336->mutex);
543 return -ENOTTY;
544 #endif
545 } else {
546 sc4336->cur_mode = mode;
547 h_blank = mode->hts_def - mode->width;
548 __v4l2_ctrl_modify_range(sc4336->hblank, h_blank,
549 h_blank, 1, h_blank);
550 vblank_def = mode->vts_def - mode->height;
551 __v4l2_ctrl_modify_range(sc4336->vblank, vblank_def,
552 SC4336_VTS_MAX - mode->height,
553 1, vblank_def);
554 sc4336->cur_fps = mode->max_fps;
555 }
556
557 mutex_unlock(&sc4336->mutex);
558
559 return 0;
560 }
561
sc4336_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)562 static int sc4336_get_fmt(struct v4l2_subdev *sd,
563 struct v4l2_subdev_pad_config *cfg,
564 struct v4l2_subdev_format *fmt)
565 {
566 struct sc4336 *sc4336 = to_sc4336(sd);
567 const struct sc4336_mode *mode = sc4336->cur_mode;
568
569 mutex_lock(&sc4336->mutex);
570 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
571 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
572 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
573 #else
574 mutex_unlock(&sc4336->mutex);
575 return -ENOTTY;
576 #endif
577 } else {
578 fmt->format.width = mode->width;
579 fmt->format.height = mode->height;
580 fmt->format.code = mode->bus_fmt;
581 fmt->format.field = V4L2_FIELD_NONE;
582 /* format info: width/height/data type/virctual channel */
583 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
584 fmt->reserved[0] = mode->vc[fmt->pad];
585 else
586 fmt->reserved[0] = mode->vc[PAD0];
587 }
588 mutex_unlock(&sc4336->mutex);
589
590 return 0;
591 }
592
sc4336_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)593 static int sc4336_enum_mbus_code(struct v4l2_subdev *sd,
594 struct v4l2_subdev_pad_config *cfg,
595 struct v4l2_subdev_mbus_code_enum *code)
596 {
597 struct sc4336 *sc4336 = to_sc4336(sd);
598
599 if (code->index != 0)
600 return -EINVAL;
601 code->code = sc4336->cur_mode->bus_fmt;
602
603 return 0;
604 }
605
sc4336_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)606 static int sc4336_enum_frame_sizes(struct v4l2_subdev *sd,
607 struct v4l2_subdev_pad_config *cfg,
608 struct v4l2_subdev_frame_size_enum *fse)
609 {
610 if (fse->index >= ARRAY_SIZE(supported_modes))
611 return -EINVAL;
612
613 if (fse->code != supported_modes[0].bus_fmt)
614 return -EINVAL;
615
616 fse->min_width = supported_modes[fse->index].width;
617 fse->max_width = supported_modes[fse->index].width;
618 fse->max_height = supported_modes[fse->index].height;
619 fse->min_height = supported_modes[fse->index].height;
620
621 return 0;
622 }
623
sc4336_enable_test_pattern(struct sc4336 * sc4336,u32 pattern)624 static int sc4336_enable_test_pattern(struct sc4336 *sc4336, u32 pattern)
625 {
626 u32 val = 0;
627 int ret = 0;
628
629 ret = sc4336_read_reg(sc4336->client, SC4336_REG_TEST_PATTERN,
630 SC4336_REG_VALUE_08BIT, &val);
631 if (pattern)
632 val |= SC4336_TEST_PATTERN_BIT_MASK;
633 else
634 val &= ~SC4336_TEST_PATTERN_BIT_MASK;
635
636 ret |= sc4336_write_reg(sc4336->client, SC4336_REG_TEST_PATTERN,
637 SC4336_REG_VALUE_08BIT, val);
638 return ret;
639 }
640
sc4336_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)641 static int sc4336_g_frame_interval(struct v4l2_subdev *sd,
642 struct v4l2_subdev_frame_interval *fi)
643 {
644 struct sc4336 *sc4336 = to_sc4336(sd);
645 const struct sc4336_mode *mode = sc4336->cur_mode;
646
647 if (sc4336->streaming)
648 fi->interval = sc4336->cur_fps;
649 else
650 fi->interval = mode->max_fps;
651
652 return 0;
653 }
654
sc4336_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)655 static int sc4336_g_mbus_config(struct v4l2_subdev *sd,
656 unsigned int pad_id,
657 struct v4l2_mbus_config *config)
658 {
659 struct sc4336 *sc4336 = to_sc4336(sd);
660 const struct sc4336_mode *mode = sc4336->cur_mode;
661 u32 val = 1 << (SC4336_LANES - 1) |
662 V4L2_MBUS_CSI2_CHANNEL_0 |
663 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
664
665 if (mode->hdr_mode != NO_HDR)
666 val |= V4L2_MBUS_CSI2_CHANNEL_1;
667 if (mode->hdr_mode == HDR_X3)
668 val |= V4L2_MBUS_CSI2_CHANNEL_2;
669
670 config->type = V4L2_MBUS_CSI2_DPHY;
671 config->flags = val;
672
673 return 0;
674 }
675
sc4336_get_module_inf(struct sc4336 * sc4336,struct rkmodule_inf * inf)676 static void sc4336_get_module_inf(struct sc4336 *sc4336,
677 struct rkmodule_inf *inf)
678 {
679 memset(inf, 0, sizeof(*inf));
680 strscpy(inf->base.sensor, SC4336_NAME, sizeof(inf->base.sensor));
681 strscpy(inf->base.module, sc4336->module_name,
682 sizeof(inf->base.module));
683 strscpy(inf->base.lens, sc4336->len_name, sizeof(inf->base.lens));
684 }
685
sc4336_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)686 static long sc4336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
687 {
688 struct sc4336 *sc4336 = to_sc4336(sd);
689 struct rkmodule_hdr_cfg *hdr;
690 u32 i, h, w;
691 long ret = 0;
692 u32 stream = 0;
693
694 switch (cmd) {
695 case RKMODULE_GET_MODULE_INFO:
696 sc4336_get_module_inf(sc4336, (struct rkmodule_inf *)arg);
697 break;
698 case RKMODULE_GET_HDR_CFG:
699 hdr = (struct rkmodule_hdr_cfg *)arg;
700 hdr->esp.mode = HDR_NORMAL_VC;
701 hdr->hdr_mode = sc4336->cur_mode->hdr_mode;
702 break;
703 case RKMODULE_SET_HDR_CFG:
704 hdr = (struct rkmodule_hdr_cfg *)arg;
705 w = sc4336->cur_mode->width;
706 h = sc4336->cur_mode->height;
707 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
708 if (w == supported_modes[i].width &&
709 h == supported_modes[i].height &&
710 supported_modes[i].hdr_mode == hdr->hdr_mode) {
711 sc4336->cur_mode = &supported_modes[i];
712 break;
713 }
714 }
715 if (i == ARRAY_SIZE(supported_modes)) {
716 dev_err(&sc4336->client->dev,
717 "not find hdr mode:%d %dx%d config\n",
718 hdr->hdr_mode, w, h);
719 ret = -EINVAL;
720 } else {
721 w = sc4336->cur_mode->hts_def - sc4336->cur_mode->width;
722 h = sc4336->cur_mode->vts_def - sc4336->cur_mode->height;
723 __v4l2_ctrl_modify_range(sc4336->hblank, w, w, 1, w);
724 __v4l2_ctrl_modify_range(sc4336->vblank, h,
725 SC4336_VTS_MAX - sc4336->cur_mode->height, 1, h);
726 }
727 break;
728 case PREISP_CMD_SET_HDRAE_EXP:
729 break;
730 case RKMODULE_SET_QUICK_STREAM:
731
732 stream = *((u32 *)arg);
733
734 if (stream)
735 ret = sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
736 SC4336_REG_VALUE_08BIT, SC4336_MODE_STREAMING);
737 else
738 ret = sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
739 SC4336_REG_VALUE_08BIT, SC4336_MODE_SW_STANDBY);
740 break;
741 default:
742 ret = -ENOIOCTLCMD;
743 break;
744 }
745
746 return ret;
747 }
748
749 #ifdef CONFIG_COMPAT
sc4336_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)750 static long sc4336_compat_ioctl32(struct v4l2_subdev *sd,
751 unsigned int cmd, unsigned long arg)
752 {
753 void __user *up = compat_ptr(arg);
754 struct rkmodule_inf *inf;
755 struct rkmodule_hdr_cfg *hdr;
756 struct preisp_hdrae_exp_s *hdrae;
757 long ret;
758 u32 stream = 0;
759
760 switch (cmd) {
761 case RKMODULE_GET_MODULE_INFO:
762 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
763 if (!inf) {
764 ret = -ENOMEM;
765 return ret;
766 }
767
768 ret = sc4336_ioctl(sd, cmd, inf);
769 if (!ret) {
770 if (copy_to_user(up, inf, sizeof(*inf)))
771 ret = -EFAULT;
772 }
773 kfree(inf);
774 break;
775 case RKMODULE_GET_HDR_CFG:
776 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
777 if (!hdr) {
778 ret = -ENOMEM;
779 return ret;
780 }
781
782 ret = sc4336_ioctl(sd, cmd, hdr);
783 if (!ret) {
784 if (copy_to_user(up, hdr, sizeof(*hdr)))
785 ret = -EFAULT;
786 }
787 kfree(hdr);
788 break;
789 case RKMODULE_SET_HDR_CFG:
790 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
791 if (!hdr) {
792 ret = -ENOMEM;
793 return ret;
794 }
795
796 ret = copy_from_user(hdr, up, sizeof(*hdr));
797 if (!ret)
798 ret = sc4336_ioctl(sd, cmd, hdr);
799 else
800 ret = -EFAULT;
801 kfree(hdr);
802 break;
803 case PREISP_CMD_SET_HDRAE_EXP:
804 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
805 if (!hdrae) {
806 ret = -ENOMEM;
807 return ret;
808 }
809
810 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
811 if (!ret)
812 ret = sc4336_ioctl(sd, cmd, hdrae);
813 else
814 ret = -EFAULT;
815 kfree(hdrae);
816 break;
817 case RKMODULE_SET_QUICK_STREAM:
818 ret = copy_from_user(&stream, up, sizeof(u32));
819 if (!ret)
820 ret = sc4336_ioctl(sd, cmd, &stream);
821 else
822 ret = -EFAULT;
823 break;
824 default:
825 ret = -ENOIOCTLCMD;
826 break;
827 }
828
829 return ret;
830 }
831 #endif
832
__sc4336_start_stream(struct sc4336 * sc4336)833 static int __sc4336_start_stream(struct sc4336 *sc4336)
834 {
835 int ret;
836 if (!sc4336->is_thunderboot) {
837 ret = sc4336_write_array(sc4336->client, sc4336->cur_mode->reg_list);
838 if (ret)
839 return ret;
840
841 /* In case these controls are set before streaming */
842 ret = __v4l2_ctrl_handler_setup(&sc4336->ctrl_handler);
843 if (ret)
844 return ret;
845 }
846
847 return sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
848 SC4336_REG_VALUE_08BIT, SC4336_MODE_STREAMING);
849 }
850
__sc4336_stop_stream(struct sc4336 * sc4336)851 static int __sc4336_stop_stream(struct sc4336 *sc4336)
852 {
853 if (sc4336->is_thunderboot) {
854 sc4336->is_first_streamoff = true;
855 pm_runtime_put(&sc4336->client->dev);
856 }
857 return sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
858 SC4336_REG_VALUE_08BIT, SC4336_MODE_SW_STANDBY);
859 }
860
861 static int __sc4336_power_on(struct sc4336 *sc4336);
sc4336_s_stream(struct v4l2_subdev * sd,int on)862 static int sc4336_s_stream(struct v4l2_subdev *sd, int on)
863 {
864 struct sc4336 *sc4336 = to_sc4336(sd);
865 struct i2c_client *client = sc4336->client;
866 int ret = 0;
867
868 mutex_lock(&sc4336->mutex);
869 on = !!on;
870 if (on == sc4336->streaming)
871 goto unlock_and_return;
872
873 if (on) {
874 if (sc4336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
875 sc4336->is_thunderboot = false;
876 __sc4336_power_on(sc4336);
877 }
878
879 ret = pm_runtime_get_sync(&client->dev);
880 if (ret < 0) {
881 pm_runtime_put_noidle(&client->dev);
882 goto unlock_and_return;
883 }
884
885 ret = __sc4336_start_stream(sc4336);
886 if (ret) {
887 v4l2_err(sd, "start stream failed while write regs\n");
888 pm_runtime_put(&client->dev);
889 goto unlock_and_return;
890 }
891 } else {
892 __sc4336_stop_stream(sc4336);
893 pm_runtime_put(&client->dev);
894 }
895
896 sc4336->streaming = on;
897
898 unlock_and_return:
899 mutex_unlock(&sc4336->mutex);
900
901 return ret;
902 }
903
sc4336_s_power(struct v4l2_subdev * sd,int on)904 static int sc4336_s_power(struct v4l2_subdev *sd, int on)
905 {
906 struct sc4336 *sc4336 = to_sc4336(sd);
907 struct i2c_client *client = sc4336->client;
908 int ret = 0;
909
910 mutex_lock(&sc4336->mutex);
911
912 /* If the power state is not modified - no work to do. */
913 if (sc4336->power_on == !!on)
914 goto unlock_and_return;
915
916 if (on) {
917 ret = pm_runtime_get_sync(&client->dev);
918 if (ret < 0) {
919 pm_runtime_put_noidle(&client->dev);
920 goto unlock_and_return;
921 }
922
923 if (!sc4336->is_thunderboot) {
924 ret = sc4336_write_array(sc4336->client, sc4336_global_regs);
925 if (ret) {
926 v4l2_err(sd, "could not set init registers\n");
927 pm_runtime_put_noidle(&client->dev);
928 goto unlock_and_return;
929 }
930 }
931
932 sc4336->power_on = true;
933 } else {
934 pm_runtime_put(&client->dev);
935 sc4336->power_on = false;
936 }
937
938 unlock_and_return:
939 mutex_unlock(&sc4336->mutex);
940
941 return ret;
942 }
943
944 /* Calculate the delay in us by clock rate and clock cycles */
sc4336_cal_delay(u32 cycles)945 static inline u32 sc4336_cal_delay(u32 cycles)
946 {
947 return DIV_ROUND_UP(cycles, SC4336_XVCLK_FREQ / 1000 / 1000);
948 }
949
__sc4336_power_on(struct sc4336 * sc4336)950 static int __sc4336_power_on(struct sc4336 *sc4336)
951 {
952 int ret;
953 u32 delay_us;
954 struct device *dev = &sc4336->client->dev;
955
956 if (!IS_ERR_OR_NULL(sc4336->pins_default)) {
957 ret = pinctrl_select_state(sc4336->pinctrl,
958 sc4336->pins_default);
959 if (ret < 0)
960 dev_err(dev, "could not set pins\n");
961 }
962 ret = clk_set_rate(sc4336->xvclk, SC4336_XVCLK_FREQ);
963 if (ret < 0)
964 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
965 if (clk_get_rate(sc4336->xvclk) != SC4336_XVCLK_FREQ)
966 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
967 ret = clk_prepare_enable(sc4336->xvclk);
968 if (ret < 0) {
969 dev_err(dev, "Failed to enable xvclk\n");
970 return ret;
971 }
972 if (sc4336->is_thunderboot)
973 return 0;
974
975 if (!IS_ERR(sc4336->reset_gpio))
976 gpiod_set_value_cansleep(sc4336->reset_gpio, 0);
977
978 ret = regulator_bulk_enable(SC4336_NUM_SUPPLIES, sc4336->supplies);
979 if (ret < 0) {
980 dev_err(dev, "Failed to enable regulators\n");
981 goto disable_clk;
982 }
983
984 if (!IS_ERR(sc4336->reset_gpio))
985 gpiod_set_value_cansleep(sc4336->reset_gpio, 1);
986
987 usleep_range(500, 1000);
988 if (!IS_ERR(sc4336->pwdn_gpio))
989 gpiod_set_value_cansleep(sc4336->pwdn_gpio, 1);
990
991 if (!IS_ERR(sc4336->reset_gpio))
992 usleep_range(6000, 8000);
993 else
994 usleep_range(12000, 16000);
995
996 /* 8192 cycles prior to first SCCB transaction */
997 delay_us = sc4336_cal_delay(8192);
998 usleep_range(delay_us, delay_us * 2);
999
1000 return 0;
1001
1002 disable_clk:
1003 clk_disable_unprepare(sc4336->xvclk);
1004
1005 return ret;
1006 }
1007
__sc4336_power_off(struct sc4336 * sc4336)1008 static void __sc4336_power_off(struct sc4336 *sc4336)
1009 {
1010 int ret;
1011 struct device *dev = &sc4336->client->dev;
1012
1013 clk_disable_unprepare(sc4336->xvclk);
1014 if (sc4336->is_thunderboot) {
1015 if (sc4336->is_first_streamoff) {
1016 sc4336->is_thunderboot = false;
1017 sc4336->is_first_streamoff = false;
1018 } else {
1019 return;
1020 }
1021 }
1022
1023 if (!IS_ERR(sc4336->pwdn_gpio))
1024 gpiod_set_value_cansleep(sc4336->pwdn_gpio, 0);
1025 if (!IS_ERR(sc4336->reset_gpio))
1026 gpiod_set_value_cansleep(sc4336->reset_gpio, 0);
1027 if (!IS_ERR_OR_NULL(sc4336->pins_sleep)) {
1028 ret = pinctrl_select_state(sc4336->pinctrl,
1029 sc4336->pins_sleep);
1030 if (ret < 0)
1031 dev_dbg(dev, "could not set pins\n");
1032 }
1033 regulator_bulk_disable(SC4336_NUM_SUPPLIES, sc4336->supplies);
1034 }
1035
sc4336_runtime_resume(struct device * dev)1036 static int __maybe_unused sc4336_runtime_resume(struct device *dev)
1037 {
1038 struct i2c_client *client = to_i2c_client(dev);
1039 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1040 struct sc4336 *sc4336 = to_sc4336(sd);
1041
1042 return __sc4336_power_on(sc4336);
1043 }
1044
sc4336_runtime_suspend(struct device * dev)1045 static int __maybe_unused sc4336_runtime_suspend(struct device *dev)
1046 {
1047 struct i2c_client *client = to_i2c_client(dev);
1048 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1049 struct sc4336 *sc4336 = to_sc4336(sd);
1050
1051 __sc4336_power_off(sc4336);
1052
1053 return 0;
1054 }
1055
1056 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc4336_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1057 static int sc4336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1058 {
1059 struct sc4336 *sc4336 = to_sc4336(sd);
1060 struct v4l2_mbus_framefmt *try_fmt =
1061 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1062 const struct sc4336_mode *def_mode = &supported_modes[0];
1063
1064 mutex_lock(&sc4336->mutex);
1065 /* Initialize try_fmt */
1066 try_fmt->width = def_mode->width;
1067 try_fmt->height = def_mode->height;
1068 try_fmt->code = def_mode->bus_fmt;
1069 try_fmt->field = V4L2_FIELD_NONE;
1070
1071 mutex_unlock(&sc4336->mutex);
1072 /* No crop or compose */
1073
1074 return 0;
1075 }
1076 #endif
1077
sc4336_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1078 static int sc4336_enum_frame_interval(struct v4l2_subdev *sd,
1079 struct v4l2_subdev_pad_config *cfg,
1080 struct v4l2_subdev_frame_interval_enum *fie)
1081 {
1082 if (fie->index >= ARRAY_SIZE(supported_modes))
1083 return -EINVAL;
1084
1085 fie->code = supported_modes[fie->index].bus_fmt;
1086 fie->width = supported_modes[fie->index].width;
1087 fie->height = supported_modes[fie->index].height;
1088 fie->interval = supported_modes[fie->index].max_fps;
1089 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1090 return 0;
1091 }
1092
1093 static const struct dev_pm_ops sc4336_pm_ops = {
1094 SET_RUNTIME_PM_OPS(sc4336_runtime_suspend,
1095 sc4336_runtime_resume, NULL)
1096 };
1097
1098 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1099 static const struct v4l2_subdev_internal_ops sc4336_internal_ops = {
1100 .open = sc4336_open,
1101 };
1102 #endif
1103
1104 static const struct v4l2_subdev_core_ops sc4336_core_ops = {
1105 .s_power = sc4336_s_power,
1106 .ioctl = sc4336_ioctl,
1107 #ifdef CONFIG_COMPAT
1108 .compat_ioctl32 = sc4336_compat_ioctl32,
1109 #endif
1110 };
1111
1112 static const struct v4l2_subdev_video_ops sc4336_video_ops = {
1113 .s_stream = sc4336_s_stream,
1114 .g_frame_interval = sc4336_g_frame_interval,
1115 };
1116
1117 static const struct v4l2_subdev_pad_ops sc4336_pad_ops = {
1118 .enum_mbus_code = sc4336_enum_mbus_code,
1119 .enum_frame_size = sc4336_enum_frame_sizes,
1120 .enum_frame_interval = sc4336_enum_frame_interval,
1121 .get_fmt = sc4336_get_fmt,
1122 .set_fmt = sc4336_set_fmt,
1123 .get_mbus_config = sc4336_g_mbus_config,
1124 };
1125
1126 static const struct v4l2_subdev_ops sc4336_subdev_ops = {
1127 .core = &sc4336_core_ops,
1128 .video = &sc4336_video_ops,
1129 .pad = &sc4336_pad_ops,
1130 };
1131
sc4336_modify_fps_info(struct sc4336 * sc4336)1132 static void sc4336_modify_fps_info(struct sc4336 *sc4336)
1133 {
1134 const struct sc4336_mode *mode = sc4336->cur_mode;
1135
1136 sc4336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1137 sc4336->cur_vts;
1138 }
1139
sc4336_set_ctrl(struct v4l2_ctrl * ctrl)1140 static int sc4336_set_ctrl(struct v4l2_ctrl *ctrl)
1141 {
1142 struct sc4336 *sc4336 = container_of(ctrl->handler,
1143 struct sc4336, ctrl_handler);
1144 struct i2c_client *client = sc4336->client;
1145 s64 max;
1146 int ret = 0;
1147 u32 val = 0;
1148
1149 /* Propagate change of current control to all related controls */
1150 switch (ctrl->id) {
1151 case V4L2_CID_VBLANK:
1152 /* Update max exposure while meeting expected vblanking */
1153 max = sc4336->cur_mode->height + ctrl->val - 8;
1154 __v4l2_ctrl_modify_range(sc4336->exposure,
1155 sc4336->exposure->minimum, max,
1156 sc4336->exposure->step,
1157 sc4336->exposure->default_value);
1158 break;
1159 }
1160
1161 if (!pm_runtime_get_if_in_use(&client->dev))
1162 return 0;
1163
1164 switch (ctrl->id) {
1165 case V4L2_CID_EXPOSURE:
1166 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1167 if (sc4336->cur_mode->hdr_mode == NO_HDR) {
1168 val = ctrl->val;
1169 /* 4 least significant bits of expsoure are fractional part */
1170 ret = sc4336_write_reg(sc4336->client,
1171 SC4336_REG_EXPOSURE_H,
1172 SC4336_REG_VALUE_08BIT,
1173 SC4336_FETCH_EXP_H(val));
1174 ret |= sc4336_write_reg(sc4336->client,
1175 SC4336_REG_EXPOSURE_M,
1176 SC4336_REG_VALUE_08BIT,
1177 SC4336_FETCH_EXP_M(val));
1178 ret |= sc4336_write_reg(sc4336->client,
1179 SC4336_REG_EXPOSURE_L,
1180 SC4336_REG_VALUE_08BIT,
1181 SC4336_FETCH_EXP_L(val));
1182 }
1183 break;
1184 case V4L2_CID_ANALOGUE_GAIN:
1185 dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1186 if (sc4336->cur_mode->hdr_mode == NO_HDR)
1187 ret = sc4336_set_gain_reg(sc4336, ctrl->val);
1188 break;
1189 case V4L2_CID_VBLANK:
1190 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1191 ret = sc4336_write_reg(sc4336->client,
1192 SC4336_REG_VTS_H,
1193 SC4336_REG_VALUE_08BIT,
1194 (ctrl->val + sc4336->cur_mode->height)
1195 >> 8);
1196 ret |= sc4336_write_reg(sc4336->client,
1197 SC4336_REG_VTS_L,
1198 SC4336_REG_VALUE_08BIT,
1199 (ctrl->val + sc4336->cur_mode->height)
1200 & 0xff);
1201 sc4336->cur_vts = ctrl->val + sc4336->cur_mode->height;
1202 sc4336_modify_fps_info(sc4336);
1203 break;
1204 case V4L2_CID_TEST_PATTERN:
1205 ret = sc4336_enable_test_pattern(sc4336, ctrl->val);
1206 break;
1207 case V4L2_CID_HFLIP:
1208 ret = sc4336_read_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
1209 SC4336_REG_VALUE_08BIT, &val);
1210 ret |= sc4336_write_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
1211 SC4336_REG_VALUE_08BIT,
1212 SC4336_FETCH_MIRROR(val, ctrl->val));
1213 break;
1214 case V4L2_CID_VFLIP:
1215 ret = sc4336_read_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
1216 SC4336_REG_VALUE_08BIT, &val);
1217 ret |= sc4336_write_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
1218 SC4336_REG_VALUE_08BIT,
1219 SC4336_FETCH_FLIP(val, ctrl->val));
1220 break;
1221 default:
1222 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1223 __func__, ctrl->id, ctrl->val);
1224 break;
1225 }
1226
1227 pm_runtime_put(&client->dev);
1228
1229 return ret;
1230 }
1231
1232 static const struct v4l2_ctrl_ops sc4336_ctrl_ops = {
1233 .s_ctrl = sc4336_set_ctrl,
1234 };
1235
sc4336_initialize_controls(struct sc4336 * sc4336)1236 static int sc4336_initialize_controls(struct sc4336 *sc4336)
1237 {
1238 const struct sc4336_mode *mode;
1239 struct v4l2_ctrl_handler *handler;
1240 struct v4l2_ctrl *ctrl;
1241 s64 exposure_max, vblank_def;
1242 u32 h_blank;
1243 int ret;
1244
1245 handler = &sc4336->ctrl_handler;
1246 mode = sc4336->cur_mode;
1247 ret = v4l2_ctrl_handler_init(handler, 9);
1248 if (ret)
1249 return ret;
1250 handler->lock = &sc4336->mutex;
1251
1252 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1253 0, 0, link_freq_menu_items);
1254 if (ctrl)
1255 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1256
1257 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1258 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT);
1259
1260 h_blank = mode->hts_def - mode->width;
1261 sc4336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1262 h_blank, h_blank, 1, h_blank);
1263 if (sc4336->hblank)
1264 sc4336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1265 vblank_def = mode->vts_def - mode->height;
1266 sc4336->vblank = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
1267 V4L2_CID_VBLANK, vblank_def,
1268 SC4336_VTS_MAX - mode->height,
1269 1, vblank_def);
1270 sc4336->cur_fps = mode->max_fps;
1271 exposure_max = mode->vts_def - 8;
1272 sc4336->exposure = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
1273 V4L2_CID_EXPOSURE, SC4336_EXPOSURE_MIN,
1274 exposure_max, SC4336_EXPOSURE_STEP,
1275 mode->exp_def);
1276 sc4336->anal_gain = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
1277 V4L2_CID_ANALOGUE_GAIN, SC4336_GAIN_MIN,
1278 SC4336_GAIN_MAX, SC4336_GAIN_STEP,
1279 SC4336_GAIN_DEFAULT);
1280 sc4336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1281 &sc4336_ctrl_ops,
1282 V4L2_CID_TEST_PATTERN,
1283 ARRAY_SIZE(sc4336_test_pattern_menu) - 1,
1284 0, 0, sc4336_test_pattern_menu);
1285 v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
1286 V4L2_CID_HFLIP, 0, 1, 1, 0);
1287 v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
1288 V4L2_CID_VFLIP, 0, 1, 1, 0);
1289 if (handler->error) {
1290 ret = handler->error;
1291 dev_err(&sc4336->client->dev,
1292 "Failed to init controls(%d)\n", ret);
1293 goto err_free_handler;
1294 }
1295
1296 sc4336->subdev.ctrl_handler = handler;
1297
1298 return 0;
1299
1300 err_free_handler:
1301 v4l2_ctrl_handler_free(handler);
1302
1303 return ret;
1304 }
1305
sc4336_check_sensor_id(struct sc4336 * sc4336,struct i2c_client * client)1306 static int sc4336_check_sensor_id(struct sc4336 *sc4336,
1307 struct i2c_client *client)
1308 {
1309 struct device *dev = &sc4336->client->dev;
1310 u32 id = 0;
1311 int ret;
1312
1313 if (sc4336->is_thunderboot) {
1314 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1315 return 0;
1316 }
1317
1318 ret = sc4336_read_reg(client, SC4336_REG_CHIP_ID,
1319 SC4336_REG_VALUE_16BIT, &id);
1320 if (id != CHIP_ID) {
1321 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1322 return -ENODEV;
1323 }
1324
1325 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1326
1327 return 0;
1328 }
1329
sc4336_configure_regulators(struct sc4336 * sc4336)1330 static int sc4336_configure_regulators(struct sc4336 *sc4336)
1331 {
1332 unsigned int i;
1333
1334 for (i = 0; i < SC4336_NUM_SUPPLIES; i++)
1335 sc4336->supplies[i].supply = sc4336_supply_names[i];
1336
1337 return devm_regulator_bulk_get(&sc4336->client->dev,
1338 SC4336_NUM_SUPPLIES,
1339 sc4336->supplies);
1340 }
1341
sc4336_probe(struct i2c_client * client,const struct i2c_device_id * id)1342 static int sc4336_probe(struct i2c_client *client,
1343 const struct i2c_device_id *id)
1344 {
1345 struct device *dev = &client->dev;
1346 struct device_node *node = dev->of_node;
1347 struct sc4336 *sc4336;
1348 struct v4l2_subdev *sd;
1349 char facing[2];
1350 int ret;
1351
1352 dev_info(dev, "driver version: %02x.%02x.%02x",
1353 DRIVER_VERSION >> 16,
1354 (DRIVER_VERSION & 0xff00) >> 8,
1355 DRIVER_VERSION & 0x00ff);
1356
1357 sc4336 = devm_kzalloc(dev, sizeof(*sc4336), GFP_KERNEL);
1358 if (!sc4336)
1359 return -ENOMEM;
1360
1361 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1362 &sc4336->module_index);
1363 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1364 &sc4336->module_facing);
1365 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1366 &sc4336->module_name);
1367 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1368 &sc4336->len_name);
1369 if (ret) {
1370 dev_err(dev, "could not get module information!\n");
1371 return -EINVAL;
1372 }
1373
1374 sc4336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1375 sc4336->client = client;
1376 sc4336->cur_mode = &supported_modes[0];
1377
1378 sc4336->xvclk = devm_clk_get(dev, "xvclk");
1379 if (IS_ERR(sc4336->xvclk)) {
1380 dev_err(dev, "Failed to get xvclk\n");
1381 return -EINVAL;
1382 }
1383
1384 if (sc4336->is_thunderboot) {
1385 sc4336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1386 if (IS_ERR(sc4336->reset_gpio))
1387 dev_warn(dev, "Failed to get reset-gpios\n");
1388
1389 sc4336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1390 if (IS_ERR(sc4336->pwdn_gpio))
1391 dev_warn(dev, "Failed to get pwdn-gpios\n");
1392 } else {
1393 sc4336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1394 if (IS_ERR(sc4336->reset_gpio))
1395 dev_warn(dev, "Failed to get reset-gpios\n");
1396
1397 sc4336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1398 if (IS_ERR(sc4336->pwdn_gpio))
1399 dev_warn(dev, "Failed to get pwdn-gpios\n");
1400 }
1401 sc4336->pinctrl = devm_pinctrl_get(dev);
1402 if (!IS_ERR(sc4336->pinctrl)) {
1403 sc4336->pins_default =
1404 pinctrl_lookup_state(sc4336->pinctrl,
1405 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1406 if (IS_ERR(sc4336->pins_default))
1407 dev_err(dev, "could not get default pinstate\n");
1408
1409 sc4336->pins_sleep =
1410 pinctrl_lookup_state(sc4336->pinctrl,
1411 OF_CAMERA_PINCTRL_STATE_SLEEP);
1412 if (IS_ERR(sc4336->pins_sleep))
1413 dev_err(dev, "could not get sleep pinstate\n");
1414 } else {
1415 dev_err(dev, "no pinctrl\n");
1416 }
1417
1418 ret = sc4336_configure_regulators(sc4336);
1419 if (ret) {
1420 dev_err(dev, "Failed to get power regulators\n");
1421 return ret;
1422 }
1423
1424 mutex_init(&sc4336->mutex);
1425
1426 sd = &sc4336->subdev;
1427 v4l2_i2c_subdev_init(sd, client, &sc4336_subdev_ops);
1428 ret = sc4336_initialize_controls(sc4336);
1429 if (ret)
1430 goto err_destroy_mutex;
1431
1432 ret = __sc4336_power_on(sc4336);
1433 if (ret)
1434 goto err_free_handler;
1435
1436 ret = sc4336_check_sensor_id(sc4336, client);
1437 if (ret)
1438 goto err_power_off;
1439
1440 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1441 sd->internal_ops = &sc4336_internal_ops;
1442 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1443 V4L2_SUBDEV_FL_HAS_EVENTS;
1444 #endif
1445 #if defined(CONFIG_MEDIA_CONTROLLER)
1446 sc4336->pad.flags = MEDIA_PAD_FL_SOURCE;
1447 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1448 ret = media_entity_pads_init(&sd->entity, 1, &sc4336->pad);
1449 if (ret < 0)
1450 goto err_power_off;
1451 #endif
1452
1453 memset(facing, 0, sizeof(facing));
1454 if (strcmp(sc4336->module_facing, "back") == 0)
1455 facing[0] = 'b';
1456 else
1457 facing[0] = 'f';
1458
1459 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1460 sc4336->module_index, facing,
1461 SC4336_NAME, dev_name(sd->dev));
1462 ret = v4l2_async_register_subdev_sensor_common(sd);
1463 if (ret) {
1464 dev_err(dev, "v4l2 async register subdev failed\n");
1465 goto err_clean_entity;
1466 }
1467
1468 pm_runtime_set_active(dev);
1469 pm_runtime_enable(dev);
1470 if (sc4336->is_thunderboot)
1471 pm_runtime_get_sync(dev);
1472 else
1473 pm_runtime_idle(dev);
1474
1475 return 0;
1476
1477 err_clean_entity:
1478 #if defined(CONFIG_MEDIA_CONTROLLER)
1479 media_entity_cleanup(&sd->entity);
1480 #endif
1481 err_power_off:
1482 __sc4336_power_off(sc4336);
1483 err_free_handler:
1484 v4l2_ctrl_handler_free(&sc4336->ctrl_handler);
1485 err_destroy_mutex:
1486 mutex_destroy(&sc4336->mutex);
1487
1488 return ret;
1489 }
1490
sc4336_remove(struct i2c_client * client)1491 static int sc4336_remove(struct i2c_client *client)
1492 {
1493 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1494 struct sc4336 *sc4336 = to_sc4336(sd);
1495
1496 v4l2_async_unregister_subdev(sd);
1497 #if defined(CONFIG_MEDIA_CONTROLLER)
1498 media_entity_cleanup(&sd->entity);
1499 #endif
1500 v4l2_ctrl_handler_free(&sc4336->ctrl_handler);
1501 mutex_destroy(&sc4336->mutex);
1502
1503 pm_runtime_disable(&client->dev);
1504 if (!pm_runtime_status_suspended(&client->dev))
1505 __sc4336_power_off(sc4336);
1506 pm_runtime_set_suspended(&client->dev);
1507
1508 return 0;
1509 }
1510
1511 #if IS_ENABLED(CONFIG_OF)
1512 static const struct of_device_id sc4336_of_match[] = {
1513 { .compatible = "smartsens,sc4336" },
1514 {},
1515 };
1516 MODULE_DEVICE_TABLE(of, sc4336_of_match);
1517 #endif
1518
1519 static const struct i2c_device_id sc4336_match_id[] = {
1520 { "smartsens,sc4336", 0 },
1521 { },
1522 };
1523
1524 static struct i2c_driver sc4336_i2c_driver = {
1525 .driver = {
1526 .name = SC4336_NAME,
1527 .pm = &sc4336_pm_ops,
1528 .of_match_table = of_match_ptr(sc4336_of_match),
1529 },
1530 .probe = &sc4336_probe,
1531 .remove = &sc4336_remove,
1532 .id_table = sc4336_match_id,
1533 };
1534
sensor_mod_init(void)1535 static int __init sensor_mod_init(void)
1536 {
1537 return i2c_add_driver(&sc4336_i2c_driver);
1538 }
1539
sensor_mod_exit(void)1540 static void __exit sensor_mod_exit(void)
1541 {
1542 i2c_del_driver(&sc4336_i2c_driver);
1543 }
1544
1545 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1546 subsys_initcall(sensor_mod_init);
1547 #else
1548 device_initcall_sync(sensor_mod_init);
1549 #endif
1550 module_exit(sensor_mod_exit);
1551
1552 MODULE_DESCRIPTION("smartsens sc4336 sensor driver");
1553 MODULE_LICENSE("GPL");
1554