1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc430cs driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 add quick stream on/off
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <linux/rk-preisp.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-async.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-subdev.h>
31 #include <linux/pinctrl/consumer.h>
32
33 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
34
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define SC430CS_LANES 4
40 #define SC430CS_BITS_PER_SAMPLE 10
41 #define SC430CS_LINK_FREQ_315 157500000// 315Mbps
42
43 #define PIXEL_RATE_WITH_315M_10BIT (SC430CS_LINK_FREQ_315 * 2 * \
44 SC430CS_LANES / SC430CS_BITS_PER_SAMPLE)
45 #define SC430CS_XVCLK_FREQ 27000000
46
47 #define CHIP_ID 0xcd2e
48 #define SC430CS_REG_CHIP_ID 0x3107
49
50 #define SC430CS_REG_CTRL_MODE 0x0100
51 #define SC430CS_MODE_SW_STANDBY 0x0
52 #define SC430CS_MODE_STREAMING BIT(0)
53
54 #define SC430CS_REG_EXPOSURE_H 0x3e00
55 #define SC430CS_REG_EXPOSURE_M 0x3e01
56 #define SC430CS_REG_EXPOSURE_L 0x3e02
57 #define SC430CS_EXPOSURE_MIN 1
58 #define SC430CS_EXPOSURE_STEP 1
59 #define SC430CS_VTS_MAX 0x7fff
60
61 #define SC430CS_REG_DIG_GAIN 0x3e06
62 #define SC430CS_REG_DIG_FINE_GAIN 0x3e07
63 #define SC430CS_REG_ANA_GAIN 0x3e08
64 #define SC430CS_REG_ANA_FINE_GAIN 0x3e09
65 #define SC430CS_GAIN_MIN 0x0040
66 #define SC430CS_GAIN_MAX (24 * 32 * 64) //23.32*31.75*64
67 #define SC430CS_GAIN_STEP 1
68 #define SC430CS_GAIN_DEFAULT 0x0800
69
70
71 #define SC430CS_REG_GROUP_HOLD 0x3812
72 #define SC430CS_GROUP_HOLD_START 0x00
73 #define SC430CS_GROUP_HOLD_END 0x30
74
75 #define SC430CS_REG_HIGH_TEMP_H 0x3974
76 #define SC430CS_REG_HIGH_TEMP_L 0x3975
77
78 #define SC430CS_REG_TEST_PATTERN 0x4501
79 #define SC430CS_TEST_PATTERN_BIT_MASK BIT(3)
80
81 #define SC430CS_REG_VTS_H 0x320e
82 #define SC430CS_REG_VTS_L 0x320f
83
84 #define SC430CS_FLIP_MIRROR_REG 0x3221
85
86 #define SC430CS_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
87 #define SC430CS_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
88 #define SC430CS_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
89
90 #define SC430CS_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
91 #define SC430CS_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
92
93 #define SC430CS_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
94 #define SC430CS_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
95
96 #define REG_DELAY 0xFFFE
97 #define REG_NULL 0xFFFF
98
99 #define SC430CS_REG_VALUE_08BIT 1
100 #define SC430CS_REG_VALUE_16BIT 2
101 #define SC430CS_REG_VALUE_24BIT 3
102
103 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
104 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
105 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
106 #define SC430CS_NAME "sc430cs"
107
108 static const char * const sc430cs_supply_names[] = {
109 "avdd", /* Analog power */
110 "dovdd", /* Digital I/O power */
111 "dvdd", /* Digital core power */
112 };
113
114 #define SC430CS_NUM_SUPPLIES ARRAY_SIZE(sc430cs_supply_names)
115
116 struct regval {
117 u16 addr;
118 u8 val;
119 };
120
121 struct sc430cs_mode {
122 u32 bus_fmt;
123 u32 width;
124 u32 height;
125 struct v4l2_fract max_fps;
126 u32 hts_def;
127 u32 vts_def;
128 u32 exp_def;
129 const struct regval *reg_list;
130 u32 hdr_mode;
131 u32 vc[PAD_MAX];
132 };
133
134 struct sc430cs {
135 struct i2c_client *client;
136 struct clk *xvclk;
137 struct gpio_desc *reset_gpio;
138 struct gpio_desc *pwdn_gpio;
139 struct regulator_bulk_data supplies[SC430CS_NUM_SUPPLIES];
140
141 struct pinctrl *pinctrl;
142 struct pinctrl_state *pins_default;
143 struct pinctrl_state *pins_sleep;
144 struct v4l2_fract cur_fps;
145 struct v4l2_subdev subdev;
146 struct media_pad pad;
147 struct v4l2_ctrl_handler ctrl_handler;
148 struct v4l2_ctrl *exposure;
149 struct v4l2_ctrl *anal_gain;
150 struct v4l2_ctrl *digi_gain;
151 struct v4l2_ctrl *hblank;
152 struct v4l2_ctrl *vblank;
153 struct v4l2_ctrl *test_pattern;
154 struct mutex mutex;
155 bool streaming;
156 bool power_on;
157 const struct sc430cs_mode *cur_mode;
158 u32 module_index;
159 const char *module_facing;
160 const char *module_name;
161 const char *len_name;
162 u32 cur_vts;
163 struct preisp_hdrae_exp_s init_hdrae_exp;
164 };
165
166 #define to_sc430cs(sd) container_of(sd, struct sc430cs, subdev)
167
168 /*
169 * Xclk 24Mhz
170 */
171 static const struct regval sc430cs_global_regs[] = {
172 {REG_NULL, 0x00},
173 };
174
175 /*
176 * Xclk 27Mhz
177 * max_framerate 30fps
178 * mipi_datarate per lane 315Mbps, 4lane
179 */
180 static const struct regval sc430cs_linear_10_2560x1440_regs[] = {
181 {0x0103, 0x01},
182 {0x0100, 0x00},
183 {0x36e9, 0x80},
184 {0x36f9, 0x80},
185 {0x301c, 0x78},
186 {0x301f, 0x01},
187 {0x3208, 0x0a},
188 {0x3209, 0x00},
189 {0x320a, 0x05},
190 {0x320b, 0xa0},
191 {0x320e, 0x05},
192 {0x320f, 0xdc},
193 {0x3214, 0x11},
194 {0x3215, 0x11},
195 {0x3223, 0x80},
196 {0x3250, 0x00},
197 {0x3253, 0x08},
198 {0x3274, 0x01},
199 {0x3301, 0x20},
200 {0x3302, 0x18},
201 {0x3303, 0x10},
202 {0x3304, 0x50},
203 {0x3306, 0x38},
204 {0x3308, 0x18},
205 {0x3309, 0x60},
206 {0x330b, 0xc0},
207 {0x330d, 0x10},
208 {0x330e, 0x18},
209 {0x330f, 0x04},
210 {0x3310, 0x02},
211 {0x331c, 0x04},
212 {0x331e, 0x41},
213 {0x331f, 0x51},
214 {0x3320, 0x09},
215 {0x3333, 0x10},
216 {0x334c, 0x08},
217 {0x3356, 0x09},
218 {0x3364, 0x17},
219 {0x338e, 0xfd},
220 {0x3390, 0x08},
221 {0x3391, 0x18},
222 {0x3392, 0x38},
223 {0x3393, 0x20},
224 {0x3394, 0x20},
225 {0x3395, 0x20},
226 {0x3396, 0x08},
227 {0x3397, 0x18},
228 {0x3398, 0x38},
229 {0x3399, 0x20},
230 {0x339a, 0x20},
231 {0x339b, 0x20},
232 {0x339c, 0x20},
233 {0x33ac, 0x10},
234 {0x33ae, 0x18},
235 {0x33af, 0x19},
236 {0x360f, 0x01},
237 {0x3620, 0x08},
238 {0x3637, 0x25},
239 {0x363a, 0x12},
240 {0x3670, 0x0a},
241 {0x3671, 0x07},
242 {0x3672, 0x57},
243 {0x3673, 0x5e},
244 {0x3674, 0x84},
245 {0x3675, 0x88},
246 {0x3676, 0x8a},
247 {0x367a, 0x58},
248 {0x367b, 0x78},
249 {0x367c, 0x58},
250 {0x367d, 0x78},
251 {0x3690, 0x33},
252 {0x3691, 0x43},
253 {0x3692, 0x34},
254 {0x369c, 0x40},
255 {0x369d, 0x78},
256 {0x36ea, 0x39},
257 {0x36eb, 0x0d},
258 {0x36ec, 0x2c},
259 {0x36ed, 0x24},
260 {0x36fa, 0x39},
261 {0x36fb, 0x33},
262 {0x36fc, 0x10},
263 {0x36fd, 0x14},
264 {0x3908, 0x41},
265 {0x396c, 0x0e},
266 {0x3e00, 0x00},
267 {0x3e01, 0xb6},
268 {0x3e02, 0x00},
269 {0x3e03, 0x0b},
270 {0x3e08, 0x03},
271 {0x3e09, 0x40},
272 {0x3e1b, 0x2a},
273 {0x4509, 0x30},
274 {0x57a8, 0xd0},
275 {0x36e9, 0x14},
276 {0x36f9, 0x14},
277 {REG_NULL, 0x00},
278 };
279
280 static const struct sc430cs_mode supported_modes[] = {
281 {
282 .width = 2560,
283 .height = 1440,
284 .max_fps = {
285 .numerator = 10000,
286 .denominator = 300000,
287 },
288 .exp_def = 0x0080,
289 .hts_def = 0x0578 * 2,
290 .vts_def = 0x05dc,
291 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
292 .reg_list = sc430cs_linear_10_2560x1440_regs,
293 .hdr_mode = NO_HDR,
294 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
295 }
296 };
297
298 static const s64 link_freq_menu_items[] = {
299 SC430CS_LINK_FREQ_315
300 };
301
302 static const char * const sc430cs_test_pattern_menu[] = {
303 "Disabled",
304 "Vertical Color Bar Type 1",
305 "Vertical Color Bar Type 2",
306 "Vertical Color Bar Type 3",
307 "Vertical Color Bar Type 4"
308 };
309
310 /* Write registers up to 4 at a time */
sc430cs_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)311 static int sc430cs_write_reg(struct i2c_client *client, u16 reg,
312 u32 len, u32 val)
313 {
314 u32 buf_i, val_i;
315 u8 buf[6];
316 u8 *val_p;
317 __be32 val_be;
318
319 if (len > 4)
320 return -EINVAL;
321
322 buf[0] = reg >> 8;
323 buf[1] = reg & 0xff;
324
325 val_be = cpu_to_be32(val);
326 val_p = (u8 *)&val_be;
327 buf_i = 2;
328 val_i = 4 - len;
329
330 while (val_i < 4)
331 buf[buf_i++] = val_p[val_i++];
332
333 if (i2c_master_send(client, buf, len + 2) != len + 2)
334 return -EIO;
335 return 0;
336 }
337
sc430cs_write_array(struct i2c_client * client,const struct regval * regs)338 static int sc430cs_write_array(struct i2c_client *client,
339 const struct regval *regs)
340 {
341 u32 i;
342 int ret = 0;
343
344 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
345 ret = sc430cs_write_reg(client, regs[i].addr,
346 SC430CS_REG_VALUE_08BIT, regs[i].val);
347
348 return ret;
349 }
350
351 /* Read registers up to 4 at a time */
sc430cs_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)352 static int sc430cs_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
353 u32 *val)
354 {
355 struct i2c_msg msgs[2];
356 u8 *data_be_p;
357 __be32 data_be = 0;
358 __be16 reg_addr_be = cpu_to_be16(reg);
359 int ret;
360
361 if (len > 4 || !len)
362 return -EINVAL;
363
364 data_be_p = (u8 *)&data_be;
365 /* Write register address */
366 msgs[0].addr = client->addr;
367 msgs[0].flags = 0;
368 msgs[0].len = 2;
369 msgs[0].buf = (u8 *)®_addr_be;
370
371 /* Read data from register */
372 msgs[1].addr = client->addr;
373 msgs[1].flags = I2C_M_RD;
374 msgs[1].len = len;
375 msgs[1].buf = &data_be_p[4 - len];
376
377 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
378 if (ret != ARRAY_SIZE(msgs))
379 return -EIO;
380
381 *val = be32_to_cpu(data_be);
382
383 return 0;
384 }
385
sc430cs_set_gain_reg(struct sc430cs * sc430cs,u32 gain)386 static int sc430cs_set_gain_reg(struct sc430cs *sc430cs, u32 gain)
387 {
388 u8 Coarse_gain = 1, DIG_gain = 1;
389 u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1;
390 u8 Coarse_gain_reg = 0, DIG_gain_reg = 0;
391 u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80;
392 int ret = 0;
393
394 gain = gain * 16;
395 if (gain <= 1024)
396 gain = 1024;
397 else if (gain > SC430CS_GAIN_MAX * 16)
398 gain = SC430CS_GAIN_MAX * 16;
399
400 if (gain < 1504) { // start again
401 Dcg_gainx100 = 100;
402 Coarse_gain = 1;
403 DIG_gain = 1;
404 Coarse_gain_reg = 0x03;
405 DIG_gain_reg = 0x0;
406 DIG_Fine_gain_reg = 0x80;
407 } else if (gain <= 3008) {
408 Dcg_gainx100 = 147;
409 Coarse_gain = 1;
410 DIG_gain = 1;
411 Coarse_gain_reg = 0x23;
412 DIG_gain_reg = 0x0;
413 DIG_Fine_gain_reg = 0x80;
414 } else if (gain <= 6017) {
415 Dcg_gainx100 = 147;
416 Coarse_gain = 2;
417 DIG_gain = 1;
418 Coarse_gain_reg = 0x27;
419 DIG_gain_reg = 0x0;
420 DIG_Fine_gain_reg = 0x80;
421 } else if (gain <= 12034) {
422 Dcg_gainx100 = 147;
423 Coarse_gain = 4;
424 DIG_gain = 1;
425 Coarse_gain_reg = 0x2f;
426 DIG_gain_reg = 0x0;
427 DIG_Fine_gain_reg = 0x80;
428 } else if (gain <= 23879) { // end again
429 Dcg_gainx100 = 147;
430 Coarse_gain = 8;
431 DIG_gain = 1;
432 Coarse_gain_reg = 0x3f;
433 DIG_gain_reg = 0x0;
434 DIG_Fine_gain_reg = 0x80;
435 } else if (gain < 23879 * 2) { // start dgain
436 Dcg_gainx100 = 147;
437 Coarse_gain = 8;
438 DIG_gain = 1;
439 ANA_Fine_gainx64 = 127;
440 Coarse_gain_reg = 0x3f;
441 DIG_gain_reg = 0x0;
442 ANA_Fine_gain_reg = 0x7f;
443 } else if (gain < 23879 * 4) {
444 Dcg_gainx100 = 147;
445 Coarse_gain = 8;
446 DIG_gain = 2;
447 ANA_Fine_gainx64 = 127;
448 Coarse_gain_reg = 0x3f;
449 DIG_gain_reg = 0x1;
450 ANA_Fine_gain_reg = 0x7f;
451 } else if (gain < 23879 * 8) {
452 Dcg_gainx100 = 147;
453 Coarse_gain = 8;
454 DIG_gain = 4;
455 ANA_Fine_gainx64 = 127;
456 Coarse_gain_reg = 0x3f;
457 DIG_gain_reg = 0x3;
458 ANA_Fine_gain_reg = 0x7f;
459 } else if (gain < 23879 * 16) {
460 Dcg_gainx100 = 147;
461 Coarse_gain = 8;
462 DIG_gain = 8;
463 ANA_Fine_gainx64 = 127;
464 Coarse_gain_reg = 0x3f;
465 DIG_gain_reg = 0x7;
466 ANA_Fine_gain_reg = 0x7f;
467 } else if (gain <= 1754822) {
468 Dcg_gainx100 = 147;
469 Coarse_gain = 8;
470 DIG_gain = 16;
471 ANA_Fine_gainx64 = 127;
472 Coarse_gain_reg = 0x3f;
473 DIG_gain_reg = 0xF;
474 ANA_Fine_gain_reg = 0x7f;
475 }
476
477 if (gain < 1504)
478 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
479 else if (gain == 1504)
480 ANA_Fine_gain_reg = 0x40;
481 else if (gain < 23879)
482 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
483 else
484 DIG_Fine_gain_reg = abs(800 * gain / (Dcg_gainx100 * Coarse_gain *
485 DIG_gain) / ANA_Fine_gainx64);
486
487 ret = sc430cs_write_reg(sc430cs->client,
488 SC430CS_REG_DIG_GAIN,
489 SC430CS_REG_VALUE_08BIT,
490 DIG_gain_reg & 0xF);
491 ret |= sc430cs_write_reg(sc430cs->client,
492 SC430CS_REG_DIG_FINE_GAIN,
493 SC430CS_REG_VALUE_08BIT,
494 DIG_Fine_gain_reg);
495 ret |= sc430cs_write_reg(sc430cs->client,
496 SC430CS_REG_ANA_GAIN,
497 SC430CS_REG_VALUE_08BIT,
498 Coarse_gain_reg);
499 ret |= sc430cs_write_reg(sc430cs->client,
500 SC430CS_REG_ANA_FINE_GAIN,
501 SC430CS_REG_VALUE_08BIT,
502 ANA_Fine_gain_reg);
503
504 return ret;
505 }
506
sc430cs_get_reso_dist(const struct sc430cs_mode * mode,struct v4l2_mbus_framefmt * framefmt)507 static int sc430cs_get_reso_dist(const struct sc430cs_mode *mode,
508 struct v4l2_mbus_framefmt *framefmt)
509 {
510 return abs(mode->width - framefmt->width) +
511 abs(mode->height - framefmt->height);
512 }
513
514 static const struct sc430cs_mode *
sc430cs_find_best_fit(struct v4l2_subdev_format * fmt)515 sc430cs_find_best_fit(struct v4l2_subdev_format *fmt)
516 {
517 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
518 int dist;
519 int cur_best_fit = 0;
520 int cur_best_fit_dist = -1;
521 unsigned int i;
522
523 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
524 dist = sc430cs_get_reso_dist(&supported_modes[i], framefmt);
525 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
526 cur_best_fit_dist = dist;
527 cur_best_fit = i;
528 }
529 }
530
531 return &supported_modes[cur_best_fit];
532 }
533
sc430cs_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)534 static int sc430cs_set_fmt(struct v4l2_subdev *sd,
535 struct v4l2_subdev_pad_config *cfg,
536 struct v4l2_subdev_format *fmt)
537 {
538 struct sc430cs *sc430cs = to_sc430cs(sd);
539 const struct sc430cs_mode *mode;
540 s64 h_blank, vblank_def;
541
542 mutex_lock(&sc430cs->mutex);
543
544 mode = sc430cs_find_best_fit(fmt);
545 fmt->format.code = mode->bus_fmt;
546 fmt->format.width = mode->width;
547 fmt->format.height = mode->height;
548 fmt->format.field = V4L2_FIELD_NONE;
549 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
550 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
551 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
552 #else
553 mutex_unlock(&sc430cs->mutex);
554 return -ENOTTY;
555 #endif
556 } else {
557 sc430cs->cur_mode = mode;
558 h_blank = mode->hts_def - mode->width;
559 __v4l2_ctrl_modify_range(sc430cs->hblank, h_blank,
560 h_blank, 1, h_blank);
561 vblank_def = mode->vts_def - mode->height;
562 __v4l2_ctrl_modify_range(sc430cs->vblank, vblank_def,
563 SC430CS_VTS_MAX - mode->height,
564 1, vblank_def);
565 sc430cs->cur_fps = mode->max_fps;
566 sc430cs->cur_vts = (u32)mode->vts_def;
567 }
568
569 mutex_unlock(&sc430cs->mutex);
570
571 return 0;
572 }
573
sc430cs_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)574 static int sc430cs_get_fmt(struct v4l2_subdev *sd,
575 struct v4l2_subdev_pad_config *cfg,
576 struct v4l2_subdev_format *fmt)
577 {
578 struct sc430cs *sc430cs = to_sc430cs(sd);
579 const struct sc430cs_mode *mode = sc430cs->cur_mode;
580
581 mutex_lock(&sc430cs->mutex);
582 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
583 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
584 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
585 #else
586 mutex_unlock(&sc430cs->mutex);
587 return -ENOTTY;
588 #endif
589 } else {
590 fmt->format.width = mode->width;
591 fmt->format.height = mode->height;
592 fmt->format.code = mode->bus_fmt;
593 fmt->format.field = V4L2_FIELD_NONE;
594 /* format info: width/height/data type/virctual channel */
595 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
596 fmt->reserved[0] = mode->vc[fmt->pad];
597 else
598 fmt->reserved[0] = mode->vc[PAD0];
599 }
600 mutex_unlock(&sc430cs->mutex);
601
602 return 0;
603 }
604
sc430cs_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)605 static int sc430cs_enum_mbus_code(struct v4l2_subdev *sd,
606 struct v4l2_subdev_pad_config *cfg,
607 struct v4l2_subdev_mbus_code_enum *code)
608 {
609 struct sc430cs *sc430cs = to_sc430cs(sd);
610
611 if (code->index != 0)
612 return -EINVAL;
613 code->code = sc430cs->cur_mode->bus_fmt;
614
615 return 0;
616 }
617
sc430cs_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)618 static int sc430cs_enum_frame_sizes(struct v4l2_subdev *sd,
619 struct v4l2_subdev_pad_config *cfg,
620 struct v4l2_subdev_frame_size_enum *fse)
621 {
622 if (fse->index >= ARRAY_SIZE(supported_modes))
623 return -EINVAL;
624
625 if (fse->code != supported_modes[0].bus_fmt)
626 return -EINVAL;
627
628 fse->min_width = supported_modes[fse->index].width;
629 fse->max_width = supported_modes[fse->index].width;
630 fse->max_height = supported_modes[fse->index].height;
631 fse->min_height = supported_modes[fse->index].height;
632
633 return 0;
634 }
635
sc430cs_enable_test_pattern(struct sc430cs * sc430cs,u32 pattern)636 static int sc430cs_enable_test_pattern(struct sc430cs *sc430cs, u32 pattern)
637 {
638 u32 val = 0;
639 int ret = 0;
640
641 ret = sc430cs_read_reg(sc430cs->client, SC430CS_REG_TEST_PATTERN,
642 SC430CS_REG_VALUE_08BIT, &val);
643 if (pattern)
644 val |= SC430CS_TEST_PATTERN_BIT_MASK;
645 else
646 val &= ~SC430CS_TEST_PATTERN_BIT_MASK;
647
648 ret |= sc430cs_write_reg(sc430cs->client, SC430CS_REG_TEST_PATTERN,
649 SC430CS_REG_VALUE_08BIT, val);
650 return ret;
651 }
652
sc430cs_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)653 static int sc430cs_g_frame_interval(struct v4l2_subdev *sd,
654 struct v4l2_subdev_frame_interval *fi)
655 {
656 struct sc430cs *sc430cs = to_sc430cs(sd);
657 const struct sc430cs_mode *mode = sc430cs->cur_mode;
658
659 if (sc430cs->streaming)
660 fi->interval = sc430cs->cur_fps;
661 else
662 fi->interval = mode->max_fps;
663
664 return 0;
665 }
666
sc430cs_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)667 static int sc430cs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
668 struct v4l2_mbus_config *config)
669 {
670 struct sc430cs *sc430cs = to_sc430cs(sd);
671 const struct sc430cs_mode *mode = sc430cs->cur_mode;
672 u32 val = 1 << (SC430CS_LANES - 1) |
673 V4L2_MBUS_CSI2_CHANNEL_0 |
674 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
675
676 if (mode->hdr_mode != NO_HDR)
677 val |= V4L2_MBUS_CSI2_CHANNEL_1;
678 if (mode->hdr_mode == HDR_X3)
679 val |= V4L2_MBUS_CSI2_CHANNEL_2;
680
681 config->type = V4L2_MBUS_CSI2_DPHY;
682 config->flags = val;
683
684 return 0;
685 }
686
sc430cs_get_module_inf(struct sc430cs * sc430cs,struct rkmodule_inf * inf)687 static void sc430cs_get_module_inf(struct sc430cs *sc430cs,
688 struct rkmodule_inf *inf)
689 {
690 memset(inf, 0, sizeof(*inf));
691 strlcpy(inf->base.sensor, SC430CS_NAME, sizeof(inf->base.sensor));
692 strlcpy(inf->base.module, sc430cs->module_name,
693 sizeof(inf->base.module));
694 strlcpy(inf->base.lens, sc430cs->len_name, sizeof(inf->base.lens));
695 }
696
sc430cs_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)697 static long sc430cs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
698 {
699 struct sc430cs *sc430cs = to_sc430cs(sd);
700 struct rkmodule_hdr_cfg *hdr;
701 u32 i, h, w;
702 long ret = 0;
703 u32 stream = 0;
704
705 switch (cmd) {
706 case RKMODULE_GET_MODULE_INFO:
707 sc430cs_get_module_inf(sc430cs, (struct rkmodule_inf *)arg);
708 break;
709 case RKMODULE_GET_HDR_CFG:
710 hdr = (struct rkmodule_hdr_cfg *)arg;
711 hdr->esp.mode = HDR_NORMAL_VC;
712 hdr->hdr_mode = sc430cs->cur_mode->hdr_mode;
713 break;
714 case RKMODULE_SET_HDR_CFG:
715 hdr = (struct rkmodule_hdr_cfg *)arg;
716 w = sc430cs->cur_mode->width;
717 h = sc430cs->cur_mode->height;
718 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
719 if (w == supported_modes[i].width &&
720 h == supported_modes[i].height &&
721 supported_modes[i].hdr_mode == hdr->hdr_mode) {
722 sc430cs->cur_mode = &supported_modes[i];
723 break;
724 }
725 }
726 if (i == ARRAY_SIZE(supported_modes)) {
727 dev_err(&sc430cs->client->dev,
728 "not find hdr mode:%d %dx%d config\n",
729 hdr->hdr_mode, w, h);
730 ret = -EINVAL;
731 } else {
732 w = sc430cs->cur_mode->hts_def - sc430cs->cur_mode->width;
733 h = sc430cs->cur_mode->vts_def - sc430cs->cur_mode->height;
734 __v4l2_ctrl_modify_range(sc430cs->hblank, w, w, 1, w);
735 __v4l2_ctrl_modify_range(sc430cs->vblank, h,
736 SC430CS_VTS_MAX - sc430cs->cur_mode->height, 1, h);
737 sc430cs->cur_fps = sc430cs->cur_mode->max_fps;
738 sc430cs->cur_vts = sc430cs->cur_mode->vts_def;
739 }
740 break;
741 case PREISP_CMD_SET_HDRAE_EXP:
742 break;
743 case RKMODULE_SET_QUICK_STREAM:
744
745 stream = *((u32 *)arg);
746
747 if (stream)
748 ret = sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
749 SC430CS_REG_VALUE_08BIT, SC430CS_MODE_STREAMING);
750 else
751 ret = sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
752 SC430CS_REG_VALUE_08BIT, SC430CS_MODE_SW_STANDBY);
753 break;
754 default:
755 ret = -ENOIOCTLCMD;
756 break;
757 }
758
759 return ret;
760 }
761
762 #ifdef CONFIG_COMPAT
sc430cs_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)763 static long sc430cs_compat_ioctl32(struct v4l2_subdev *sd,
764 unsigned int cmd, unsigned long arg)
765 {
766 void __user *up = compat_ptr(arg);
767 struct rkmodule_inf *inf;
768 struct rkmodule_awb_cfg *cfg;
769 struct rkmodule_hdr_cfg *hdr;
770 struct preisp_hdrae_exp_s *hdrae;
771 long ret;
772 u32 stream = 0;
773
774 switch (cmd) {
775 case RKMODULE_GET_MODULE_INFO:
776 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
777 if (!inf) {
778 ret = -ENOMEM;
779 return ret;
780 }
781
782 ret = sc430cs_ioctl(sd, cmd, inf);
783 if (!ret) {
784 ret = copy_to_user(up, inf, sizeof(*inf));
785 if (ret)
786 ret = -EFAULT;
787 }
788 kfree(inf);
789 break;
790 case RKMODULE_AWB_CFG:
791 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
792 if (!cfg) {
793 ret = -ENOMEM;
794 return ret;
795 }
796
797 ret = copy_from_user(cfg, up, sizeof(*cfg));
798 if (!ret)
799 ret = sc430cs_ioctl(sd, cmd, cfg);
800 else
801 ret = -EFAULT;
802 kfree(cfg);
803 break;
804 case RKMODULE_GET_HDR_CFG:
805 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
806 if (!hdr) {
807 ret = -ENOMEM;
808 return ret;
809 }
810
811 ret = sc430cs_ioctl(sd, cmd, hdr);
812 if (!ret) {
813 ret = copy_to_user(up, hdr, sizeof(*hdr));
814 if (ret)
815 ret = -EFAULT;
816 }
817 kfree(hdr);
818 break;
819 case RKMODULE_SET_HDR_CFG:
820 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
821 if (!hdr) {
822 ret = -ENOMEM;
823 return ret;
824 }
825
826 ret = copy_from_user(hdr, up, sizeof(*hdr));
827 if (!ret)
828 ret = sc430cs_ioctl(sd, cmd, hdr);
829 else
830 ret = -EFAULT;
831 kfree(hdr);
832 break;
833 case PREISP_CMD_SET_HDRAE_EXP:
834 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
835 if (!hdrae) {
836 ret = -ENOMEM;
837 return ret;
838 }
839
840 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
841 if (!ret)
842 ret = sc430cs_ioctl(sd, cmd, hdrae);
843 else
844 ret = -EFAULT;
845 kfree(hdrae);
846 break;
847 case RKMODULE_SET_QUICK_STREAM:
848 ret = copy_from_user(&stream, up, sizeof(u32));
849 if (!ret)
850 ret = sc430cs_ioctl(sd, cmd, &stream);
851 else
852 ret = -EFAULT;
853 break;
854 default:
855 ret = -ENOIOCTLCMD;
856 break;
857 }
858
859 return ret;
860 }
861 #endif
862
__sc430cs_start_stream(struct sc430cs * sc430cs)863 static int __sc430cs_start_stream(struct sc430cs *sc430cs)
864 {
865 int ret;
866
867 ret = sc430cs_write_array(sc430cs->client, sc430cs->cur_mode->reg_list);
868 if (ret)
869 return ret;
870
871 /* In case these controls are set before streaming */
872 ret = __v4l2_ctrl_handler_setup(&sc430cs->ctrl_handler);
873 if (ret)
874 return ret;
875
876 return sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
877 SC430CS_REG_VALUE_08BIT, SC430CS_MODE_STREAMING);
878 }
879
__sc430cs_stop_stream(struct sc430cs * sc430cs)880 static int __sc430cs_stop_stream(struct sc430cs *sc430cs)
881 {
882 return sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
883 SC430CS_REG_VALUE_08BIT, SC430CS_MODE_SW_STANDBY);
884 }
885
sc430cs_s_stream(struct v4l2_subdev * sd,int on)886 static int sc430cs_s_stream(struct v4l2_subdev *sd, int on)
887 {
888 struct sc430cs *sc430cs = to_sc430cs(sd);
889 struct i2c_client *client = sc430cs->client;
890 int ret = 0;
891
892 mutex_lock(&sc430cs->mutex);
893 on = !!on;
894 if (on == sc430cs->streaming)
895 goto unlock_and_return;
896
897 if (on) {
898 ret = pm_runtime_get_sync(&client->dev);
899 if (ret < 0) {
900 pm_runtime_put_noidle(&client->dev);
901 goto unlock_and_return;
902 }
903
904 ret = __sc430cs_start_stream(sc430cs);
905 if (ret) {
906 v4l2_err(sd, "start stream failed while write regs\n");
907 pm_runtime_put(&client->dev);
908 goto unlock_and_return;
909 }
910 } else {
911 __sc430cs_stop_stream(sc430cs);
912 pm_runtime_put(&client->dev);
913 }
914
915 sc430cs->streaming = on;
916
917 unlock_and_return:
918 mutex_unlock(&sc430cs->mutex);
919
920 return ret;
921 }
922
sc430cs_s_power(struct v4l2_subdev * sd,int on)923 static int sc430cs_s_power(struct v4l2_subdev *sd, int on)
924 {
925 struct sc430cs *sc430cs = to_sc430cs(sd);
926 struct i2c_client *client = sc430cs->client;
927 int ret = 0;
928
929 mutex_lock(&sc430cs->mutex);
930
931 /* If the power state is not modified - no work to do. */
932 if (sc430cs->power_on == !!on)
933 goto unlock_and_return;
934
935 if (on) {
936 ret = pm_runtime_get_sync(&client->dev);
937 if (ret < 0) {
938 pm_runtime_put_noidle(&client->dev);
939 goto unlock_and_return;
940 }
941
942 ret = sc430cs_write_array(sc430cs->client, sc430cs_global_regs);
943 if (ret) {
944 v4l2_err(sd, "could not set init registers\n");
945 pm_runtime_put_noidle(&client->dev);
946 goto unlock_and_return;
947 }
948
949 sc430cs->power_on = true;
950 } else {
951 pm_runtime_put(&client->dev);
952 sc430cs->power_on = false;
953 }
954
955 unlock_and_return:
956 mutex_unlock(&sc430cs->mutex);
957
958 return ret;
959 }
960
961 /* Calculate the delay in us by clock rate and clock cycles */
sc430cs_cal_delay(u32 cycles)962 static inline u32 sc430cs_cal_delay(u32 cycles)
963 {
964 return DIV_ROUND_UP(cycles, SC430CS_XVCLK_FREQ / 1000 / 1000);
965 }
966
__sc430cs_power_on(struct sc430cs * sc430cs)967 static int __sc430cs_power_on(struct sc430cs *sc430cs)
968 {
969 int ret;
970 u32 delay_us;
971 struct device *dev = &sc430cs->client->dev;
972
973 if (!IS_ERR_OR_NULL(sc430cs->pins_default)) {
974 ret = pinctrl_select_state(sc430cs->pinctrl,
975 sc430cs->pins_default);
976 if (ret < 0)
977 dev_err(dev, "could not set pins\n");
978 }
979 ret = clk_set_rate(sc430cs->xvclk, SC430CS_XVCLK_FREQ);
980 if (ret < 0)
981 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
982 if (clk_get_rate(sc430cs->xvclk) != SC430CS_XVCLK_FREQ)
983 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
984 ret = clk_prepare_enable(sc430cs->xvclk);
985 if (ret < 0) {
986 dev_err(dev, "Failed to enable xvclk\n");
987 return ret;
988 }
989 if (!IS_ERR(sc430cs->reset_gpio))
990 gpiod_set_value_cansleep(sc430cs->reset_gpio, 0);
991
992 ret = regulator_bulk_enable(SC430CS_NUM_SUPPLIES, sc430cs->supplies);
993 if (ret < 0) {
994 dev_err(dev, "Failed to enable regulators\n");
995 goto disable_clk;
996 }
997
998 if (!IS_ERR(sc430cs->reset_gpio))
999 gpiod_set_value_cansleep(sc430cs->reset_gpio, 1);
1000
1001 usleep_range(500, 1000);
1002 if (!IS_ERR(sc430cs->pwdn_gpio))
1003 gpiod_set_value_cansleep(sc430cs->pwdn_gpio, 1);
1004
1005 if (!IS_ERR(sc430cs->reset_gpio))
1006 usleep_range(6000, 8000);
1007 else
1008 usleep_range(12000, 16000);
1009
1010 /* 8192 cycles prior to first SCCB transaction */
1011 delay_us = sc430cs_cal_delay(8192);
1012 usleep_range(delay_us, delay_us * 2);
1013
1014 return 0;
1015
1016 disable_clk:
1017 clk_disable_unprepare(sc430cs->xvclk);
1018
1019 return ret;
1020 }
1021
__sc430cs_power_off(struct sc430cs * sc430cs)1022 static void __sc430cs_power_off(struct sc430cs *sc430cs)
1023 {
1024 int ret;
1025 struct device *dev = &sc430cs->client->dev;
1026
1027 if (!IS_ERR(sc430cs->pwdn_gpio))
1028 gpiod_set_value_cansleep(sc430cs->pwdn_gpio, 0);
1029 clk_disable_unprepare(sc430cs->xvclk);
1030 if (!IS_ERR(sc430cs->reset_gpio))
1031 gpiod_set_value_cansleep(sc430cs->reset_gpio, 0);
1032 if (!IS_ERR_OR_NULL(sc430cs->pins_sleep)) {
1033 ret = pinctrl_select_state(sc430cs->pinctrl,
1034 sc430cs->pins_sleep);
1035 if (ret < 0)
1036 dev_dbg(dev, "could not set pins\n");
1037 }
1038 regulator_bulk_disable(SC430CS_NUM_SUPPLIES, sc430cs->supplies);
1039 }
1040
sc430cs_runtime_resume(struct device * dev)1041 static int sc430cs_runtime_resume(struct device *dev)
1042 {
1043 struct i2c_client *client = to_i2c_client(dev);
1044 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1045 struct sc430cs *sc430cs = to_sc430cs(sd);
1046
1047 return __sc430cs_power_on(sc430cs);
1048 }
1049
sc430cs_runtime_suspend(struct device * dev)1050 static int sc430cs_runtime_suspend(struct device *dev)
1051 {
1052 struct i2c_client *client = to_i2c_client(dev);
1053 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1054 struct sc430cs *sc430cs = to_sc430cs(sd);
1055
1056 __sc430cs_power_off(sc430cs);
1057
1058 return 0;
1059 }
1060
1061 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc430cs_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1062 static int sc430cs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1063 {
1064 struct sc430cs *sc430cs = to_sc430cs(sd);
1065 struct v4l2_mbus_framefmt *try_fmt =
1066 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1067 const struct sc430cs_mode *def_mode = &supported_modes[0];
1068
1069 mutex_lock(&sc430cs->mutex);
1070 /* Initialize try_fmt */
1071 try_fmt->width = def_mode->width;
1072 try_fmt->height = def_mode->height;
1073 try_fmt->code = def_mode->bus_fmt;
1074 try_fmt->field = V4L2_FIELD_NONE;
1075
1076 mutex_unlock(&sc430cs->mutex);
1077 /* No crop or compose */
1078
1079 return 0;
1080 }
1081 #endif
1082
sc430cs_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1083 static int sc430cs_enum_frame_interval(struct v4l2_subdev *sd,
1084 struct v4l2_subdev_pad_config *cfg,
1085 struct v4l2_subdev_frame_interval_enum *fie)
1086 {
1087 if (fie->index >= ARRAY_SIZE(supported_modes))
1088 return -EINVAL;
1089
1090 fie->code = supported_modes[fie->index].bus_fmt;
1091 fie->width = supported_modes[fie->index].width;
1092 fie->height = supported_modes[fie->index].height;
1093 fie->interval = supported_modes[fie->index].max_fps;
1094 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1095 return 0;
1096 }
1097
1098 static const struct dev_pm_ops sc430cs_pm_ops = {
1099 SET_RUNTIME_PM_OPS(sc430cs_runtime_suspend,
1100 sc430cs_runtime_resume, NULL)
1101 };
1102
1103 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1104 static const struct v4l2_subdev_internal_ops sc430cs_internal_ops = {
1105 .open = sc430cs_open,
1106 };
1107 #endif
1108
1109 static const struct v4l2_subdev_core_ops sc430cs_core_ops = {
1110 .s_power = sc430cs_s_power,
1111 .ioctl = sc430cs_ioctl,
1112 #ifdef CONFIG_COMPAT
1113 .compat_ioctl32 = sc430cs_compat_ioctl32,
1114 #endif
1115 };
1116
1117 static const struct v4l2_subdev_video_ops sc430cs_video_ops = {
1118 .s_stream = sc430cs_s_stream,
1119 .g_frame_interval = sc430cs_g_frame_interval,
1120 };
1121
1122 static const struct v4l2_subdev_pad_ops sc430cs_pad_ops = {
1123 .enum_mbus_code = sc430cs_enum_mbus_code,
1124 .enum_frame_size = sc430cs_enum_frame_sizes,
1125 .enum_frame_interval = sc430cs_enum_frame_interval,
1126 .get_fmt = sc430cs_get_fmt,
1127 .set_fmt = sc430cs_set_fmt,
1128 .get_mbus_config = sc430cs_g_mbus_config,
1129 };
1130
1131 static const struct v4l2_subdev_ops sc430cs_subdev_ops = {
1132 .core = &sc430cs_core_ops,
1133 .video = &sc430cs_video_ops,
1134 .pad = &sc430cs_pad_ops,
1135 };
1136
sc430cs_modify_fps_info(struct sc430cs * sc430cs)1137 static void sc430cs_modify_fps_info(struct sc430cs *sc430cs)
1138 {
1139 const struct sc430cs_mode *mode = sc430cs->cur_mode;
1140
1141 sc430cs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1142 sc430cs->cur_vts;
1143 }
1144
sc430cs_set_ctrl(struct v4l2_ctrl * ctrl)1145 static int sc430cs_set_ctrl(struct v4l2_ctrl *ctrl)
1146 {
1147 struct sc430cs *sc430cs = container_of(ctrl->handler,
1148 struct sc430cs, ctrl_handler);
1149 struct i2c_client *client = sc430cs->client;
1150 s64 max;
1151 int ret = 0;
1152 u32 val = 0;
1153
1154 /* Propagate change of current control to all related controls */
1155 switch (ctrl->id) {
1156 case V4L2_CID_VBLANK:
1157 /* Update max exposure while meeting expected vblanking */
1158 max = sc430cs->cur_mode->height + ctrl->val - 4;
1159 __v4l2_ctrl_modify_range(sc430cs->exposure,
1160 sc430cs->exposure->minimum, max,
1161 sc430cs->exposure->step,
1162 sc430cs->exposure->default_value);
1163 break;
1164 }
1165
1166 if (!pm_runtime_get_if_in_use(&client->dev))
1167 return 0;
1168
1169 switch (ctrl->id) {
1170 case V4L2_CID_EXPOSURE:
1171 if (sc430cs->cur_mode->hdr_mode == NO_HDR) {
1172 val = ctrl->val << 1;
1173 /* 4 least significant bits of expsoure are fractional part */
1174 ret = sc430cs_write_reg(sc430cs->client,
1175 SC430CS_REG_EXPOSURE_H,
1176 SC430CS_REG_VALUE_08BIT,
1177 SC430CS_FETCH_EXP_H(val));
1178 ret |= sc430cs_write_reg(sc430cs->client,
1179 SC430CS_REG_EXPOSURE_M,
1180 SC430CS_REG_VALUE_08BIT,
1181 SC430CS_FETCH_EXP_M(val));
1182 ret |= sc430cs_write_reg(sc430cs->client,
1183 SC430CS_REG_EXPOSURE_L,
1184 SC430CS_REG_VALUE_08BIT,
1185 SC430CS_FETCH_EXP_L(val));
1186 }
1187 break;
1188 case V4L2_CID_ANALOGUE_GAIN:
1189 if (sc430cs->cur_mode->hdr_mode == NO_HDR)
1190 ret = sc430cs_set_gain_reg(sc430cs, ctrl->val);
1191 break;
1192 case V4L2_CID_VBLANK:
1193 ret = sc430cs_write_reg(sc430cs->client,
1194 SC430CS_REG_VTS_H,
1195 SC430CS_REG_VALUE_08BIT,
1196 (ctrl->val + sc430cs->cur_mode->height)
1197 >> 8);
1198 ret |= sc430cs_write_reg(sc430cs->client,
1199 SC430CS_REG_VTS_L,
1200 SC430CS_REG_VALUE_08BIT,
1201 (ctrl->val + sc430cs->cur_mode->height)
1202 & 0xff);
1203 if (!ret)
1204 sc430cs->cur_vts = ctrl->val + sc430cs->cur_mode->height;
1205 sc430cs_modify_fps_info(sc430cs);
1206 break;
1207 case V4L2_CID_TEST_PATTERN:
1208 ret = sc430cs_enable_test_pattern(sc430cs, ctrl->val);
1209 break;
1210 case V4L2_CID_HFLIP:
1211 ret = sc430cs_read_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
1212 SC430CS_REG_VALUE_08BIT, &val);
1213 ret |= sc430cs_write_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
1214 SC430CS_REG_VALUE_08BIT,
1215 SC430CS_FETCH_MIRROR(val, ctrl->val));
1216 break;
1217 case V4L2_CID_VFLIP:
1218 ret = sc430cs_read_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
1219 SC430CS_REG_VALUE_08BIT, &val);
1220 ret |= sc430cs_write_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
1221 SC430CS_REG_VALUE_08BIT,
1222 SC430CS_FETCH_FLIP(val, ctrl->val));
1223 break;
1224 default:
1225 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1226 __func__, ctrl->id, ctrl->val);
1227 break;
1228 }
1229
1230 pm_runtime_put(&client->dev);
1231
1232 return ret;
1233 }
1234
1235 static const struct v4l2_ctrl_ops sc430cs_ctrl_ops = {
1236 .s_ctrl = sc430cs_set_ctrl,
1237 };
1238
sc430cs_initialize_controls(struct sc430cs * sc430cs)1239 static int sc430cs_initialize_controls(struct sc430cs *sc430cs)
1240 {
1241 const struct sc430cs_mode *mode;
1242 struct v4l2_ctrl_handler *handler;
1243 struct v4l2_ctrl *ctrl;
1244 s64 exposure_max, vblank_def;
1245 u32 h_blank;
1246 int ret;
1247
1248 handler = &sc430cs->ctrl_handler;
1249 mode = sc430cs->cur_mode;
1250 ret = v4l2_ctrl_handler_init(handler, 9);
1251 if (ret)
1252 return ret;
1253 handler->lock = &sc430cs->mutex;
1254
1255 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1256 0, 0, link_freq_menu_items);
1257 if (ctrl)
1258 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1259
1260 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1261 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT);
1262
1263 h_blank = mode->hts_def - mode->width;
1264 sc430cs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1265 h_blank, h_blank, 1, h_blank);
1266 if (sc430cs->hblank)
1267 sc430cs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1268 vblank_def = mode->vts_def - mode->height;
1269 sc430cs->vblank = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
1270 V4L2_CID_VBLANK, vblank_def,
1271 SC430CS_VTS_MAX - mode->height,
1272 1, vblank_def);
1273 exposure_max = mode->vts_def - 4;
1274 sc430cs->exposure = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
1275 V4L2_CID_EXPOSURE, SC430CS_EXPOSURE_MIN,
1276 exposure_max, SC430CS_EXPOSURE_STEP,
1277 mode->exp_def);
1278 sc430cs->anal_gain = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
1279 V4L2_CID_ANALOGUE_GAIN, SC430CS_GAIN_MIN,
1280 SC430CS_GAIN_MAX, SC430CS_GAIN_STEP,
1281 SC430CS_GAIN_DEFAULT);
1282 sc430cs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1283 &sc430cs_ctrl_ops,
1284 V4L2_CID_TEST_PATTERN,
1285 ARRAY_SIZE(sc430cs_test_pattern_menu) - 1,
1286 0, 0, sc430cs_test_pattern_menu);
1287 v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
1288 V4L2_CID_HFLIP, 0, 1, 1, 0);
1289 v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
1290 V4L2_CID_VFLIP, 0, 1, 1, 0);
1291 if (handler->error) {
1292 ret = handler->error;
1293 dev_err(&sc430cs->client->dev,
1294 "Failed to init controls(%d)\n", ret);
1295 goto err_free_handler;
1296 }
1297
1298 sc430cs->subdev.ctrl_handler = handler;
1299 sc430cs->cur_fps = mode->max_fps;
1300 sc430cs->cur_vts = mode->vts_def;
1301
1302 return 0;
1303
1304 err_free_handler:
1305 v4l2_ctrl_handler_free(handler);
1306
1307 return ret;
1308 }
1309
sc430cs_check_sensor_id(struct sc430cs * sc430cs,struct i2c_client * client)1310 static int sc430cs_check_sensor_id(struct sc430cs *sc430cs,
1311 struct i2c_client *client)
1312 {
1313 struct device *dev = &sc430cs->client->dev;
1314 u32 id = 0;
1315 int ret;
1316
1317 ret = sc430cs_read_reg(client, SC430CS_REG_CHIP_ID,
1318 SC430CS_REG_VALUE_16BIT, &id);
1319 if (id != CHIP_ID) {
1320 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1321 return -ENODEV;
1322 }
1323
1324 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1325
1326 return 0;
1327 }
1328
sc430cs_configure_regulators(struct sc430cs * sc430cs)1329 static int sc430cs_configure_regulators(struct sc430cs *sc430cs)
1330 {
1331 unsigned int i;
1332
1333 for (i = 0; i < SC430CS_NUM_SUPPLIES; i++)
1334 sc430cs->supplies[i].supply = sc430cs_supply_names[i];
1335
1336 return devm_regulator_bulk_get(&sc430cs->client->dev,
1337 SC430CS_NUM_SUPPLIES,
1338 sc430cs->supplies);
1339 }
1340
sc430cs_probe(struct i2c_client * client,const struct i2c_device_id * id)1341 static int sc430cs_probe(struct i2c_client *client,
1342 const struct i2c_device_id *id)
1343 {
1344 struct device *dev = &client->dev;
1345 struct device_node *node = dev->of_node;
1346 struct sc430cs *sc430cs;
1347 struct v4l2_subdev *sd;
1348 char facing[2];
1349 int ret;
1350 u32 i, hdr_mode = 0;
1351
1352 dev_info(dev, "driver version: %02x.%02x.%02x",
1353 DRIVER_VERSION >> 16,
1354 (DRIVER_VERSION & 0xff00) >> 8,
1355 DRIVER_VERSION & 0x00ff);
1356
1357 sc430cs = devm_kzalloc(dev, sizeof(*sc430cs), GFP_KERNEL);
1358 if (!sc430cs)
1359 return -ENOMEM;
1360
1361 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1362 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1363 &sc430cs->module_index);
1364 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1365 &sc430cs->module_facing);
1366 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1367 &sc430cs->module_name);
1368 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1369 &sc430cs->len_name);
1370 if (ret) {
1371 dev_err(dev, "could not get module information!\n");
1372 return -EINVAL;
1373 }
1374
1375 sc430cs->client = client;
1376 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1377 if (hdr_mode == supported_modes[i].hdr_mode) {
1378 sc430cs->cur_mode = &supported_modes[i];
1379 break;
1380 }
1381 }
1382 if (i == ARRAY_SIZE(supported_modes))
1383 sc430cs->cur_mode = &supported_modes[0];
1384
1385 sc430cs->xvclk = devm_clk_get(dev, "xvclk");
1386 if (IS_ERR(sc430cs->xvclk)) {
1387 dev_err(dev, "Failed to get xvclk\n");
1388 return -EINVAL;
1389 }
1390
1391 sc430cs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1392 if (IS_ERR(sc430cs->reset_gpio))
1393 dev_warn(dev, "Failed to get reset-gpios\n");
1394
1395 sc430cs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1396 if (IS_ERR(sc430cs->pwdn_gpio))
1397 dev_warn(dev, "Failed to get pwdn-gpios\n");
1398
1399 sc430cs->pinctrl = devm_pinctrl_get(dev);
1400 if (!IS_ERR(sc430cs->pinctrl)) {
1401 sc430cs->pins_default =
1402 pinctrl_lookup_state(sc430cs->pinctrl,
1403 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1404 if (IS_ERR(sc430cs->pins_default))
1405 dev_err(dev, "could not get default pinstate\n");
1406
1407 sc430cs->pins_sleep =
1408 pinctrl_lookup_state(sc430cs->pinctrl,
1409 OF_CAMERA_PINCTRL_STATE_SLEEP);
1410 if (IS_ERR(sc430cs->pins_sleep))
1411 dev_err(dev, "could not get sleep pinstate\n");
1412 } else {
1413 dev_err(dev, "no pinctrl\n");
1414 }
1415
1416 ret = sc430cs_configure_regulators(sc430cs);
1417 if (ret) {
1418 dev_err(dev, "Failed to get power regulators\n");
1419 return ret;
1420 }
1421
1422 mutex_init(&sc430cs->mutex);
1423
1424 sd = &sc430cs->subdev;
1425 v4l2_i2c_subdev_init(sd, client, &sc430cs_subdev_ops);
1426 ret = sc430cs_initialize_controls(sc430cs);
1427 if (ret)
1428 goto err_destroy_mutex;
1429
1430 ret = __sc430cs_power_on(sc430cs);
1431 if (ret)
1432 goto err_free_handler;
1433
1434 ret = sc430cs_check_sensor_id(sc430cs, client);
1435 if (ret)
1436 goto err_power_off;
1437
1438 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1439 sd->internal_ops = &sc430cs_internal_ops;
1440 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1441 V4L2_SUBDEV_FL_HAS_EVENTS;
1442 #endif
1443 #if defined(CONFIG_MEDIA_CONTROLLER)
1444 sc430cs->pad.flags = MEDIA_PAD_FL_SOURCE;
1445 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1446 ret = media_entity_pads_init(&sd->entity, 1, &sc430cs->pad);
1447 if (ret < 0)
1448 goto err_power_off;
1449 #endif
1450
1451 memset(facing, 0, sizeof(facing));
1452 if (strcmp(sc430cs->module_facing, "back") == 0)
1453 facing[0] = 'b';
1454 else
1455 facing[0] = 'f';
1456
1457 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1458 sc430cs->module_index, facing,
1459 SC430CS_NAME, dev_name(sd->dev));
1460 ret = v4l2_async_register_subdev_sensor_common(sd);
1461 if (ret) {
1462 dev_err(dev, "v4l2 async register subdev failed\n");
1463 goto err_clean_entity;
1464 }
1465
1466 pm_runtime_set_active(dev);
1467 pm_runtime_enable(dev);
1468 pm_runtime_idle(dev);
1469
1470 return 0;
1471
1472 err_clean_entity:
1473 #if defined(CONFIG_MEDIA_CONTROLLER)
1474 media_entity_cleanup(&sd->entity);
1475 #endif
1476 err_power_off:
1477 __sc430cs_power_off(sc430cs);
1478 err_free_handler:
1479 v4l2_ctrl_handler_free(&sc430cs->ctrl_handler);
1480 err_destroy_mutex:
1481 mutex_destroy(&sc430cs->mutex);
1482
1483 return ret;
1484 }
1485
sc430cs_remove(struct i2c_client * client)1486 static int sc430cs_remove(struct i2c_client *client)
1487 {
1488 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1489 struct sc430cs *sc430cs = to_sc430cs(sd);
1490
1491 v4l2_async_unregister_subdev(sd);
1492 #if defined(CONFIG_MEDIA_CONTROLLER)
1493 media_entity_cleanup(&sd->entity);
1494 #endif
1495 v4l2_ctrl_handler_free(&sc430cs->ctrl_handler);
1496 mutex_destroy(&sc430cs->mutex);
1497
1498 pm_runtime_disable(&client->dev);
1499 if (!pm_runtime_status_suspended(&client->dev))
1500 __sc430cs_power_off(sc430cs);
1501 pm_runtime_set_suspended(&client->dev);
1502
1503 return 0;
1504 }
1505
1506 #if IS_ENABLED(CONFIG_OF)
1507 static const struct of_device_id sc430cs_of_match[] = {
1508 { .compatible = "smartsens,sc430cs" },
1509 {},
1510 };
1511 MODULE_DEVICE_TABLE(of, sc430cs_of_match);
1512 #endif
1513
1514 static const struct i2c_device_id sc430cs_match_id[] = {
1515 { "smartsens,sc430cs", 0 },
1516 { },
1517 };
1518
1519 static struct i2c_driver sc430cs_i2c_driver = {
1520 .driver = {
1521 .name = SC430CS_NAME,
1522 .pm = &sc430cs_pm_ops,
1523 .of_match_table = of_match_ptr(sc430cs_of_match),
1524 },
1525 .probe = &sc430cs_probe,
1526 .remove = &sc430cs_remove,
1527 .id_table = sc430cs_match_id,
1528 };
1529
sensor_mod_init(void)1530 static int __init sensor_mod_init(void)
1531 {
1532 return i2c_add_driver(&sc430cs_i2c_driver);
1533 }
1534
sensor_mod_exit(void)1535 static void __exit sensor_mod_exit(void)
1536 {
1537 i2c_del_driver(&sc430cs_i2c_driver);
1538 }
1539
1540 device_initcall_sync(sensor_mod_init);
1541 module_exit(sensor_mod_exit);
1542
1543 MODULE_DESCRIPTION("smartsens sc430cs sensor driver");
1544 MODULE_LICENSE("GPL v2");
1545