1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc401ai driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 add quick stream on/off
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/rk-camera-module.h>
28 #include <linux/rk-preisp.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define SC401AI_BITS_PER_SAMPLE 10
42
43 #define SC401AI_LINK_FREQ_315 157500000// 315Mbps
44 #define SC401AI_LINK_FREQ_630 315000000// 630Mbps
45
46 #define PIXEL_RATE_WITH_315M_10BIT (SC401AI_LINK_FREQ_315 * 2 * \
47 4 / SC401AI_BITS_PER_SAMPLE)
48 #define PIXEL_RATE_WITH_630M_10BIT (SC401AI_LINK_FREQ_630 * 2 * \
49 2 / SC401AI_BITS_PER_SAMPLE)
50 #define PIXEL_RATE_WITH_MAX (SC401AI_LINK_FREQ_630 * 2 * \
51 2 / SC401AI_BITS_PER_SAMPLE)
52
53 #define SC401AI_XVCLK_FREQ 27000000
54
55 #define CHIP_ID 0xcd2e
56 #define SC401AI_REG_CHIP_ID 0x3107
57
58 #define SC401AI_REG_CTRL_MODE 0x0100
59 #define SC401AI_MODE_SW_STANDBY 0x0
60 #define SC401AI_MODE_STREAMING BIT(0)
61
62 #define SC401AI_REG_EXPOSURE_H 0x3e00
63 #define SC401AI_REG_EXPOSURE_M 0x3e01
64 #define SC401AI_REG_EXPOSURE_L 0x3e02
65 #define SC401AI_EXPOSURE_MIN 1
66 #define SC401AI_EXPOSURE_STEP 1
67 #define SC401AI_VTS_MAX 0x7fff
68
69 #define SC401AI_REG_DIG_GAIN 0x3e06
70 #define SC401AI_REG_DIG_FINE_GAIN 0x3e07
71 #define SC401AI_REG_ANA_GAIN 0x3e08
72 #define SC401AI_REG_ANA_FINE_GAIN 0x3e09
73 #define SC401AI_GAIN_MIN 0x0040
74 #define SC401AI_GAIN_MAX (24 * 32 * 64) //23.32*31.75*64
75 #define SC401AI_GAIN_STEP 1
76 #define SC401AI_GAIN_DEFAULT 0x0800
77
78 #define SC401AI_REG_GROUP_HOLD 0x3812
79 #define SC401AI_GROUP_HOLD_START 0x00
80 #define SC401AI_GROUP_HOLD_END 0x30
81
82 #define SC401AI_REG_HIGH_TEMP_H 0x3974
83 #define SC401AI_REG_HIGH_TEMP_L 0x3975
84
85 #define SC401AI_REG_TEST_PATTERN 0x4501
86 #define SC401AI_TEST_PATTERN_BIT_MASK BIT(3)
87
88 #define SC401AI_REG_VTS_H 0x320e
89 #define SC401AI_REG_VTS_L 0x320f
90
91 #define SC401AI_FLIP_MIRROR_REG 0x3221
92
93 #define SC401AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
94 #define SC401AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
95 #define SC401AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
96
97 #define SC401AI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
98 #define SC401AI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
99
100 #define SC401AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
101 #define SC401AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
102
103 #define REG_DELAY 0xFFFE
104 #define REG_NULL 0xFFFF
105
106 #define SC401AI_REG_VALUE_08BIT 1
107 #define SC401AI_REG_VALUE_16BIT 2
108 #define SC401AI_REG_VALUE_24BIT 3
109
110 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
111 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
112 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
113 #define SC401AI_NAME "sc401ai"
114
115 static const char * const sc401ai_supply_names[] = {
116 "avdd", /* Analog power */
117 "dovdd", /* Digital I/O power */
118 "dvdd", /* Digital core power */
119 };
120
121 #define SC401AI_NUM_SUPPLIES ARRAY_SIZE(sc401ai_supply_names)
122
123 struct regval {
124 u16 addr;
125 u8 val;
126 };
127
128 struct sc401ai_mode {
129 u32 bus_fmt;
130 u32 width;
131 u32 height;
132 struct v4l2_fract max_fps;
133 u32 hts_def;
134 u32 vts_def;
135 u32 exp_def;
136 const struct regval *reg_list;
137 u32 hdr_mode;
138 u32 mipi_freq_idx;
139 u32 vc[PAD_MAX];
140 };
141
142 struct sc401ai {
143 struct i2c_client *client;
144 struct clk *xvclk;
145 struct gpio_desc *reset_gpio;
146 struct gpio_desc *pwdn_gpio;
147 struct regulator_bulk_data supplies[SC401AI_NUM_SUPPLIES];
148
149 struct pinctrl *pinctrl;
150 struct pinctrl_state *pins_default;
151 struct pinctrl_state *pins_sleep;
152
153 struct v4l2_subdev subdev;
154 struct media_pad pad;
155 struct v4l2_ctrl_handler ctrl_handler;
156 struct v4l2_ctrl *exposure;
157 struct v4l2_ctrl *anal_gain;
158 struct v4l2_ctrl *digi_gain;
159 struct v4l2_ctrl *hblank;
160 struct v4l2_ctrl *vblank;
161 struct v4l2_ctrl *test_pattern;
162 struct v4l2_ctrl *pixel_rate;
163 struct v4l2_ctrl *link_freq;
164 struct mutex mutex;
165 struct v4l2_fract cur_fps;
166 bool streaming;
167 bool power_on;
168 unsigned int lane_num;
169 unsigned int cfg_num;
170 const struct sc401ai_mode *cur_mode;
171 u32 module_index;
172 const char *module_facing;
173 const char *module_name;
174 const char *len_name;
175 u32 cur_vts;
176 struct preisp_hdrae_exp_s init_hdrae_exp;
177 };
178
179 #define to_sc401ai(sd) container_of(sd, struct sc401ai, subdev)
180
181 /*
182 * Xclk 24Mhz
183 */
184 static const struct regval sc401ai_global_regs[] = {
185 {REG_NULL, 0x00},
186 };
187
188 /*
189 * Xclk 27Mhz
190 * max_framerate 30fps
191 * mipi_datarate per lane 315Mbps, 4lane
192 */
193 static const struct regval sc401ai_linear_10_2560x1440_4lane_regs[] = {
194 {0x0103, 0x01},
195 {0x0100, 0x00},
196 {0x36e9, 0x80},
197 {0x36f9, 0x80},
198 {0x301c, 0x78},
199 {0x301f, 0x01},
200 {0x3208, 0x0a},
201 {0x3209, 0x00},
202 {0x320a, 0x05},
203 {0x320b, 0xa0},
204 {0x320e, 0x05},
205 {0x320f, 0xdc},
206 {0x3214, 0x11},
207 {0x3215, 0x11},
208 {0x3223, 0x80},
209 {0x3250, 0x00},
210 {0x3253, 0x08},
211 {0x3274, 0x01},
212 {0x3301, 0x20},
213 {0x3302, 0x18},
214 {0x3303, 0x10},
215 {0x3304, 0x50},
216 {0x3306, 0x38},
217 {0x3308, 0x18},
218 {0x3309, 0x60},
219 {0x330b, 0xc0},
220 {0x330d, 0x10},
221 {0x330e, 0x18},
222 {0x330f, 0x04},
223 {0x3310, 0x02},
224 {0x331c, 0x04},
225 {0x331e, 0x41},
226 {0x331f, 0x51},
227 {0x3320, 0x09},
228 {0x3333, 0x10},
229 {0x334c, 0x08},
230 {0x3356, 0x09},
231 {0x3364, 0x17},
232 {0x338e, 0xfd},
233 {0x3390, 0x08},
234 {0x3391, 0x18},
235 {0x3392, 0x38},
236 {0x3393, 0x20},
237 {0x3394, 0x20},
238 {0x3395, 0x20},
239 {0x3396, 0x08},
240 {0x3397, 0x18},
241 {0x3398, 0x38},
242 {0x3399, 0x20},
243 {0x339a, 0x20},
244 {0x339b, 0x20},
245 {0x339c, 0x20},
246 {0x33ac, 0x10},
247 {0x33ae, 0x18},
248 {0x33af, 0x19},
249 {0x360f, 0x01},
250 {0x3620, 0x08},
251 {0x3637, 0x25},
252 {0x363a, 0x12},
253 {0x3670, 0x0a},
254 {0x3671, 0x07},
255 {0x3672, 0x57},
256 {0x3673, 0x5e},
257 {0x3674, 0x84},
258 {0x3675, 0x88},
259 {0x3676, 0x8a},
260 {0x367a, 0x58},
261 {0x367b, 0x78},
262 {0x367c, 0x58},
263 {0x367d, 0x78},
264 {0x3690, 0x33},
265 {0x3691, 0x43},
266 {0x3692, 0x34},
267 {0x369c, 0x40},
268 {0x369d, 0x78},
269 {0x36ea, 0x39},
270 {0x36eb, 0x0d},
271 {0x36ec, 0x2c},
272 {0x36ed, 0x24},
273 {0x36fa, 0x39},
274 {0x36fb, 0x33},
275 {0x36fc, 0x10},
276 {0x36fd, 0x14},
277 {0x3908, 0x41},
278 {0x396c, 0x0e},
279 {0x3e00, 0x00},
280 {0x3e01, 0xb6},
281 {0x3e02, 0x00},
282 {0x3e03, 0x0b},
283 {0x3e08, 0x03},
284 {0x3e09, 0x40},
285 {0x3e1b, 0x2a},
286 {0x4509, 0x30},
287 {0x57a8, 0xd0},
288 {0x36e9, 0x14},
289 {0x36f9, 0x14},
290 {REG_NULL, 0x00},
291 };
292
293 /*
294 * Xclk 27Mhz
295 * max_framerate 30fps
296 * mipi_datarate per lane 630Mbps, 2lane
297 */
298 static const struct regval sc401ai_linear_10_2560x1440_2lane_regs[] = {
299 {0x0103, 0x01},
300 {0x0100, 0x00},
301 {0x36e9, 0x80},
302 {0x36f9, 0x80},
303 {0x3018, 0x3a},
304 {0x3019, 0x0c},
305 {0x301c, 0x78},
306 {0x301f, 0x05},
307 {0x3208, 0x0a},
308 {0x3209, 0x00},
309 {0x320a, 0x05},
310 {0x320b, 0xa0},
311 {0x320e, 0x05},
312 {0x320f, 0xdc},
313 {0x3214, 0x11},
314 {0x3215, 0x11},
315 {0x3223, 0x80},
316 {0x3250, 0x00},
317 {0x3253, 0x08},
318 {0x3274, 0x01},
319 {0x3301, 0x20},
320 {0x3302, 0x18},
321 {0x3303, 0x10},
322 {0x3304, 0x50},
323 {0x3306, 0x38},
324 {0x3308, 0x18},
325 {0x3309, 0x60},
326 {0x330b, 0xc0},
327 {0x330d, 0x10},
328 {0x330e, 0x18},
329 {0x330f, 0x04},
330 {0x3310, 0x02},
331 {0x331c, 0x04},
332 {0x331e, 0x41},
333 {0x331f, 0x51},
334 {0x3320, 0x09},
335 {0x3333, 0x10},
336 {0x334c, 0x08},
337 {0x3356, 0x09},
338 {0x3364, 0x17},
339 {0x338e, 0xfd},
340 {0x3390, 0x08},
341 {0x3391, 0x18},
342 {0x3392, 0x38},
343 {0x3393, 0x20},
344 {0x3394, 0x20},
345 {0x3395, 0x20},
346 {0x3396, 0x08},
347 {0x3397, 0x18},
348 {0x3398, 0x38},
349 {0x3399, 0x20},
350 {0x339a, 0x20},
351 {0x339b, 0x20},
352 {0x339c, 0x20},
353 {0x33ac, 0x10},
354 {0x33ae, 0x18},
355 {0x33af, 0x19},
356 {0x360f, 0x01},
357 {0x3620, 0x08},
358 {0x3637, 0x25},
359 {0x363a, 0x12},
360 {0x3670, 0x0a},
361 {0x3671, 0x07},
362 {0x3672, 0x57},
363 {0x3673, 0x5e},
364 {0x3674, 0x84},
365 {0x3675, 0x88},
366 {0x3676, 0x8a},
367 {0x367a, 0x58},
368 {0x367b, 0x78},
369 {0x367c, 0x58},
370 {0x367d, 0x78},
371 {0x3690, 0x33},
372 {0x3691, 0x43},
373 {0x3692, 0x34},
374 {0x369c, 0x40},
375 {0x369d, 0x78},
376 {0x36ea, 0x39},
377 {0x36eb, 0x0d},
378 {0x36ec, 0x1c},
379 {0x36ed, 0x24},
380 {0x36fa, 0x39},
381 {0x36fb, 0x33},
382 {0x36fc, 0x10},
383 {0x36fd, 0x14},
384 {0x3908, 0x41},
385 {0x396c, 0x0e},
386 {0x3e00, 0x00},
387 {0x3e01, 0xb6},
388 {0x3e02, 0x00},
389 {0x3e03, 0x0b},
390 {0x3e08, 0x03},
391 {0x3e09, 0x40},
392 {0x3e1b, 0x2a},
393 {0x4509, 0x30},
394 {0x4819, 0x08},
395 {0x481b, 0x05},
396 {0x481d, 0x11},
397 {0x481f, 0x04},
398 {0x4821, 0x09},
399 {0x4823, 0x04},
400 {0x4825, 0x04},
401 {0x4827, 0x04},
402 {0x4829, 0x07},
403 {0x57a8, 0xd0},
404 {0x36e9, 0x14},
405 {0x36f9, 0x14},
406 //{0x0100, 0x01},
407 {REG_NULL, 0x00},
408 };
409
410 static const struct sc401ai_mode supported_modes[] = {
411 {
412 .width = 2560,
413 .height = 1440,
414 .max_fps = {
415 .numerator = 10000,
416 .denominator = 300000,
417 },
418 .exp_def = 0x0080,
419 .hts_def = 0x0578 * 2,
420 .vts_def = 0x05dc,
421 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
422 .reg_list = sc401ai_linear_10_2560x1440_4lane_regs,
423 .hdr_mode = NO_HDR,
424 .mipi_freq_idx = 0,
425 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
426 },
427 {
428 .width = 2560,
429 .height = 1440,
430 .max_fps = {
431 .numerator = 10000,
432 .denominator = 300000,
433 },
434 .exp_def = 0x0080,
435 .hts_def = 0x0578 * 2,
436 .vts_def = 0x05dc,
437 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
438 .reg_list = sc401ai_linear_10_2560x1440_2lane_regs,
439 .hdr_mode = NO_HDR,
440 .mipi_freq_idx = 1,
441 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
442 },
443 };
444
445 static const s64 link_freq_menu_items[] = {
446 SC401AI_LINK_FREQ_315,
447 SC401AI_LINK_FREQ_630,
448 };
449
450 /* Write registers up to 4 at a time */
sc401ai_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)451 static int sc401ai_write_reg(struct i2c_client *client, u16 reg,
452 u32 len, u32 val)
453 {
454 u32 buf_i, val_i;
455 u8 buf[6];
456 u8 *val_p;
457 __be32 val_be;
458
459 if (len > 4)
460 return -EINVAL;
461
462 buf[0] = reg >> 8;
463 buf[1] = reg & 0xff;
464
465 val_be = cpu_to_be32(val);
466 val_p = (u8 *)&val_be;
467 buf_i = 2;
468 val_i = 4 - len;
469
470 while (val_i < 4)
471 buf[buf_i++] = val_p[val_i++];
472
473 if (i2c_master_send(client, buf, len + 2) != len + 2)
474 return -EIO;
475 return 0;
476 }
477
sc401ai_write_array(struct i2c_client * client,const struct regval * regs)478 static int sc401ai_write_array(struct i2c_client *client,
479 const struct regval *regs)
480 {
481 u32 i;
482 int ret = 0;
483
484 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
485 ret = sc401ai_write_reg(client, regs[i].addr,
486 SC401AI_REG_VALUE_08BIT, regs[i].val);
487
488 return ret;
489 }
490
491 /* Read registers up to 4 at a time */
sc401ai_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)492 static int sc401ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
493 u32 *val)
494 {
495 struct i2c_msg msgs[2];
496 u8 *data_be_p;
497 __be32 data_be = 0;
498 __be16 reg_addr_be = cpu_to_be16(reg);
499 int ret;
500
501 if (len > 4 || !len)
502 return -EINVAL;
503
504 data_be_p = (u8 *)&data_be;
505 /* Write register address */
506 msgs[0].addr = client->addr;
507 msgs[0].flags = 0;
508 msgs[0].len = 2;
509 msgs[0].buf = (u8 *)®_addr_be;
510
511 /* Read data from register */
512 msgs[1].addr = client->addr;
513 msgs[1].flags = I2C_M_RD;
514 msgs[1].len = len;
515 msgs[1].buf = &data_be_p[4 - len];
516
517 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
518 if (ret != ARRAY_SIZE(msgs))
519 return -EIO;
520
521 *val = be32_to_cpu(data_be);
522
523 return 0;
524 }
525
sc401ai_set_gain_reg(struct sc401ai * sc401ai,u32 gain)526 static int sc401ai_set_gain_reg(struct sc401ai *sc401ai, u32 gain)
527 {
528 u8 Coarse_gain = 1, DIG_gain = 1;
529 u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1;
530 u8 Coarse_gain_reg = 0, DIG_gain_reg = 0;
531 u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80;
532 int ret = 0;
533
534 gain = gain * 16;
535 if (gain <= 1024)
536 gain = 1024;
537 else if (gain > SC401AI_GAIN_MAX * 16)
538 gain = SC401AI_GAIN_MAX * 16;
539
540 if (gain < 1504) { // start again
541 Dcg_gainx100 = 100;
542 Coarse_gain = 1;
543 DIG_gain = 1;
544 Coarse_gain_reg = 0x03;
545 DIG_gain_reg = 0x0;
546 DIG_Fine_gain_reg = 0x80;
547 } else if (gain <= 3008) {
548 Dcg_gainx100 = 147;
549 Coarse_gain = 1;
550 DIG_gain = 1;
551 Coarse_gain_reg = 0x23;
552 DIG_gain_reg = 0x0;
553 DIG_Fine_gain_reg = 0x80;
554 } else if (gain <= 6017) {
555 Dcg_gainx100 = 147;
556 Coarse_gain = 2;
557 DIG_gain = 1;
558 Coarse_gain_reg = 0x27;
559 DIG_gain_reg = 0x0;
560 DIG_Fine_gain_reg = 0x80;
561 } else if (gain <= 12034) {
562 Dcg_gainx100 = 147;
563 Coarse_gain = 4;
564 DIG_gain = 1;
565 Coarse_gain_reg = 0x2f;
566 DIG_gain_reg = 0x0;
567 DIG_Fine_gain_reg = 0x80;
568 } else if (gain <= 23879) { // end again
569 Dcg_gainx100 = 147;
570 Coarse_gain = 8;
571 DIG_gain = 1;
572 Coarse_gain_reg = 0x3f;
573 DIG_gain_reg = 0x0;
574 DIG_Fine_gain_reg = 0x80;
575 } else if (gain < 23879 * 2) { // start dgain
576 Dcg_gainx100 = 147;
577 Coarse_gain = 8;
578 DIG_gain = 1;
579 ANA_Fine_gainx64 = 127;
580 Coarse_gain_reg = 0x3f;
581 DIG_gain_reg = 0x0;
582 ANA_Fine_gain_reg = 0x7f;
583 } else if (gain < 23879 * 4) {
584 Dcg_gainx100 = 147;
585 Coarse_gain = 8;
586 DIG_gain = 2;
587 ANA_Fine_gainx64 = 127;
588 Coarse_gain_reg = 0x3f;
589 DIG_gain_reg = 0x1;
590 ANA_Fine_gain_reg = 0x7f;
591 } else if (gain < 23879 * 8) {
592 Dcg_gainx100 = 147;
593 Coarse_gain = 8;
594 DIG_gain = 4;
595 ANA_Fine_gainx64 = 127;
596 Coarse_gain_reg = 0x3f;
597 DIG_gain_reg = 0x3;
598 ANA_Fine_gain_reg = 0x7f;
599 } else if (gain < 23879 * 16) {
600 Dcg_gainx100 = 147;
601 Coarse_gain = 8;
602 DIG_gain = 8;
603 ANA_Fine_gainx64 = 127;
604 Coarse_gain_reg = 0x3f;
605 DIG_gain_reg = 0x7;
606 ANA_Fine_gain_reg = 0x7f;
607 } else if (gain <= 1754822) {
608 Dcg_gainx100 = 147;
609 Coarse_gain = 8;
610 DIG_gain = 16;
611 ANA_Fine_gainx64 = 127;
612 Coarse_gain_reg = 0x3f;
613 DIG_gain_reg = 0xF;
614 ANA_Fine_gain_reg = 0x7f;
615 }
616
617 if (gain < 1504)
618 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
619 else if (gain == 1504)
620 ANA_Fine_gain_reg = 0x40;
621 else if (gain < 23879)
622 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
623 else
624 DIG_Fine_gain_reg = abs(800 * gain / (Dcg_gainx100 * Coarse_gain *
625 DIG_gain) / ANA_Fine_gainx64);
626
627 ret = sc401ai_write_reg(sc401ai->client,
628 SC401AI_REG_DIG_GAIN,
629 SC401AI_REG_VALUE_08BIT,
630 DIG_gain_reg & 0xF);
631 ret |= sc401ai_write_reg(sc401ai->client,
632 SC401AI_REG_DIG_FINE_GAIN,
633 SC401AI_REG_VALUE_08BIT,
634 DIG_Fine_gain_reg);
635 ret |= sc401ai_write_reg(sc401ai->client,
636 SC401AI_REG_ANA_GAIN,
637 SC401AI_REG_VALUE_08BIT,
638 Coarse_gain_reg);
639 ret |= sc401ai_write_reg(sc401ai->client,
640 SC401AI_REG_ANA_FINE_GAIN,
641 SC401AI_REG_VALUE_08BIT,
642 ANA_Fine_gain_reg);
643
644 return ret;
645 }
646
sc401ai_get_reso_dist(const struct sc401ai_mode * mode,struct v4l2_mbus_framefmt * framefmt)647 static int sc401ai_get_reso_dist(const struct sc401ai_mode *mode,
648 struct v4l2_mbus_framefmt *framefmt)
649 {
650 return abs(mode->width - framefmt->width) +
651 abs(mode->height - framefmt->height);
652 }
653
654 static const struct sc401ai_mode *
sc401ai_find_best_fit(struct v4l2_subdev_format * fmt)655 sc401ai_find_best_fit(struct v4l2_subdev_format *fmt)
656 {
657 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
658 int dist;
659 int cur_best_fit = 0;
660 int cur_best_fit_dist = -1;
661 unsigned int i;
662
663 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
664 dist = sc401ai_get_reso_dist(&supported_modes[i], framefmt);
665 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
666 cur_best_fit_dist = dist;
667 cur_best_fit = i;
668 }
669 }
670
671 return &supported_modes[cur_best_fit];
672 }
673
sc401ai_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)674 static int sc401ai_set_fmt(struct v4l2_subdev *sd,
675 struct v4l2_subdev_pad_config *cfg,
676 struct v4l2_subdev_format *fmt)
677 {
678 struct sc401ai *sc401ai = to_sc401ai(sd);
679 const struct sc401ai_mode *mode;
680 s64 h_blank, vblank_def;
681
682 mutex_lock(&sc401ai->mutex);
683
684 mode = sc401ai_find_best_fit(fmt);
685 fmt->format.code = mode->bus_fmt;
686 fmt->format.width = mode->width;
687 fmt->format.height = mode->height;
688 fmt->format.field = V4L2_FIELD_NONE;
689 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
690 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
691 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
692 #else
693 mutex_unlock(&sc401ai->mutex);
694 return -ENOTTY;
695 #endif
696 } else {
697 sc401ai->cur_mode = mode;
698 h_blank = mode->hts_def - mode->width;
699 __v4l2_ctrl_modify_range(sc401ai->hblank, h_blank,
700 h_blank, 1, h_blank);
701 vblank_def = mode->vts_def - mode->height;
702 __v4l2_ctrl_modify_range(sc401ai->vblank, vblank_def,
703 SC401AI_VTS_MAX - mode->height,
704 1, vblank_def);
705 sc401ai->cur_fps = mode->max_fps;
706 sc401ai->cur_vts = mode->vts_def;
707 }
708
709 mutex_unlock(&sc401ai->mutex);
710
711 return 0;
712 }
713
sc401ai_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)714 static int sc401ai_get_fmt(struct v4l2_subdev *sd,
715 struct v4l2_subdev_pad_config *cfg,
716 struct v4l2_subdev_format *fmt)
717 {
718 struct sc401ai *sc401ai = to_sc401ai(sd);
719 const struct sc401ai_mode *mode = sc401ai->cur_mode;
720
721 mutex_lock(&sc401ai->mutex);
722 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
723 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
724 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
725 #else
726 mutex_unlock(&sc401ai->mutex);
727 return -ENOTTY;
728 #endif
729 } else {
730 fmt->format.width = mode->width;
731 fmt->format.height = mode->height;
732 fmt->format.code = mode->bus_fmt;
733 fmt->format.field = V4L2_FIELD_NONE;
734 /* format info: width/height/data type/virctual channel */
735 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
736 fmt->reserved[0] = mode->vc[fmt->pad];
737 else
738 fmt->reserved[0] = mode->vc[PAD0];
739 }
740 mutex_unlock(&sc401ai->mutex);
741
742 return 0;
743 }
744
sc401ai_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)745 static int sc401ai_enum_mbus_code(struct v4l2_subdev *sd,
746 struct v4l2_subdev_pad_config *cfg,
747 struct v4l2_subdev_mbus_code_enum *code)
748 {
749 struct sc401ai *sc401ai = to_sc401ai(sd);
750
751 if (code->index != 0)
752 return -EINVAL;
753 code->code = sc401ai->cur_mode->bus_fmt;
754
755 return 0;
756 }
757
sc401ai_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)758 static int sc401ai_enum_frame_sizes(struct v4l2_subdev *sd,
759 struct v4l2_subdev_pad_config *cfg,
760 struct v4l2_subdev_frame_size_enum *fse)
761 {
762 if (fse->index >= ARRAY_SIZE(supported_modes))
763 return -EINVAL;
764
765 if (fse->code != supported_modes[1].bus_fmt)
766 return -EINVAL;
767
768 fse->min_width = supported_modes[fse->index].width;
769 fse->max_width = supported_modes[fse->index].width;
770 fse->max_height = supported_modes[fse->index].height;
771 fse->min_height = supported_modes[fse->index].height;
772
773 return 0;
774 }
775
sc401ai_enable_test_pattern(struct sc401ai * sc401ai,u32 pattern)776 static int sc401ai_enable_test_pattern(struct sc401ai *sc401ai, u32 pattern)
777 {
778 u32 val = 0;
779 int ret = 0;
780
781 ret = sc401ai_read_reg(sc401ai->client, SC401AI_REG_TEST_PATTERN,
782 SC401AI_REG_VALUE_08BIT, &val);
783 if (pattern)
784 val |= SC401AI_TEST_PATTERN_BIT_MASK;
785 else
786 val &= ~SC401AI_TEST_PATTERN_BIT_MASK;
787 ret |= sc401ai_write_reg(sc401ai->client, SC401AI_REG_TEST_PATTERN,
788 SC401AI_REG_VALUE_08BIT, val);
789 return ret;
790 }
791
sc401ai_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)792 static int sc401ai_g_frame_interval(struct v4l2_subdev *sd,
793 struct v4l2_subdev_frame_interval *fi)
794 {
795 struct sc401ai *sc401ai = to_sc401ai(sd);
796 const struct sc401ai_mode *mode = sc401ai->cur_mode;
797
798 if (sc401ai->streaming)
799 fi->interval = sc401ai->cur_fps;
800 else
801 fi->interval = mode->max_fps;
802
803 return 0;
804 }
805
sc401ai_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)806 static int sc401ai_g_mbus_config(struct v4l2_subdev *sd,
807 unsigned int pad_id,
808 struct v4l2_mbus_config *config)
809 {
810 struct sc401ai *sc401ai = to_sc401ai(sd);
811 const struct sc401ai_mode *mode = sc401ai->cur_mode;
812 u32 val = 0;
813
814 val = 1 << (sc401ai->lane_num - 1) |
815 V4L2_MBUS_CSI2_CHANNEL_0 |
816 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
817
818 if (mode->hdr_mode != NO_HDR)
819 val |= V4L2_MBUS_CSI2_CHANNEL_1;
820 if (mode->hdr_mode == HDR_X3)
821 val |= V4L2_MBUS_CSI2_CHANNEL_2;
822
823 config->type = V4L2_MBUS_CSI2_DPHY;
824 config->flags = val;
825
826 return 0;
827 }
828
sc401ai_get_module_inf(struct sc401ai * sc401ai,struct rkmodule_inf * inf)829 static void sc401ai_get_module_inf(struct sc401ai *sc401ai,
830 struct rkmodule_inf *inf)
831 {
832 memset(inf, 0, sizeof(*inf));
833 strscpy(inf->base.sensor, SC401AI_NAME, sizeof(inf->base.sensor));
834 strscpy(inf->base.module, sc401ai->module_name,
835 sizeof(inf->base.module));
836 strscpy(inf->base.lens, sc401ai->len_name, sizeof(inf->base.lens));
837 }
838
sc401ai_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)839 static long sc401ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
840 {
841 struct sc401ai *sc401ai = to_sc401ai(sd);
842 struct rkmodule_hdr_cfg *hdr;
843 long ret = 0;
844 u32 stream = 0;
845
846 switch (cmd) {
847 case RKMODULE_GET_MODULE_INFO:
848 sc401ai_get_module_inf(sc401ai, (struct rkmodule_inf *)arg);
849 break;
850 case RKMODULE_GET_HDR_CFG:
851 hdr = (struct rkmodule_hdr_cfg *)arg;
852 hdr->esp.mode = HDR_NORMAL_VC;
853 hdr->hdr_mode = sc401ai->cur_mode->hdr_mode;
854 break;
855 case RKMODULE_SET_HDR_CFG:
856 hdr = (struct rkmodule_hdr_cfg *)arg;
857 if (hdr->hdr_mode != 0)
858 ret = -1;
859 break;
860 case PREISP_CMD_SET_HDRAE_EXP:
861 break;
862 case RKMODULE_SET_QUICK_STREAM:
863
864 stream = *((u32 *)arg);
865
866 if (stream)
867 ret = sc401ai_write_reg(sc401ai->client,
868 SC401AI_REG_CTRL_MODE,
869 SC401AI_REG_VALUE_08BIT,
870 SC401AI_MODE_STREAMING);
871 else
872 ret = sc401ai_write_reg(sc401ai->client,
873 SC401AI_REG_CTRL_MODE,
874 SC401AI_REG_VALUE_08BIT,
875 SC401AI_MODE_SW_STANDBY);
876 break;
877 default:
878 ret = -ENOIOCTLCMD;
879 break;
880 }
881
882 return ret;
883 }
884
885 #ifdef CONFIG_COMPAT
sc401ai_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)886 static long sc401ai_compat_ioctl32(struct v4l2_subdev *sd,
887 unsigned int cmd, unsigned long arg)
888 {
889 void __user *up = compat_ptr(arg);
890 struct rkmodule_inf *inf;
891 struct rkmodule_awb_cfg *cfg;
892 struct rkmodule_hdr_cfg *hdr;
893 struct preisp_hdrae_exp_s *hdrae;
894 long ret = 0;
895 u32 stream = 0;
896
897 switch (cmd) {
898 case RKMODULE_GET_MODULE_INFO:
899 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
900 if (!inf) {
901 ret = -ENOMEM;
902 return ret;
903 }
904
905 ret = sc401ai_ioctl(sd, cmd, inf);
906 if (!ret) {
907 ret = copy_to_user(up, inf, sizeof(*inf));
908 if (ret)
909 ret = -EFAULT;
910 }
911 kfree(inf);
912 break;
913 case RKMODULE_AWB_CFG:
914 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
915 if (!cfg) {
916 ret = -ENOMEM;
917 return ret;
918 }
919
920 if (copy_from_user(cfg, up, sizeof(*cfg))) {
921 kfree(cfg);
922 return -EFAULT;
923 }
924
925 sc401ai_ioctl(sd, cmd, cfg);
926 kfree(cfg);
927 break;
928 case RKMODULE_GET_HDR_CFG:
929 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
930 if (!hdr) {
931 ret = -ENOMEM;
932 return ret;
933 }
934
935 ret = sc401ai_ioctl(sd, cmd, hdr);
936 if (!ret) {
937 ret = copy_to_user(up, hdr, sizeof(*hdr));
938 if (ret)
939 ret = -EFAULT;
940 }
941 kfree(hdr);
942 break;
943 case RKMODULE_SET_HDR_CFG:
944 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
945 if (!hdr) {
946 ret = -ENOMEM;
947 return ret;
948 }
949
950 if (copy_from_user(hdr, up, sizeof(*hdr))) {
951 kfree(hdr);
952 return -EFAULT;
953 }
954
955 sc401ai_ioctl(sd, cmd, hdr);
956 kfree(hdr);
957 break;
958 case PREISP_CMD_SET_HDRAE_EXP:
959 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
960 if (!hdrae) {
961 ret = -ENOMEM;
962 return ret;
963 }
964
965 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
966 kfree(hdrae);
967 return -EFAULT;
968 }
969
970 sc401ai_ioctl(sd, cmd, hdrae);
971 kfree(hdrae);
972 break;
973 case RKMODULE_SET_QUICK_STREAM:
974 if (copy_from_user(&stream, up, sizeof(u32)))
975 return -EFAULT;
976
977 sc401ai_ioctl(sd, cmd, &stream);
978 break;
979 default:
980 ret = -ENOIOCTLCMD;
981 break;
982 }
983
984 return ret;
985 }
986 #endif
987
__sc401ai_start_stream(struct sc401ai * sc401ai)988 static int __sc401ai_start_stream(struct sc401ai *sc401ai)
989 {
990 int ret;
991
992 ret = sc401ai_write_array(sc401ai->client, sc401ai->cur_mode->reg_list);
993 if (ret)
994 return ret;
995
996 /* In case these controls are set before streaming */
997 ret = __v4l2_ctrl_handler_setup(&sc401ai->ctrl_handler);
998 if (ret)
999 return ret;
1000
1001 return sc401ai_write_reg(sc401ai->client,
1002 SC401AI_REG_CTRL_MODE,
1003 SC401AI_REG_VALUE_08BIT,
1004 SC401AI_MODE_STREAMING);
1005 }
1006
__sc401ai_stop_stream(struct sc401ai * sc401ai)1007 static int __sc401ai_stop_stream(struct sc401ai *sc401ai)
1008 {
1009 return sc401ai_write_reg(sc401ai->client,
1010 SC401AI_REG_CTRL_MODE,
1011 SC401AI_REG_VALUE_08BIT,
1012 SC401AI_MODE_SW_STANDBY);
1013 }
1014
sc401ai_s_stream(struct v4l2_subdev * sd,int on)1015 static int sc401ai_s_stream(struct v4l2_subdev *sd, int on)
1016 {
1017 struct sc401ai *sc401ai = to_sc401ai(sd);
1018 struct i2c_client *client = sc401ai->client;
1019 int ret = 0;
1020
1021 mutex_lock(&sc401ai->mutex);
1022 on = !!on;
1023 if (on == sc401ai->streaming)
1024 goto unlock_and_return;
1025
1026 if (on) {
1027 ret = pm_runtime_get_sync(&client->dev);
1028 if (ret < 0) {
1029 pm_runtime_put_noidle(&client->dev);
1030 goto unlock_and_return;
1031 }
1032
1033 ret = __sc401ai_start_stream(sc401ai);
1034 if (ret) {
1035 v4l2_err(sd, "start stream failed while write regs\n");
1036 pm_runtime_put(&client->dev);
1037 goto unlock_and_return;
1038 }
1039 } else {
1040 __sc401ai_stop_stream(sc401ai);
1041 pm_runtime_put(&client->dev);
1042 }
1043
1044 sc401ai->streaming = on;
1045
1046 unlock_and_return:
1047 mutex_unlock(&sc401ai->mutex);
1048
1049 return ret;
1050 }
1051
sc401ai_s_power(struct v4l2_subdev * sd,int on)1052 static int sc401ai_s_power(struct v4l2_subdev *sd, int on)
1053 {
1054 struct sc401ai *sc401ai = to_sc401ai(sd);
1055 struct i2c_client *client = sc401ai->client;
1056 int ret = 0;
1057
1058 mutex_lock(&sc401ai->mutex);
1059
1060 /* If the power state is not modified - no work to do. */
1061 if (sc401ai->power_on == !!on)
1062 goto unlock_and_return;
1063
1064 if (on) {
1065 ret = pm_runtime_get_sync(&client->dev);
1066 if (ret < 0) {
1067 pm_runtime_put_noidle(&client->dev);
1068 goto unlock_and_return;
1069 }
1070
1071 ret = sc401ai_write_array(sc401ai->client, sc401ai_global_regs);
1072 if (ret) {
1073 v4l2_err(sd, "could not set init registers\n");
1074 pm_runtime_put_noidle(&client->dev);
1075 goto unlock_and_return;
1076 }
1077
1078 sc401ai->power_on = true;
1079 } else {
1080 pm_runtime_put(&client->dev);
1081 sc401ai->power_on = false;
1082 }
1083
1084 unlock_and_return:
1085 mutex_unlock(&sc401ai->mutex);
1086
1087 return ret;
1088 }
1089
1090 /* Calculate the delay in us by clock rate and clock cycles */
sc401ai_cal_delay(u32 cycles)1091 static inline u32 sc401ai_cal_delay(u32 cycles)
1092 {
1093 return DIV_ROUND_UP(cycles, SC401AI_XVCLK_FREQ / 1000 / 1000);
1094 }
1095
__sc401ai_power_on(struct sc401ai * sc401ai)1096 static int __sc401ai_power_on(struct sc401ai *sc401ai)
1097 {
1098 int ret;
1099 u32 delay_us;
1100 struct device *dev = &sc401ai->client->dev;
1101
1102 if (!IS_ERR_OR_NULL(sc401ai->pins_default)) {
1103 ret = pinctrl_select_state(sc401ai->pinctrl,
1104 sc401ai->pins_default);
1105 if (ret < 0)
1106 dev_err(dev, "could not set pins\n");
1107 }
1108 ret = clk_set_rate(sc401ai->xvclk, SC401AI_XVCLK_FREQ);
1109 if (ret < 0)
1110 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1111 if (clk_get_rate(sc401ai->xvclk) != SC401AI_XVCLK_FREQ)
1112 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1113 ret = clk_prepare_enable(sc401ai->xvclk);
1114 if (ret < 0) {
1115 dev_err(dev, "Failed to enable xvclk\n");
1116 return ret;
1117 }
1118 if (!IS_ERR(sc401ai->reset_gpio))
1119 gpiod_set_value_cansleep(sc401ai->reset_gpio, 0);
1120
1121 ret = regulator_bulk_enable(SC401AI_NUM_SUPPLIES, sc401ai->supplies);
1122 if (ret < 0) {
1123 dev_err(dev, "Failed to enable regulators\n");
1124 goto disable_clk;
1125 }
1126
1127 if (!IS_ERR(sc401ai->reset_gpio))
1128 gpiod_set_value_cansleep(sc401ai->reset_gpio, 1);
1129
1130 usleep_range(500, 1000);
1131 if (!IS_ERR(sc401ai->pwdn_gpio))
1132 gpiod_set_value_cansleep(sc401ai->pwdn_gpio, 1);
1133
1134 if (!IS_ERR(sc401ai->reset_gpio))
1135 usleep_range(6000, 8000);
1136 else
1137 usleep_range(12000, 16000);
1138
1139 /* 8192 cycles prior to first SCCB transaction */
1140 delay_us = sc401ai_cal_delay(8192);
1141 usleep_range(delay_us, delay_us * 2);
1142
1143 return 0;
1144
1145 disable_clk:
1146 clk_disable_unprepare(sc401ai->xvclk);
1147
1148 return ret;
1149 }
1150
__sc401ai_power_off(struct sc401ai * sc401ai)1151 static void __sc401ai_power_off(struct sc401ai *sc401ai)
1152 {
1153 int ret;
1154 struct device *dev = &sc401ai->client->dev;
1155
1156 if (!IS_ERR(sc401ai->pwdn_gpio))
1157 gpiod_set_value_cansleep(sc401ai->pwdn_gpio, 0);
1158 clk_disable_unprepare(sc401ai->xvclk);
1159 if (!IS_ERR(sc401ai->reset_gpio))
1160 gpiod_set_value_cansleep(sc401ai->reset_gpio, 0);
1161 if (!IS_ERR_OR_NULL(sc401ai->pins_sleep)) {
1162 ret = pinctrl_select_state(sc401ai->pinctrl,
1163 sc401ai->pins_sleep);
1164 if (ret < 0)
1165 dev_dbg(dev, "could not set pins\n");
1166 }
1167 regulator_bulk_disable(SC401AI_NUM_SUPPLIES, sc401ai->supplies);
1168 }
1169
sc401ai_runtime_resume(struct device * dev)1170 static int sc401ai_runtime_resume(struct device *dev)
1171 {
1172 struct i2c_client *client = to_i2c_client(dev);
1173 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1174 struct sc401ai *sc401ai = to_sc401ai(sd);
1175
1176 return __sc401ai_power_on(sc401ai);
1177 }
1178
sc401ai_runtime_suspend(struct device * dev)1179 static int sc401ai_runtime_suspend(struct device *dev)
1180 {
1181 struct i2c_client *client = to_i2c_client(dev);
1182 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1183 struct sc401ai *sc401ai = to_sc401ai(sd);
1184
1185 __sc401ai_power_off(sc401ai);
1186
1187 return 0;
1188 }
1189
1190 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc401ai_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1191 static int sc401ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1192 {
1193 struct sc401ai *sc401ai = to_sc401ai(sd);
1194 struct v4l2_mbus_framefmt *try_fmt =
1195 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1196 const struct sc401ai_mode *def_mode = &supported_modes[0];
1197
1198 mutex_lock(&sc401ai->mutex);
1199 /* Initialize try_fmt */
1200 try_fmt->width = def_mode->width;
1201 try_fmt->height = def_mode->height;
1202 try_fmt->code = def_mode->bus_fmt;
1203 try_fmt->field = V4L2_FIELD_NONE;
1204
1205 mutex_unlock(&sc401ai->mutex);
1206 /* No crop or compose */
1207
1208 return 0;
1209 }
1210 #endif
1211
sc401ai_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1212 static int sc401ai_enum_frame_interval(struct v4l2_subdev *sd,
1213 struct v4l2_subdev_pad_config *cfg,
1214 struct v4l2_subdev_frame_interval_enum *fie)
1215 {
1216 if (fie->index >= ARRAY_SIZE(supported_modes))
1217 return -EINVAL;
1218
1219 fie->code = supported_modes[fie->index].bus_fmt;
1220 fie->width = supported_modes[fie->index].width;
1221 fie->height = supported_modes[fie->index].height;
1222 fie->interval = supported_modes[fie->index].max_fps;
1223 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1224 return 0;
1225 }
1226
1227 static const struct dev_pm_ops sc401ai_pm_ops = {
1228 SET_RUNTIME_PM_OPS(sc401ai_runtime_suspend,
1229 sc401ai_runtime_resume, NULL)
1230 };
1231
1232 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1233 static const struct v4l2_subdev_internal_ops sc401ai_internal_ops = {
1234 .open = sc401ai_open,
1235 };
1236 #endif
1237
1238 static const struct v4l2_subdev_core_ops sc401ai_core_ops = {
1239 .s_power = sc401ai_s_power,
1240 .ioctl = sc401ai_ioctl,
1241 #ifdef CONFIG_COMPAT
1242 .compat_ioctl32 = sc401ai_compat_ioctl32,
1243 #endif
1244 };
1245
1246 static const struct v4l2_subdev_video_ops sc401ai_video_ops = {
1247 .s_stream = sc401ai_s_stream,
1248 .g_frame_interval = sc401ai_g_frame_interval,
1249 };
1250
1251 static const struct v4l2_subdev_pad_ops sc401ai_pad_ops = {
1252 .enum_mbus_code = sc401ai_enum_mbus_code,
1253 .enum_frame_size = sc401ai_enum_frame_sizes,
1254 .enum_frame_interval = sc401ai_enum_frame_interval,
1255 .get_fmt = sc401ai_get_fmt,
1256 .set_fmt = sc401ai_set_fmt,
1257 .get_mbus_config = sc401ai_g_mbus_config,
1258 };
1259
1260 static const struct v4l2_subdev_ops sc401ai_subdev_ops = {
1261 .core = &sc401ai_core_ops,
1262 .video = &sc401ai_video_ops,
1263 .pad = &sc401ai_pad_ops,
1264 };
1265
sc401ai_modify_fps_info(struct sc401ai * sc401ai)1266 static void sc401ai_modify_fps_info(struct sc401ai *sc401ai)
1267 {
1268 const struct sc401ai_mode *mode = sc401ai->cur_mode;
1269
1270 sc401ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1271 sc401ai->cur_vts;
1272 }
1273
sc401ai_set_ctrl(struct v4l2_ctrl * ctrl)1274 static int sc401ai_set_ctrl(struct v4l2_ctrl *ctrl)
1275 {
1276 struct sc401ai *sc401ai = container_of(ctrl->handler,
1277 struct sc401ai, ctrl_handler);
1278 struct i2c_client *client = sc401ai->client;
1279 s64 max;
1280 int ret = 0;
1281 u32 val = 0;
1282
1283 /* Propagate change of current control to all related controls */
1284 switch (ctrl->id) {
1285 case V4L2_CID_VBLANK:
1286 /* Update max exposure while meeting expected vblanking */
1287 max = sc401ai->cur_mode->height + ctrl->val - 4;
1288 __v4l2_ctrl_modify_range(sc401ai->exposure,
1289 sc401ai->exposure->minimum, max,
1290 sc401ai->exposure->step,
1291 sc401ai->exposure->default_value);
1292 break;
1293 }
1294
1295 if (!pm_runtime_get_if_in_use(&client->dev))
1296 return 0;
1297
1298 switch (ctrl->id) {
1299 case V4L2_CID_EXPOSURE:
1300 if (sc401ai->cur_mode->hdr_mode == NO_HDR) {
1301 val = ctrl->val << 1;
1302 /* 4 least significant bits of expsoure are fractional part */
1303 ret = sc401ai_write_reg(sc401ai->client,
1304 SC401AI_REG_EXPOSURE_H,
1305 SC401AI_REG_VALUE_08BIT,
1306 SC401AI_FETCH_EXP_H(val));
1307 ret |= sc401ai_write_reg(sc401ai->client,
1308 SC401AI_REG_EXPOSURE_M,
1309 SC401AI_REG_VALUE_08BIT,
1310 SC401AI_FETCH_EXP_M(val));
1311 ret |= sc401ai_write_reg(sc401ai->client,
1312 SC401AI_REG_EXPOSURE_L,
1313 SC401AI_REG_VALUE_08BIT,
1314 SC401AI_FETCH_EXP_L(val));
1315 }
1316 break;
1317 case V4L2_CID_ANALOGUE_GAIN:
1318 if (sc401ai->cur_mode->hdr_mode == NO_HDR)
1319 ret = sc401ai_set_gain_reg(sc401ai, ctrl->val);
1320 break;
1321 case V4L2_CID_VBLANK:
1322 ret = sc401ai_write_reg(sc401ai->client,
1323 SC401AI_REG_VTS_H,
1324 SC401AI_REG_VALUE_08BIT,
1325 (ctrl->val + sc401ai->cur_mode->height)
1326 >> 8);
1327 ret |= sc401ai_write_reg(sc401ai->client,
1328 SC401AI_REG_VTS_L,
1329 SC401AI_REG_VALUE_08BIT,
1330 (ctrl->val + sc401ai->cur_mode->height)
1331 & 0xff);
1332 if (!ret)
1333 sc401ai->cur_vts = ctrl->val + sc401ai->cur_mode->height;
1334 sc401ai_modify_fps_info(sc401ai);
1335 break;
1336 case V4L2_CID_TEST_PATTERN:
1337 ret = sc401ai_enable_test_pattern(sc401ai, ctrl->val);
1338 break;
1339 case V4L2_CID_HFLIP:
1340 ret = sc401ai_read_reg(sc401ai->client, SC401AI_FLIP_MIRROR_REG,
1341 SC401AI_REG_VALUE_08BIT, &val);
1342 ret |= sc401ai_write_reg(sc401ai->client,
1343 SC401AI_FLIP_MIRROR_REG,
1344 SC401AI_REG_VALUE_08BIT,
1345 SC401AI_FETCH_MIRROR(val, ctrl->val));
1346 break;
1347 case V4L2_CID_VFLIP:
1348 ret = sc401ai_read_reg(sc401ai->client, SC401AI_FLIP_MIRROR_REG,
1349 SC401AI_REG_VALUE_08BIT, &val);
1350 ret |= sc401ai_write_reg(sc401ai->client,
1351 SC401AI_FLIP_MIRROR_REG,
1352 SC401AI_REG_VALUE_08BIT,
1353 SC401AI_FETCH_FLIP(val, ctrl->val));
1354 break;
1355 default:
1356 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1357 __func__, ctrl->id, ctrl->val);
1358 break;
1359 }
1360
1361 pm_runtime_put(&client->dev);
1362
1363 return ret;
1364 }
1365
1366 static const struct v4l2_ctrl_ops sc401ai_ctrl_ops = {
1367 .s_ctrl = sc401ai_set_ctrl,
1368 };
1369
sc401ai_parse_of(struct sc401ai * sc401ai)1370 static int sc401ai_parse_of(struct sc401ai *sc401ai)
1371 {
1372 struct device *dev = &sc401ai->client->dev;
1373 struct device_node *endpoint;
1374 struct fwnode_handle *fwnode;
1375 int rval;
1376
1377 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1378 if (!endpoint) {
1379 dev_err(dev, "Failed to get endpoint\n");
1380 return -EINVAL;
1381 }
1382 fwnode = of_fwnode_handle(endpoint);
1383 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1384 if (rval <= 0) {
1385 dev_warn(dev, " Get mipi lane num failed!\n");
1386 return -1;
1387 }
1388
1389 sc401ai->lane_num = rval;
1390
1391 if (sc401ai->lane_num == 2) {
1392 sc401ai->cur_mode = &supported_modes[1];
1393 dev_info(dev, "lane_num(%d)\n", sc401ai->lane_num);
1394 } else if (sc401ai->lane_num == 4) {
1395 sc401ai->cur_mode = &supported_modes[0];
1396 dev_info(dev, "lane_num(%d)\n", sc401ai->lane_num);
1397 } else {
1398 dev_err(dev, "unsupported lane_num(%d)\n", sc401ai->lane_num);
1399 return -1;
1400 }
1401 return 0;
1402 }
1403
sc401ai_initialize_controls(struct sc401ai * sc401ai)1404 static int sc401ai_initialize_controls(struct sc401ai *sc401ai)
1405 {
1406 const struct sc401ai_mode *mode;
1407 struct v4l2_ctrl_handler *handler;
1408 struct device *dev = &sc401ai->client->dev;
1409
1410 s64 exposure_max, vblank_def;
1411 u32 h_blank;
1412 int ret;
1413 int dst_pixel_rate = 0;
1414
1415 handler = &sc401ai->ctrl_handler;
1416 mode = sc401ai->cur_mode;
1417 ret = v4l2_ctrl_handler_init(handler, 9);
1418 if (ret)
1419 return ret;
1420 handler->lock = &sc401ai->mutex;
1421
1422 sc401ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1423 V4L2_CID_LINK_FREQ,
1424 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1425 link_freq_menu_items);
1426 __v4l2_ctrl_s_ctrl(sc401ai->link_freq, mode->mipi_freq_idx);
1427
1428 if (ret < 0)
1429 dev_err(dev, "get data num failed");
1430
1431 if (mode->mipi_freq_idx == 0)
1432 dst_pixel_rate = PIXEL_RATE_WITH_315M_10BIT;
1433 else if (mode->mipi_freq_idx == 1)
1434 dst_pixel_rate = PIXEL_RATE_WITH_630M_10BIT;
1435
1436 sc401ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1437 V4L2_CID_PIXEL_RATE, 0,
1438 PIXEL_RATE_WITH_MAX,
1439 1, dst_pixel_rate);
1440
1441 h_blank = mode->hts_def - mode->width;
1442 sc401ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1443 h_blank, h_blank, 1, h_blank);
1444 if (sc401ai->hblank)
1445 sc401ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1446 vblank_def = mode->vts_def - mode->height;
1447 sc401ai->vblank = v4l2_ctrl_new_std(handler, &sc401ai_ctrl_ops,
1448 V4L2_CID_VBLANK, vblank_def,
1449 SC401AI_VTS_MAX - mode->height,
1450 1, vblank_def);
1451 exposure_max = mode->vts_def - 4;
1452 sc401ai->exposure = v4l2_ctrl_new_std(handler, &sc401ai_ctrl_ops,
1453 V4L2_CID_EXPOSURE,
1454 SC401AI_EXPOSURE_MIN,
1455 exposure_max,
1456 SC401AI_EXPOSURE_STEP,
1457 mode->exp_def);
1458 sc401ai->anal_gain = v4l2_ctrl_new_std(handler, &sc401ai_ctrl_ops,
1459 V4L2_CID_ANALOGUE_GAIN,
1460 SC401AI_GAIN_MIN,
1461 SC401AI_GAIN_MAX,
1462 SC401AI_GAIN_STEP,
1463 SC401AI_GAIN_DEFAULT);
1464 v4l2_ctrl_new_std(handler, &sc401ai_ctrl_ops,
1465 V4L2_CID_HFLIP, 0, 1, 1, 0);
1466 v4l2_ctrl_new_std(handler, &sc401ai_ctrl_ops,
1467 V4L2_CID_VFLIP, 0, 1, 1, 0);
1468 if (handler->error) {
1469 ret = handler->error;
1470 dev_err(&sc401ai->client->dev,
1471 "Failed to init controls(%d)\n", ret);
1472 goto err_free_handler;
1473 }
1474
1475 sc401ai->subdev.ctrl_handler = handler;
1476 sc401ai->cur_fps = mode->max_fps;
1477 sc401ai->cur_vts = mode->vts_def;
1478
1479 return 0;
1480
1481 err_free_handler:
1482 v4l2_ctrl_handler_free(handler);
1483
1484 return ret;
1485 }
1486
sc401ai_check_sensor_id(struct sc401ai * sc401ai,struct i2c_client * client)1487 static int sc401ai_check_sensor_id(struct sc401ai *sc401ai,
1488 struct i2c_client *client)
1489 {
1490 struct device *dev = &sc401ai->client->dev;
1491 u32 id = 0;
1492 int ret;
1493
1494 ret = sc401ai_read_reg(client, SC401AI_REG_CHIP_ID,
1495 SC401AI_REG_VALUE_16BIT, &id);
1496 if (id != CHIP_ID) {
1497 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1498 return -ENODEV;
1499 }
1500
1501 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1502
1503 return 0;
1504 }
1505
sc401ai_configure_regulators(struct sc401ai * sc401ai)1506 static int sc401ai_configure_regulators(struct sc401ai *sc401ai)
1507 {
1508 unsigned int i;
1509
1510 for (i = 0; i < SC401AI_NUM_SUPPLIES; i++)
1511 sc401ai->supplies[i].supply = sc401ai_supply_names[i];
1512
1513 return devm_regulator_bulk_get(&sc401ai->client->dev,
1514 SC401AI_NUM_SUPPLIES,
1515 sc401ai->supplies);
1516 }
1517
sc401ai_probe(struct i2c_client * client,const struct i2c_device_id * id)1518 static int sc401ai_probe(struct i2c_client *client,
1519 const struct i2c_device_id *id)
1520 {
1521 struct device *dev = &client->dev;
1522 struct device_node *node = dev->of_node;
1523 struct sc401ai *sc401ai;
1524 struct v4l2_subdev *sd;
1525 char facing[2];
1526 int ret;
1527 u32 i, hdr_mode = 0;
1528
1529 dev_info(dev, "driver version: %02x.%02x.%02x",
1530 DRIVER_VERSION >> 16,
1531 (DRIVER_VERSION & 0xff00) >> 8,
1532 DRIVER_VERSION & 0x00ff);
1533
1534 sc401ai = devm_kzalloc(dev, sizeof(*sc401ai), GFP_KERNEL);
1535 if (!sc401ai)
1536 return -ENOMEM;
1537
1538 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1539 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1540 &sc401ai->module_index);
1541 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1542 &sc401ai->module_facing);
1543 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1544 &sc401ai->module_name);
1545 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1546 &sc401ai->len_name);
1547 if (ret) {
1548 dev_err(dev, "could not get module information!\n");
1549 return -EINVAL;
1550 }
1551
1552 sc401ai->client = client;
1553 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1554 if (hdr_mode == supported_modes[i].hdr_mode) {
1555 sc401ai->cur_mode = &supported_modes[i];
1556 break;
1557 }
1558 }
1559 if (i == ARRAY_SIZE(supported_modes))
1560 sc401ai->cur_mode = &supported_modes[0];
1561
1562 sc401ai->xvclk = devm_clk_get(dev, "xvclk");
1563 if (IS_ERR(sc401ai->xvclk)) {
1564 dev_err(dev, "Failed to get xvclk\n");
1565 return -EINVAL;
1566 }
1567
1568 sc401ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1569 if (IS_ERR(sc401ai->reset_gpio))
1570 dev_warn(dev, "Failed to get reset-gpios\n");
1571
1572 sc401ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1573 if (IS_ERR(sc401ai->pwdn_gpio))
1574 dev_warn(dev, "Failed to get pwdn-gpios\n");
1575
1576 sc401ai->pinctrl = devm_pinctrl_get(dev);
1577 if (!IS_ERR(sc401ai->pinctrl)) {
1578 sc401ai->pins_default =
1579 pinctrl_lookup_state(sc401ai->pinctrl,
1580 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1581 if (IS_ERR(sc401ai->pins_default))
1582 dev_err(dev, "could not get default pinstate\n");
1583
1584 sc401ai->pins_sleep =
1585 pinctrl_lookup_state(sc401ai->pinctrl,
1586 OF_CAMERA_PINCTRL_STATE_SLEEP);
1587 if (IS_ERR(sc401ai->pins_sleep))
1588 dev_err(dev, "could not get sleep pinstate\n");
1589 } else {
1590 dev_err(dev, "no pinctrl\n");
1591 }
1592
1593 ret = sc401ai_configure_regulators(sc401ai);
1594 if (ret) {
1595 dev_err(dev, "Failed to get power regulators\n");
1596 return ret;
1597 }
1598
1599 ret = sc401ai_parse_of(sc401ai);
1600 if (ret != 0)
1601 return -EINVAL;
1602
1603 mutex_init(&sc401ai->mutex);
1604
1605 sd = &sc401ai->subdev;
1606 v4l2_i2c_subdev_init(sd, client, &sc401ai_subdev_ops);
1607 ret = sc401ai_initialize_controls(sc401ai);
1608 if (ret)
1609 goto err_destroy_mutex;
1610
1611 ret = __sc401ai_power_on(sc401ai);
1612 if (ret)
1613 goto err_free_handler;
1614
1615 ret = sc401ai_check_sensor_id(sc401ai, client);
1616 if (ret)
1617 goto err_power_off;
1618
1619 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1620 sd->internal_ops = &sc401ai_internal_ops;
1621 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1622 V4L2_SUBDEV_FL_HAS_EVENTS;
1623 #endif
1624 #if defined(CONFIG_MEDIA_CONTROLLER)
1625 sc401ai->pad.flags = MEDIA_PAD_FL_SOURCE;
1626 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1627 ret = media_entity_pads_init(&sd->entity, 1, &sc401ai->pad);
1628 if (ret < 0)
1629 goto err_power_off;
1630 #endif
1631
1632 memset(facing, 0, sizeof(facing));
1633 if (strcmp(sc401ai->module_facing, "back") == 0)
1634 facing[0] = 'b';
1635 else
1636 facing[0] = 'f';
1637
1638 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1639 sc401ai->module_index, facing,
1640 SC401AI_NAME, dev_name(sd->dev));
1641 ret = v4l2_async_register_subdev_sensor_common(sd);
1642 if (ret) {
1643 dev_err(dev, "v4l2 async register subdev failed\n");
1644 goto err_clean_entity;
1645 }
1646
1647 pm_runtime_set_active(dev);
1648 pm_runtime_enable(dev);
1649 pm_runtime_idle(dev);
1650
1651 return 0;
1652
1653 err_clean_entity:
1654 #if defined(CONFIG_MEDIA_CONTROLLER)
1655 media_entity_cleanup(&sd->entity);
1656 #endif
1657 err_power_off:
1658 __sc401ai_power_off(sc401ai);
1659 err_free_handler:
1660 v4l2_ctrl_handler_free(&sc401ai->ctrl_handler);
1661 err_destroy_mutex:
1662 mutex_destroy(&sc401ai->mutex);
1663
1664 return ret;
1665 }
1666
sc401ai_remove(struct i2c_client * client)1667 static int sc401ai_remove(struct i2c_client *client)
1668 {
1669 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1670 struct sc401ai *sc401ai = to_sc401ai(sd);
1671
1672 v4l2_async_unregister_subdev(sd);
1673 #if defined(CONFIG_MEDIA_CONTROLLER)
1674 media_entity_cleanup(&sd->entity);
1675 #endif
1676 v4l2_ctrl_handler_free(&sc401ai->ctrl_handler);
1677 mutex_destroy(&sc401ai->mutex);
1678
1679 pm_runtime_disable(&client->dev);
1680 if (!pm_runtime_status_suspended(&client->dev))
1681 __sc401ai_power_off(sc401ai);
1682 pm_runtime_set_suspended(&client->dev);
1683
1684 return 0;
1685 }
1686
1687 #if IS_ENABLED(CONFIG_OF)
1688 static const struct of_device_id sc401ai_of_match[] = {
1689 { .compatible = "smartsens,sc401ai" },
1690 {},
1691 };
1692 MODULE_DEVICE_TABLE(of, sc401ai_of_match);
1693 #endif
1694
1695 static const struct i2c_device_id sc401ai_match_id[] = {
1696 { "smartsens,sc401ai", 0 },
1697 { },
1698 };
1699
1700 static struct i2c_driver sc401ai_i2c_driver = {
1701 .driver = {
1702 .name = SC401AI_NAME,
1703 .pm = &sc401ai_pm_ops,
1704 .of_match_table = of_match_ptr(sc401ai_of_match),
1705 },
1706 .probe = &sc401ai_probe,
1707 .remove = &sc401ai_remove,
1708 .id_table = sc401ai_match_id,
1709 };
1710
sensor_mod_init(void)1711 static int __init sensor_mod_init(void)
1712 {
1713 return i2c_add_driver(&sc401ai_i2c_driver);
1714 }
1715
sensor_mod_exit(void)1716 static void __exit sensor_mod_exit(void)
1717 {
1718 i2c_del_driver(&sc401ai_i2c_driver);
1719 }
1720
1721 device_initcall_sync(sensor_mod_init);
1722 module_exit(sensor_mod_exit);
1723
1724 MODULE_DESCRIPTION("smartsens sc401ai sensor driver");
1725 MODULE_LICENSE("GPL");
1726