1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc3338 driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 */
9
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/rk-preisp.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define SC3338_LANES 2
38 #define SC3338_BITS_PER_SAMPLE 10
39 #define SC3338_LINK_FREQ_253 253125000
40
41 #define PIXEL_RATE_WITH_253M_10BIT (SC3338_LINK_FREQ_253 * 2 * \
42 SC3338_LANES / SC3338_BITS_PER_SAMPLE)
43 #define SC3338_XVCLK_FREQ 27000000
44
45 #define CHIP_ID 0xcc41
46 #define SC3338_REG_CHIP_ID 0x3107
47
48 #define SC3338_REG_CTRL_MODE 0x0100
49 #define SC3338_MODE_SW_STANDBY 0x0
50 #define SC3338_MODE_STREAMING BIT(0)
51
52 #define SC3338_REG_EXPOSURE_H 0x3e00
53 #define SC3338_REG_EXPOSURE_M 0x3e01
54 #define SC3338_REG_EXPOSURE_L 0x3e02
55 #define SC3338_EXPOSURE_MIN 2
56 #define SC3338_EXPOSURE_STEP 1
57 #define SC3338_VTS_MAX 0x7fff
58
59 #define SC3338_REG_DIG_GAIN 0x3e06
60 #define SC3338_REG_DIG_FINE_GAIN 0x3e07
61 #define SC3338_REG_ANA_GAIN 0x3e09
62 #define SC3338_GAIN_MIN 0x0080
63 #define SC3338_GAIN_MAX (99614) //48.64*16*128
64 #define SC3338_GAIN_STEP 1
65 #define SC3338_GAIN_DEFAULT 0x80
66
67
68 #define SC3338_REG_GROUP_HOLD 0x3812
69 #define SC3338_GROUP_HOLD_START 0x00
70 #define SC3338_GROUP_HOLD_END 0x30
71
72 #define SC3338_REG_TEST_PATTERN 0x4501
73 #define SC3338_TEST_PATTERN_BIT_MASK BIT(3)
74
75 #define SC3338_REG_VTS_H 0x320e
76 #define SC3338_REG_VTS_L 0x320f
77
78 #define SC3338_FLIP_MIRROR_REG 0x3221
79
80 #define SC3338_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
81 #define SC3338_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
82 #define SC3338_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
83
84 #define SC3338_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
85 #define SC3338_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
86
87 #define SC3338_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
88 #define SC3338_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
89
90 #define REG_DELAY 0xFFFE
91 #define REG_NULL 0xFFFF
92
93 #define SC3338_REG_VALUE_08BIT 1
94 #define SC3338_REG_VALUE_16BIT 2
95 #define SC3338_REG_VALUE_24BIT 3
96
97 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
98 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
99 #define SC3338_NAME "sc3338"
100
101 static const char * const sc3338_supply_names[] = {
102 "avdd", /* Analog power */
103 "dovdd", /* Digital I/O power */
104 "dvdd", /* Digital core power */
105 };
106
107 #define SC3338_NUM_SUPPLIES ARRAY_SIZE(sc3338_supply_names)
108
109 struct regval {
110 u16 addr;
111 u8 val;
112 };
113
114 struct sc3338_mode {
115 u32 bus_fmt;
116 u32 width;
117 u32 height;
118 struct v4l2_fract max_fps;
119 u32 hts_def;
120 u32 vts_def;
121 u32 exp_def;
122 const struct regval *reg_list;
123 u32 hdr_mode;
124 u32 vc[PAD_MAX];
125 };
126
127 struct sc3338 {
128 struct i2c_client *client;
129 struct clk *xvclk;
130 struct gpio_desc *reset_gpio;
131 struct gpio_desc *pwdn_gpio;
132 struct regulator_bulk_data supplies[SC3338_NUM_SUPPLIES];
133
134 struct pinctrl *pinctrl;
135 struct pinctrl_state *pins_default;
136 struct pinctrl_state *pins_sleep;
137
138 struct v4l2_subdev subdev;
139 struct media_pad pad;
140 struct v4l2_ctrl_handler ctrl_handler;
141 struct v4l2_ctrl *exposure;
142 struct v4l2_ctrl *anal_gain;
143 struct v4l2_ctrl *digi_gain;
144 struct v4l2_ctrl *hblank;
145 struct v4l2_ctrl *vblank;
146 struct v4l2_ctrl *test_pattern;
147 struct mutex mutex;
148 struct v4l2_fract cur_fps;
149 bool streaming;
150 bool power_on;
151 const struct sc3338_mode *cur_mode;
152 u32 module_index;
153 const char *module_facing;
154 const char *module_name;
155 const char *len_name;
156 u32 cur_vts;
157 bool has_init_exp;
158 bool is_thunderboot;
159 bool is_first_streamoff;
160 struct preisp_hdrae_exp_s init_hdrae_exp;
161 };
162
163 #define to_sc3338(sd) container_of(sd, struct sc3338, subdev)
164
165 /*
166 * Xclk 27Mhz
167 */
168 static const struct regval sc3338_global_regs[] = {
169 {REG_NULL, 0x00},
170 };
171
172 /*
173 * Xclk 27Mhz
174 * max_framerate 25fps
175 * mipi_datarate per lane 506.25Mbps, 2lane
176 */
177 static const struct regval sc3338_linear_10_2304x1296_regs[] = {
178 {0x0103, 0x01},
179 {0x36e9, 0x80},
180 {0x37f9, 0x80},
181 {0x301f, 0x01},
182 {0x30b8, 0x33},
183 {0x320e, 0x06},
184 {0x320f, 0x54},
185 {0x3253, 0x10},
186 {0x325f, 0x20},
187 {0x3301, 0x04},
188 {0x3306, 0x50},
189 {0x3309, 0xa8},
190 {0x330a, 0x00},
191 {0x330b, 0xd8},
192 {0x3314, 0x13},
193 {0x331f, 0x99},
194 {0x3333, 0x10},
195 {0x3334, 0x40},
196 {0x335e, 0x06},
197 {0x335f, 0x0a},
198 {0x3364, 0x5e},
199 {0x337c, 0x02},
200 {0x337d, 0x0e},
201 {0x3390, 0x01},
202 {0x3391, 0x03},
203 {0x3392, 0x07},
204 {0x3393, 0x04},
205 {0x3394, 0x04},
206 {0x3395, 0x04},
207 {0x3396, 0x08},
208 {0x3397, 0x0b},
209 {0x3398, 0x1f},
210 {0x3399, 0x04},
211 {0x339a, 0x0a},
212 {0x339b, 0x3a},
213 {0x339c, 0xb4},
214 {0x33a2, 0x04},
215 {0x33ac, 0x08},
216 {0x33ad, 0x1c},
217 {0x33ae, 0x10},
218 {0x33af, 0x30},
219 {0x33b1, 0x80},
220 {0x33b3, 0x48},
221 {0x33f9, 0x60},
222 {0x33fb, 0x74},
223 {0x33fc, 0x4b},
224 {0x33fd, 0x5f},
225 {0x349f, 0x03},
226 {0x34a6, 0x4b},
227 {0x34a7, 0x5f},
228 {0x34a8, 0x20},
229 {0x34a9, 0x18},
230 {0x34ab, 0xe8},
231 {0x34ac, 0x01},
232 {0x34ad, 0x00},
233 {0x34f8, 0x5f},
234 {0x34f9, 0x18},
235 {0x3630, 0xc0},
236 {0x3631, 0x84},
237 {0x3632, 0x64},
238 {0x3633, 0x32},
239 {0x363b, 0x03},
240 {0x363c, 0x08},
241 {0x3641, 0x38},
242 {0x3670, 0x4e},
243 {0x3674, 0xc0},
244 {0x3675, 0xc0},
245 {0x3676, 0xc0},
246 {0x3677, 0x84},
247 {0x3678, 0x84},
248 {0x3679, 0x84},
249 {0x367c, 0x48},
250 {0x367d, 0x49},
251 {0x367e, 0x4b},
252 {0x367f, 0x5f},
253 {0x3690, 0x32},
254 {0x3691, 0x32},
255 {0x3692, 0x42},
256 {0x369c, 0x4b},
257 {0x369d, 0x5f},
258 {0x36b0, 0x87},
259 {0x36b1, 0x90},
260 {0x36b2, 0xa1},
261 {0x36b3, 0xd8},
262 {0x36b4, 0x49},
263 {0x36b5, 0x4b},
264 {0x36b6, 0x4f},
265 {0x370f, 0x01},
266 {0x3722, 0x09},
267 {0x3724, 0x41},
268 {0x3725, 0xc1},
269 {0x3771, 0x09},
270 {0x3772, 0x09},
271 {0x3773, 0x05},
272 {0x377a, 0x48},
273 {0x377b, 0x5f},
274 {0x3904, 0x04},
275 {0x3905, 0x8c},
276 {0x391d, 0x04},
277 {0x3921, 0x20},
278 {0x3926, 0x21},
279 {0x3933, 0x80},
280 {0x3934, 0x0a},
281 {0x3935, 0x00},
282 {0x3936, 0x2a},
283 {0x3937, 0x6a},
284 {0x3938, 0x6a},
285 {0x39dc, 0x02},
286 {0x3e01, 0x53},
287 {0x3e02, 0xe0},
288 {0x3e09, 0x00},
289 {0x440e, 0x02},
290 {0x4509, 0x20},
291 {0x5ae0, 0xfe},
292 {0x5ae1, 0x40},
293 {0x5ae2, 0x38},
294 {0x5ae3, 0x30},
295 {0x5ae4, 0x28},
296 {0x5ae5, 0x38},
297 {0x5ae6, 0x30},
298 {0x5ae7, 0x28},
299 {0x5ae8, 0x3f},
300 {0x5ae9, 0x34},
301 {0x5aea, 0x2c},
302 {0x5aeb, 0x3f},
303 {0x5aec, 0x34},
304 {0x5aed, 0x2c},
305 {0x36e9, 0x54},
306 {0x37f9, 0x27},
307 {0x3028, 0x05},
308 {REG_NULL, 0x00},
309 };
310
311 static const struct sc3338_mode supported_modes[] = {
312 {
313 .width = 2304,
314 .height = 1296,
315 .max_fps = {
316 .numerator = 10000,
317 .denominator = 250000,
318 },
319 .exp_def = 0x0080,
320 .hts_def = 0x05dc * 2,
321 .vts_def = 0x0654,
322 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
323 .reg_list = sc3338_linear_10_2304x1296_regs,
324 .hdr_mode = NO_HDR,
325 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
326 }
327 };
328
329 static const s64 link_freq_menu_items[] = {
330 SC3338_LINK_FREQ_253
331 };
332
333 static const char * const sc3338_test_pattern_menu[] = {
334 "Disabled",
335 "Vertical Color Bar Type 1",
336 "Vertical Color Bar Type 2",
337 "Vertical Color Bar Type 3",
338 "Vertical Color Bar Type 4"
339 };
340
341 /* Write registers up to 4 at a time */
sc3338_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)342 static int sc3338_write_reg(struct i2c_client *client, u16 reg,
343 u32 len, u32 val)
344 {
345 u32 buf_i, val_i;
346 u8 buf[6];
347 u8 *val_p;
348 __be32 val_be;
349
350 if (len > 4)
351 return -EINVAL;
352
353 buf[0] = reg >> 8;
354 buf[1] = reg & 0xff;
355
356 val_be = cpu_to_be32(val);
357 val_p = (u8 *)&val_be;
358 buf_i = 2;
359 val_i = 4 - len;
360
361 while (val_i < 4)
362 buf[buf_i++] = val_p[val_i++];
363
364 if (i2c_master_send(client, buf, len + 2) != len + 2)
365 return -EIO;
366 return 0;
367 }
368
sc3338_write_array(struct i2c_client * client,const struct regval * regs)369 static int sc3338_write_array(struct i2c_client *client,
370 const struct regval *regs)
371 {
372 u32 i;
373 int ret = 0;
374
375 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
376 ret = sc3338_write_reg(client, regs[i].addr,
377 SC3338_REG_VALUE_08BIT, regs[i].val);
378
379 return ret;
380 }
381
382 /* Read registers up to 4 at a time */
sc3338_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)383 static int sc3338_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
384 u32 *val)
385 {
386 struct i2c_msg msgs[2];
387 u8 *data_be_p;
388 __be32 data_be = 0;
389 __be16 reg_addr_be = cpu_to_be16(reg);
390 int ret;
391
392 if (len > 4 || !len)
393 return -EINVAL;
394
395 data_be_p = (u8 *)&data_be;
396 /* Write register address */
397 msgs[0].addr = client->addr;
398 msgs[0].flags = 0;
399 msgs[0].len = 2;
400 msgs[0].buf = (u8 *)®_addr_be;
401
402 /* Read data from register */
403 msgs[1].addr = client->addr;
404 msgs[1].flags = I2C_M_RD;
405 msgs[1].len = len;
406 msgs[1].buf = &data_be_p[4 - len];
407
408 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
409 if (ret != ARRAY_SIZE(msgs))
410 return -EIO;
411
412 *val = be32_to_cpu(data_be);
413
414 return 0;
415 }
416
sc3338_set_gain_reg(struct sc3338 * sc3338,u32 gain)417 static int sc3338_set_gain_reg(struct sc3338 *sc3338, u32 gain)
418 {
419 struct i2c_client *client = sc3338->client;
420 u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
421 int ret = 0, gain_factor;
422
423 if (gain < 128)
424 gain = 128;
425 else if (gain > SC3338_GAIN_MAX)
426 gain = SC3338_GAIN_MAX;
427
428 gain_factor = gain * 1000 / 128;
429 if (gain_factor < 1520) {
430 coarse_again = 0x00;
431 coarse_dgain = 0x00;
432 fine_dgain = gain_factor * 128 / 1000;
433 } else if (gain_factor < 3040) {
434 coarse_again = 0x40;
435 coarse_dgain = 0x00;
436 fine_dgain = gain_factor * 128 / 1520;
437 } else if (gain_factor < 6080) {
438 coarse_again = 0x48;
439 coarse_dgain = 0x00;
440 fine_dgain = gain_factor * 128 / 3040;
441 } else if (gain_factor < 12160) {
442 coarse_again = 0x49;
443 coarse_dgain = 0x00;
444 fine_dgain = gain_factor * 128 / 6080;
445 } else if (gain_factor < 24320) {
446 coarse_again = 0x4b;
447 coarse_dgain = 0x00;
448 fine_dgain = gain_factor * 128 / 12160;
449 } else if (gain_factor < 48640) {
450 coarse_again = 0x4f;
451 coarse_dgain = 0x00;
452 fine_dgain = gain_factor * 128 / 24320;
453 } else if (gain_factor < 48640 * 2) {
454 //open dgain begin max digital gain 4X
455 coarse_again = 0x5f;
456 coarse_dgain = 0x00;
457 fine_dgain = gain_factor * 128 / 48640;
458 } else if (gain_factor < 48640 * 4) {
459 coarse_again = 0x5f;
460 coarse_dgain = 0x01;
461 fine_dgain = gain_factor * 128 / 48640 / 2;
462 } else if (gain_factor < 48640 * 8) {
463 coarse_again = 0x5f;
464 coarse_dgain = 0x03;
465 fine_dgain = gain_factor * 128 / 48640 / 4;
466 } else if (gain_factor < 48640 * 16) {
467 coarse_again = 0x5f;
468 coarse_dgain = 0x07;
469 fine_dgain = gain_factor * 128 / 48640 / 8;
470 }
471 dev_dbg(&client->dev, "c_again: 0x%x, c_dgain: 0x%x, f_dgain: 0x%0x\n",
472 coarse_again, coarse_dgain, fine_dgain);
473
474 ret = sc3338_write_reg(sc3338->client,
475 SC3338_REG_DIG_GAIN,
476 SC3338_REG_VALUE_08BIT,
477 coarse_dgain);
478 ret |= sc3338_write_reg(sc3338->client,
479 SC3338_REG_DIG_FINE_GAIN,
480 SC3338_REG_VALUE_08BIT,
481 fine_dgain);
482 ret |= sc3338_write_reg(sc3338->client,
483 SC3338_REG_ANA_GAIN,
484 SC3338_REG_VALUE_08BIT,
485 coarse_again);
486
487 return ret;
488 }
489
sc3338_get_reso_dist(const struct sc3338_mode * mode,struct v4l2_mbus_framefmt * framefmt)490 static int sc3338_get_reso_dist(const struct sc3338_mode *mode,
491 struct v4l2_mbus_framefmt *framefmt)
492 {
493 return abs(mode->width - framefmt->width) +
494 abs(mode->height - framefmt->height);
495 }
496
497 static const struct sc3338_mode *
sc3338_find_best_fit(struct v4l2_subdev_format * fmt)498 sc3338_find_best_fit(struct v4l2_subdev_format *fmt)
499 {
500 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
501 int dist;
502 int cur_best_fit = 0;
503 int cur_best_fit_dist = -1;
504 unsigned int i;
505
506 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
507 dist = sc3338_get_reso_dist(&supported_modes[i], framefmt);
508 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
509 cur_best_fit_dist = dist;
510 cur_best_fit = i;
511 }
512 }
513
514 return &supported_modes[cur_best_fit];
515 }
516
sc3338_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)517 static int sc3338_set_fmt(struct v4l2_subdev *sd,
518 struct v4l2_subdev_pad_config *cfg,
519 struct v4l2_subdev_format *fmt)
520 {
521 struct sc3338 *sc3338 = to_sc3338(sd);
522 const struct sc3338_mode *mode;
523 s64 h_blank, vblank_def;
524
525 mutex_lock(&sc3338->mutex);
526
527 mode = sc3338_find_best_fit(fmt);
528 fmt->format.code = mode->bus_fmt;
529 fmt->format.width = mode->width;
530 fmt->format.height = mode->height;
531 fmt->format.field = V4L2_FIELD_NONE;
532 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
533 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
534 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
535 #else
536 mutex_unlock(&sc3338->mutex);
537 return -ENOTTY;
538 #endif
539 } else {
540 sc3338->cur_mode = mode;
541 h_blank = mode->hts_def - mode->width;
542 __v4l2_ctrl_modify_range(sc3338->hblank, h_blank,
543 h_blank, 1, h_blank);
544 vblank_def = mode->vts_def - mode->height;
545 __v4l2_ctrl_modify_range(sc3338->vblank, vblank_def,
546 SC3338_VTS_MAX - mode->height,
547 1, vblank_def);
548 sc3338->cur_fps = mode->max_fps;
549 }
550
551 mutex_unlock(&sc3338->mutex);
552
553 return 0;
554 }
555
sc3338_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)556 static int sc3338_get_fmt(struct v4l2_subdev *sd,
557 struct v4l2_subdev_pad_config *cfg,
558 struct v4l2_subdev_format *fmt)
559 {
560 struct sc3338 *sc3338 = to_sc3338(sd);
561 const struct sc3338_mode *mode = sc3338->cur_mode;
562
563 mutex_lock(&sc3338->mutex);
564 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
565 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
566 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
567 #else
568 mutex_unlock(&sc3338->mutex);
569 return -ENOTTY;
570 #endif
571 } else {
572 fmt->format.width = mode->width;
573 fmt->format.height = mode->height;
574 fmt->format.code = mode->bus_fmt;
575 fmt->format.field = V4L2_FIELD_NONE;
576 /* format info: width/height/data type/virctual channel */
577 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
578 fmt->reserved[0] = mode->vc[fmt->pad];
579 else
580 fmt->reserved[0] = mode->vc[PAD0];
581 }
582 mutex_unlock(&sc3338->mutex);
583
584 return 0;
585 }
586
sc3338_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)587 static int sc3338_enum_mbus_code(struct v4l2_subdev *sd,
588 struct v4l2_subdev_pad_config *cfg,
589 struct v4l2_subdev_mbus_code_enum *code)
590 {
591 struct sc3338 *sc3338 = to_sc3338(sd);
592
593 if (code->index != 0)
594 return -EINVAL;
595 code->code = sc3338->cur_mode->bus_fmt;
596
597 return 0;
598 }
599
sc3338_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)600 static int sc3338_enum_frame_sizes(struct v4l2_subdev *sd,
601 struct v4l2_subdev_pad_config *cfg,
602 struct v4l2_subdev_frame_size_enum *fse)
603 {
604 if (fse->index >= ARRAY_SIZE(supported_modes))
605 return -EINVAL;
606
607 if (fse->code != supported_modes[0].bus_fmt)
608 return -EINVAL;
609
610 fse->min_width = supported_modes[fse->index].width;
611 fse->max_width = supported_modes[fse->index].width;
612 fse->max_height = supported_modes[fse->index].height;
613 fse->min_height = supported_modes[fse->index].height;
614
615 return 0;
616 }
617
sc3338_enable_test_pattern(struct sc3338 * sc3338,u32 pattern)618 static int sc3338_enable_test_pattern(struct sc3338 *sc3338, u32 pattern)
619 {
620 u32 val = 0;
621 int ret = 0;
622
623 ret = sc3338_read_reg(sc3338->client, SC3338_REG_TEST_PATTERN,
624 SC3338_REG_VALUE_08BIT, &val);
625 if (pattern)
626 val |= SC3338_TEST_PATTERN_BIT_MASK;
627 else
628 val &= ~SC3338_TEST_PATTERN_BIT_MASK;
629
630 ret |= sc3338_write_reg(sc3338->client, SC3338_REG_TEST_PATTERN,
631 SC3338_REG_VALUE_08BIT, val);
632 return ret;
633 }
634
sc3338_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)635 static int sc3338_g_frame_interval(struct v4l2_subdev *sd,
636 struct v4l2_subdev_frame_interval *fi)
637 {
638 struct sc3338 *sc3338 = to_sc3338(sd);
639 const struct sc3338_mode *mode = sc3338->cur_mode;
640
641 if (sc3338->streaming)
642 fi->interval = sc3338->cur_fps;
643 else
644 fi->interval = mode->max_fps;
645
646 return 0;
647 }
648
sc3338_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)649 static int sc3338_g_mbus_config(struct v4l2_subdev *sd,
650 unsigned int pad_id,
651 struct v4l2_mbus_config *config)
652 {
653 struct sc3338 *sc3338 = to_sc3338(sd);
654 const struct sc3338_mode *mode = sc3338->cur_mode;
655
656 u32 val = 1 << (SC3338_LANES - 1) |
657 V4L2_MBUS_CSI2_CHANNEL_0 |
658 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
659
660 if (mode->hdr_mode != NO_HDR)
661 val |= V4L2_MBUS_CSI2_CHANNEL_1;
662 if (mode->hdr_mode == HDR_X3)
663 val |= V4L2_MBUS_CSI2_CHANNEL_2;
664
665 config->type = V4L2_MBUS_CSI2_DPHY;
666 config->flags = val;
667
668 return 0;
669 }
670
sc3338_get_module_inf(struct sc3338 * sc3338,struct rkmodule_inf * inf)671 static void sc3338_get_module_inf(struct sc3338 *sc3338,
672 struct rkmodule_inf *inf)
673 {
674 memset(inf, 0, sizeof(*inf));
675 strscpy(inf->base.sensor, SC3338_NAME, sizeof(inf->base.sensor));
676 strscpy(inf->base.module, sc3338->module_name,
677 sizeof(inf->base.module));
678 strscpy(inf->base.lens, sc3338->len_name, sizeof(inf->base.lens));
679 }
680
sc3338_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)681 static long sc3338_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
682 {
683 struct sc3338 *sc3338 = to_sc3338(sd);
684 struct rkmodule_hdr_cfg *hdr;
685 u32 i, h, w;
686 long ret = 0;
687 u32 stream = 0;
688
689 switch (cmd) {
690 case RKMODULE_GET_MODULE_INFO:
691 sc3338_get_module_inf(sc3338, (struct rkmodule_inf *)arg);
692 break;
693 case RKMODULE_GET_HDR_CFG:
694 hdr = (struct rkmodule_hdr_cfg *)arg;
695 hdr->esp.mode = HDR_NORMAL_VC;
696 hdr->hdr_mode = sc3338->cur_mode->hdr_mode;
697 break;
698 case RKMODULE_SET_HDR_CFG:
699 hdr = (struct rkmodule_hdr_cfg *)arg;
700 w = sc3338->cur_mode->width;
701 h = sc3338->cur_mode->height;
702 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
703 if (w == supported_modes[i].width &&
704 h == supported_modes[i].height &&
705 supported_modes[i].hdr_mode == hdr->hdr_mode) {
706 sc3338->cur_mode = &supported_modes[i];
707 break;
708 }
709 }
710 if (i == ARRAY_SIZE(supported_modes)) {
711 dev_err(&sc3338->client->dev,
712 "not find hdr mode:%d %dx%d config\n",
713 hdr->hdr_mode, w, h);
714 ret = -EINVAL;
715 } else {
716 w = sc3338->cur_mode->hts_def - sc3338->cur_mode->width;
717 h = sc3338->cur_mode->vts_def - sc3338->cur_mode->height;
718 __v4l2_ctrl_modify_range(sc3338->hblank, w, w, 1, w);
719 __v4l2_ctrl_modify_range(sc3338->vblank, h,
720 SC3338_VTS_MAX - sc3338->cur_mode->height, 1, h);
721 sc3338->cur_fps = sc3338->cur_mode->max_fps;
722 }
723 break;
724 case PREISP_CMD_SET_HDRAE_EXP:
725 break;
726 case RKMODULE_SET_QUICK_STREAM:
727
728 stream = *((u32 *)arg);
729
730 if (stream)
731 ret = sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
732 SC3338_REG_VALUE_08BIT, SC3338_MODE_STREAMING);
733 else
734 ret = sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
735 SC3338_REG_VALUE_08BIT, SC3338_MODE_SW_STANDBY);
736 break;
737 default:
738 ret = -ENOIOCTLCMD;
739 break;
740 }
741
742 return ret;
743 }
744
745 #ifdef CONFIG_COMPAT
sc3338_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)746 static long sc3338_compat_ioctl32(struct v4l2_subdev *sd,
747 unsigned int cmd, unsigned long arg)
748 {
749 void __user *up = compat_ptr(arg);
750 struct rkmodule_inf *inf;
751 struct rkmodule_hdr_cfg *hdr;
752 struct preisp_hdrae_exp_s *hdrae;
753 long ret;
754 u32 stream = 0;
755
756 switch (cmd) {
757 case RKMODULE_GET_MODULE_INFO:
758 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
759 if (!inf) {
760 ret = -ENOMEM;
761 return ret;
762 }
763
764 ret = sc3338_ioctl(sd, cmd, inf);
765 if (!ret) {
766 if (copy_to_user(up, inf, sizeof(*inf)))
767 ret = -EFAULT;
768 }
769 kfree(inf);
770 break;
771 case RKMODULE_GET_HDR_CFG:
772 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
773 if (!hdr) {
774 ret = -ENOMEM;
775 return ret;
776 }
777
778 ret = sc3338_ioctl(sd, cmd, hdr);
779 if (!ret) {
780 if (copy_to_user(up, hdr, sizeof(*hdr)))
781 ret = -EFAULT;
782 }
783 kfree(hdr);
784 break;
785 case RKMODULE_SET_HDR_CFG:
786 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
787 if (!hdr) {
788 ret = -ENOMEM;
789 return ret;
790 }
791
792 ret = copy_from_user(hdr, up, sizeof(*hdr));
793 if (!ret)
794 ret = sc3338_ioctl(sd, cmd, hdr);
795 else
796 ret = -EFAULT;
797 kfree(hdr);
798 break;
799 case PREISP_CMD_SET_HDRAE_EXP:
800 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
801 if (!hdrae) {
802 ret = -ENOMEM;
803 return ret;
804 }
805
806 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
807 if (!ret)
808 ret = sc3338_ioctl(sd, cmd, hdrae);
809 else
810 ret = -EFAULT;
811 kfree(hdrae);
812 break;
813 case RKMODULE_SET_QUICK_STREAM:
814 ret = copy_from_user(&stream, up, sizeof(u32));
815 if (!ret)
816 ret = sc3338_ioctl(sd, cmd, &stream);
817 else
818 ret = -EFAULT;
819 break;
820 default:
821 ret = -ENOIOCTLCMD;
822 break;
823 }
824
825 return ret;
826 }
827 #endif
828
__sc3338_start_stream(struct sc3338 * sc3338)829 static int __sc3338_start_stream(struct sc3338 *sc3338)
830 {
831 int ret;
832
833 if (!sc3338->is_thunderboot) {
834 ret = sc3338_write_array(sc3338->client, sc3338->cur_mode->reg_list);
835 if (ret)
836 return ret;
837 /* In case these controls are set before streaming */
838 ret = __v4l2_ctrl_handler_setup(&sc3338->ctrl_handler);
839 if (ret)
840 return ret;
841 if (sc3338->has_init_exp && sc3338->cur_mode->hdr_mode != NO_HDR) {
842 ret = sc3338_ioctl(&sc3338->subdev, PREISP_CMD_SET_HDRAE_EXP,
843 &sc3338->init_hdrae_exp);
844 if (ret) {
845 dev_err(&sc3338->client->dev,
846 "init exp fail in hdr mode\n");
847 return ret;
848 }
849 }
850 }
851 return sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
852 SC3338_REG_VALUE_08BIT, SC3338_MODE_STREAMING);
853 }
854
__sc3338_stop_stream(struct sc3338 * sc3338)855 static int __sc3338_stop_stream(struct sc3338 *sc3338)
856 {
857 sc3338->has_init_exp = false;
858 if (sc3338->is_thunderboot) {
859 sc3338->is_first_streamoff = true;
860 pm_runtime_put(&sc3338->client->dev);
861 }
862 return sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
863 SC3338_REG_VALUE_08BIT, SC3338_MODE_SW_STANDBY);
864 }
865
866 static int __sc3338_power_on(struct sc3338 *sc3338);
sc3338_s_stream(struct v4l2_subdev * sd,int on)867 static int sc3338_s_stream(struct v4l2_subdev *sd, int on)
868 {
869 struct sc3338 *sc3338 = to_sc3338(sd);
870 struct i2c_client *client = sc3338->client;
871 int ret = 0;
872
873 mutex_lock(&sc3338->mutex);
874 on = !!on;
875 if (on == sc3338->streaming)
876 goto unlock_and_return;
877 if (on) {
878 if (sc3338->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
879 sc3338->is_thunderboot = false;
880 __sc3338_power_on(sc3338);
881 }
882 ret = pm_runtime_get_sync(&client->dev);
883 if (ret < 0) {
884 pm_runtime_put_noidle(&client->dev);
885 goto unlock_and_return;
886 }
887 ret = __sc3338_start_stream(sc3338);
888 if (ret) {
889 v4l2_err(sd, "start stream failed while write regs\n");
890 pm_runtime_put(&client->dev);
891 goto unlock_and_return;
892 }
893 } else {
894 __sc3338_stop_stream(sc3338);
895 pm_runtime_put(&client->dev);
896 }
897
898 sc3338->streaming = on;
899 unlock_and_return:
900 mutex_unlock(&sc3338->mutex);
901 return ret;
902 }
903
sc3338_s_power(struct v4l2_subdev * sd,int on)904 static int sc3338_s_power(struct v4l2_subdev *sd, int on)
905 {
906 struct sc3338 *sc3338 = to_sc3338(sd);
907 struct i2c_client *client = sc3338->client;
908 int ret = 0;
909
910 mutex_lock(&sc3338->mutex);
911
912 /* If the power state is not modified - no work to do. */
913 if (sc3338->power_on == !!on)
914 goto unlock_and_return;
915
916 if (on) {
917 ret = pm_runtime_get_sync(&client->dev);
918 if (ret < 0) {
919 pm_runtime_put_noidle(&client->dev);
920 goto unlock_and_return;
921 }
922
923 if (!sc3338->is_thunderboot) {
924 ret = sc3338_write_array(sc3338->client, sc3338_global_regs);
925 if (ret) {
926 v4l2_err(sd, "could not set init registers\n");
927 pm_runtime_put_noidle(&client->dev);
928 goto unlock_and_return;
929 }
930 }
931
932 sc3338->power_on = true;
933 } else {
934 pm_runtime_put(&client->dev);
935 sc3338->power_on = false;
936 }
937
938 unlock_and_return:
939 mutex_unlock(&sc3338->mutex);
940
941 return ret;
942 }
943
944 /* Calculate the delay in us by clock rate and clock cycles */
sc3338_cal_delay(u32 cycles)945 static inline u32 sc3338_cal_delay(u32 cycles)
946 {
947 return DIV_ROUND_UP(cycles, SC3338_XVCLK_FREQ / 1000 / 1000);
948 }
949
__sc3338_power_on(struct sc3338 * sc3338)950 static int __sc3338_power_on(struct sc3338 *sc3338)
951 {
952 int ret;
953 u32 delay_us;
954 struct device *dev = &sc3338->client->dev;
955
956 if (!IS_ERR_OR_NULL(sc3338->pins_default)) {
957 ret = pinctrl_select_state(sc3338->pinctrl,
958 sc3338->pins_default);
959 if (ret < 0)
960 dev_err(dev, "could not set pins\n");
961 }
962 ret = clk_set_rate(sc3338->xvclk, SC3338_XVCLK_FREQ);
963 if (ret < 0)
964 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
965 if (clk_get_rate(sc3338->xvclk) != SC3338_XVCLK_FREQ)
966 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
967 ret = clk_prepare_enable(sc3338->xvclk);
968 if (ret < 0) {
969 dev_err(dev, "Failed to enable xvclk\n");
970 return ret;
971 }
972
973 if (sc3338->is_thunderboot)
974 return 0;
975
976 if (!IS_ERR(sc3338->reset_gpio))
977 gpiod_set_value_cansleep(sc3338->reset_gpio, 0);
978
979 ret = regulator_bulk_enable(SC3338_NUM_SUPPLIES, sc3338->supplies);
980 if (ret < 0) {
981 dev_err(dev, "Failed to enable regulators\n");
982 goto disable_clk;
983 }
984
985 if (!IS_ERR(sc3338->reset_gpio))
986 gpiod_set_value_cansleep(sc3338->reset_gpio, 1);
987
988 usleep_range(500, 1000);
989
990 if (!IS_ERR(sc3338->pwdn_gpio))
991 gpiod_set_value_cansleep(sc3338->pwdn_gpio, 1);
992
993 if (!IS_ERR(sc3338->reset_gpio))
994 usleep_range(6000, 8000);
995 else
996 usleep_range(12000, 16000);
997
998 /* 8192 cycles prior to first SCCB transaction */
999 delay_us = sc3338_cal_delay(8192);
1000 usleep_range(delay_us, delay_us * 2);
1001
1002 return 0;
1003
1004 disable_clk:
1005 clk_disable_unprepare(sc3338->xvclk);
1006
1007 return ret;
1008 }
1009
__sc3338_power_off(struct sc3338 * sc3338)1010 static void __sc3338_power_off(struct sc3338 *sc3338)
1011 {
1012 int ret;
1013 struct device *dev = &sc3338->client->dev;
1014
1015 clk_disable_unprepare(sc3338->xvclk);
1016 if (sc3338->is_thunderboot) {
1017 if (sc3338->is_first_streamoff) {
1018 sc3338->is_thunderboot = false;
1019 sc3338->is_first_streamoff = false;
1020 } else {
1021 return;
1022 }
1023 }
1024
1025 if (!IS_ERR(sc3338->pwdn_gpio))
1026 gpiod_set_value_cansleep(sc3338->pwdn_gpio, 0);
1027 clk_disable_unprepare(sc3338->xvclk);
1028 if (!IS_ERR(sc3338->reset_gpio))
1029 gpiod_set_value_cansleep(sc3338->reset_gpio, 0);
1030 if (!IS_ERR_OR_NULL(sc3338->pins_sleep)) {
1031 ret = pinctrl_select_state(sc3338->pinctrl,
1032 sc3338->pins_sleep);
1033 if (ret < 0)
1034 dev_dbg(dev, "could not set pins\n");
1035 }
1036 regulator_bulk_disable(SC3338_NUM_SUPPLIES, sc3338->supplies);
1037 }
1038
sc3338_runtime_resume(struct device * dev)1039 static int sc3338_runtime_resume(struct device *dev)
1040 {
1041 struct i2c_client *client = to_i2c_client(dev);
1042 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1043 struct sc3338 *sc3338 = to_sc3338(sd);
1044
1045 return __sc3338_power_on(sc3338);
1046 }
1047
sc3338_runtime_suspend(struct device * dev)1048 static int sc3338_runtime_suspend(struct device *dev)
1049 {
1050 struct i2c_client *client = to_i2c_client(dev);
1051 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1052 struct sc3338 *sc3338 = to_sc3338(sd);
1053
1054 __sc3338_power_off(sc3338);
1055
1056 return 0;
1057 }
1058
1059 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc3338_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1060 static int sc3338_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1061 {
1062 struct sc3338 *sc3338 = to_sc3338(sd);
1063 struct v4l2_mbus_framefmt *try_fmt =
1064 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1065 const struct sc3338_mode *def_mode = &supported_modes[0];
1066
1067 mutex_lock(&sc3338->mutex);
1068 /* Initialize try_fmt */
1069 try_fmt->width = def_mode->width;
1070 try_fmt->height = def_mode->height;
1071 try_fmt->code = def_mode->bus_fmt;
1072 try_fmt->field = V4L2_FIELD_NONE;
1073
1074 mutex_unlock(&sc3338->mutex);
1075 /* No crop or compose */
1076
1077 return 0;
1078 }
1079 #endif
1080
sc3338_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1081 static int sc3338_enum_frame_interval(struct v4l2_subdev *sd,
1082 struct v4l2_subdev_pad_config *cfg,
1083 struct v4l2_subdev_frame_interval_enum *fie)
1084 {
1085 if (fie->index >= ARRAY_SIZE(supported_modes))
1086 return -EINVAL;
1087
1088 fie->code = supported_modes[fie->index].bus_fmt;
1089 fie->width = supported_modes[fie->index].width;
1090 fie->height = supported_modes[fie->index].height;
1091 fie->interval = supported_modes[fie->index].max_fps;
1092 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1093 return 0;
1094 }
1095
1096 static const struct dev_pm_ops sc3338_pm_ops = {
1097 SET_RUNTIME_PM_OPS(sc3338_runtime_suspend,
1098 sc3338_runtime_resume, NULL)
1099 };
1100
1101 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1102 static const struct v4l2_subdev_internal_ops sc3338_internal_ops = {
1103 .open = sc3338_open,
1104 };
1105 #endif
1106
1107 static const struct v4l2_subdev_core_ops sc3338_core_ops = {
1108 .s_power = sc3338_s_power,
1109 .ioctl = sc3338_ioctl,
1110 #ifdef CONFIG_COMPAT
1111 .compat_ioctl32 = sc3338_compat_ioctl32,
1112 #endif
1113 };
1114
1115 static const struct v4l2_subdev_video_ops sc3338_video_ops = {
1116 .s_stream = sc3338_s_stream,
1117 .g_frame_interval = sc3338_g_frame_interval,
1118 };
1119
1120 static const struct v4l2_subdev_pad_ops sc3338_pad_ops = {
1121 .enum_mbus_code = sc3338_enum_mbus_code,
1122 .enum_frame_size = sc3338_enum_frame_sizes,
1123 .enum_frame_interval = sc3338_enum_frame_interval,
1124 .get_fmt = sc3338_get_fmt,
1125 .set_fmt = sc3338_set_fmt,
1126 .get_mbus_config = sc3338_g_mbus_config,
1127 };
1128
1129 static const struct v4l2_subdev_ops sc3338_subdev_ops = {
1130 .core = &sc3338_core_ops,
1131 .video = &sc3338_video_ops,
1132 .pad = &sc3338_pad_ops,
1133 };
1134
sc3338_modify_fps_info(struct sc3338 * sc3338)1135 static void sc3338_modify_fps_info(struct sc3338 *sc3338)
1136 {
1137 const struct sc3338_mode *mode = sc3338->cur_mode;
1138
1139 sc3338->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1140 sc3338->cur_vts;
1141 }
1142
sc3338_set_ctrl(struct v4l2_ctrl * ctrl)1143 static int sc3338_set_ctrl(struct v4l2_ctrl *ctrl)
1144 {
1145 struct sc3338 *sc3338 = container_of(ctrl->handler,
1146 struct sc3338, ctrl_handler);
1147 struct i2c_client *client = sc3338->client;
1148 s64 max;
1149 int ret = 0;
1150 u32 val = 0;
1151
1152 /* Propagate change of current control to all related controls */
1153 switch (ctrl->id) {
1154 case V4L2_CID_VBLANK:
1155 /* Update max exposure while meeting expected vblanking */
1156 max = sc3338->cur_mode->height + ctrl->val - 8;
1157 __v4l2_ctrl_modify_range(sc3338->exposure,
1158 sc3338->exposure->minimum, max,
1159 sc3338->exposure->step,
1160 sc3338->exposure->default_value);
1161 break;
1162 }
1163
1164 if (!pm_runtime_get_if_in_use(&client->dev))
1165 return 0;
1166
1167 switch (ctrl->id) {
1168 case V4L2_CID_EXPOSURE:
1169 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1170 if (sc3338->cur_mode->hdr_mode == NO_HDR) {
1171 val = ctrl->val;
1172 /* 4 least significant bits of expsoure are fractional part */
1173 ret = sc3338_write_reg(sc3338->client,
1174 SC3338_REG_EXPOSURE_H,
1175 SC3338_REG_VALUE_08BIT,
1176 SC3338_FETCH_EXP_H(val));
1177 ret |= sc3338_write_reg(sc3338->client,
1178 SC3338_REG_EXPOSURE_M,
1179 SC3338_REG_VALUE_08BIT,
1180 SC3338_FETCH_EXP_M(val));
1181 ret |= sc3338_write_reg(sc3338->client,
1182 SC3338_REG_EXPOSURE_L,
1183 SC3338_REG_VALUE_08BIT,
1184 SC3338_FETCH_EXP_L(val));
1185 }
1186 break;
1187 case V4L2_CID_ANALOGUE_GAIN:
1188 dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1189 if (sc3338->cur_mode->hdr_mode == NO_HDR)
1190 ret = sc3338_set_gain_reg(sc3338, ctrl->val);
1191 break;
1192 case V4L2_CID_VBLANK:
1193 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1194 ret = sc3338_write_reg(sc3338->client,
1195 SC3338_REG_VTS_H,
1196 SC3338_REG_VALUE_08BIT,
1197 (ctrl->val + sc3338->cur_mode->height)
1198 >> 8);
1199 ret |= sc3338_write_reg(sc3338->client,
1200 SC3338_REG_VTS_L,
1201 SC3338_REG_VALUE_08BIT,
1202 (ctrl->val + sc3338->cur_mode->height)
1203 & 0xff);
1204 sc3338->cur_vts = ctrl->val + sc3338->cur_mode->height;
1205 sc3338_modify_fps_info(sc3338);
1206 break;
1207 case V4L2_CID_TEST_PATTERN:
1208 ret = sc3338_enable_test_pattern(sc3338, ctrl->val);
1209 break;
1210 case V4L2_CID_HFLIP:
1211 ret = sc3338_read_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
1212 SC3338_REG_VALUE_08BIT, &val);
1213 ret |= sc3338_write_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
1214 SC3338_REG_VALUE_08BIT,
1215 SC3338_FETCH_MIRROR(val, ctrl->val));
1216 break;
1217 case V4L2_CID_VFLIP:
1218 ret = sc3338_read_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
1219 SC3338_REG_VALUE_08BIT, &val);
1220 ret |= sc3338_write_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
1221 SC3338_REG_VALUE_08BIT,
1222 SC3338_FETCH_FLIP(val, ctrl->val));
1223 break;
1224 default:
1225 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1226 __func__, ctrl->id, ctrl->val);
1227 break;
1228 }
1229
1230 pm_runtime_put(&client->dev);
1231
1232 return ret;
1233 }
1234
1235 static const struct v4l2_ctrl_ops sc3338_ctrl_ops = {
1236 .s_ctrl = sc3338_set_ctrl,
1237 };
1238
sc3338_initialize_controls(struct sc3338 * sc3338)1239 static int sc3338_initialize_controls(struct sc3338 *sc3338)
1240 {
1241 const struct sc3338_mode *mode;
1242 struct v4l2_ctrl_handler *handler;
1243 struct v4l2_ctrl *ctrl;
1244 s64 exposure_max, vblank_def;
1245 u32 h_blank;
1246 int ret;
1247
1248 handler = &sc3338->ctrl_handler;
1249 mode = sc3338->cur_mode;
1250 ret = v4l2_ctrl_handler_init(handler, 9);
1251 if (ret)
1252 return ret;
1253 handler->lock = &sc3338->mutex;
1254
1255 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1256 0, 0, link_freq_menu_items);
1257 if (ctrl)
1258 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1259
1260 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1261 0, PIXEL_RATE_WITH_253M_10BIT, 1, PIXEL_RATE_WITH_253M_10BIT);
1262
1263 h_blank = mode->hts_def - mode->width;
1264 sc3338->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1265 h_blank, h_blank, 1, h_blank);
1266 if (sc3338->hblank)
1267 sc3338->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1268 vblank_def = mode->vts_def - mode->height;
1269 sc3338->vblank = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
1270 V4L2_CID_VBLANK, vblank_def,
1271 SC3338_VTS_MAX - mode->height,
1272 1, vblank_def);
1273 exposure_max = mode->vts_def - 8;
1274 sc3338->exposure = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
1275 V4L2_CID_EXPOSURE, SC3338_EXPOSURE_MIN,
1276 exposure_max, SC3338_EXPOSURE_STEP,
1277 mode->exp_def);
1278 sc3338->anal_gain = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
1279 V4L2_CID_ANALOGUE_GAIN, SC3338_GAIN_MIN,
1280 SC3338_GAIN_MAX, SC3338_GAIN_STEP,
1281 SC3338_GAIN_DEFAULT);
1282 sc3338->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1283 &sc3338_ctrl_ops,
1284 V4L2_CID_TEST_PATTERN,
1285 ARRAY_SIZE(sc3338_test_pattern_menu) - 1,
1286 0, 0, sc3338_test_pattern_menu);
1287 v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
1288 V4L2_CID_HFLIP, 0, 1, 1, 0);
1289 v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
1290 V4L2_CID_VFLIP, 0, 1, 1, 0);
1291 if (handler->error) {
1292 ret = handler->error;
1293 dev_err(&sc3338->client->dev,
1294 "Failed to init controls(%d)\n", ret);
1295 goto err_free_handler;
1296 }
1297
1298 sc3338->subdev.ctrl_handler = handler;
1299 sc3338->has_init_exp = false;
1300 sc3338->cur_fps = mode->max_fps;
1301
1302 return 0;
1303
1304 err_free_handler:
1305 v4l2_ctrl_handler_free(handler);
1306
1307 return ret;
1308 }
1309
sc3338_check_sensor_id(struct sc3338 * sc3338,struct i2c_client * client)1310 static int sc3338_check_sensor_id(struct sc3338 *sc3338,
1311 struct i2c_client *client)
1312 {
1313 struct device *dev = &sc3338->client->dev;
1314 u32 id = 0;
1315 int ret;
1316
1317 if (sc3338->is_thunderboot) {
1318 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1319 return 0;
1320 }
1321
1322 ret = sc3338_read_reg(client, SC3338_REG_CHIP_ID,
1323 SC3338_REG_VALUE_16BIT, &id);
1324 if (id != CHIP_ID) {
1325 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1326 return -ENODEV;
1327 }
1328
1329 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1330
1331 return 0;
1332 }
1333
sc3338_configure_regulators(struct sc3338 * sc3338)1334 static int sc3338_configure_regulators(struct sc3338 *sc3338)
1335 {
1336 unsigned int i;
1337
1338 for (i = 0; i < SC3338_NUM_SUPPLIES; i++)
1339 sc3338->supplies[i].supply = sc3338_supply_names[i];
1340
1341 return devm_regulator_bulk_get(&sc3338->client->dev,
1342 SC3338_NUM_SUPPLIES,
1343 sc3338->supplies);
1344 }
1345
sc3338_probe(struct i2c_client * client,const struct i2c_device_id * id)1346 static int sc3338_probe(struct i2c_client *client,
1347 const struct i2c_device_id *id)
1348 {
1349 struct device *dev = &client->dev;
1350 struct device_node *node = dev->of_node;
1351 struct sc3338 *sc3338;
1352 struct v4l2_subdev *sd;
1353 char facing[2];
1354 int ret;
1355 int i, hdr_mode = 0;
1356
1357 dev_info(dev, "driver version: %02x.%02x.%02x",
1358 DRIVER_VERSION >> 16,
1359 (DRIVER_VERSION & 0xff00) >> 8,
1360 DRIVER_VERSION & 0x00ff);
1361
1362 sc3338 = devm_kzalloc(dev, sizeof(*sc3338), GFP_KERNEL);
1363 if (!sc3338)
1364 return -ENOMEM;
1365
1366 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1367 &sc3338->module_index);
1368 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1369 &sc3338->module_facing);
1370 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1371 &sc3338->module_name);
1372 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1373 &sc3338->len_name);
1374 if (ret) {
1375 dev_err(dev, "could not get module information!\n");
1376 return -EINVAL;
1377 }
1378
1379 sc3338->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1380
1381 sc3338->client = client;
1382 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1383 if (hdr_mode == supported_modes[i].hdr_mode) {
1384 sc3338->cur_mode = &supported_modes[i];
1385 break;
1386 }
1387 }
1388 if (i == ARRAY_SIZE(supported_modes))
1389 sc3338->cur_mode = &supported_modes[0];
1390
1391 sc3338->xvclk = devm_clk_get(dev, "xvclk");
1392 if (IS_ERR(sc3338->xvclk)) {
1393 dev_err(dev, "Failed to get xvclk\n");
1394 return -EINVAL;
1395 }
1396
1397 sc3338->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1398 if (IS_ERR(sc3338->reset_gpio))
1399 dev_warn(dev, "Failed to get reset-gpios\n");
1400
1401 sc3338->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1402 if (IS_ERR(sc3338->pwdn_gpio))
1403 dev_warn(dev, "Failed to get pwdn-gpios\n");
1404
1405 sc3338->pinctrl = devm_pinctrl_get(dev);
1406 if (!IS_ERR(sc3338->pinctrl)) {
1407 sc3338->pins_default =
1408 pinctrl_lookup_state(sc3338->pinctrl,
1409 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1410 if (IS_ERR(sc3338->pins_default))
1411 dev_err(dev, "could not get default pinstate\n");
1412
1413 sc3338->pins_sleep =
1414 pinctrl_lookup_state(sc3338->pinctrl,
1415 OF_CAMERA_PINCTRL_STATE_SLEEP);
1416 if (IS_ERR(sc3338->pins_sleep))
1417 dev_err(dev, "could not get sleep pinstate\n");
1418 } else {
1419 dev_err(dev, "no pinctrl\n");
1420 }
1421
1422 ret = sc3338_configure_regulators(sc3338);
1423 if (ret) {
1424 dev_err(dev, "Failed to get power regulators\n");
1425 return ret;
1426 }
1427
1428 mutex_init(&sc3338->mutex);
1429
1430 sd = &sc3338->subdev;
1431 v4l2_i2c_subdev_init(sd, client, &sc3338_subdev_ops);
1432 ret = sc3338_initialize_controls(sc3338);
1433 if (ret)
1434 goto err_destroy_mutex;
1435
1436 ret = __sc3338_power_on(sc3338);
1437 if (ret)
1438 goto err_free_handler;
1439
1440 ret = sc3338_check_sensor_id(sc3338, client);
1441 if (ret)
1442 goto err_power_off;
1443
1444 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1445 sd->internal_ops = &sc3338_internal_ops;
1446 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1447 V4L2_SUBDEV_FL_HAS_EVENTS;
1448 #endif
1449 #if defined(CONFIG_MEDIA_CONTROLLER)
1450 sc3338->pad.flags = MEDIA_PAD_FL_SOURCE;
1451 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1452 ret = media_entity_pads_init(&sd->entity, 1, &sc3338->pad);
1453 if (ret < 0)
1454 goto err_power_off;
1455 #endif
1456
1457 memset(facing, 0, sizeof(facing));
1458 if (strcmp(sc3338->module_facing, "back") == 0)
1459 facing[0] = 'b';
1460 else
1461 facing[0] = 'f';
1462
1463 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1464 sc3338->module_index, facing,
1465 SC3338_NAME, dev_name(sd->dev));
1466 ret = v4l2_async_register_subdev_sensor_common(sd);
1467 if (ret) {
1468 dev_err(dev, "v4l2 async register subdev failed\n");
1469 goto err_clean_entity;
1470 }
1471
1472 pm_runtime_set_active(dev);
1473 pm_runtime_enable(dev);
1474 if (sc3338->is_thunderboot)
1475 pm_runtime_get_sync(dev);
1476 else
1477 pm_runtime_idle(dev);
1478
1479 return 0;
1480
1481 err_clean_entity:
1482 #if defined(CONFIG_MEDIA_CONTROLLER)
1483 media_entity_cleanup(&sd->entity);
1484 #endif
1485 err_power_off:
1486 __sc3338_power_off(sc3338);
1487 err_free_handler:
1488 v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
1489 err_destroy_mutex:
1490 mutex_destroy(&sc3338->mutex);
1491
1492 return ret;
1493 }
1494
sc3338_remove(struct i2c_client * client)1495 static int sc3338_remove(struct i2c_client *client)
1496 {
1497 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1498 struct sc3338 *sc3338 = to_sc3338(sd);
1499
1500 v4l2_async_unregister_subdev(sd);
1501 #if defined(CONFIG_MEDIA_CONTROLLER)
1502 media_entity_cleanup(&sd->entity);
1503 #endif
1504 v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
1505 mutex_destroy(&sc3338->mutex);
1506
1507 pm_runtime_disable(&client->dev);
1508 if (!pm_runtime_status_suspended(&client->dev))
1509 __sc3338_power_off(sc3338);
1510 pm_runtime_set_suspended(&client->dev);
1511
1512 return 0;
1513 }
1514
1515 #if IS_ENABLED(CONFIG_OF)
1516 static const struct of_device_id sc3338_of_match[] = {
1517 { .compatible = "smartsens,sc3338" },
1518 {},
1519 };
1520 MODULE_DEVICE_TABLE(of, sc3338_of_match);
1521 #endif
1522
1523 static const struct i2c_device_id sc3338_match_id[] = {
1524 { "smartsens,sc3338", 0 },
1525 { },
1526 };
1527
1528 static struct i2c_driver sc3338_i2c_driver = {
1529 .driver = {
1530 .name = SC3338_NAME,
1531 .pm = &sc3338_pm_ops,
1532 .of_match_table = of_match_ptr(sc3338_of_match),
1533 },
1534 .probe = &sc3338_probe,
1535 .remove = &sc3338_remove,
1536 .id_table = sc3338_match_id,
1537 };
1538
sensor_mod_init(void)1539 static int __init sensor_mod_init(void)
1540 {
1541 return i2c_add_driver(&sc3338_i2c_driver);
1542 }
1543
sensor_mod_exit(void)1544 static void __exit sensor_mod_exit(void)
1545 {
1546 i2c_del_driver(&sc3338_i2c_driver);
1547 }
1548
1549 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1550 subsys_initcall(sensor_mod_init);
1551 #else
1552 device_initcall_sync(sensor_mod_init);
1553 #endif
1554 module_exit(sensor_mod_exit);
1555
1556 MODULE_DESCRIPTION("smartsens sc3338 sensor driver");
1557 MODULE_LICENSE("GPL");
1558