1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc3336 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 */
9
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/rk-preisp.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define SC3336_LANES 2
38 #define SC3336_BITS_PER_SAMPLE 10
39 #define SC3336_LINK_FREQ_253 253125000
40 #define SC3336_LINK_FREQ_255 255000000
41
42 #define PIXEL_RATE_WITH_253M_10BIT (SC3336_LINK_FREQ_253 * 2 * \
43 SC3336_LANES / SC3336_BITS_PER_SAMPLE)
44 #define PIXEL_RATE_WITH_255M_10BIT (SC3336_LINK_FREQ_255 * 2 * \
45 SC3336_LANES / SC3336_BITS_PER_SAMPLE)
46
47 #define SC3336_XVCLK_FREQ 27000000
48
49 #define CHIP_ID 0xcc41
50 #define SC3336_REG_CHIP_ID 0x3107
51
52 #define SC3336_REG_CTRL_MODE 0x0100
53 #define SC3336_MODE_SW_STANDBY 0x0
54 #define SC3336_MODE_STREAMING BIT(0)
55
56 #define SC3336_REG_EXPOSURE_H 0x3e00
57 #define SC3336_REG_EXPOSURE_M 0x3e01
58 #define SC3336_REG_EXPOSURE_L 0x3e02
59 #define SC3336_EXPOSURE_MIN 1
60 #define SC3336_EXPOSURE_STEP 1
61 #define SC3336_VTS_MAX 0x7fff
62
63 #define SC3336_REG_DIG_GAIN 0x3e06
64 #define SC3336_REG_DIG_FINE_GAIN 0x3e07
65 #define SC3336_REG_ANA_GAIN 0x3e09
66 #define SC3336_GAIN_MIN 0x0080
67 #define SC3336_GAIN_MAX (99614) //48.64*16*128
68 #define SC3336_GAIN_STEP 1
69 #define SC3336_GAIN_DEFAULT 0x80
70
71
72 #define SC3336_REG_GROUP_HOLD 0x3812
73 #define SC3336_GROUP_HOLD_START 0x00
74 #define SC3336_GROUP_HOLD_END 0x30
75
76 #define SC3336_REG_TEST_PATTERN 0x4501
77 #define SC3336_TEST_PATTERN_BIT_MASK BIT(3)
78
79 #define SC3336_REG_VTS_H 0x320e
80 #define SC3336_REG_VTS_L 0x320f
81
82 #define SC3336_FLIP_MIRROR_REG 0x3221
83
84 #define SC3336_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
85 #define SC3336_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
86 #define SC3336_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
87
88 #define SC3336_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
89 #define SC3336_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
90
91 #define SC3336_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
92 #define SC3336_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
93
94 #define REG_DELAY 0xFFFE
95 #define REG_NULL 0xFFFF
96
97 #define SC3336_REG_VALUE_08BIT 1
98 #define SC3336_REG_VALUE_16BIT 2
99 #define SC3336_REG_VALUE_24BIT 3
100
101 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
102 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
103 #define SC3336_NAME "sc3336"
104
105 static const char * const sc3336_supply_names[] = {
106 "avdd", /* Analog power */
107 "dovdd", /* Digital I/O power */
108 "dvdd", /* Digital core power */
109 };
110
111 #define SC3336_NUM_SUPPLIES ARRAY_SIZE(sc3336_supply_names)
112
113 struct regval {
114 u16 addr;
115 u8 val;
116 };
117
118 struct sc3336_mode {
119 u32 bus_fmt;
120 u32 width;
121 u32 height;
122 struct v4l2_fract max_fps;
123 u32 hts_def;
124 u32 vts_def;
125 u32 exp_def;
126 const struct regval *reg_list;
127 u32 hdr_mode;
128 u32 xvclk_freq;
129 u32 link_freq_idx;
130 u32 vc[PAD_MAX];
131 };
132
133 struct sc3336 {
134 struct i2c_client *client;
135 struct clk *xvclk;
136 struct gpio_desc *reset_gpio;
137 struct gpio_desc *pwdn_gpio;
138 struct regulator_bulk_data supplies[SC3336_NUM_SUPPLIES];
139
140 struct pinctrl *pinctrl;
141 struct pinctrl_state *pins_default;
142 struct pinctrl_state *pins_sleep;
143
144 struct v4l2_subdev subdev;
145 struct media_pad pad;
146 struct v4l2_ctrl_handler ctrl_handler;
147 struct v4l2_ctrl *exposure;
148 struct v4l2_ctrl *anal_gain;
149 struct v4l2_ctrl *digi_gain;
150 struct v4l2_ctrl *hblank;
151 struct v4l2_ctrl *vblank;
152 struct v4l2_ctrl *pixel_rate;
153 struct v4l2_ctrl *link_freq;
154 struct v4l2_ctrl *test_pattern;
155 struct mutex mutex;
156 struct v4l2_fract cur_fps;
157 bool streaming;
158 bool power_on;
159 const struct sc3336_mode *cur_mode;
160 u32 module_index;
161 const char *module_facing;
162 const char *module_name;
163 const char *len_name;
164 u32 cur_vts;
165 bool has_init_exp;
166 bool is_thunderboot;
167 bool is_first_streamoff;
168 struct preisp_hdrae_exp_s init_hdrae_exp;
169 };
170
171 #define to_sc3336(sd) container_of(sd, struct sc3336, subdev)
172
173 /*
174 * Xclk 24Mhz
175 */
176 static const struct regval sc3336_global_regs[] = {
177 {REG_NULL, 0x00},
178 };
179
180 /*
181 * Xclk 27Mhz
182 * max_framerate 25fps
183 * mipi_datarate per lane 506.25Mbps, 2lane
184 */
185 static const struct regval sc3336_linear_10_2304x1296_25fps_regs[] = {
186 {0x0103, 0x01},
187 {0x36e9, 0x80},
188 {0x37f9, 0x80},
189 {0x301f, 0x01},
190 {0x30b8, 0x33},
191 {0x320e, 0x06},
192 {0x320f, 0x54},
193 {0x3253, 0x10},
194 {0x325f, 0x20},
195 {0x3301, 0x04},
196 {0x3306, 0x50},
197 {0x3309, 0xa8},
198 {0x330a, 0x00},
199 {0x330b, 0xd8},
200 {0x3314, 0x13},
201 {0x331f, 0x99},
202 {0x3333, 0x10},
203 {0x3334, 0x40},
204 {0x335e, 0x06},
205 {0x335f, 0x0a},
206 {0x3364, 0x5e},
207 {0x337c, 0x02},
208 {0x337d, 0x0e},
209 {0x3390, 0x01},
210 {0x3391, 0x03},
211 {0x3392, 0x07},
212 {0x3393, 0x04},
213 {0x3394, 0x04},
214 {0x3395, 0x04},
215 {0x3396, 0x08},
216 {0x3397, 0x0b},
217 {0x3398, 0x1f},
218 {0x3399, 0x04},
219 {0x339a, 0x0a},
220 {0x339b, 0x3a},
221 {0x339c, 0xb4},
222 {0x33a2, 0x04},
223 {0x33ac, 0x08},
224 {0x33ad, 0x1c},
225 {0x33ae, 0x10},
226 {0x33af, 0x30},
227 {0x33b1, 0x80},
228 {0x33b3, 0x48},
229 {0x33f9, 0x60},
230 {0x33fb, 0x74},
231 {0x33fc, 0x4b},
232 {0x33fd, 0x5f},
233 {0x349f, 0x03},
234 {0x34a6, 0x4b},
235 {0x34a7, 0x5f},
236 {0x34a8, 0x20},
237 {0x34a9, 0x18},
238 {0x34ab, 0xe8},
239 {0x34ac, 0x01},
240 {0x34ad, 0x00},
241 {0x34f8, 0x5f},
242 {0x34f9, 0x18},
243 {0x3630, 0xc0},
244 {0x3631, 0x84},
245 {0x3632, 0x64},
246 {0x3633, 0x32},
247 {0x363b, 0x03},
248 {0x363c, 0x08},
249 {0x3641, 0x38},
250 {0x3670, 0x4e},
251 {0x3674, 0xc0},
252 {0x3675, 0xc0},
253 {0x3676, 0xc0},
254 {0x3677, 0x84},
255 {0x3678, 0x84},
256 {0x3679, 0x84},
257 {0x367c, 0x48},
258 {0x367d, 0x49},
259 {0x367e, 0x4b},
260 {0x367f, 0x5f},
261 {0x3690, 0x32},
262 {0x3691, 0x32},
263 {0x3692, 0x42},
264 {0x369c, 0x4b},
265 {0x369d, 0x5f},
266 {0x36b0, 0x87},
267 {0x36b1, 0x90},
268 {0x36b2, 0xa1},
269 {0x36b3, 0xd8},
270 {0x36b4, 0x49},
271 {0x36b5, 0x4b},
272 {0x36b6, 0x4f},
273 {0x370f, 0x01},
274 {0x3722, 0x09},
275 {0x3724, 0x41},
276 {0x3725, 0xc1},
277 {0x3771, 0x09},
278 {0x3772, 0x09},
279 {0x3773, 0x05},
280 {0x377a, 0x48},
281 {0x377b, 0x5f},
282 {0x3904, 0x04},
283 {0x3905, 0x8c},
284 {0x391d, 0x04},
285 {0x3921, 0x20},
286 {0x3926, 0x21},
287 {0x3933, 0x80},
288 {0x3934, 0x0a},
289 {0x3935, 0x00},
290 {0x3936, 0x2a},
291 {0x3937, 0x6a},
292 {0x3938, 0x6a},
293 {0x39dc, 0x02},
294 {0x3e01, 0x53},
295 {0x3e02, 0xe0},
296 {0x3e09, 0x00},
297 {0x440e, 0x02},
298 {0x4509, 0x20},
299 {0x5ae0, 0xfe},
300 {0x5ae1, 0x40},
301 {0x5ae2, 0x38},
302 {0x5ae3, 0x30},
303 {0x5ae4, 0x28},
304 {0x5ae5, 0x38},
305 {0x5ae6, 0x30},
306 {0x5ae7, 0x28},
307 {0x5ae8, 0x3f},
308 {0x5ae9, 0x34},
309 {0x5aea, 0x2c},
310 {0x5aeb, 0x3f},
311 {0x5aec, 0x34},
312 {0x5aed, 0x2c},
313 {0x36e9, 0x54},
314 {0x37f9, 0x27},
315 {0x3028, 0x05},
316 {REG_NULL, 0x00},
317 };
318
319 /*
320 * Xclk 24Mhz
321 * max_framerate 30fps
322 * mipi_datarate per lane 510Mbps, 2lane
323 */
324 static const struct regval sc3336_linear_10_2304x1296_30fps_regs[] = {
325 {0x0103, 0x01},
326 {0x36e9, 0x80},
327 {0x37f9, 0x80},
328 {0x301f, 0x02},
329 {0x30b8, 0x33},
330 {0x320e, 0x05},
331 {0x320f, 0x50},
332 {0x3253, 0x10},
333 {0x325f, 0x20},
334 {0x3301, 0x04},
335 {0x3306, 0x50},
336 {0x330a, 0x00},
337 {0x330b, 0xd8},
338 {0x3314, 0x13},
339 {0x3333, 0x10},
340 {0x3334, 0x40},
341 {0x335e, 0x06},
342 {0x335f, 0x0a},
343 {0x3364, 0x5e},
344 {0x337c, 0x02},
345 {0x337d, 0x0e},
346 {0x3390, 0x01},
347 {0x3391, 0x03},
348 {0x3392, 0x07},
349 {0x3393, 0x04},
350 {0x3394, 0x04},
351 {0x3395, 0x04},
352 {0x3396, 0x08},
353 {0x3397, 0x0b},
354 {0x3398, 0x1f},
355 {0x3399, 0x04},
356 {0x339a, 0x0a},
357 {0x339b, 0x3a},
358 {0x339c, 0xc4},
359 {0x33a2, 0x04},
360 {0x33ac, 0x08},
361 {0x33ad, 0x1c},
362 {0x33ae, 0x10},
363 {0x33af, 0x30},
364 {0x33b1, 0x80},
365 {0x33b3, 0x48},
366 {0x33f9, 0x60},
367 {0x33fb, 0x74},
368 {0x33fc, 0x4b},
369 {0x33fd, 0x5f},
370 {0x349f, 0x03},
371 {0x34a6, 0x4b},
372 {0x34a7, 0x5f},
373 {0x34a8, 0x20},
374 {0x34a9, 0x18},
375 {0x34ab, 0xe8},
376 {0x34ac, 0x01},
377 {0x34ad, 0x00},
378 {0x34f8, 0x5f},
379 {0x34f9, 0x18},
380 {0x3630, 0xc0},
381 {0x3631, 0x84},
382 {0x3632, 0x64},
383 {0x3633, 0x32},
384 {0x363b, 0x03},
385 {0x363c, 0x08},
386 {0x3641, 0x38},
387 {0x3670, 0x4e},
388 {0x3674, 0xc0},
389 {0x3675, 0xc0},
390 {0x3676, 0xc0},
391 {0x3677, 0x84},
392 {0x3678, 0x8a},
393 {0x3679, 0x8c},
394 {0x367c, 0x48},
395 {0x367d, 0x49},
396 {0x367e, 0x4b},
397 {0x367f, 0x5f},
398 {0x3690, 0x33},
399 {0x3691, 0x33},
400 {0x3692, 0x44},
401 {0x369c, 0x4b},
402 {0x369d, 0x5f},
403 {0x36b0, 0x87},
404 {0x36b1, 0x90},
405 {0x36b2, 0xa1},
406 {0x36b3, 0xd8},
407 {0x36b4, 0x49},
408 {0x36b5, 0x4b},
409 {0x36b6, 0x4f},
410 {0x36ea, 0x11},
411 {0x36eb, 0x0d},
412 {0x36ec, 0x1c},
413 {0x36ed, 0x26},
414 {0x370f, 0x01},
415 {0x3722, 0x09},
416 {0x3724, 0x41},
417 {0x3725, 0xc1},
418 {0x3771, 0x09},
419 {0x3772, 0x09},
420 {0x3773, 0x05},
421 {0x377a, 0x48},
422 {0x377b, 0x5f},
423 {0x37fa, 0x11},
424 {0x37fb, 0x33},
425 {0x37fc, 0x11},
426 {0x37fd, 0x08},
427 {0x3904, 0x04},
428 {0x3905, 0x8c},
429 {0x391d, 0x04},
430 {0x3921, 0x20},
431 {0x3926, 0x21},
432 {0x3933, 0x80},
433 {0x3934, 0x0a},
434 {0x3935, 0x00},
435 {0x3936, 0x2a},
436 {0x3937, 0x6a},
437 {0x3938, 0x6a},
438 {0x39dc, 0x02},
439 {0x3e01, 0x54},
440 {0x3e02, 0x80},
441 {0x3e09, 0x00},
442 {0x440e, 0x02},
443 {0x4509, 0x20},
444 {0x5ae0, 0xfe},
445 {0x5ae1, 0x40},
446 {0x5ae2, 0x38},
447 {0x5ae3, 0x30},
448 {0x5ae4, 0x28},
449 {0x5ae5, 0x38},
450 {0x5ae6, 0x30},
451 {0x5ae7, 0x28},
452 {0x5ae8, 0x3f},
453 {0x5ae9, 0x34},
454 {0x5aea, 0x2c},
455 {0x5aeb, 0x3f},
456 {0x5aec, 0x34},
457 {0x5aed, 0x2c},
458 {0x36e9, 0x54},
459 {0x37f9, 0x47},
460 {REG_NULL, 0x00},
461 };
462
463 static const struct sc3336_mode supported_modes[] = {
464 {
465 .width = 2304,
466 .height = 1296,
467 .max_fps = {
468 .numerator = 10000,
469 .denominator = 250000,
470 },
471 .exp_def = 0x0080,
472 .hts_def = 0x05dc,
473 .vts_def = 0x0654,
474 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
475 .reg_list = sc3336_linear_10_2304x1296_25fps_regs,
476 .hdr_mode = NO_HDR,
477 .xvclk_freq = 27000000,
478 .link_freq_idx = 0,
479 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
480 },
481 {
482 .width = 2304,
483 .height = 1296,
484 .max_fps = {
485 .numerator = 10000,
486 .denominator = 300000,
487 },
488 .exp_def = 0x0080,
489 .hts_def = 0x0578 * 2,
490 .vts_def = 0x0550,
491 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
492 .reg_list = sc3336_linear_10_2304x1296_30fps_regs,
493 .hdr_mode = NO_HDR,
494 .xvclk_freq = 24000000,
495 .link_freq_idx = 1,
496 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
497 }
498 };
499
500 static const s64 link_freq_menu_items[] = {
501 SC3336_LINK_FREQ_253,
502 SC3336_LINK_FREQ_255,
503 };
504
505 static const char * const sc3336_test_pattern_menu[] = {
506 "Disabled",
507 "Vertical Color Bar Type 1",
508 "Vertical Color Bar Type 2",
509 "Vertical Color Bar Type 3",
510 "Vertical Color Bar Type 4",
511 };
512
513 /* Write registers up to 4 at a time */
sc3336_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)514 static int sc3336_write_reg(struct i2c_client *client, u16 reg,
515 u32 len, u32 val)
516 {
517 u32 buf_i, val_i;
518 u8 buf[6];
519 u8 *val_p;
520 __be32 val_be;
521
522 if (len > 4)
523 return -EINVAL;
524
525 buf[0] = reg >> 8;
526 buf[1] = reg & 0xff;
527
528 val_be = cpu_to_be32(val);
529 val_p = (u8 *)&val_be;
530 buf_i = 2;
531 val_i = 4 - len;
532
533 while (val_i < 4)
534 buf[buf_i++] = val_p[val_i++];
535
536 if (i2c_master_send(client, buf, len + 2) != len + 2)
537 return -EIO;
538 return 0;
539 }
540
sc3336_write_array(struct i2c_client * client,const struct regval * regs)541 static int sc3336_write_array(struct i2c_client *client,
542 const struct regval *regs)
543 {
544 u32 i;
545 int ret = 0;
546
547 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
548 ret = sc3336_write_reg(client, regs[i].addr,
549 SC3336_REG_VALUE_08BIT, regs[i].val);
550
551 return ret;
552 }
553
554 /* Read registers up to 4 at a time */
sc3336_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)555 static int sc3336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
556 u32 *val)
557 {
558 struct i2c_msg msgs[2];
559 u8 *data_be_p;
560 __be32 data_be = 0;
561 __be16 reg_addr_be = cpu_to_be16(reg);
562 int ret;
563
564 if (len > 4 || !len)
565 return -EINVAL;
566
567 data_be_p = (u8 *)&data_be;
568 /* Write register address */
569 msgs[0].addr = client->addr;
570 msgs[0].flags = 0;
571 msgs[0].len = 2;
572 msgs[0].buf = (u8 *)®_addr_be;
573
574 /* Read data from register */
575 msgs[1].addr = client->addr;
576 msgs[1].flags = I2C_M_RD;
577 msgs[1].len = len;
578 msgs[1].buf = &data_be_p[4 - len];
579
580 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
581 if (ret != ARRAY_SIZE(msgs))
582 return -EIO;
583
584 *val = be32_to_cpu(data_be);
585
586 return 0;
587 }
588
sc3336_set_gain_reg(struct sc3336 * sc3336,u32 gain)589 static int sc3336_set_gain_reg(struct sc3336 *sc3336, u32 gain)
590 {
591 struct i2c_client *client = sc3336->client;
592 u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
593 int ret = 0, gain_factor;
594
595 if (gain < 128)
596 gain = 128;
597 else if (gain > SC3336_GAIN_MAX)
598 gain = SC3336_GAIN_MAX;
599
600 gain_factor = gain * 1000 / 128;
601 if (gain_factor < 1520) {
602 coarse_again = 0x00;
603 coarse_dgain = 0x00;
604 fine_dgain = gain_factor * 128 / 1000;
605 } else if (gain_factor < 3040) {
606 coarse_again = 0x40;
607 coarse_dgain = 0x00;
608 fine_dgain = gain_factor * 128 / 1520;
609 } else if (gain_factor < 6080) {
610 coarse_again = 0x48;
611 coarse_dgain = 0x00;
612 fine_dgain = gain_factor * 128 / 3040;
613 } else if (gain_factor < 12160) {
614 coarse_again = 0x49;
615 coarse_dgain = 0x00;
616 fine_dgain = gain_factor * 128 / 6080;
617 } else if (gain_factor < 24320) {
618 coarse_again = 0x4b;
619 coarse_dgain = 0x00;
620 fine_dgain = gain_factor * 128 / 12160;
621 } else if (gain_factor < 48640) {
622 coarse_again = 0x4f;
623 coarse_dgain = 0x00;
624 fine_dgain = gain_factor * 128 / 24320;
625 } else if (gain_factor < 48640 * 2) {
626 //open dgain begin max digital gain 4X
627 coarse_again = 0x5f;
628 coarse_dgain = 0x00;
629 fine_dgain = gain_factor * 128 / 48640;
630 } else if (gain_factor < 48640 * 4) {
631 coarse_again = 0x5f;
632 coarse_dgain = 0x01;
633 fine_dgain = gain_factor * 128 / 48640 / 2;
634 } else if (gain_factor < 48640 * 8) {
635 coarse_again = 0x5f;
636 coarse_dgain = 0x03;
637 fine_dgain = gain_factor * 128 / 48640 / 4;
638 } else if (gain_factor < 48640 * 16) {
639 coarse_again = 0x5f;
640 coarse_dgain = 0x07;
641 fine_dgain = gain_factor * 128 / 48640 / 8;
642 }
643 dev_dbg(&client->dev, "c_again: 0x%x, c_dgain: 0x%x, f_dgain: 0x%0x\n",
644 coarse_again, coarse_dgain, fine_dgain);
645
646 ret = sc3336_write_reg(sc3336->client,
647 SC3336_REG_DIG_GAIN,
648 SC3336_REG_VALUE_08BIT,
649 coarse_dgain);
650 ret |= sc3336_write_reg(sc3336->client,
651 SC3336_REG_DIG_FINE_GAIN,
652 SC3336_REG_VALUE_08BIT,
653 fine_dgain);
654 ret |= sc3336_write_reg(sc3336->client,
655 SC3336_REG_ANA_GAIN,
656 SC3336_REG_VALUE_08BIT,
657 coarse_again);
658
659 return ret;
660 }
661
sc3336_get_reso_dist(const struct sc3336_mode * mode,struct v4l2_mbus_framefmt * framefmt)662 static int sc3336_get_reso_dist(const struct sc3336_mode *mode,
663 struct v4l2_mbus_framefmt *framefmt)
664 {
665 return abs(mode->width - framefmt->width) +
666 abs(mode->height - framefmt->height);
667 }
668
669 static const struct sc3336_mode *
sc3336_find_best_fit(struct v4l2_subdev_format * fmt)670 sc3336_find_best_fit(struct v4l2_subdev_format *fmt)
671 {
672 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
673 int dist;
674 int cur_best_fit = 0;
675 int cur_best_fit_dist = -1;
676 unsigned int i;
677
678 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
679 dist = sc3336_get_reso_dist(&supported_modes[i], framefmt);
680 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
681 cur_best_fit_dist = dist;
682 cur_best_fit = i;
683 }
684 }
685
686 return &supported_modes[cur_best_fit];
687 }
688
sc3336_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)689 static int sc3336_set_fmt(struct v4l2_subdev *sd,
690 struct v4l2_subdev_pad_config *cfg,
691 struct v4l2_subdev_format *fmt)
692 {
693 struct sc3336 *sc3336 = to_sc3336(sd);
694 const struct sc3336_mode *mode;
695 s64 h_blank, vblank_def;
696 u64 dst_link_freq = 0;
697 u64 dst_pixel_rate = 0;
698
699 mutex_lock(&sc3336->mutex);
700
701 mode = sc3336_find_best_fit(fmt);
702 fmt->format.code = mode->bus_fmt;
703 fmt->format.width = mode->width;
704 fmt->format.height = mode->height;
705 fmt->format.field = V4L2_FIELD_NONE;
706 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
707 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
708 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
709 #else
710 mutex_unlock(&sc3336->mutex);
711 return -ENOTTY;
712 #endif
713 } else {
714 sc3336->cur_mode = mode;
715 h_blank = mode->hts_def - mode->width;
716 __v4l2_ctrl_modify_range(sc3336->hblank, h_blank,
717 h_blank, 1, h_blank);
718 vblank_def = mode->vts_def - mode->height;
719 __v4l2_ctrl_modify_range(sc3336->vblank, vblank_def,
720 SC3336_VTS_MAX - mode->height,
721 1, vblank_def);
722 dst_link_freq = mode->link_freq_idx;
723 dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
724 SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
725 __v4l2_ctrl_s_ctrl_int64(sc3336->pixel_rate,
726 dst_pixel_rate);
727 __v4l2_ctrl_s_ctrl(sc3336->link_freq,
728 dst_link_freq);
729 sc3336->cur_fps = mode->max_fps;
730 }
731
732 mutex_unlock(&sc3336->mutex);
733
734 return 0;
735 }
736
sc3336_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)737 static int sc3336_get_fmt(struct v4l2_subdev *sd,
738 struct v4l2_subdev_pad_config *cfg,
739 struct v4l2_subdev_format *fmt)
740 {
741 struct sc3336 *sc3336 = to_sc3336(sd);
742 const struct sc3336_mode *mode = sc3336->cur_mode;
743
744 mutex_lock(&sc3336->mutex);
745 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
746 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
747 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
748 #else
749 mutex_unlock(&sc3336->mutex);
750 return -ENOTTY;
751 #endif
752 } else {
753 fmt->format.width = mode->width;
754 fmt->format.height = mode->height;
755 fmt->format.code = mode->bus_fmt;
756 fmt->format.field = V4L2_FIELD_NONE;
757 /* format info: width/height/data type/virctual channel */
758 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
759 fmt->reserved[0] = mode->vc[fmt->pad];
760 else
761 fmt->reserved[0] = mode->vc[PAD0];
762 }
763 mutex_unlock(&sc3336->mutex);
764
765 return 0;
766 }
767
sc3336_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)768 static int sc3336_enum_mbus_code(struct v4l2_subdev *sd,
769 struct v4l2_subdev_pad_config *cfg,
770 struct v4l2_subdev_mbus_code_enum *code)
771 {
772 struct sc3336 *sc3336 = to_sc3336(sd);
773
774 if (code->index != 0)
775 return -EINVAL;
776 code->code = sc3336->cur_mode->bus_fmt;
777
778 return 0;
779 }
780
sc3336_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)781 static int sc3336_enum_frame_sizes(struct v4l2_subdev *sd,
782 struct v4l2_subdev_pad_config *cfg,
783 struct v4l2_subdev_frame_size_enum *fse)
784 {
785 if (fse->index >= ARRAY_SIZE(supported_modes))
786 return -EINVAL;
787
788 if (fse->code != supported_modes[0].bus_fmt)
789 return -EINVAL;
790
791 fse->min_width = supported_modes[fse->index].width;
792 fse->max_width = supported_modes[fse->index].width;
793 fse->max_height = supported_modes[fse->index].height;
794 fse->min_height = supported_modes[fse->index].height;
795
796 return 0;
797 }
798
sc3336_enable_test_pattern(struct sc3336 * sc3336,u32 pattern)799 static int sc3336_enable_test_pattern(struct sc3336 *sc3336, u32 pattern)
800 {
801 u32 val = 0;
802 int ret = 0;
803
804 ret = sc3336_read_reg(sc3336->client, SC3336_REG_TEST_PATTERN,
805 SC3336_REG_VALUE_08BIT, &val);
806 if (pattern)
807 val |= SC3336_TEST_PATTERN_BIT_MASK;
808 else
809 val &= ~SC3336_TEST_PATTERN_BIT_MASK;
810
811 ret |= sc3336_write_reg(sc3336->client, SC3336_REG_TEST_PATTERN,
812 SC3336_REG_VALUE_08BIT, val);
813 return ret;
814 }
815
sc3336_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)816 static int sc3336_g_frame_interval(struct v4l2_subdev *sd,
817 struct v4l2_subdev_frame_interval *fi)
818 {
819 struct sc3336 *sc3336 = to_sc3336(sd);
820 const struct sc3336_mode *mode = sc3336->cur_mode;
821
822 if (sc3336->streaming)
823 fi->interval = sc3336->cur_fps;
824 else
825 fi->interval = mode->max_fps;
826 return 0;
827 }
828
sc3336_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)829 static int sc3336_g_mbus_config(struct v4l2_subdev *sd,
830 unsigned int pad_id,
831 struct v4l2_mbus_config *config)
832 {
833 struct sc3336 *sc3336 = to_sc3336(sd);
834 const struct sc3336_mode *mode = sc3336->cur_mode;
835
836 u32 val = 1 << (SC3336_LANES - 1) |
837 V4L2_MBUS_CSI2_CHANNEL_0 |
838 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
839
840 if (mode->hdr_mode != NO_HDR)
841 val |= V4L2_MBUS_CSI2_CHANNEL_1;
842 if (mode->hdr_mode == HDR_X3)
843 val |= V4L2_MBUS_CSI2_CHANNEL_2;
844
845 config->type = V4L2_MBUS_CSI2_DPHY;
846 config->flags = val;
847
848 return 0;
849 }
850
sc3336_get_module_inf(struct sc3336 * sc3336,struct rkmodule_inf * inf)851 static void sc3336_get_module_inf(struct sc3336 *sc3336,
852 struct rkmodule_inf *inf)
853 {
854 memset(inf, 0, sizeof(*inf));
855 strscpy(inf->base.sensor, SC3336_NAME, sizeof(inf->base.sensor));
856 strscpy(inf->base.module, sc3336->module_name,
857 sizeof(inf->base.module));
858 strscpy(inf->base.lens, sc3336->len_name, sizeof(inf->base.lens));
859 }
860
sc3336_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)861 static long sc3336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
862 {
863 struct sc3336 *sc3336 = to_sc3336(sd);
864 struct rkmodule_hdr_cfg *hdr;
865 u32 i, h, w;
866 long ret = 0;
867 u32 stream = 0;
868
869 switch (cmd) {
870 case RKMODULE_GET_MODULE_INFO:
871 sc3336_get_module_inf(sc3336, (struct rkmodule_inf *)arg);
872 break;
873 case RKMODULE_GET_HDR_CFG:
874 hdr = (struct rkmodule_hdr_cfg *)arg;
875 hdr->esp.mode = HDR_NORMAL_VC;
876 hdr->hdr_mode = sc3336->cur_mode->hdr_mode;
877 break;
878 case RKMODULE_SET_HDR_CFG:
879 hdr = (struct rkmodule_hdr_cfg *)arg;
880 w = sc3336->cur_mode->width;
881 h = sc3336->cur_mode->height;
882 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
883 if (w == supported_modes[i].width &&
884 h == supported_modes[i].height &&
885 supported_modes[i].hdr_mode == hdr->hdr_mode) {
886 sc3336->cur_mode = &supported_modes[i];
887 break;
888 }
889 }
890 if (i == ARRAY_SIZE(supported_modes)) {
891 dev_err(&sc3336->client->dev,
892 "not find hdr mode:%d %dx%d config\n",
893 hdr->hdr_mode, w, h);
894 ret = -EINVAL;
895 } else {
896 w = sc3336->cur_mode->hts_def - sc3336->cur_mode->width;
897 h = sc3336->cur_mode->vts_def - sc3336->cur_mode->height;
898 __v4l2_ctrl_modify_range(sc3336->hblank, w, w, 1, w);
899 __v4l2_ctrl_modify_range(sc3336->vblank, h,
900 SC3336_VTS_MAX - sc3336->cur_mode->height, 1, h);
901 sc3336->cur_fps = sc3336->cur_mode->max_fps;
902 }
903 break;
904 case PREISP_CMD_SET_HDRAE_EXP:
905 break;
906 case RKMODULE_SET_QUICK_STREAM:
907
908 stream = *((u32 *)arg);
909
910 if (stream)
911 ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
912 SC3336_REG_VALUE_08BIT, SC3336_MODE_STREAMING);
913 else
914 ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
915 SC3336_REG_VALUE_08BIT, SC3336_MODE_SW_STANDBY);
916 break;
917 default:
918 ret = -ENOIOCTLCMD;
919 break;
920 }
921
922 return ret;
923 }
924
925 #ifdef CONFIG_COMPAT
sc3336_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)926 static long sc3336_compat_ioctl32(struct v4l2_subdev *sd,
927 unsigned int cmd, unsigned long arg)
928 {
929 void __user *up = compat_ptr(arg);
930 struct rkmodule_inf *inf;
931 struct rkmodule_hdr_cfg *hdr;
932 struct preisp_hdrae_exp_s *hdrae;
933 long ret;
934 u32 stream = 0;
935
936 switch (cmd) {
937 case RKMODULE_GET_MODULE_INFO:
938 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
939 if (!inf) {
940 ret = -ENOMEM;
941 return ret;
942 }
943
944 ret = sc3336_ioctl(sd, cmd, inf);
945 if (!ret) {
946 if (copy_to_user(up, inf, sizeof(*inf)))
947 ret = -EFAULT;
948 }
949 kfree(inf);
950 break;
951 case RKMODULE_GET_HDR_CFG:
952 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
953 if (!hdr) {
954 ret = -ENOMEM;
955 return ret;
956 }
957
958 ret = sc3336_ioctl(sd, cmd, hdr);
959 if (!ret) {
960 if (copy_to_user(up, hdr, sizeof(*hdr)))
961 ret = -EFAULT;
962 }
963 kfree(hdr);
964 break;
965 case RKMODULE_SET_HDR_CFG:
966 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
967 if (!hdr) {
968 ret = -ENOMEM;
969 return ret;
970 }
971
972 ret = copy_from_user(hdr, up, sizeof(*hdr));
973 if (!ret)
974 ret = sc3336_ioctl(sd, cmd, hdr);
975 else
976 ret = -EFAULT;
977 kfree(hdr);
978 break;
979 case PREISP_CMD_SET_HDRAE_EXP:
980 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
981 if (!hdrae) {
982 ret = -ENOMEM;
983 return ret;
984 }
985
986 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
987 if (!ret)
988 ret = sc3336_ioctl(sd, cmd, hdrae);
989 else
990 ret = -EFAULT;
991 kfree(hdrae);
992 break;
993 case RKMODULE_SET_QUICK_STREAM:
994 ret = copy_from_user(&stream, up, sizeof(u32));
995 if (!ret)
996 ret = sc3336_ioctl(sd, cmd, &stream);
997 else
998 ret = -EFAULT;
999 break;
1000 default:
1001 ret = -ENOIOCTLCMD;
1002 break;
1003 }
1004
1005 return ret;
1006 }
1007 #endif
1008
__sc3336_start_stream(struct sc3336 * sc3336)1009 static int __sc3336_start_stream(struct sc3336 *sc3336)
1010 {
1011 int ret;
1012
1013 if (!sc3336->is_thunderboot) {
1014 ret = sc3336_write_array(sc3336->client, sc3336->cur_mode->reg_list);
1015 if (ret)
1016 return ret;
1017 /* In case these controls are set before streaming */
1018 ret = __v4l2_ctrl_handler_setup(&sc3336->ctrl_handler);
1019 if (ret)
1020 return ret;
1021 if (sc3336->has_init_exp && sc3336->cur_mode->hdr_mode != NO_HDR) {
1022 ret = sc3336_ioctl(&sc3336->subdev, PREISP_CMD_SET_HDRAE_EXP,
1023 &sc3336->init_hdrae_exp);
1024 if (ret) {
1025 dev_err(&sc3336->client->dev,
1026 "init exp fail in hdr mode\n");
1027 return ret;
1028 }
1029 }
1030 }
1031 ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
1032 SC3336_REG_VALUE_08BIT, SC3336_MODE_STREAMING);
1033 return ret;
1034 }
1035
__sc3336_stop_stream(struct sc3336 * sc3336)1036 static int __sc3336_stop_stream(struct sc3336 *sc3336)
1037 {
1038 sc3336->has_init_exp = false;
1039 if (sc3336->is_thunderboot)
1040 sc3336->is_first_streamoff = true;
1041 return sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
1042 SC3336_REG_VALUE_08BIT, SC3336_MODE_SW_STANDBY);
1043 }
1044
1045 static int __sc3336_power_on(struct sc3336 *sc3336);
sc3336_s_stream(struct v4l2_subdev * sd,int on)1046 static int sc3336_s_stream(struct v4l2_subdev *sd, int on)
1047 {
1048 struct sc3336 *sc3336 = to_sc3336(sd);
1049 struct i2c_client *client = sc3336->client;
1050 int ret = 0;
1051
1052 mutex_lock(&sc3336->mutex);
1053 on = !!on;
1054 if (on == sc3336->streaming)
1055 goto unlock_and_return;
1056 if (on) {
1057 if (sc3336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1058 sc3336->is_thunderboot = false;
1059 __sc3336_power_on(sc3336);
1060 }
1061 ret = pm_runtime_get_sync(&client->dev);
1062 if (ret < 0) {
1063 pm_runtime_put_noidle(&client->dev);
1064 goto unlock_and_return;
1065 }
1066 ret = __sc3336_start_stream(sc3336);
1067 if (ret) {
1068 v4l2_err(sd, "start stream failed while write regs\n");
1069 pm_runtime_put(&client->dev);
1070 goto unlock_and_return;
1071 }
1072 } else {
1073 __sc3336_stop_stream(sc3336);
1074 pm_runtime_put(&client->dev);
1075 }
1076
1077 sc3336->streaming = on;
1078 unlock_and_return:
1079 mutex_unlock(&sc3336->mutex);
1080 return ret;
1081 }
1082
sc3336_s_power(struct v4l2_subdev * sd,int on)1083 static int sc3336_s_power(struct v4l2_subdev *sd, int on)
1084 {
1085 struct sc3336 *sc3336 = to_sc3336(sd);
1086 struct i2c_client *client = sc3336->client;
1087 int ret = 0;
1088
1089 mutex_lock(&sc3336->mutex);
1090
1091 /* If the power state is not modified - no work to do. */
1092 if (sc3336->power_on == !!on)
1093 goto unlock_and_return;
1094
1095 if (on) {
1096 ret = pm_runtime_get_sync(&client->dev);
1097 if (ret < 0) {
1098 pm_runtime_put_noidle(&client->dev);
1099 goto unlock_and_return;
1100 }
1101
1102 if (!sc3336->is_thunderboot) {
1103 ret = sc3336_write_array(sc3336->client, sc3336_global_regs);
1104 if (ret) {
1105 v4l2_err(sd, "could not set init registers\n");
1106 pm_runtime_put_noidle(&client->dev);
1107 goto unlock_and_return;
1108 }
1109 }
1110
1111 sc3336->power_on = true;
1112 } else {
1113 pm_runtime_put(&client->dev);
1114 sc3336->power_on = false;
1115 }
1116
1117 unlock_and_return:
1118 mutex_unlock(&sc3336->mutex);
1119
1120 return ret;
1121 }
1122
1123 /* Calculate the delay in us by clock rate and clock cycles */
sc3336_cal_delay(u32 cycles,struct sc3336 * sc3336)1124 static inline u32 sc3336_cal_delay(u32 cycles, struct sc3336 *sc3336)
1125 {
1126 return DIV_ROUND_UP(cycles, sc3336->cur_mode->xvclk_freq / 1000 / 1000);
1127 }
1128
__sc3336_power_on(struct sc3336 * sc3336)1129 static int __sc3336_power_on(struct sc3336 *sc3336)
1130 {
1131 int ret;
1132 u32 delay_us;
1133 struct device *dev = &sc3336->client->dev;
1134
1135 if (!IS_ERR_OR_NULL(sc3336->pins_default)) {
1136 ret = pinctrl_select_state(sc3336->pinctrl,
1137 sc3336->pins_default);
1138 if (ret < 0)
1139 dev_err(dev, "could not set pins\n");
1140 }
1141 ret = clk_set_rate(sc3336->xvclk, sc3336->cur_mode->xvclk_freq);
1142 if (ret < 0)
1143 dev_warn(dev, "Failed to set xvclk rate (%dHz)\n", sc3336->cur_mode->xvclk_freq);
1144 if (clk_get_rate(sc3336->xvclk) != sc3336->cur_mode->xvclk_freq)
1145 dev_warn(dev, "xvclk mismatched, modes are based on %dHz\n",
1146 sc3336->cur_mode->xvclk_freq);
1147 ret = clk_prepare_enable(sc3336->xvclk);
1148 if (ret < 0) {
1149 dev_err(dev, "Failed to enable xvclk\n");
1150 return ret;
1151 }
1152
1153 if (sc3336->is_thunderboot)
1154 return 0;
1155
1156 if (!IS_ERR(sc3336->reset_gpio))
1157 gpiod_set_value_cansleep(sc3336->reset_gpio, 0);
1158
1159 ret = regulator_bulk_enable(SC3336_NUM_SUPPLIES, sc3336->supplies);
1160 if (ret < 0) {
1161 dev_err(dev, "Failed to enable regulators\n");
1162 goto disable_clk;
1163 }
1164
1165 if (!IS_ERR(sc3336->reset_gpio))
1166 gpiod_set_value_cansleep(sc3336->reset_gpio, 1);
1167
1168 usleep_range(500, 1000);
1169
1170 if (!IS_ERR(sc3336->pwdn_gpio))
1171 gpiod_set_value_cansleep(sc3336->pwdn_gpio, 1);
1172
1173 if (!IS_ERR(sc3336->reset_gpio))
1174 usleep_range(6000, 8000);
1175 else
1176 usleep_range(12000, 16000);
1177
1178 /* 8192 cycles prior to first SCCB transaction */
1179 delay_us = sc3336_cal_delay(8192, sc3336);
1180 usleep_range(delay_us, delay_us * 2);
1181
1182 return 0;
1183
1184 disable_clk:
1185 clk_disable_unprepare(sc3336->xvclk);
1186
1187 return ret;
1188 }
1189
__sc3336_power_off(struct sc3336 * sc3336)1190 static void __sc3336_power_off(struct sc3336 *sc3336)
1191 {
1192 int ret;
1193 struct device *dev = &sc3336->client->dev;
1194
1195 clk_disable_unprepare(sc3336->xvclk);
1196 if (sc3336->is_thunderboot) {
1197 if (sc3336->is_first_streamoff) {
1198 sc3336->is_thunderboot = false;
1199 sc3336->is_first_streamoff = false;
1200 } else {
1201 return;
1202 }
1203 }
1204
1205 if (!IS_ERR(sc3336->pwdn_gpio))
1206 gpiod_set_value_cansleep(sc3336->pwdn_gpio, 0);
1207 clk_disable_unprepare(sc3336->xvclk);
1208 if (!IS_ERR(sc3336->reset_gpio))
1209 gpiod_set_value_cansleep(sc3336->reset_gpio, 0);
1210 if (!IS_ERR_OR_NULL(sc3336->pins_sleep)) {
1211 ret = pinctrl_select_state(sc3336->pinctrl,
1212 sc3336->pins_sleep);
1213 if (ret < 0)
1214 dev_dbg(dev, "could not set pins\n");
1215 }
1216 regulator_bulk_disable(SC3336_NUM_SUPPLIES, sc3336->supplies);
1217 }
1218
sc3336_runtime_resume(struct device * dev)1219 static int __maybe_unused sc3336_runtime_resume(struct device *dev)
1220 {
1221 struct i2c_client *client = to_i2c_client(dev);
1222 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1223 struct sc3336 *sc3336 = to_sc3336(sd);
1224
1225 return __sc3336_power_on(sc3336);
1226 }
1227
sc3336_runtime_suspend(struct device * dev)1228 static int __maybe_unused sc3336_runtime_suspend(struct device *dev)
1229 {
1230 struct i2c_client *client = to_i2c_client(dev);
1231 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1232 struct sc3336 *sc3336 = to_sc3336(sd);
1233
1234 __sc3336_power_off(sc3336);
1235
1236 return 0;
1237 }
1238
1239 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc3336_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1240 static int sc3336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1241 {
1242 struct sc3336 *sc3336 = to_sc3336(sd);
1243 struct v4l2_mbus_framefmt *try_fmt =
1244 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1245 const struct sc3336_mode *def_mode = &supported_modes[0];
1246
1247 mutex_lock(&sc3336->mutex);
1248 /* Initialize try_fmt */
1249 try_fmt->width = def_mode->width;
1250 try_fmt->height = def_mode->height;
1251 try_fmt->code = def_mode->bus_fmt;
1252 try_fmt->field = V4L2_FIELD_NONE;
1253
1254 mutex_unlock(&sc3336->mutex);
1255 /* No crop or compose */
1256
1257 return 0;
1258 }
1259 #endif
1260
sc3336_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1261 static int sc3336_enum_frame_interval(struct v4l2_subdev *sd,
1262 struct v4l2_subdev_pad_config *cfg,
1263 struct v4l2_subdev_frame_interval_enum *fie)
1264 {
1265 if (fie->index >= ARRAY_SIZE(supported_modes))
1266 return -EINVAL;
1267
1268 fie->code = supported_modes[fie->index].bus_fmt;
1269 fie->width = supported_modes[fie->index].width;
1270 fie->height = supported_modes[fie->index].height;
1271 fie->interval = supported_modes[fie->index].max_fps;
1272 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1273 return 0;
1274 }
1275
1276 static const struct dev_pm_ops sc3336_pm_ops = {
1277 SET_RUNTIME_PM_OPS(sc3336_runtime_suspend,
1278 sc3336_runtime_resume, NULL)
1279 };
1280
1281 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1282 static const struct v4l2_subdev_internal_ops sc3336_internal_ops = {
1283 .open = sc3336_open,
1284 };
1285 #endif
1286
1287 static const struct v4l2_subdev_core_ops sc3336_core_ops = {
1288 .s_power = sc3336_s_power,
1289 .ioctl = sc3336_ioctl,
1290 #ifdef CONFIG_COMPAT
1291 .compat_ioctl32 = sc3336_compat_ioctl32,
1292 #endif
1293 };
1294
1295 static const struct v4l2_subdev_video_ops sc3336_video_ops = {
1296 .s_stream = sc3336_s_stream,
1297 .g_frame_interval = sc3336_g_frame_interval,
1298 };
1299
1300 static const struct v4l2_subdev_pad_ops sc3336_pad_ops = {
1301 .enum_mbus_code = sc3336_enum_mbus_code,
1302 .enum_frame_size = sc3336_enum_frame_sizes,
1303 .enum_frame_interval = sc3336_enum_frame_interval,
1304 .get_fmt = sc3336_get_fmt,
1305 .set_fmt = sc3336_set_fmt,
1306 .get_mbus_config = sc3336_g_mbus_config,
1307 };
1308
1309 static const struct v4l2_subdev_ops sc3336_subdev_ops = {
1310 .core = &sc3336_core_ops,
1311 .video = &sc3336_video_ops,
1312 .pad = &sc3336_pad_ops,
1313 };
1314
sc3336_modify_fps_info(struct sc3336 * sc3336)1315 static void sc3336_modify_fps_info(struct sc3336 *sc3336)
1316 {
1317 const struct sc3336_mode *mode = sc3336->cur_mode;
1318
1319 sc3336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1320 sc3336->cur_vts;
1321 }
1322
sc3336_set_ctrl(struct v4l2_ctrl * ctrl)1323 static int sc3336_set_ctrl(struct v4l2_ctrl *ctrl)
1324 {
1325 struct sc3336 *sc3336 = container_of(ctrl->handler,
1326 struct sc3336, ctrl_handler);
1327 struct i2c_client *client = sc3336->client;
1328 s64 max;
1329 int ret = 0;
1330 u32 val = 0;
1331
1332 /* Propagate change of current control to all related controls */
1333 switch (ctrl->id) {
1334 case V4L2_CID_VBLANK:
1335 /* Update max exposure while meeting expected vblanking */
1336 max = sc3336->cur_mode->height + ctrl->val - 8;
1337 __v4l2_ctrl_modify_range(sc3336->exposure,
1338 sc3336->exposure->minimum, max,
1339 sc3336->exposure->step,
1340 sc3336->exposure->default_value);
1341 break;
1342 }
1343
1344 if (!pm_runtime_get_if_in_use(&client->dev))
1345 return 0;
1346
1347 switch (ctrl->id) {
1348 case V4L2_CID_EXPOSURE:
1349 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1350 if (sc3336->cur_mode->hdr_mode == NO_HDR) {
1351 val = ctrl->val;
1352 /* 4 least significant bits of expsoure are fractional part */
1353 ret = sc3336_write_reg(sc3336->client,
1354 SC3336_REG_EXPOSURE_H,
1355 SC3336_REG_VALUE_08BIT,
1356 SC3336_FETCH_EXP_H(val));
1357 ret |= sc3336_write_reg(sc3336->client,
1358 SC3336_REG_EXPOSURE_M,
1359 SC3336_REG_VALUE_08BIT,
1360 SC3336_FETCH_EXP_M(val));
1361 ret |= sc3336_write_reg(sc3336->client,
1362 SC3336_REG_EXPOSURE_L,
1363 SC3336_REG_VALUE_08BIT,
1364 SC3336_FETCH_EXP_L(val));
1365 }
1366 break;
1367 case V4L2_CID_ANALOGUE_GAIN:
1368 dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1369 if (sc3336->cur_mode->hdr_mode == NO_HDR)
1370 ret = sc3336_set_gain_reg(sc3336, ctrl->val);
1371 break;
1372 case V4L2_CID_VBLANK:
1373 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1374 ret = sc3336_write_reg(sc3336->client,
1375 SC3336_REG_VTS_H,
1376 SC3336_REG_VALUE_08BIT,
1377 (ctrl->val + sc3336->cur_mode->height)
1378 >> 8);
1379 ret |= sc3336_write_reg(sc3336->client,
1380 SC3336_REG_VTS_L,
1381 SC3336_REG_VALUE_08BIT,
1382 (ctrl->val + sc3336->cur_mode->height)
1383 & 0xff);
1384 sc3336->cur_vts = ctrl->val + sc3336->cur_mode->height;
1385 sc3336_modify_fps_info(sc3336);
1386 break;
1387 case V4L2_CID_TEST_PATTERN:
1388 ret = sc3336_enable_test_pattern(sc3336, ctrl->val);
1389 break;
1390 case V4L2_CID_HFLIP:
1391 ret = sc3336_read_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
1392 SC3336_REG_VALUE_08BIT, &val);
1393 ret |= sc3336_write_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
1394 SC3336_REG_VALUE_08BIT,
1395 SC3336_FETCH_MIRROR(val, ctrl->val));
1396 break;
1397 case V4L2_CID_VFLIP:
1398 ret = sc3336_read_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
1399 SC3336_REG_VALUE_08BIT, &val);
1400 ret |= sc3336_write_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
1401 SC3336_REG_VALUE_08BIT,
1402 SC3336_FETCH_FLIP(val, ctrl->val));
1403 break;
1404 default:
1405 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1406 __func__, ctrl->id, ctrl->val);
1407 break;
1408 }
1409
1410 pm_runtime_put(&client->dev);
1411
1412 return ret;
1413 }
1414
1415 static const struct v4l2_ctrl_ops sc3336_ctrl_ops = {
1416 .s_ctrl = sc3336_set_ctrl,
1417 };
1418
sc3336_initialize_controls(struct sc3336 * sc3336)1419 static int sc3336_initialize_controls(struct sc3336 *sc3336)
1420 {
1421 const struct sc3336_mode *mode;
1422 struct v4l2_ctrl_handler *handler;
1423 s64 exposure_max, vblank_def;
1424 u32 h_blank;
1425 int ret;
1426 u64 dst_link_freq = 0;
1427 u64 dst_pixel_rate = 0;
1428
1429 handler = &sc3336->ctrl_handler;
1430 mode = sc3336->cur_mode;
1431 ret = v4l2_ctrl_handler_init(handler, 9);
1432 if (ret)
1433 return ret;
1434 handler->lock = &sc3336->mutex;
1435
1436 sc3336->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1437 V4L2_CID_LINK_FREQ,
1438 ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
1439 if (sc3336->link_freq)
1440 sc3336->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1441
1442 dst_link_freq = mode->link_freq_idx;
1443 dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1444 SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
1445 sc3336->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1446 0, PIXEL_RATE_WITH_255M_10BIT, 1, dst_pixel_rate);
1447
1448 __v4l2_ctrl_s_ctrl(sc3336->link_freq, dst_link_freq);
1449
1450 h_blank = mode->hts_def - mode->width;
1451 sc3336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1452 h_blank, h_blank, 1, h_blank);
1453 if (sc3336->hblank)
1454 sc3336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1455 vblank_def = mode->vts_def - mode->height;
1456 sc3336->vblank = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
1457 V4L2_CID_VBLANK, vblank_def,
1458 SC3336_VTS_MAX - mode->height,
1459 1, vblank_def);
1460 exposure_max = mode->vts_def - 8;
1461 sc3336->exposure = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
1462 V4L2_CID_EXPOSURE, SC3336_EXPOSURE_MIN,
1463 exposure_max, SC3336_EXPOSURE_STEP,
1464 mode->exp_def);
1465 sc3336->anal_gain = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
1466 V4L2_CID_ANALOGUE_GAIN, SC3336_GAIN_MIN,
1467 SC3336_GAIN_MAX, SC3336_GAIN_STEP,
1468 SC3336_GAIN_DEFAULT);
1469 sc3336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1470 &sc3336_ctrl_ops,
1471 V4L2_CID_TEST_PATTERN,
1472 ARRAY_SIZE(sc3336_test_pattern_menu) - 1,
1473 0, 0, sc3336_test_pattern_menu);
1474 v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
1475 V4L2_CID_HFLIP, 0, 1, 1, 0);
1476 v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
1477 V4L2_CID_VFLIP, 0, 1, 1, 0);
1478 if (handler->error) {
1479 ret = handler->error;
1480 dev_err(&sc3336->client->dev,
1481 "Failed to init controls(%d)\n", ret);
1482 goto err_free_handler;
1483 }
1484
1485 sc3336->subdev.ctrl_handler = handler;
1486 sc3336->has_init_exp = false;
1487 sc3336->cur_fps = mode->max_fps;
1488
1489 return 0;
1490
1491 err_free_handler:
1492 v4l2_ctrl_handler_free(handler);
1493
1494 return ret;
1495 }
1496
sc3336_check_sensor_id(struct sc3336 * sc3336,struct i2c_client * client)1497 static int sc3336_check_sensor_id(struct sc3336 *sc3336,
1498 struct i2c_client *client)
1499 {
1500 struct device *dev = &sc3336->client->dev;
1501 u32 id = 0;
1502 int ret;
1503
1504 if (sc3336->is_thunderboot) {
1505 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1506 return 0;
1507 }
1508
1509 ret = sc3336_read_reg(client, SC3336_REG_CHIP_ID,
1510 SC3336_REG_VALUE_16BIT, &id);
1511 if (id != CHIP_ID) {
1512 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1513 return -ENODEV;
1514 }
1515
1516 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1517
1518 return 0;
1519 }
1520
sc3336_configure_regulators(struct sc3336 * sc3336)1521 static int sc3336_configure_regulators(struct sc3336 *sc3336)
1522 {
1523 unsigned int i;
1524
1525 for (i = 0; i < SC3336_NUM_SUPPLIES; i++)
1526 sc3336->supplies[i].supply = sc3336_supply_names[i];
1527
1528 return devm_regulator_bulk_get(&sc3336->client->dev,
1529 SC3336_NUM_SUPPLIES,
1530 sc3336->supplies);
1531 }
1532
sc3336_probe(struct i2c_client * client,const struct i2c_device_id * id)1533 static int sc3336_probe(struct i2c_client *client,
1534 const struct i2c_device_id *id)
1535 {
1536 struct device *dev = &client->dev;
1537 struct device_node *node = dev->of_node;
1538 struct sc3336 *sc3336;
1539 struct v4l2_subdev *sd;
1540 char facing[2];
1541 int ret;
1542 int i, hdr_mode = 0;
1543
1544 dev_info(dev, "driver version: %02x.%02x.%02x",
1545 DRIVER_VERSION >> 16,
1546 (DRIVER_VERSION & 0xff00) >> 8,
1547 DRIVER_VERSION & 0x00ff);
1548
1549 sc3336 = devm_kzalloc(dev, sizeof(*sc3336), GFP_KERNEL);
1550 if (!sc3336)
1551 return -ENOMEM;
1552
1553 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1554 &sc3336->module_index);
1555 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1556 &sc3336->module_facing);
1557 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1558 &sc3336->module_name);
1559 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1560 &sc3336->len_name);
1561 if (ret) {
1562 dev_err(dev, "could not get module information!\n");
1563 return -EINVAL;
1564 }
1565
1566 sc3336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1567
1568 sc3336->client = client;
1569 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1570 if (hdr_mode == supported_modes[i].hdr_mode) {
1571 sc3336->cur_mode = &supported_modes[i];
1572 break;
1573 }
1574 }
1575 if (i == ARRAY_SIZE(supported_modes))
1576 sc3336->cur_mode = &supported_modes[0];
1577
1578 sc3336->xvclk = devm_clk_get(dev, "xvclk");
1579 if (IS_ERR(sc3336->xvclk)) {
1580 dev_err(dev, "Failed to get xvclk\n");
1581 return -EINVAL;
1582 }
1583
1584 if (!sc3336->is_thunderboot)
1585 sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1586 else
1587 sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1588 if (IS_ERR(sc3336->reset_gpio))
1589 dev_warn(dev, "Failed to get reset-gpios\n");
1590
1591 if (!sc3336->is_thunderboot)
1592 sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1593 else
1594 sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1595 if (IS_ERR(sc3336->pwdn_gpio))
1596 dev_warn(dev, "Failed to get pwdn-gpios\n");
1597
1598 sc3336->pinctrl = devm_pinctrl_get(dev);
1599 if (!IS_ERR(sc3336->pinctrl)) {
1600 sc3336->pins_default =
1601 pinctrl_lookup_state(sc3336->pinctrl,
1602 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1603 if (IS_ERR(sc3336->pins_default))
1604 dev_err(dev, "could not get default pinstate\n");
1605
1606 sc3336->pins_sleep =
1607 pinctrl_lookup_state(sc3336->pinctrl,
1608 OF_CAMERA_PINCTRL_STATE_SLEEP);
1609 if (IS_ERR(sc3336->pins_sleep))
1610 dev_err(dev, "could not get sleep pinstate\n");
1611 } else {
1612 dev_err(dev, "no pinctrl\n");
1613 }
1614
1615 ret = sc3336_configure_regulators(sc3336);
1616 if (ret) {
1617 dev_err(dev, "Failed to get power regulators\n");
1618 return ret;
1619 }
1620
1621 mutex_init(&sc3336->mutex);
1622
1623 sd = &sc3336->subdev;
1624 v4l2_i2c_subdev_init(sd, client, &sc3336_subdev_ops);
1625 ret = sc3336_initialize_controls(sc3336);
1626 if (ret)
1627 goto err_destroy_mutex;
1628
1629 ret = __sc3336_power_on(sc3336);
1630 if (ret)
1631 goto err_free_handler;
1632
1633 ret = sc3336_check_sensor_id(sc3336, client);
1634 if (ret)
1635 goto err_power_off;
1636
1637 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1638 sd->internal_ops = &sc3336_internal_ops;
1639 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1640 V4L2_SUBDEV_FL_HAS_EVENTS;
1641 #endif
1642 #if defined(CONFIG_MEDIA_CONTROLLER)
1643 sc3336->pad.flags = MEDIA_PAD_FL_SOURCE;
1644 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1645 ret = media_entity_pads_init(&sd->entity, 1, &sc3336->pad);
1646 if (ret < 0)
1647 goto err_power_off;
1648 #endif
1649
1650 memset(facing, 0, sizeof(facing));
1651 if (strcmp(sc3336->module_facing, "back") == 0)
1652 facing[0] = 'b';
1653 else
1654 facing[0] = 'f';
1655
1656 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1657 sc3336->module_index, facing,
1658 SC3336_NAME, dev_name(sd->dev));
1659 ret = v4l2_async_register_subdev_sensor_common(sd);
1660 if (ret) {
1661 dev_err(dev, "v4l2 async register subdev failed\n");
1662 goto err_clean_entity;
1663 }
1664
1665 pm_runtime_set_active(dev);
1666 pm_runtime_enable(dev);
1667 pm_runtime_idle(dev);
1668
1669 return 0;
1670
1671 err_clean_entity:
1672 #if defined(CONFIG_MEDIA_CONTROLLER)
1673 media_entity_cleanup(&sd->entity);
1674 #endif
1675 err_power_off:
1676 __sc3336_power_off(sc3336);
1677 err_free_handler:
1678 v4l2_ctrl_handler_free(&sc3336->ctrl_handler);
1679 err_destroy_mutex:
1680 mutex_destroy(&sc3336->mutex);
1681
1682 return ret;
1683 }
1684
sc3336_remove(struct i2c_client * client)1685 static int sc3336_remove(struct i2c_client *client)
1686 {
1687 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1688 struct sc3336 *sc3336 = to_sc3336(sd);
1689
1690 v4l2_async_unregister_subdev(sd);
1691 #if defined(CONFIG_MEDIA_CONTROLLER)
1692 media_entity_cleanup(&sd->entity);
1693 #endif
1694 v4l2_ctrl_handler_free(&sc3336->ctrl_handler);
1695 mutex_destroy(&sc3336->mutex);
1696
1697 pm_runtime_disable(&client->dev);
1698 if (!pm_runtime_status_suspended(&client->dev))
1699 __sc3336_power_off(sc3336);
1700 pm_runtime_set_suspended(&client->dev);
1701
1702 return 0;
1703 }
1704
1705 #if IS_ENABLED(CONFIG_OF)
1706 static const struct of_device_id sc3336_of_match[] = {
1707 { .compatible = "smartsens,sc3336" },
1708 {},
1709 };
1710 MODULE_DEVICE_TABLE(of, sc3336_of_match);
1711 #endif
1712
1713 static const struct i2c_device_id sc3336_match_id[] = {
1714 { "smartsens,sc3336", 0 },
1715 { },
1716 };
1717
1718 static struct i2c_driver sc3336_i2c_driver = {
1719 .driver = {
1720 .name = SC3336_NAME,
1721 .pm = &sc3336_pm_ops,
1722 .of_match_table = of_match_ptr(sc3336_of_match),
1723 },
1724 .probe = &sc3336_probe,
1725 .remove = &sc3336_remove,
1726 .id_table = sc3336_match_id,
1727 };
1728
sensor_mod_init(void)1729 static int __init sensor_mod_init(void)
1730 {
1731 return i2c_add_driver(&sc3336_i2c_driver);
1732 }
1733
sensor_mod_exit(void)1734 static void __exit sensor_mod_exit(void)
1735 {
1736 i2c_del_driver(&sc3336_i2c_driver);
1737 }
1738
1739 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1740 subsys_initcall(sensor_mod_init);
1741 #else
1742 device_initcall_sync(sensor_mod_init);
1743 #endif
1744 module_exit(sensor_mod_exit);
1745
1746 MODULE_DESCRIPTION("smartsens sc3336 sensor driver");
1747 MODULE_LICENSE("GPL v2");
1748