1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SC301IOT driver
4 *
5 * Copyright (C) 2022 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 */
8
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/sysfs.h>
18 #include <linux/slab.h>
19 #include <linux/version.h>
20 #include <linux/rk-camera-module.h>
21 #include <linux/rk-preisp.h>
22 #include <media/media-entity.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-subdev.h>
26 #include <linux/pinctrl/consumer.h>
27 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
28
29 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
30
31 #ifndef V4L2_CID_DIGITAL_GAIN
32 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
33 #endif
34
35 #define SC301IOT_LANES 2
36 #define SC301IOT_BITS_PER_SAMPLE 10
37 #define SC301IOT_LINK_FREQ_594 540000000// 540Mbps
38
39 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
40 #define PIXEL_RATE_WITH_594M_10BIT (SC301IOT_LINK_FREQ_594 / SC301IOT_BITS_PER_SAMPLE * \
41 2 * SC301IOT_LANES)
42 #define SC301IOT_XVCLK_FREQ 24000000
43
44
45 #define CHIP_ID 0xcc40
46 #define SC301IOT_REG_CHIP_ID 0x3107
47
48 #define SC301IOT_REG_CTRL_MODE 0x0100
49 #define SC301IOT_MODE_SW_STANDBY 0x0
50 #define SC301IOT_MODE_STREAMING BIT(0)
51
52 #define SC301IOT_REG_EXPOSURE_H 0x3e00
53 #define SC301IOT_REG_EXPOSURE_M 0x3e01
54 #define SC301IOT_REG_EXPOSURE_L 0x3e02
55 #define SC301IOT_REG_SEXPOSURE_H 0x3e22
56 #define SC301IOT_REG_SEXPOSURE_M 0x3e04
57 #define SC301IOT_REG_SEXPOSURE_L 0x3e05
58 #define SC301IOT_EXPOSURE_MIN 2
59 #define SC301IOT_EXPOSURE_STEP 1
60 #define SC301IOT_VTS_MIN 0x640
61 #define SC301IOT_VTS_MAX 0x7fff
62
63 #define SC301IOT_REG_DIG_GAIN 0x3e06
64 #define SC301IOT_REG_DIG_FINE_GAIN 0x3e07
65 //#define SC301IOT_REG_ANA_GAIN 0x3e08
66 #define SC301IOT_REG_ANA_GAIN 0x3e09
67 #define SC301IOT_REG_SDIG_GAIN 0x3e10
68 #define SC301IOT_REG_SDIG_FINE_GAIN 0x3e11
69 //#define SC301IOT_REG_SANA_GAIN 0x3e12
70 #define SC301IOT_REG_SANA_GAIN 0x3e13
71 #define SC301IOT_GAIN_MIN 0x0040
72 #define SC301IOT_GAIN_MAX (6426) //(100.416*64)
73 #define SC301IOT_GAIN_STEP 1
74 #define SC301IOT_GAIN_DEFAULT 0x0400
75 #define SC301IOT_LGAIN 0
76 #define SC301IOT_SGAIN 1
77
78 #define SC301IOT_REG_GROUP_HOLD 0x3812
79 #define SC301IOT_GROUP_HOLD_START 0x00
80 #define SC301IOT_GROUP_HOLD_END 0x30
81
82 //#define SC301IOT_REG_HIGH_TEMP_H 0x3974
83 //#define SC301IOT_REG_HIGH_TEMP_L 0x3975
84
85 #define SC301IOT_REG_TEST_PATTERN 0x4501
86 #define SC301IOT_TEST_PATTERN_BIT_MASK BIT(3)
87
88 #define SC301IOT_REG_VTS_H 0x320e
89 #define SC301IOT_REG_VTS_L 0x320f
90
91 #define SC301IOT_FLIP_MIRROR_REG 0x3221
92
93 #define SC301IOT_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
94 #define SC301IOT_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
95 #define SC301IOT_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
96
97 #define SC301IOT_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
98 #define SC301IOT_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
99
100 #define SC301IOT_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
101 #define SC301IOT_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
102
103 #define REG_DELAY 0xFFFE
104 #define REG_NULL 0xFFFF
105
106 #define SC301IOT_REG_VALUE_08BIT 1
107 #define SC301IOT_REG_VALUE_16BIT 2
108 #define SC301IOT_REG_VALUE_24BIT 3
109
110 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
111 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
112 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
113 #define SC301IOT_NAME "SC301IOT"
114
115 static const char * const SC301IOT_supply_names[] = {
116 "avdd", /* Analog power */
117 "dovdd", /* Digital I/O power */
118 "dvdd", /* Digital core power */
119 };
120
121 #define SC301IOT_NUM_SUPPLIES ARRAY_SIZE(SC301IOT_supply_names)
122
123 struct regval {
124 u16 addr;
125 u8 val;
126 };
127
128 struct SC301IOT_mode {
129 u32 bus_fmt;
130 u32 width;
131 u32 height;
132 struct v4l2_fract max_fps;
133 u32 hts_def;
134 u32 vts_def;
135 u32 exp_def;
136 const struct regval *reg_list;
137 u32 hdr_mode;
138 u32 vc[PAD_MAX];
139 };
140
141 struct SC301IOT {
142 struct i2c_client *client;
143 struct clk *xvclk;
144 struct gpio_desc *reset_gpio;
145 struct gpio_desc *pwdn_gpio;
146 struct regulator_bulk_data supplies[SC301IOT_NUM_SUPPLIES];
147
148 struct pinctrl *pinctrl;
149 struct pinctrl_state *pins_default;
150 struct pinctrl_state *pins_sleep;
151
152 struct v4l2_subdev subdev;
153 struct media_pad pad;
154 struct v4l2_ctrl_handler ctrl_handler;
155 struct v4l2_ctrl *exposure;
156 struct v4l2_ctrl *anal_gain;
157 struct v4l2_ctrl *digi_gain;
158 struct v4l2_ctrl *hblank;
159 struct v4l2_ctrl *vblank;
160 struct v4l2_ctrl *test_pattern;
161 struct mutex mutex;
162 struct v4l2_fract cur_fps;
163 bool streaming;
164 bool power_on;
165 const struct SC301IOT_mode *cur_mode;
166 u32 module_index;
167 const char *module_facing;
168 const char *module_name;
169 const char *len_name;
170 u32 cur_vts;
171 bool has_init_exp;
172 struct preisp_hdrae_exp_s init_hdrae_exp;
173 bool is_thunderboot;
174 bool is_first_streamoff;
175 u32 sync_mode;
176 };
177
178 #define to_SC301IOT(sd) container_of(sd, struct SC301IOT, subdev)
179
180 /*
181 * Xclk 24Mhz
182 */
183 static const struct regval SC301IOT_global_regs[] = {
184 {REG_NULL, 0x00},
185 };
186
187 /*
188 * Xclk 24Mhz
189 * max_framerate 30fps
190 * mipi_datarate per lane 540Mbps, 2lane
191 */
192 static const struct regval SC301IOT_linear_10_2048x1536_regs[] = {
193 {0x0103, 0x01},
194 {0x0100, 0x00},
195 {0x36e9, 0x80},
196 {0x37f9, 0x80},
197 {0x301c, 0x78},
198 {0x301f, 0x11},
199 {0x30b8, 0x44},
200 {0x3208, 0x08},
201 {0x3209, 0x00},
202 {0x320a, 0x06},
203 {0x320b, 0x00},
204 {0x320c, 0x04},
205 {0x320d, 0x65},
206 {0x320e, 0x06},
207 {0x320f, 0x40},
208 {0x3214, 0x11},
209 {0x3215, 0x11},
210 // {0x3223, 0xc0},
211 {0x3253, 0x0c},
212 {0x3274, 0x09},
213 {0x3301, 0x08},
214 {0x3306, 0x58},
215 {0x3308, 0x08},
216 {0x330a, 0x00},
217 {0x330b, 0xe0},
218 {0x330e, 0x10},
219 {0x3314, 0x14},
220 {0x331e, 0x55},
221 {0x331f, 0x7d},
222 {0x3333, 0x10},
223 {0x3334, 0x40},
224 {0x335e, 0x06},
225 {0x335f, 0x08},
226 {0x3364, 0x5e},
227 {0x337c, 0x02},
228 {0x337d, 0x0a},
229 {0x3390, 0x01},
230 {0x3391, 0x03},
231 {0x3392, 0x07},
232 {0x3393, 0x08},
233 {0x3394, 0x08},
234 {0x3395, 0x08},
235 {0x3396, 0x08},
236 {0x3397, 0x09},
237 {0x3398, 0x1f},
238 {0x3399, 0x08},
239 {0x339a, 0x0a},
240 {0x339b, 0x40},
241 {0x339c, 0x88},
242 {0x33a2, 0x04},
243 {0x33ad, 0x0c},
244 {0x33b1, 0x80},
245 {0x33b3, 0x30},
246 {0x33f9, 0x68},
247 {0x33fb, 0x80},
248 {0x33fc, 0x48},
249 {0x33fd, 0x5f},
250 {0x349f, 0x03},
251 {0x34a6, 0x48},
252 {0x34a7, 0x5f},
253 {0x34a8, 0x30},
254 {0x34a9, 0x30},
255 {0x34aa, 0x00},
256 {0x34ab, 0xf0},
257 {0x34ac, 0x01},
258 {0x34ad, 0x08},
259 {0x34f8, 0x5f},
260 {0x34f9, 0x10},
261 {0x3630, 0xf0},
262 {0x3631, 0x85},
263 {0x3632, 0x74},
264 {0x3633, 0x22},
265 {0x3637, 0x4d},
266 {0x3638, 0xcb},
267 {0x363a, 0x8b},
268 {0x363c, 0x08},
269 {0x3640, 0x00},
270 {0x3641, 0x38},
271 {0x3670, 0x4e},
272 {0x3674, 0xc0},
273 {0x3675, 0xb0},
274 {0x3676, 0xa0},
275 {0x3677, 0x83},
276 {0x3678, 0x87},
277 {0x3679, 0x8a},
278 {0x367c, 0x49},
279 {0x367d, 0x4f},
280 {0x367e, 0x48},
281 {0x367f, 0x4b},
282 {0x3690, 0x33},
283 {0x3691, 0x33},
284 {0x3692, 0x44},
285 {0x3699, 0x8a},
286 {0x369a, 0xa1},
287 {0x369b, 0xc2},
288 {0x369c, 0x48},
289 {0x369d, 0x4f},
290 {0x36a2, 0x4b},
291 {0x36a3, 0x4f},
292 {0x36ea, 0x09},
293 {0x36eb, 0x0d},
294 {0x36ec, 0x1c},
295 {0x36ed, 0x25},
296 {0x370f, 0x01},
297 {0x3714, 0x00},
298 {0x3722, 0x09},
299 {0x3724, 0x41},
300 {0x3725, 0xc1},
301 {0x3728, 0x00},
302 {0x3771, 0x09},
303 {0x3772, 0x05},
304 {0x3773, 0x05},
305 {0x377a, 0x48},
306 {0x377b, 0x49},
307 {0x37fa, 0x09},
308 {0x37fb, 0x33},
309 {0x37fc, 0x11},
310 {0x37fd, 0x18},
311 {0x3905, 0x8d},
312 {0x391d, 0x08},
313 {0x3922, 0x1a},
314 {0x3926, 0x21},
315 {0x3933, 0x80},
316 {0x3934, 0x0d},
317 {0x3937, 0x6a},
318 {0x3939, 0x00},
319 {0x393a, 0x0e},
320 {0x39dc, 0x02},
321 {0x3e00, 0x00},
322 {0x3e01, 0x63},
323 {0x3e02, 0x80},
324 {0x3e03, 0x0b},
325 {0x3e1b, 0x2a},
326 {0x4407, 0x34},
327 {0x440e, 0x02},
328 {0x5001, 0x40},
329 {0x5007, 0x80},
330 {0x36e9, 0x24},
331 {0x37f9, 0x24},
332 {0x3251, 0x90},
333
334 /* strong signal */
335 {0x3650, 0x33},
336 {0x3651, 0x7f},
337
338 {0x3028, 0x05},
339 {REG_NULL, 0x00},
340 };
341
342 /*
343 * Xclk 24Mhz
344 * max_framerate 30fps
345 * mipi_datarate per lane 1080Mbps, HDR 2lane
346 */
347 static const struct regval SC301IOT_hdr_10_2048x1536_regs[] = {
348 {0x0103, 0x01},
349 {0x0100, 0x00},
350 {0x36e9, 0x80},
351 {0x37f9, 0x80},
352 {0x301c, 0x78},
353 {0x301f, 0x12},
354 {0x30b8, 0x44},
355 {0x3208, 0x08},
356 {0x3209, 0x00},
357 {0x320a, 0x06},
358 {0x320b, 0x00},
359 {0x320c, 0x04},
360 {0x320d, 0x65},
361 {0x320e, 0x0c},
362 {0x320f, 0x80},
363 {0x3214, 0x11},
364 {0x3215, 0x11},
365 // {0x3223, 0xc0},
366 {0x3250, 0xff},
367 {0x3253, 0x0c},
368 {0x3274, 0x09},
369 {0x3281, 0x01},
370 {0x3301, 0x08},
371 {0x3304, 0x80},
372 {0x3306, 0x58},
373 {0x3308, 0x08},
374 {0x3309, 0xa0},
375 {0x330a, 0x00},
376 {0x330b, 0xe0},
377 {0x330e, 0x10},
378 {0x3314, 0x14},
379 {0x331e, 0x71},
380 {0x331f, 0x91},
381 {0x3333, 0x10},
382 {0x3334, 0x40},
383 {0x335e, 0x06},
384 {0x335f, 0x08},
385 {0x3364, 0x5e},
386 {0x337c, 0x02},
387 {0x337d, 0x0a},
388 {0x3390, 0x01},
389 {0x3391, 0x03},
390 {0x3392, 0x07},
391 {0x3393, 0x08},
392 {0x3394, 0x08},
393 {0x3395, 0x08},
394 {0x3396, 0x08},
395 {0x3397, 0x09},
396 {0x3398, 0x1f},
397 {0x3399, 0x08},
398 {0x339a, 0x14},
399 {0x339b, 0x28},
400 {0x339c, 0x78},
401 {0x33a2, 0x04},
402 {0x33ad, 0x0c},
403 {0x33b1, 0x80},
404 {0x33b3, 0x38},
405 {0x33f9, 0x58},
406 {0x33fb, 0x80},
407 {0x33fc, 0x48},
408 {0x33fd, 0x4f},
409 {0x349f, 0x03},
410 {0x34a6, 0x48},
411 {0x34a7, 0x4f},
412 {0x34a8, 0x38},
413 {0x34a9, 0x28},
414 {0x34aa, 0x00},
415 {0x34ab, 0xe0},
416 {0x34ac, 0x01},
417 {0x34ad, 0x08},
418 {0x34f8, 0x5f},
419 {0x34f9, 0x18},
420 {0x3630, 0xf0},
421 {0x3631, 0x85},
422 {0x3632, 0x74},
423 {0x3633, 0x22},
424 {0x3637, 0x4d},
425 {0x3638, 0xcb},
426 {0x363a, 0x8b},
427 {0x363c, 0x08},
428 {0x3641, 0x38},
429 {0x3670, 0x4e},
430 {0x3674, 0xc0},
431 {0x3675, 0xa0},
432 {0x3676, 0x90},
433 {0x3677, 0x83},
434 {0x3678, 0x86},
435 {0x3679, 0x89},
436 {0x367c, 0x48},
437 {0x367d, 0x4f},
438 {0x367e, 0x48},
439 {0x367f, 0x4b},
440 {0x3690, 0x33},
441 {0x3691, 0x44},
442 {0x3692, 0x55},
443 {0x3699, 0x8a},
444 {0x369a, 0xa1},
445 {0x369b, 0xc2},
446 {0x369c, 0x48},
447 {0x369d, 0x4f},
448 {0x36a2, 0x4b},
449 {0x36a3, 0x4f},
450 {0x36ea, 0x09},
451 {0x36eb, 0x0d},
452 {0x36ec, 0x0c},
453 {0x36ed, 0x25},
454 {0x370f, 0x01},
455 {0x3714, 0x00},
456 {0x3722, 0x01},
457 {0x3724, 0x41},
458 {0x3725, 0xc1},
459 {0x3728, 0x00},
460 {0x3771, 0x09},
461 {0x3772, 0x09},
462 {0x3773, 0x05},
463 {0x377a, 0x48},
464 {0x377b, 0x4f},
465 {0x37fa, 0x09},
466 {0x37fb, 0x31},
467 {0x37fc, 0x10},
468 {0x37fd, 0x18},
469 {0x3905, 0x8d},
470 {0x391d, 0x08},
471 {0x3922, 0x1a},
472 {0x3926, 0x21},
473 {0x3933, 0x80},
474 {0x3934, 0x0d},
475 {0x3937, 0x6a},
476 {0x3939, 0x00},
477 {0x393a, 0x0e},
478 {0x39dc, 0x02},
479 {0x3e00, 0x00},
480 {0x3e01, 0xb9},
481 {0x3e02, 0xc0},
482 {0x3e03, 0x0b},
483 {0x3e04, 0x0b},
484 {0x3e05, 0xa0},
485 {0x3e1b, 0x2a},
486 {0x3e23, 0x00},
487 {0x3e24, 0xbf},
488 {0x4407, 0x34},
489 {0x440e, 0x02},
490 {0x4509, 0x10},
491 {0x4816, 0x71},
492 {0x5001, 0x40},
493 {0x5007, 0x80},
494 {0x36e9, 0x24},
495 {0x37f9, 0x24},
496 {0x3251, 0x90},
497
498 /* strong signal */
499 {0x3650, 0x33},
500 {0x3651, 0x7f},
501
502 {0x3028, 0x05},
503 {REG_NULL, 0x00},
504 };
505
506 /*
507 * Xclk 24Mhz
508 * max_framerate 30fps
509 * mipi_datarate per lane 540Mbps, 2lane
510 */
511 static const struct regval SC301IOT_linear_10_1536x1536_regs[] = {
512 {0x0103, 0x01},
513 {0x0100, 0x00},
514 {0x36e9, 0x80},
515 {0x37f9, 0x80},
516 {0x301c, 0x78},
517 {0x301f, 0x11},
518 {0x30b8, 0x44},
519 {0x3208, 0x06},
520 {0x3209, 0x00},
521 {0x320a, 0x06},
522 {0x320b, 0x00},
523 {0x320c, 0x04},
524 {0x320d, 0x65},
525 {0x320e, 0x06},
526 {0x320f, 0x40},
527 {0x3210, 0x01},
528 {0x3214, 0x11},
529 {0x3215, 0x11},
530 // {0x3223, 0xc0},
531 {0x3253, 0x0c},
532 {0x3274, 0x09},
533 {0x3301, 0x08},
534 {0x3306, 0x58},
535 {0x3308, 0x08},
536 {0x330a, 0x00},
537 {0x330b, 0xe0},
538 {0x330e, 0x10},
539 {0x3314, 0x14},
540 {0x331e, 0x55},
541 {0x331f, 0x7d},
542 {0x3333, 0x10},
543 {0x3334, 0x40},
544 {0x335e, 0x06},
545 {0x335f, 0x08},
546 {0x3364, 0x5e},
547 {0x337c, 0x02},
548 {0x337d, 0x0a},
549 {0x3390, 0x01},
550 {0x3391, 0x03},
551 {0x3392, 0x07},
552 {0x3393, 0x08},
553 {0x3394, 0x08},
554 {0x3395, 0x08},
555 {0x3396, 0x08},
556 {0x3397, 0x09},
557 {0x3398, 0x1f},
558 {0x3399, 0x08},
559 {0x339a, 0x0a},
560 {0x339b, 0x40},
561 {0x339c, 0x88},
562 {0x33a2, 0x04},
563 {0x33ad, 0x0c},
564 {0x33b1, 0x80},
565 {0x33b3, 0x30},
566 {0x33f9, 0x68},
567 {0x33fb, 0x80},
568 {0x33fc, 0x48},
569 {0x33fd, 0x5f},
570 {0x349f, 0x03},
571 {0x34a6, 0x48},
572 {0x34a7, 0x5f},
573 {0x34a8, 0x30},
574 {0x34a9, 0x30},
575 {0x34aa, 0x00},
576 {0x34ab, 0xf0},
577 {0x34ac, 0x01},
578 {0x34ad, 0x08},
579 {0x34f8, 0x5f},
580 {0x34f9, 0x10},
581 {0x3630, 0xf0},
582 {0x3631, 0x85},
583 {0x3632, 0x74},
584 {0x3633, 0x22},
585 {0x3637, 0x4d},
586 {0x3638, 0xcb},
587 {0x363a, 0x8b},
588 {0x363c, 0x08},
589 {0x3640, 0x00},
590 {0x3641, 0x38},
591 {0x3670, 0x4e},
592 {0x3674, 0xc0},
593 {0x3675, 0xb0},
594 {0x3676, 0xa0},
595 {0x3677, 0x83},
596 {0x3678, 0x87},
597 {0x3679, 0x8a},
598 {0x367c, 0x49},
599 {0x367d, 0x4f},
600 {0x367e, 0x48},
601 {0x367f, 0x4b},
602 {0x3690, 0x33},
603 {0x3691, 0x33},
604 {0x3692, 0x44},
605 {0x3699, 0x8a},
606 {0x369a, 0xa1},
607 {0x369b, 0xc2},
608 {0x369c, 0x48},
609 {0x369d, 0x4f},
610 {0x36a2, 0x4b},
611 {0x36a3, 0x4f},
612 {0x36ea, 0x09},
613 {0x36eb, 0x0d},
614 {0x36ec, 0x1c},
615 {0x36ed, 0x25},
616 {0x370f, 0x01},
617 {0x3714, 0x00},
618 {0x3722, 0x09},
619 {0x3724, 0x41},
620 {0x3725, 0xc1},
621 {0x3728, 0x00},
622 {0x3771, 0x09},
623 {0x3772, 0x05},
624 {0x3773, 0x05},
625 {0x377a, 0x48},
626 {0x377b, 0x49},
627 {0x37fa, 0x09},
628 {0x37fb, 0x33},
629 {0x37fc, 0x11},
630 {0x37fd, 0x18},
631 {0x3905, 0x8d},
632 {0x391d, 0x08},
633 {0x3922, 0x1a},
634 {0x3926, 0x21},
635 {0x3933, 0x80},
636 {0x3934, 0x0d},
637 {0x3937, 0x6a},
638 {0x3939, 0x00},
639 {0x393a, 0x0e},
640 {0x39dc, 0x02},
641 {0x3e00, 0x00},
642 {0x3e01, 0x63},
643 {0x3e02, 0x80},
644 {0x3e03, 0x0b},
645 {0x3e1b, 0x2a},
646 {0x4407, 0x34},
647 {0x440e, 0x02},
648 {0x5001, 0x40},
649 {0x5007, 0x80},
650 {0x36e9, 0x24},
651 {0x37f9, 0x24},
652 {0x3251, 0x90},
653
654 /* strong signal */
655 {0x3650, 0x33},
656 {0x3651, 0x7f},
657
658 {0x3028, 0x05},
659 {REG_NULL, 0x00},
660 };
661
662 /*
663 * Xclk 24Mhz
664 * max_framerate 30fps
665 * mipi_datarate per lane 1080Mbps, HDR 2lane
666 */
667 static const struct regval SC301IOT_hdr_10_1536x1536_regs[] = {
668 {0x0103, 0x01},
669 {0x0100, 0x00},
670 {0x36e9, 0x80},
671 {0x37f9, 0x80},
672 {0x301c, 0x78},
673 {0x301f, 0x12},
674 {0x30b8, 0x44},
675 {0x3208, 0x06},
676 {0x3209, 0x00},
677 {0x320a, 0x06},
678 {0x320b, 0x00},
679 {0x320c, 0x04},
680 {0x320d, 0x65},
681 {0x320e, 0x0c},
682 {0x320f, 0x80},
683 {0x3210, 0x01},
684 {0x3214, 0x11},
685 {0x3215, 0x11},
686 // {0x3223, 0xc0},
687 {0x3250, 0xff},
688 {0x3253, 0x0c},
689 {0x3274, 0x09},
690 {0x3281, 0x01},
691 {0x3301, 0x08},
692 {0x3304, 0x80},
693 {0x3306, 0x58},
694 {0x3308, 0x08},
695 {0x3309, 0xa0},
696 {0x330a, 0x00},
697 {0x330b, 0xe0},
698 {0x330e, 0x10},
699 {0x3314, 0x14},
700 {0x331e, 0x71},
701 {0x331f, 0x91},
702 {0x3333, 0x10},
703 {0x3334, 0x40},
704 {0x335e, 0x06},
705 {0x335f, 0x08},
706 {0x3364, 0x5e},
707 {0x337c, 0x02},
708 {0x337d, 0x0a},
709 {0x3390, 0x01},
710 {0x3391, 0x03},
711 {0x3392, 0x07},
712 {0x3393, 0x08},
713 {0x3394, 0x08},
714 {0x3395, 0x08},
715 {0x3396, 0x08},
716 {0x3397, 0x09},
717 {0x3398, 0x1f},
718 {0x3399, 0x08},
719 {0x339a, 0x14},
720 {0x339b, 0x28},
721 {0x339c, 0x78},
722 {0x33a2, 0x04},
723 {0x33ad, 0x0c},
724 {0x33b1, 0x80},
725 {0x33b3, 0x38},
726 {0x33f9, 0x58},
727 {0x33fb, 0x80},
728 {0x33fc, 0x48},
729 {0x33fd, 0x4f},
730 {0x349f, 0x03},
731 {0x34a6, 0x48},
732 {0x34a7, 0x4f},
733 {0x34a8, 0x38},
734 {0x34a9, 0x28},
735 {0x34aa, 0x00},
736 {0x34ab, 0xe0},
737 {0x34ac, 0x01},
738 {0x34ad, 0x08},
739 {0x34f8, 0x5f},
740 {0x34f9, 0x18},
741 {0x3630, 0xf0},
742 {0x3631, 0x85},
743 {0x3632, 0x74},
744 {0x3633, 0x22},
745 {0x3637, 0x4d},
746 {0x3638, 0xcb},
747 {0x363a, 0x8b},
748 {0x363c, 0x08},
749 {0x3641, 0x38},
750 {0x3670, 0x4e},
751 {0x3674, 0xc0},
752 {0x3675, 0xa0},
753 {0x3676, 0x90},
754 {0x3677, 0x83},
755 {0x3678, 0x86},
756 {0x3679, 0x89},
757 {0x367c, 0x48},
758 {0x367d, 0x4f},
759 {0x367e, 0x48},
760 {0x367f, 0x4b},
761 {0x3690, 0x33},
762 {0x3691, 0x44},
763 {0x3692, 0x55},
764 {0x3699, 0x8a},
765 {0x369a, 0xa1},
766 {0x369b, 0xc2},
767 {0x369c, 0x48},
768 {0x369d, 0x4f},
769 {0x36a2, 0x4b},
770 {0x36a3, 0x4f},
771 {0x36ea, 0x09},
772 {0x36eb, 0x0d},
773 {0x36ec, 0x0c},
774 {0x36ed, 0x25},
775 {0x370f, 0x01},
776 {0x3714, 0x00},
777 {0x3722, 0x01},
778 {0x3724, 0x41},
779 {0x3725, 0xc1},
780 {0x3728, 0x00},
781 {0x3771, 0x09},
782 {0x3772, 0x09},
783 {0x3773, 0x05},
784 {0x377a, 0x48},
785 {0x377b, 0x4f},
786 {0x37fa, 0x09},
787 {0x37fb, 0x31},
788 {0x37fc, 0x10},
789 {0x37fd, 0x18},
790 {0x3905, 0x8d},
791 {0x391d, 0x08},
792 {0x3922, 0x1a},
793 {0x3926, 0x21},
794 {0x3933, 0x80},
795 {0x3934, 0x0d},
796 {0x3937, 0x6a},
797 {0x3939, 0x00},
798 {0x393a, 0x0e},
799 {0x39dc, 0x02},
800 {0x3e00, 0x00},
801 {0x3e01, 0xb9},
802 {0x3e02, 0xc0},
803 {0x3e03, 0x0b},
804 {0x3e04, 0x0b},
805 {0x3e05, 0xa0},
806 {0x3e1b, 0x2a},
807 {0x3e23, 0x00},
808 {0x3e24, 0xbf},
809 {0x4407, 0x34},
810 {0x440e, 0x02},
811 {0x4509, 0x10},
812 {0x4816, 0x71},
813 {0x5001, 0x40},
814 {0x5007, 0x80},
815 {0x36e9, 0x24},
816 {0x37f9, 0x24},
817 {0x3251, 0x90},
818
819 /* strong signal */
820 {0x3650, 0x33},
821 {0x3651, 0x7f},
822
823 {0x3028, 0x05},
824 {REG_NULL, 0x00},
825 };
826
827 static const struct SC301IOT_mode supported_modes[] = {
828 {
829 .width = 2048,
830 .height = 1536,
831 .max_fps = {
832 .numerator = 10000,
833 .denominator = 300000,
834 },
835 .exp_def = 0x638,
836 .hts_def = 0x8ca,
837 .vts_def = 0x640,
838 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
839 .reg_list = SC301IOT_linear_10_2048x1536_regs,
840 .hdr_mode = NO_HDR,
841 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
842 }, {
843 .width = 2048,
844 .height = 1536,
845 .max_fps = {
846 .numerator = 10000,
847 .denominator = 300000,
848 },
849 .exp_def = 0xb9c,
850 .hts_def = 0x8ca,
851 .vts_def = 0xc80,
852 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
853 .reg_list = SC301IOT_hdr_10_2048x1536_regs,
854 .hdr_mode = HDR_X2,
855 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
856 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
857 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
858 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
859 }, {
860 .width = 1536,
861 .height = 1536,
862 .max_fps = {
863 .numerator = 10000,
864 .denominator = 300000,
865 },
866 .exp_def = 0x96,
867 .hts_def = 0x8ca,
868 .vts_def = 0x640,
869 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
870 .reg_list = SC301IOT_linear_10_1536x1536_regs,
871 .hdr_mode = NO_HDR,
872 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
873 }, {
874 .width = 1536,
875 .height = 1536,
876 .max_fps = {
877 .numerator = 10000,
878 .denominator = 300000,
879 },
880 .exp_def = 0xb9c,
881 .hts_def = 0x8ca,
882 .vts_def = 0xc80,
883 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
884 .reg_list = SC301IOT_hdr_10_1536x1536_regs,
885 .hdr_mode = HDR_X2,
886 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
887 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
888 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
889 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
890 },
891 };
892
893 static const s64 link_freq_menu_items[] = {
894 SC301IOT_LINK_FREQ_594
895 };
896
897 static const char * const SC301IOT_test_pattern_menu[] = {
898 "Disabled",
899 "Vertical Color Bar Type 1",
900 "Vertical Color Bar Type 2",
901 "Vertical Color Bar Type 3",
902 "Vertical Color Bar Type 4"
903 };
904
905 /* Write registers up to 4 at a time */
SC301IOT_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)906 static int SC301IOT_write_reg(struct i2c_client *client, u16 reg,
907 u32 len, u32 val)
908 {
909 u32 buf_i, val_i;
910 u8 buf[6];
911 u8 *val_p;
912 __be32 val_be;
913
914 if (len > 4)
915 return -EINVAL;
916
917 buf[0] = reg >> 8;
918 buf[1] = reg & 0xff;
919
920 val_be = cpu_to_be32(val);
921 val_p = (u8 *)&val_be;
922 buf_i = 2;
923 val_i = 4 - len;
924
925 while (val_i < 4)
926 buf[buf_i++] = val_p[val_i++];
927
928 if (i2c_master_send(client, buf, len + 2) != len + 2)
929 return -EIO;
930
931 return 0;
932 }
933
SC301IOT_write_array(struct i2c_client * client,const struct regval * regs)934 static int SC301IOT_write_array(struct i2c_client *client,
935 const struct regval *regs)
936 {
937 u32 i;
938 int ret = 0;
939
940 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
941 ret = SC301IOT_write_reg(client, regs[i].addr,
942 SC301IOT_REG_VALUE_08BIT, regs[i].val);
943
944 return ret;
945 }
946
947 /* Read registers up to 4 at a time */
SC301IOT_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)948 static int SC301IOT_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
949 u32 *val)
950 {
951 struct i2c_msg msgs[2];
952 u8 *data_be_p;
953 __be32 data_be = 0;
954 __be16 reg_addr_be = cpu_to_be16(reg);
955 int ret;
956
957 if (len > 4 || !len)
958 return -EINVAL;
959
960 data_be_p = (u8 *)&data_be;
961 /* Write register address */
962 msgs[0].addr = client->addr;
963 msgs[0].flags = 0;
964 msgs[0].len = 2;
965 msgs[0].buf = (u8 *)®_addr_be;
966
967 /* Read data from register */
968 msgs[1].addr = client->addr;
969 msgs[1].flags = I2C_M_RD;
970 msgs[1].len = len;
971 msgs[1].buf = &data_be_p[4 - len];
972
973 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
974 if (ret != ARRAY_SIZE(msgs))
975 return -EIO;
976
977 *val = be32_to_cpu(data_be);
978
979 return 0;
980 }
981
982
983
984
985 /* mode: 0 = lgain 1 = sgain */
SC301IOT_set_gain_reg(struct SC301IOT * SC301IOT,u32 gain,int mode)986 static int SC301IOT_set_gain_reg(struct SC301IOT *SC301IOT, u32 gain, int mode)
987 {
988 u8 ANA_Coarse_gain_reg = 0x00, DIG_Fine_gain_reg = 0x80;
989 u32 ANA_Coarse_gain = 1024, DIG_gain_reg = 0x00;
990 int ret = 0;
991
992
993 gain = gain * 16;
994 if (gain <= 1024)
995 gain = 1024;
996 else if (gain > SC301IOT_GAIN_MAX * 16)
997 gain = SC301IOT_GAIN_MAX * 16;
998
999 if (gain < 1606) { // start Ana again
1000 ANA_Coarse_gain = 1024;
1001 ANA_Coarse_gain_reg = 0x00;
1002 } else if (gain < 3397) {
1003 ANA_Coarse_gain = 1606;
1004 ANA_Coarse_gain_reg = 0x40;
1005 } else if (gain < 6426) {
1006 ANA_Coarse_gain = 3397;
1007 ANA_Coarse_gain_reg = 0x48;
1008 } else if (gain < 12853) {
1009 ANA_Coarse_gain = 6426;
1010 ANA_Coarse_gain_reg = 0x49;
1011 } else if (gain < 25706) {
1012 ANA_Coarse_gain = 12853;
1013 ANA_Coarse_gain_reg = 0x4b;
1014 } else if (gain < 51412) {
1015 ANA_Coarse_gain = 25706;
1016 ANA_Coarse_gain_reg = 0x4f;
1017 } else {
1018 ANA_Coarse_gain = 51412;
1019 ANA_Coarse_gain_reg = 0x5f;
1020 }
1021 gain = gain * 1024 / ANA_Coarse_gain; // start Dig again
1022 if (gain <= 1024)
1023 gain = 1024;
1024 else if (gain >= 2031)
1025 gain = 2031;
1026 DIG_Fine_gain_reg = gain/8;
1027
1028 if (mode == SC301IOT_LGAIN) {
1029 ret = SC301IOT_write_reg(SC301IOT->client,
1030 SC301IOT_REG_DIG_GAIN,
1031 SC301IOT_REG_VALUE_08BIT,
1032 DIG_gain_reg & 0xF);
1033 ret |= SC301IOT_write_reg(SC301IOT->client,
1034 SC301IOT_REG_DIG_FINE_GAIN,
1035 SC301IOT_REG_VALUE_08BIT,
1036 DIG_Fine_gain_reg);
1037 ret |= SC301IOT_write_reg(SC301IOT->client,
1038 SC301IOT_REG_ANA_GAIN,
1039 SC301IOT_REG_VALUE_08BIT,
1040 ANA_Coarse_gain_reg);
1041 } else {
1042 ret = SC301IOT_write_reg(SC301IOT->client,
1043 SC301IOT_REG_SDIG_GAIN,
1044 SC301IOT_REG_VALUE_08BIT,
1045 DIG_gain_reg & 0xF);
1046 ret |= SC301IOT_write_reg(SC301IOT->client,
1047 SC301IOT_REG_SDIG_FINE_GAIN,
1048 SC301IOT_REG_VALUE_08BIT,
1049 DIG_Fine_gain_reg);
1050 ret |= SC301IOT_write_reg(SC301IOT->client,
1051 SC301IOT_REG_SANA_GAIN,
1052 SC301IOT_REG_VALUE_08BIT,
1053 ANA_Coarse_gain_reg);
1054 }
1055 return ret;
1056 }
1057
SC301IOT_set_hdrae(struct SC301IOT * SC301IOT,struct preisp_hdrae_exp_s * ae)1058 static int SC301IOT_set_hdrae(struct SC301IOT *SC301IOT,
1059 struct preisp_hdrae_exp_s *ae)
1060 {
1061 int ret = 0;
1062 u32 l_exp_time, m_exp_time, s_exp_time;
1063 u32 l_a_gain, m_a_gain, s_a_gain;
1064
1065 if (!SC301IOT->has_init_exp && !SC301IOT->streaming) {
1066 SC301IOT->init_hdrae_exp = *ae;
1067 SC301IOT->has_init_exp = true;
1068 dev_dbg(&SC301IOT->client->dev, "SC301IOT don't stream, record exp for hdr!\n");
1069 return ret;
1070 }
1071 l_exp_time = ae->long_exp_reg;
1072 m_exp_time = ae->middle_exp_reg;
1073 s_exp_time = ae->short_exp_reg;
1074 l_a_gain = ae->long_gain_reg;
1075 m_a_gain = ae->middle_gain_reg;
1076 s_a_gain = ae->short_gain_reg;
1077
1078 dev_dbg(&SC301IOT->client->dev,
1079 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1080 l_exp_time, m_exp_time, s_exp_time,
1081 l_a_gain, m_a_gain, s_a_gain);
1082
1083 if (SC301IOT->cur_mode->hdr_mode == HDR_X2) {
1084 //2 stagger
1085 l_a_gain = m_a_gain;
1086 l_exp_time = m_exp_time;
1087 }
1088
1089 //set exposure
1090 //l_exp_time = ae->long_exp_reg;
1091 //s_exp_time = ae->short_exp_reg;
1092
1093 l_exp_time = l_exp_time * 2;
1094 s_exp_time = s_exp_time * 2;
1095 if (l_exp_time > 2998) //(3200 - 191 - 11)
1096 l_exp_time = 2998;
1097 if (s_exp_time > 182) //(191 - 9)
1098 s_exp_time = 182;
1099
1100 ret = SC301IOT_write_reg(SC301IOT->client,
1101 SC301IOT_REG_EXPOSURE_H,
1102 SC301IOT_REG_VALUE_08BIT,
1103 SC301IOT_FETCH_EXP_H(l_exp_time));
1104 ret |= SC301IOT_write_reg(SC301IOT->client,
1105 SC301IOT_REG_EXPOSURE_M,
1106 SC301IOT_REG_VALUE_08BIT,
1107 SC301IOT_FETCH_EXP_M(l_exp_time));
1108 ret |= SC301IOT_write_reg(SC301IOT->client,
1109 SC301IOT_REG_EXPOSURE_L,
1110 SC301IOT_REG_VALUE_08BIT,
1111 SC301IOT_FETCH_EXP_L(l_exp_time));
1112 ret |= SC301IOT_write_reg(SC301IOT->client,
1113 SC301IOT_REG_SEXPOSURE_M,
1114 SC301IOT_REG_VALUE_08BIT,
1115 SC301IOT_FETCH_EXP_M(s_exp_time));
1116 ret |= SC301IOT_write_reg(SC301IOT->client,
1117 SC301IOT_REG_SEXPOSURE_L,
1118 SC301IOT_REG_VALUE_08BIT,
1119 SC301IOT_FETCH_EXP_L(s_exp_time));
1120
1121
1122 ret |= SC301IOT_set_gain_reg(SC301IOT, l_a_gain, SC301IOT_LGAIN);
1123 ret |= SC301IOT_set_gain_reg(SC301IOT, s_a_gain, SC301IOT_SGAIN);
1124 return ret;
1125 }
1126
SC301IOT_get_reso_dist(const struct SC301IOT_mode * mode,struct v4l2_mbus_framefmt * framefmt)1127 static int SC301IOT_get_reso_dist(const struct SC301IOT_mode *mode,
1128 struct v4l2_mbus_framefmt *framefmt)
1129 {
1130 return abs(mode->width - framefmt->width) +
1131 abs(mode->height - framefmt->height);
1132 }
1133
1134 static const struct SC301IOT_mode *
SC301IOT_find_best_fit(struct v4l2_subdev_format * fmt)1135 SC301IOT_find_best_fit(struct v4l2_subdev_format *fmt)
1136 {
1137 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1138 int dist;
1139 int cur_best_fit = 0;
1140 int cur_best_fit_dist = -1;
1141 unsigned int i;
1142
1143 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1144 dist = SC301IOT_get_reso_dist(&supported_modes[i], framefmt);
1145 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1146 cur_best_fit_dist = dist;
1147 cur_best_fit = i;
1148 }
1149 }
1150
1151 return &supported_modes[cur_best_fit];
1152 }
1153
SC301IOT_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1154 static int SC301IOT_set_fmt(struct v4l2_subdev *sd,
1155 struct v4l2_subdev_pad_config *cfg,
1156 struct v4l2_subdev_format *fmt)
1157 {
1158 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1159 const struct SC301IOT_mode *mode;
1160 s64 h_blank, vblank_def;
1161
1162 mutex_lock(&SC301IOT->mutex);
1163
1164 mode = SC301IOT_find_best_fit(fmt);
1165 fmt->format.code = mode->bus_fmt;
1166 fmt->format.width = mode->width;
1167 fmt->format.height = mode->height;
1168 fmt->format.field = V4L2_FIELD_NONE;
1169 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1170 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1171 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1172 #else
1173 mutex_unlock(&SC301IOT->mutex);
1174 return -ENOTTY;
1175 #endif
1176 } else {
1177 SC301IOT->cur_mode = mode;
1178 h_blank = mode->hts_def - mode->width;
1179 __v4l2_ctrl_modify_range(SC301IOT->hblank, h_blank,
1180 h_blank, 1, h_blank);
1181 vblank_def = mode->vts_def - mode->height;
1182 __v4l2_ctrl_modify_range(SC301IOT->vblank, vblank_def,
1183 SC301IOT_VTS_MAX - mode->height,
1184 1, vblank_def);
1185 SC301IOT->cur_fps = mode->max_fps;
1186 SC301IOT->cur_vts = mode->vts_def;
1187 }
1188
1189 mutex_unlock(&SC301IOT->mutex);
1190
1191 return 0;
1192 }
1193
SC301IOT_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1194 static int SC301IOT_get_fmt(struct v4l2_subdev *sd,
1195 struct v4l2_subdev_pad_config *cfg,
1196 struct v4l2_subdev_format *fmt)
1197 {
1198 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1199 const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
1200
1201 mutex_lock(&SC301IOT->mutex);
1202 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1203 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1204 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1205 #else
1206 mutex_unlock(&SC301IOT->mutex);
1207 return -ENOTTY;
1208 #endif
1209 } else {
1210 fmt->format.width = mode->width;
1211 fmt->format.height = mode->height;
1212 fmt->format.code = mode->bus_fmt;
1213 fmt->format.field = V4L2_FIELD_NONE;
1214 /* format info: width/height/data type/virctual channel */
1215 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1216 fmt->reserved[0] = mode->vc[fmt->pad];
1217 else
1218 fmt->reserved[0] = mode->vc[PAD0];
1219 }
1220 mutex_unlock(&SC301IOT->mutex);
1221 return 0;
1222 }
1223
SC301IOT_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1224 static int SC301IOT_enum_mbus_code(struct v4l2_subdev *sd,
1225 struct v4l2_subdev_pad_config *cfg,
1226 struct v4l2_subdev_mbus_code_enum *code)
1227 {
1228 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1229
1230 if (code->index != 0)
1231 return -EINVAL;
1232 code->code = SC301IOT->cur_mode->bus_fmt;
1233
1234 return 0;
1235 }
1236
SC301IOT_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1237 static int SC301IOT_enum_frame_sizes(struct v4l2_subdev *sd,
1238 struct v4l2_subdev_pad_config *cfg,
1239 struct v4l2_subdev_frame_size_enum *fse)
1240 {
1241 if (fse->index >= ARRAY_SIZE(supported_modes))
1242 return -EINVAL;
1243
1244 if (fse->code != supported_modes[0].bus_fmt)
1245 return -EINVAL;
1246
1247 fse->min_width = supported_modes[fse->index].width;
1248 fse->max_width = supported_modes[fse->index].width;
1249 fse->max_height = supported_modes[fse->index].height;
1250 fse->min_height = supported_modes[fse->index].height;
1251
1252 return 0;
1253 }
1254
SC301IOT_enable_test_pattern(struct SC301IOT * SC301IOT,u32 pattern)1255 static int SC301IOT_enable_test_pattern(struct SC301IOT *SC301IOT, u32 pattern)
1256 {
1257 u32 val = 0;
1258 int ret = 0;
1259
1260 ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_REG_TEST_PATTERN,
1261 SC301IOT_REG_VALUE_08BIT, &val);
1262 if (pattern)
1263 val |= SC301IOT_TEST_PATTERN_BIT_MASK;
1264 else
1265 val &= ~SC301IOT_TEST_PATTERN_BIT_MASK;
1266
1267 ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_TEST_PATTERN,
1268 SC301IOT_REG_VALUE_08BIT, val);
1269 return ret;
1270 }
1271
SC301IOT_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1272 static int SC301IOT_g_frame_interval(struct v4l2_subdev *sd,
1273 struct v4l2_subdev_frame_interval *fi)
1274 {
1275 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1276 const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
1277
1278 if (SC301IOT->streaming)
1279 fi->interval = SC301IOT->cur_fps;
1280 else
1281 fi->interval = mode->max_fps;
1282
1283 return 0;
1284 }
1285
SC301IOT_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1286 static int SC301IOT_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1287 struct v4l2_mbus_config *config)
1288 {
1289 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1290 const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
1291 u32 val = 1 << (SC301IOT_LANES - 1) |
1292 V4L2_MBUS_CSI2_CHANNEL_0 |
1293 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1294
1295 if (mode->hdr_mode != NO_HDR)
1296 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1297 if (mode->hdr_mode == HDR_X3)
1298 val |= V4L2_MBUS_CSI2_CHANNEL_2;
1299
1300 config->type = V4L2_MBUS_CSI2_DPHY;
1301 config->flags = val;
1302
1303 return 0;
1304 }
1305
SC301IOT_get_module_inf(struct SC301IOT * SC301IOT,struct rkmodule_inf * inf)1306 static void SC301IOT_get_module_inf(struct SC301IOT *SC301IOT,
1307 struct rkmodule_inf *inf)
1308 {
1309 memset(inf, 0, sizeof(*inf));
1310 strscpy(inf->base.sensor, SC301IOT_NAME, sizeof(inf->base.sensor));
1311 strscpy(inf->base.module, SC301IOT->module_name,
1312 sizeof(inf->base.module));
1313 strscpy(inf->base.lens, SC301IOT->len_name, sizeof(inf->base.lens));
1314 }
1315
SC301IOT_get_channel_info(struct SC301IOT * SC301IOT,struct rkmodule_channel_info * ch_info)1316 static int SC301IOT_get_channel_info(struct SC301IOT *SC301IOT,
1317 struct rkmodule_channel_info *ch_info)
1318 {
1319 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1320 return -EINVAL;
1321 ch_info->vc = SC301IOT->cur_mode->vc[ch_info->index];
1322 ch_info->width = SC301IOT->cur_mode->width;
1323 ch_info->height = SC301IOT->cur_mode->height;
1324 ch_info->bus_fmt = SC301IOT->cur_mode->bus_fmt;
1325 return 0;
1326 }
1327
SC301IOT_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1328 static long SC301IOT_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1329 {
1330 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1331 struct rkmodule_hdr_cfg *hdr;
1332 struct rkmodule_channel_info *ch_info;
1333 u32 i, h, w;
1334 long ret = 0;
1335 u32 stream = 0;
1336 u32 sync_mode = 4;
1337
1338 switch (cmd) {
1339 case RKMODULE_GET_MODULE_INFO:
1340 SC301IOT_get_module_inf(SC301IOT, (struct rkmodule_inf *)arg);
1341 break;
1342 case RKMODULE_GET_HDR_CFG:
1343 hdr = (struct rkmodule_hdr_cfg *)arg;
1344 hdr->esp.mode = HDR_NORMAL_VC;
1345 hdr->hdr_mode = SC301IOT->cur_mode->hdr_mode;
1346 break;
1347 case RKMODULE_SET_HDR_CFG:
1348 hdr = (struct rkmodule_hdr_cfg *)arg;
1349 w = SC301IOT->cur_mode->width;
1350 h = SC301IOT->cur_mode->height;
1351 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1352 if (w == supported_modes[i].width &&
1353 h == supported_modes[i].height &&
1354 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1355 SC301IOT->cur_mode = &supported_modes[i];
1356 break;
1357 }
1358 }
1359 if (i == ARRAY_SIZE(supported_modes)) {
1360 dev_err(&SC301IOT->client->dev,
1361 "not find hdr mode:%d %dx%d config\n",
1362 hdr->hdr_mode, w, h);
1363 ret = -EINVAL;
1364 } else {
1365 w = SC301IOT->cur_mode->hts_def - SC301IOT->cur_mode->width;
1366 h = SC301IOT->cur_mode->vts_def - SC301IOT->cur_mode->height;
1367 __v4l2_ctrl_modify_range(SC301IOT->hblank, w, w, 1, w);
1368 __v4l2_ctrl_modify_range(SC301IOT->vblank,
1369 h,
1370 SC301IOT_VTS_MAX - SC301IOT->cur_mode->height, 1, h);
1371 SC301IOT->cur_fps = SC301IOT->cur_mode->max_fps;
1372 SC301IOT->cur_vts = SC301IOT->cur_mode->vts_def;
1373 }
1374 break;
1375 case PREISP_CMD_SET_HDRAE_EXP:
1376 SC301IOT_set_hdrae(SC301IOT, arg);
1377 break;
1378 case RKMODULE_SET_QUICK_STREAM:
1379
1380 stream = *((u32 *)arg);
1381
1382 if (stream)
1383 ret = SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
1384 SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_STREAMING);
1385 else
1386 ret = SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
1387 SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_SW_STANDBY);
1388 break;
1389 case RKMODULE_GET_SYNC_MODE:
1390 *((u32 *)arg) = SC301IOT->sync_mode;
1391 break;
1392 case RKMODULE_SET_SYNC_MODE:
1393 sync_mode = *((u32 *)arg);
1394 if (sync_mode > 3)
1395 break;
1396 SC301IOT->sync_mode = sync_mode;
1397 dev_info(&SC301IOT->client->dev, "sync_mode = [%u]\n", SC301IOT->sync_mode);
1398 break;
1399 case RKMODULE_GET_CHANNEL_INFO:
1400 ch_info = (struct rkmodule_channel_info *)arg;
1401 ret = SC301IOT_get_channel_info(SC301IOT, ch_info);
1402 break;
1403 default:
1404 ret = -ENOIOCTLCMD;
1405 break;
1406 }
1407
1408 return ret;
1409 }
1410
1411 #ifdef CONFIG_COMPAT
SC301IOT_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1412 static long SC301IOT_compat_ioctl32(struct v4l2_subdev *sd,
1413 unsigned int cmd, unsigned long arg)
1414 {
1415 void __user *up = compat_ptr(arg);
1416 struct rkmodule_inf *inf;
1417 struct rkmodule_awb_cfg *cfg;
1418 struct rkmodule_hdr_cfg *hdr;
1419 struct preisp_hdrae_exp_s *hdrae;
1420 struct rkmodule_channel_info *ch_info;
1421 long ret;
1422 u32 stream = 0;
1423
1424 switch (cmd) {
1425 case RKMODULE_GET_MODULE_INFO:
1426 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1427 if (!inf) {
1428 ret = -ENOMEM;
1429 return ret;
1430 }
1431
1432 ret = SC301IOT_ioctl(sd, cmd, inf);
1433 if (!ret) {
1434 if (copy_to_user(up, inf, sizeof(*inf))) {
1435 kfree(inf);
1436 return -EFAULT;
1437 }
1438 }
1439 kfree(inf);
1440 break;
1441 case RKMODULE_AWB_CFG:
1442 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1443 if (!cfg) {
1444 ret = -ENOMEM;
1445 return ret;
1446 }
1447 if (copy_from_user(cfg, up, sizeof(*cfg))) {
1448 kfree(cfg);
1449 return -EFAULT;
1450 }
1451 ret = SC301IOT_ioctl(sd, cmd, cfg);
1452 kfree(cfg);
1453 break;
1454 case RKMODULE_GET_HDR_CFG:
1455 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1456 if (!hdr) {
1457 ret = -ENOMEM;
1458 return ret;
1459 }
1460
1461 ret = SC301IOT_ioctl(sd, cmd, hdr);
1462 if (!ret) {
1463 if (copy_to_user(up, hdr, sizeof(*hdr))) {
1464 kfree(hdr);
1465 return -EFAULT;
1466 }
1467 }
1468 kfree(hdr);
1469 break;
1470 case RKMODULE_SET_HDR_CFG:
1471 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1472 if (!hdr) {
1473 ret = -ENOMEM;
1474 return ret;
1475 }
1476 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1477 kfree(hdr);
1478 return -EFAULT;
1479 }
1480 ret = SC301IOT_ioctl(sd, cmd, hdr);
1481 kfree(hdr);
1482 break;
1483 case PREISP_CMD_SET_HDRAE_EXP:
1484 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1485 if (!hdrae) {
1486 ret = -ENOMEM;
1487 return ret;
1488 }
1489 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1490 kfree(hdrae);
1491 return -EFAULT;
1492 }
1493 ret = SC301IOT_ioctl(sd, cmd, hdrae);
1494 kfree(hdrae);
1495 break;
1496 case RKMODULE_SET_QUICK_STREAM:
1497 if (copy_from_user(&stream, up, sizeof(u32)))
1498 return -EFAULT;
1499 ret = SC301IOT_ioctl(sd, cmd, &stream);
1500 break;
1501 case RKMODULE_GET_CHANNEL_INFO:
1502 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1503 if (!ch_info) {
1504 ret = -ENOMEM;
1505 return ret;
1506 }
1507
1508 ret = SC301IOT_ioctl(sd, cmd, ch_info);
1509 if (!ret) {
1510 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1511 if (ret)
1512 ret = -EFAULT;
1513 }
1514 kfree(ch_info);
1515 break;
1516 default:
1517 ret = -ENOIOCTLCMD;
1518 break;
1519 }
1520
1521 return ret;
1522 }
1523 #endif
1524
SC301IOT_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1525 static int SC301IOT_s_frame_interval(struct v4l2_subdev *sd,
1526 struct v4l2_subdev_frame_interval *fi)
1527 {
1528 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1529 struct device *dev = sd->dev;
1530 int ret = -1;
1531 s64 vblank_def;
1532 u32 fps_set, current_fps;
1533
1534 fps_set = DIV_ROUND_CLOSEST(fi->interval.denominator, fi->interval.numerator);
1535 dev_info(dev, "%s set fps = %u\n", __func__, fps_set);
1536
1537 mutex_lock(&SC301IOT->mutex);
1538
1539 current_fps = DIV_ROUND_CLOSEST(SC301IOT->cur_mode->max_fps.denominator,
1540 SC301IOT->cur_mode->max_fps.numerator);
1541 vblank_def = SC301IOT->cur_mode->vts_def * current_fps / fps_set -
1542 SC301IOT->cur_mode->height;
1543 if (SC301IOT->sync_mode == SLAVE_MODE)
1544 vblank_def -= 3; // adjust vts
1545 ret = __v4l2_ctrl_s_ctrl(SC301IOT->vblank, vblank_def);
1546 mutex_unlock(&SC301IOT->mutex);
1547 if (ret < 0)
1548 dev_err(dev, "%s __v4l2_ctrl_s_ctrl error - %d\n", __func__, ret);
1549 return ret;
1550 }
1551
__SC301IOT_start_stream(struct SC301IOT * SC301IOT)1552 static int __SC301IOT_start_stream(struct SC301IOT *SC301IOT)
1553 {
1554 int ret;
1555
1556 if (!SC301IOT->is_thunderboot) {
1557 ret = SC301IOT_write_array(SC301IOT->client, SC301IOT->cur_mode->reg_list);
1558 if (ret)
1559 return ret;
1560
1561 /* In case these controls are set before streaming */
1562 ret = __v4l2_ctrl_handler_setup(&SC301IOT->ctrl_handler);
1563 if (ret)
1564 return ret;
1565 if (SC301IOT->has_init_exp && SC301IOT->cur_mode->hdr_mode != NO_HDR) {
1566 ret = SC301IOT_ioctl(&SC301IOT->subdev, PREISP_CMD_SET_HDRAE_EXP,
1567 &SC301IOT->init_hdrae_exp);
1568 if (ret) {
1569 dev_err(&SC301IOT->client->dev,
1570 "init exp fail in hdr mode\n");
1571 return ret;
1572 }
1573 }
1574
1575 if (SC301IOT->sync_mode == SLAVE_MODE) {
1576 SC301IOT_write_reg(SC301IOT->client, 0x3222,
1577 SC301IOT_REG_VALUE_08BIT, 0x01);
1578 SC301IOT_write_reg(SC301IOT->client, 0x3223,
1579 SC301IOT_REG_VALUE_08BIT, 0xc8);
1580 SC301IOT_write_reg(SC301IOT->client, 0x3225,
1581 SC301IOT_REG_VALUE_08BIT, 0x10);
1582 SC301IOT_write_reg(SC301IOT->client, 0x322e,
1583 SC301IOT_REG_VALUE_08BIT, (SC301IOT->cur_vts - 4) >> 8);
1584 SC301IOT_write_reg(SC301IOT->client, 0x322f,
1585 SC301IOT_REG_VALUE_08BIT, (SC301IOT->cur_vts - 4) & 0xff);
1586 } else if (SC301IOT->sync_mode == NO_SYNC_MODE) {
1587 SC301IOT_write_reg(SC301IOT->client, 0x3222,
1588 SC301IOT_REG_VALUE_08BIT, 0x00);
1589 SC301IOT_write_reg(SC301IOT->client, 0x3223,
1590 SC301IOT_REG_VALUE_08BIT, 0xd0);
1591 SC301IOT_write_reg(SC301IOT->client, 0x3225,
1592 SC301IOT_REG_VALUE_08BIT, 0x00);
1593 SC301IOT_write_reg(SC301IOT->client, 0x322e,
1594 SC301IOT_REG_VALUE_08BIT, 0x00);
1595 SC301IOT_write_reg(SC301IOT->client, 0x322f,
1596 SC301IOT_REG_VALUE_08BIT, 0x02);
1597 }
1598 }
1599
1600 dev_dbg(&SC301IOT->client->dev, "start stream\n");
1601 return SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
1602 SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_STREAMING);
1603 }
1604
__SC301IOT_stop_stream(struct SC301IOT * SC301IOT)1605 static int __SC301IOT_stop_stream(struct SC301IOT *SC301IOT)
1606 {
1607 SC301IOT->has_init_exp = false;
1608 dev_dbg(&SC301IOT->client->dev, "stop stream\n");
1609 if (SC301IOT->is_thunderboot)
1610 SC301IOT->is_first_streamoff = true;
1611 return SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
1612 SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_SW_STANDBY);
1613 }
1614
1615 static int __SC301IOT_power_on(struct SC301IOT *SC301IOT);
SC301IOT_s_stream(struct v4l2_subdev * sd,int on)1616 static int SC301IOT_s_stream(struct v4l2_subdev *sd, int on)
1617 {
1618 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1619 struct i2c_client *client = SC301IOT->client;
1620 int ret = 0;
1621
1622 mutex_lock(&SC301IOT->mutex);
1623 on = !!on;
1624 if (on == SC301IOT->streaming)
1625 goto unlock_and_return;
1626
1627 if (on) {
1628 if (SC301IOT->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1629 SC301IOT->is_thunderboot = false;
1630 __SC301IOT_power_on(SC301IOT);
1631 }
1632
1633 ret = pm_runtime_get_sync(&client->dev);
1634 if (ret < 0) {
1635 pm_runtime_put_noidle(&client->dev);
1636 goto unlock_and_return;
1637 }
1638
1639 ret = __SC301IOT_start_stream(SC301IOT);
1640 if (ret) {
1641 v4l2_err(sd, "start stream failed while write regs\n");
1642 pm_runtime_put(&client->dev);
1643 goto unlock_and_return;
1644 }
1645 } else {
1646 __SC301IOT_stop_stream(SC301IOT);
1647 pm_runtime_put(&client->dev);
1648 }
1649
1650 SC301IOT->streaming = on;
1651
1652 unlock_and_return:
1653 mutex_unlock(&SC301IOT->mutex);
1654
1655 return ret;
1656 }
1657
SC301IOT_s_power(struct v4l2_subdev * sd,int on)1658 static int SC301IOT_s_power(struct v4l2_subdev *sd, int on)
1659 {
1660 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1661 struct i2c_client *client = SC301IOT->client;
1662 int ret = 0;
1663
1664 mutex_lock(&SC301IOT->mutex);
1665
1666 /* If the power state is not modified - no work to do. */
1667 if (SC301IOT->power_on == !!on)
1668 goto unlock_and_return;
1669
1670 if (on) {
1671 ret = pm_runtime_get_sync(&client->dev);
1672 if (ret < 0) {
1673 pm_runtime_put_noidle(&client->dev);
1674 goto unlock_and_return;
1675 }
1676
1677 if (!SC301IOT->is_thunderboot) {
1678 ret = SC301IOT_write_array(SC301IOT->client, SC301IOT_global_regs);
1679 if (ret) {
1680 v4l2_err(sd, "could not set init registers\n");
1681 pm_runtime_put_noidle(&client->dev);
1682 goto unlock_and_return;
1683 }
1684 }
1685
1686 SC301IOT->power_on = true;
1687 } else {
1688 pm_runtime_put(&client->dev);
1689 SC301IOT->power_on = false;
1690 }
1691
1692 unlock_and_return:
1693 mutex_unlock(&SC301IOT->mutex);
1694
1695 return ret;
1696 }
1697
1698 /* Calculate the delay in us by clock rate and clock cycles */
SC301IOT_cal_delay(u32 cycles)1699 static inline u32 SC301IOT_cal_delay(u32 cycles)
1700 {
1701 return DIV_ROUND_UP(cycles, SC301IOT_XVCLK_FREQ / 1000 / 1000);
1702 }
1703
__SC301IOT_power_on(struct SC301IOT * SC301IOT)1704 static int __SC301IOT_power_on(struct SC301IOT *SC301IOT)
1705 {
1706 int ret;
1707 u32 delay_us;
1708 struct device *dev = &SC301IOT->client->dev;
1709
1710 if (!IS_ERR_OR_NULL(SC301IOT->pins_default)) {
1711 ret = pinctrl_select_state(SC301IOT->pinctrl,
1712 SC301IOT->pins_default);
1713 if (ret < 0)
1714 dev_err(dev, "could not set pins\n");
1715 }
1716 ret = clk_set_rate(SC301IOT->xvclk, SC301IOT_XVCLK_FREQ);
1717 if (ret < 0)
1718 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1719 if (clk_get_rate(SC301IOT->xvclk) != SC301IOT_XVCLK_FREQ)
1720 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1721 ret = clk_prepare_enable(SC301IOT->xvclk);
1722 if (ret < 0) {
1723 dev_err(dev, "Failed to enable xvclk\n");
1724 goto disable_clk;
1725 }
1726 if (SC301IOT->is_thunderboot)
1727 return 0;
1728 if (!IS_ERR(SC301IOT->reset_gpio))
1729 gpiod_set_value_cansleep(SC301IOT->reset_gpio, 0);
1730
1731 ret = regulator_bulk_enable(SC301IOT_NUM_SUPPLIES, SC301IOT->supplies);
1732 if (ret < 0) {
1733 dev_err(dev, "Failed to enable regulators\n");
1734 goto disable_clk;
1735 }
1736 if (!IS_ERR(SC301IOT->reset_gpio))
1737 gpiod_set_value_cansleep(SC301IOT->reset_gpio, 1);
1738
1739 usleep_range(500, 1000);
1740 if (!IS_ERR(SC301IOT->pwdn_gpio))
1741 gpiod_set_value_cansleep(SC301IOT->pwdn_gpio, 1);
1742 usleep_range(4500, 5000);
1743
1744 if (!IS_ERR(SC301IOT->reset_gpio))
1745 usleep_range(6000, 8000);
1746 else
1747 usleep_range(12000, 16000);
1748
1749 /* 8192 cycles prior to first SCCB transaction */
1750 delay_us = SC301IOT_cal_delay(8192);
1751 usleep_range(delay_us, delay_us * 2);
1752
1753 return 0;
1754
1755 disable_clk:
1756 clk_disable_unprepare(SC301IOT->xvclk);
1757
1758 return ret;
1759 }
1760
__SC301IOT_power_off(struct SC301IOT * SC301IOT)1761 static void __SC301IOT_power_off(struct SC301IOT *SC301IOT)
1762 {
1763 int ret;
1764 struct device *dev = &SC301IOT->client->dev;
1765
1766 clk_disable_unprepare(SC301IOT->xvclk);
1767 if (SC301IOT->is_thunderboot) {
1768 if (SC301IOT->is_first_streamoff) {
1769 SC301IOT->is_thunderboot = false;
1770 SC301IOT->is_first_streamoff = false;
1771 } else {
1772 return;
1773 }
1774 }
1775
1776 if (!IS_ERR(SC301IOT->pwdn_gpio))
1777 gpiod_set_value_cansleep(SC301IOT->pwdn_gpio, 0);
1778 if (!IS_ERR(SC301IOT->reset_gpio))
1779 gpiod_set_value_cansleep(SC301IOT->reset_gpio, 0);
1780 if (!IS_ERR_OR_NULL(SC301IOT->pins_sleep)) {
1781 ret = pinctrl_select_state(SC301IOT->pinctrl,
1782 SC301IOT->pins_sleep);
1783 if (ret < 0)
1784 dev_dbg(dev, "could not set pins\n");
1785 }
1786 regulator_bulk_disable(SC301IOT_NUM_SUPPLIES, SC301IOT->supplies);
1787 }
1788
SC301IOT_runtime_resume(struct device * dev)1789 static int SC301IOT_runtime_resume(struct device *dev)
1790 {
1791 struct i2c_client *client = to_i2c_client(dev);
1792 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1793 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1794
1795 return __SC301IOT_power_on(SC301IOT);
1796 }
1797
SC301IOT_runtime_suspend(struct device * dev)1798 static int SC301IOT_runtime_suspend(struct device *dev)
1799 {
1800 struct i2c_client *client = to_i2c_client(dev);
1801 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1802 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1803
1804 __SC301IOT_power_off(SC301IOT);
1805
1806 return 0;
1807 }
1808
1809 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
SC301IOT_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1810 static int SC301IOT_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1811 {
1812 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
1813 struct v4l2_mbus_framefmt *try_fmt =
1814 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1815 const struct SC301IOT_mode *def_mode = &supported_modes[0];
1816
1817 mutex_lock(&SC301IOT->mutex);
1818 /* Initialize try_fmt */
1819 try_fmt->width = def_mode->width;
1820 try_fmt->height = def_mode->height;
1821 try_fmt->code = def_mode->bus_fmt;
1822 try_fmt->field = V4L2_FIELD_NONE;
1823
1824 mutex_unlock(&SC301IOT->mutex);
1825 /* No crop or compose */
1826
1827 return 0;
1828 }
1829 #endif
1830
SC301IOT_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1831 static int SC301IOT_enum_frame_interval(struct v4l2_subdev *sd,
1832 struct v4l2_subdev_pad_config *cfg,
1833 struct v4l2_subdev_frame_interval_enum *fie)
1834 {
1835 if (fie->index >= ARRAY_SIZE(supported_modes))
1836 return -EINVAL;
1837
1838 fie->code = supported_modes[fie->index].bus_fmt;
1839 fie->width = supported_modes[fie->index].width;
1840 fie->height = supported_modes[fie->index].height;
1841 fie->interval = supported_modes[fie->index].max_fps;
1842 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1843 return 0;
1844 }
1845
1846 static const struct dev_pm_ops SC301IOT_pm_ops = {
1847 SET_RUNTIME_PM_OPS(SC301IOT_runtime_suspend,
1848 SC301IOT_runtime_resume, NULL)
1849 };
1850
1851 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1852 static const struct v4l2_subdev_internal_ops SC301IOT_internal_ops = {
1853 .open = SC301IOT_open,
1854 };
1855 #endif
1856
1857 static const struct v4l2_subdev_core_ops SC301IOT_core_ops = {
1858 .s_power = SC301IOT_s_power,
1859 .ioctl = SC301IOT_ioctl,
1860 #ifdef CONFIG_COMPAT
1861 .compat_ioctl32 = SC301IOT_compat_ioctl32,
1862 #endif
1863 };
1864
1865 static const struct v4l2_subdev_video_ops SC301IOT_video_ops = {
1866 .s_stream = SC301IOT_s_stream,
1867 .g_frame_interval = SC301IOT_g_frame_interval,
1868 .s_frame_interval = SC301IOT_s_frame_interval,
1869 };
1870
1871 static const struct v4l2_subdev_pad_ops SC301IOT_pad_ops = {
1872 .enum_mbus_code = SC301IOT_enum_mbus_code,
1873 .enum_frame_size = SC301IOT_enum_frame_sizes,
1874 .enum_frame_interval = SC301IOT_enum_frame_interval,
1875 .get_fmt = SC301IOT_get_fmt,
1876 .set_fmt = SC301IOT_set_fmt,
1877 .get_mbus_config = SC301IOT_g_mbus_config,
1878 };
1879
1880 static const struct v4l2_subdev_ops SC301IOT_subdev_ops = {
1881 .core = &SC301IOT_core_ops,
1882 .video = &SC301IOT_video_ops,
1883 .pad = &SC301IOT_pad_ops,
1884 };
1885
SC301IOT_modify_fps_info(struct SC301IOT * SC301IOT)1886 static void SC301IOT_modify_fps_info(struct SC301IOT *SC301IOT)
1887 {
1888 const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
1889
1890 SC301IOT->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1891 SC301IOT->cur_vts;
1892 }
1893
SC301IOT_set_ctrl(struct v4l2_ctrl * ctrl)1894 static int SC301IOT_set_ctrl(struct v4l2_ctrl *ctrl)
1895 {
1896 struct SC301IOT *SC301IOT = container_of(ctrl->handler,
1897 struct SC301IOT, ctrl_handler);
1898 struct i2c_client *client = SC301IOT->client;
1899 s64 max;
1900 int ret = 0;
1901 u32 val = 0;
1902
1903 /* Propagate change of current control to all related controls */
1904 switch (ctrl->id) {
1905 case V4L2_CID_VBLANK:
1906 /* Update max exposure while meeting expected vblanking */
1907 max = SC301IOT->cur_mode->height + ctrl->val - 4;
1908 __v4l2_ctrl_modify_range(SC301IOT->exposure,
1909 SC301IOT->exposure->minimum, max,
1910 SC301IOT->exposure->step,
1911 SC301IOT->exposure->default_value);
1912 break;
1913 }
1914
1915 if (!pm_runtime_get_if_in_use(&client->dev))
1916 return 0;
1917
1918 switch (ctrl->id) {
1919 case V4L2_CID_EXPOSURE:
1920 if (SC301IOT->cur_mode->hdr_mode == NO_HDR) {
1921 ctrl->val = ctrl->val;
1922 /* 4 least significant bits of expsoure are fractional part */
1923 ret = SC301IOT_write_reg(SC301IOT->client,
1924 SC301IOT_REG_EXPOSURE_H,
1925 SC301IOT_REG_VALUE_08BIT,
1926 SC301IOT_FETCH_EXP_H(ctrl->val));
1927 ret |= SC301IOT_write_reg(SC301IOT->client,
1928 SC301IOT_REG_EXPOSURE_M,
1929 SC301IOT_REG_VALUE_08BIT,
1930 SC301IOT_FETCH_EXP_M(ctrl->val));
1931 ret |= SC301IOT_write_reg(SC301IOT->client,
1932 SC301IOT_REG_EXPOSURE_L,
1933 SC301IOT_REG_VALUE_08BIT,
1934 SC301IOT_FETCH_EXP_L(ctrl->val));
1935 }
1936 break;
1937 case V4L2_CID_ANALOGUE_GAIN:
1938 if (SC301IOT->cur_mode->hdr_mode == NO_HDR)
1939 ret = SC301IOT_set_gain_reg(SC301IOT, ctrl->val, SC301IOT_LGAIN);
1940 break;
1941 case V4L2_CID_VBLANK:
1942 ret = SC301IOT_write_reg(SC301IOT->client,
1943 SC301IOT_REG_VTS_H,
1944 SC301IOT_REG_VALUE_08BIT,
1945 (ctrl->val + SC301IOT->cur_mode->height)
1946 >> 8);
1947 ret |= SC301IOT_write_reg(SC301IOT->client,
1948 SC301IOT_REG_VTS_L,
1949 SC301IOT_REG_VALUE_08BIT,
1950 (ctrl->val + SC301IOT->cur_mode->height)
1951 & 0xff);
1952 if (!ret)
1953 SC301IOT->cur_vts = ctrl->val + SC301IOT->cur_mode->height;
1954 SC301IOT_modify_fps_info(SC301IOT);
1955 break;
1956 case V4L2_CID_TEST_PATTERN:
1957 ret = SC301IOT_enable_test_pattern(SC301IOT, ctrl->val);
1958 break;
1959 case V4L2_CID_HFLIP:
1960 ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
1961 SC301IOT_REG_VALUE_08BIT, &val);
1962 ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
1963 SC301IOT_REG_VALUE_08BIT,
1964 SC301IOT_FETCH_MIRROR(val, ctrl->val));
1965 break;
1966 case V4L2_CID_VFLIP:
1967 ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
1968 SC301IOT_REG_VALUE_08BIT, &val);
1969 ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
1970 SC301IOT_REG_VALUE_08BIT,
1971 SC301IOT_FETCH_FLIP(val, ctrl->val));
1972 break;
1973 default:
1974 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1975 __func__, ctrl->id, ctrl->val);
1976 break;
1977 }
1978
1979 pm_runtime_put(&client->dev);
1980
1981 return ret;
1982 }
1983
1984 static const struct v4l2_ctrl_ops SC301IOT_ctrl_ops = {
1985 .s_ctrl = SC301IOT_set_ctrl,
1986 };
1987
SC301IOT_initialize_controls(struct SC301IOT * SC301IOT)1988 static int SC301IOT_initialize_controls(struct SC301IOT *SC301IOT)
1989 {
1990 const struct SC301IOT_mode *mode;
1991 struct v4l2_ctrl_handler *handler;
1992 struct v4l2_ctrl *ctrl;
1993 s64 exposure_max, vblank_def;
1994 u32 h_blank;
1995 int ret;
1996
1997 handler = &SC301IOT->ctrl_handler;
1998 mode = SC301IOT->cur_mode;
1999 ret = v4l2_ctrl_handler_init(handler, 9);
2000 if (ret)
2001 return ret;
2002 handler->lock = &SC301IOT->mutex;
2003
2004 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
2005 0, 0, link_freq_menu_items);
2006 if (ctrl)
2007 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2008
2009 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2010 0, PIXEL_RATE_WITH_594M_10BIT, 1, PIXEL_RATE_WITH_594M_10BIT);
2011
2012 h_blank = mode->hts_def - mode->width;
2013 SC301IOT->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2014 h_blank, h_blank, 1, h_blank);
2015 if (SC301IOT->hblank)
2016 SC301IOT->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2017 vblank_def = mode->vts_def - mode->height;
2018 SC301IOT->vblank = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
2019 V4L2_CID_VBLANK, vblank_def,
2020 SC301IOT_VTS_MAX - mode->height,
2021 1, vblank_def);
2022 exposure_max = mode->vts_def - 8;
2023 SC301IOT->exposure = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
2024 V4L2_CID_EXPOSURE, SC301IOT_EXPOSURE_MIN,
2025 exposure_max, SC301IOT_EXPOSURE_STEP,
2026 mode->exp_def);
2027 SC301IOT->anal_gain = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
2028 V4L2_CID_ANALOGUE_GAIN, SC301IOT_GAIN_MIN,
2029 SC301IOT_GAIN_MAX, SC301IOT_GAIN_STEP,
2030 SC301IOT_GAIN_DEFAULT);
2031 SC301IOT->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
2032 &SC301IOT_ctrl_ops,
2033 V4L2_CID_TEST_PATTERN,
2034 ARRAY_SIZE(SC301IOT_test_pattern_menu) - 1,
2035 0, 0, SC301IOT_test_pattern_menu);
2036 v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
2037 V4L2_CID_HFLIP, 0, 1, 1, 0);
2038
2039 v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
2040 V4L2_CID_VFLIP, 0, 1, 1, 0);
2041
2042 if (handler->error) {
2043 ret = handler->error;
2044 dev_err(&SC301IOT->client->dev,
2045 "Failed to init controls(%d)\n", ret);
2046 goto err_free_handler;
2047 }
2048
2049 SC301IOT->subdev.ctrl_handler = handler;
2050 SC301IOT->has_init_exp = false;
2051 SC301IOT->cur_fps = mode->max_fps;
2052 SC301IOT->cur_vts = mode->vts_def;
2053
2054 return 0;
2055
2056 err_free_handler:
2057 v4l2_ctrl_handler_free(handler);
2058
2059 return ret;
2060 }
2061
SC301IOT_check_sensor_id(struct SC301IOT * SC301IOT,struct i2c_client * client)2062 static int SC301IOT_check_sensor_id(struct SC301IOT *SC301IOT,
2063 struct i2c_client *client)
2064 {
2065 struct device *dev = &SC301IOT->client->dev;
2066 u32 id = 0;
2067 int ret;
2068
2069 if (SC301IOT->is_thunderboot) {
2070 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
2071 return 0;
2072 }
2073
2074 ret = SC301IOT_read_reg(client, SC301IOT_REG_CHIP_ID,
2075 SC301IOT_REG_VALUE_16BIT, &id);
2076 if (id != CHIP_ID) {
2077 dev_err(dev, "Unexpected chip id(0x%04x), ret(%d)\n", id, ret);
2078 return -ENODEV;
2079 }
2080
2081 dev_info(dev, "Detected chip id (0x%04x)\n", id);
2082
2083 return 0;
2084 }
2085
SC301IOT_configure_regulators(struct SC301IOT * SC301IOT)2086 static int SC301IOT_configure_regulators(struct SC301IOT *SC301IOT)
2087 {
2088 unsigned int i;
2089
2090 for (i = 0; i < SC301IOT_NUM_SUPPLIES; i++)
2091 SC301IOT->supplies[i].supply = SC301IOT_supply_names[i];
2092
2093 return devm_regulator_bulk_get(&SC301IOT->client->dev,
2094 SC301IOT_NUM_SUPPLIES,
2095 SC301IOT->supplies);
2096 }
2097
SC301IOT_probe(struct i2c_client * client,const struct i2c_device_id * id)2098 static int SC301IOT_probe(struct i2c_client *client,
2099 const struct i2c_device_id *id)
2100 {
2101 struct device *dev = &client->dev;
2102 struct device_node *node = dev->of_node;
2103 struct SC301IOT *SC301IOT;
2104 struct v4l2_subdev *sd;
2105 char facing[2];
2106 int ret;
2107 u32 i, hdr_mode = 0;
2108 const char *sync_mode_name = NULL;
2109
2110 dev_info(dev, "driver version: %02x.%02x.%02x",
2111 DRIVER_VERSION >> 16,
2112 (DRIVER_VERSION & 0xff00) >> 8,
2113 DRIVER_VERSION & 0x00ff);
2114
2115 SC301IOT = devm_kzalloc(dev, sizeof(*SC301IOT), GFP_KERNEL);
2116 if (!SC301IOT)
2117 return -ENOMEM;
2118
2119 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2120 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2121 &SC301IOT->module_index);
2122 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2123 &SC301IOT->module_facing);
2124 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2125 &SC301IOT->module_name);
2126 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2127 &SC301IOT->len_name);
2128 if (ret) {
2129 dev_err(dev, "could not get module information!\n");
2130 return -EINVAL;
2131 }
2132
2133 SC301IOT->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
2134 SC301IOT->sync_mode = NO_SYNC_MODE;
2135 ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE, &sync_mode_name);
2136 if (!ret) {
2137 if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0)
2138 SC301IOT->sync_mode = EXTERNAL_MASTER_MODE;
2139 else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0)
2140 SC301IOT->sync_mode = INTERNAL_MASTER_MODE;
2141 else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0)
2142 SC301IOT->sync_mode = SLAVE_MODE;
2143 }
2144
2145 switch (SC301IOT->sync_mode) {
2146 default:
2147 SC301IOT->sync_mode = NO_SYNC_MODE; break;
2148 case NO_SYNC_MODE:
2149 dev_info(dev, "sync_mode = [NO_SYNC_MODE]\n"); break;
2150 case EXTERNAL_MASTER_MODE:
2151 case INTERNAL_MASTER_MODE:
2152 dev_info(dev, "sync_mode = [MASTER_MODE]\n"); break;
2153 case SLAVE_MODE:
2154 dev_info(dev, "sync_mode = [SLAVE_MODE]\n"); break;
2155 }
2156
2157 SC301IOT->client = client;
2158 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
2159 if (hdr_mode == supported_modes[i].hdr_mode) {
2160 SC301IOT->cur_mode = &supported_modes[i];
2161 break;
2162 }
2163 }
2164 if (i == ARRAY_SIZE(supported_modes))
2165 SC301IOT->cur_mode = &supported_modes[0];
2166
2167 SC301IOT->xvclk = devm_clk_get(dev, "xvclk");
2168 if (IS_ERR(SC301IOT->xvclk)) {
2169 dev_err(dev, "Failed to get xvclk\n");
2170 return -EINVAL;
2171 }
2172
2173 if (SC301IOT->is_thunderboot) {
2174 SC301IOT->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
2175 if (IS_ERR(SC301IOT->reset_gpio))
2176 dev_warn(dev, "Failed to get reset-gpios\n");
2177
2178 SC301IOT->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
2179 if (IS_ERR(SC301IOT->pwdn_gpio))
2180 dev_warn(dev, "Failed to get pwdn-gpios\n");
2181 } else {
2182 SC301IOT->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2183 if (IS_ERR(SC301IOT->reset_gpio))
2184 dev_warn(dev, "Failed to get reset-gpios\n");
2185
2186 SC301IOT->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2187 if (IS_ERR(SC301IOT->pwdn_gpio))
2188 dev_warn(dev, "Failed to get pwdn-gpios\n");
2189 }
2190
2191 SC301IOT->pinctrl = devm_pinctrl_get(dev);
2192 if (!IS_ERR(SC301IOT->pinctrl)) {
2193 SC301IOT->pins_default =
2194 pinctrl_lookup_state(SC301IOT->pinctrl,
2195 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2196 if (IS_ERR(SC301IOT->pins_default))
2197 dev_err(dev, "could not get default pinstate\n");
2198
2199 SC301IOT->pins_sleep =
2200 pinctrl_lookup_state(SC301IOT->pinctrl,
2201 OF_CAMERA_PINCTRL_STATE_SLEEP);
2202 if (IS_ERR(SC301IOT->pins_sleep))
2203 dev_err(dev, "could not get sleep pinstate\n");
2204 } else {
2205 dev_err(dev, "no pinctrl\n");
2206 }
2207
2208 ret = SC301IOT_configure_regulators(SC301IOT);
2209 if (ret) {
2210 dev_err(dev, "Failed to get power regulators\n");
2211 return ret;
2212 }
2213
2214 mutex_init(&SC301IOT->mutex);
2215
2216 sd = &SC301IOT->subdev;
2217 v4l2_i2c_subdev_init(sd, client, &SC301IOT_subdev_ops);
2218 ret = SC301IOT_initialize_controls(SC301IOT);
2219 if (ret)
2220 goto err_destroy_mutex;
2221
2222 ret = __SC301IOT_power_on(SC301IOT);
2223 if (ret)
2224 goto err_free_handler;
2225
2226 ret = SC301IOT_check_sensor_id(SC301IOT, client);
2227 if (ret)
2228 goto err_power_off;
2229
2230 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2231 sd->internal_ops = &SC301IOT_internal_ops;
2232 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2233 V4L2_SUBDEV_FL_HAS_EVENTS;
2234 #endif
2235 #if defined(CONFIG_MEDIA_CONTROLLER)
2236 SC301IOT->pad.flags = MEDIA_PAD_FL_SOURCE;
2237 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2238 ret = media_entity_pads_init(&sd->entity, 1, &SC301IOT->pad);
2239 if (ret < 0)
2240 goto err_power_off;
2241 #endif
2242
2243 memset(facing, 0, sizeof(facing));
2244 if (strcmp(SC301IOT->module_facing, "back") == 0)
2245 facing[0] = 'b';
2246 else
2247 facing[0] = 'f';
2248
2249 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2250 SC301IOT->module_index, facing,
2251 SC301IOT_NAME, dev_name(sd->dev));
2252 ret = v4l2_async_register_subdev_sensor_common(sd);
2253 if (ret) {
2254 dev_err(dev, "v4l2 async register subdev failed\n");
2255 goto err_clean_entity;
2256 }
2257
2258 pm_runtime_set_active(dev);
2259 pm_runtime_enable(dev);
2260 pm_runtime_idle(dev);
2261
2262 return 0;
2263
2264 err_clean_entity:
2265 #if defined(CONFIG_MEDIA_CONTROLLER)
2266 media_entity_cleanup(&sd->entity);
2267 #endif
2268 err_power_off:
2269 __SC301IOT_power_off(SC301IOT);
2270 err_free_handler:
2271 v4l2_ctrl_handler_free(&SC301IOT->ctrl_handler);
2272 err_destroy_mutex:
2273 mutex_destroy(&SC301IOT->mutex);
2274
2275 return ret;
2276 }
2277
SC301IOT_remove(struct i2c_client * client)2278 static int SC301IOT_remove(struct i2c_client *client)
2279 {
2280 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2281 struct SC301IOT *SC301IOT = to_SC301IOT(sd);
2282
2283 v4l2_async_unregister_subdev(sd);
2284 #if defined(CONFIG_MEDIA_CONTROLLER)
2285 media_entity_cleanup(&sd->entity);
2286 #endif
2287 v4l2_ctrl_handler_free(&SC301IOT->ctrl_handler);
2288 mutex_destroy(&SC301IOT->mutex);
2289
2290 pm_runtime_disable(&client->dev);
2291 if (!pm_runtime_status_suspended(&client->dev))
2292 __SC301IOT_power_off(SC301IOT);
2293 pm_runtime_set_suspended(&client->dev);
2294
2295 return 0;
2296 }
2297
2298 #if IS_ENABLED(CONFIG_OF)
2299 static const struct of_device_id SC301IOT_of_match[] = {
2300 { .compatible = "smartsens,SC301IOT" },
2301 {},
2302 };
2303 MODULE_DEVICE_TABLE(of, SC301IOT_of_match);
2304 #endif
2305
2306 static const struct i2c_device_id SC301IOT_match_id[] = {
2307 { "smartsens,SC301IOT", 0 },
2308 { },
2309 };
2310
2311 static struct i2c_driver SC301IOT_i2c_driver = {
2312 .driver = {
2313 .name = SC301IOT_NAME,
2314 .pm = &SC301IOT_pm_ops,
2315 .of_match_table = of_match_ptr(SC301IOT_of_match),
2316 },
2317 .probe = &SC301IOT_probe,
2318 .remove = &SC301IOT_remove,
2319 .id_table = SC301IOT_match_id,
2320 };
2321
sensor_mod_init(void)2322 static int __init sensor_mod_init(void)
2323 {
2324 return i2c_add_driver(&SC301IOT_i2c_driver);
2325 }
2326
sensor_mod_exit(void)2327 static void __exit sensor_mod_exit(void)
2328 {
2329 i2c_del_driver(&SC301IOT_i2c_driver);
2330 }
2331
2332 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
2333 subsys_initcall(sensor_mod_init);
2334 #else
2335 device_initcall_sync(sensor_mod_init);
2336 #endif
2337 module_exit(sensor_mod_exit);
2338
2339 MODULE_DESCRIPTION("smartsens SC301IOT sensor driver");
2340 MODULE_LICENSE("GPL");
2341