xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/sc2336.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * sc2336 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * V0.0X01.0X01 first version
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun //#define DEBUG
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <linux/sysfs.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/version.h>
22*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
23*4882a593Smuzhiyun #include <linux/rk-preisp.h>
24*4882a593Smuzhiyun #include <media/media-entity.h>
25*4882a593Smuzhiyun #include <media/v4l2-async.h>
26*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
27*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
28*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
29*4882a593Smuzhiyun #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x01)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
34*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define SC2336_LANES			2
38*4882a593Smuzhiyun #define SC2336_BITS_PER_SAMPLE		10
39*4882a593Smuzhiyun #define SC2336_LINK_FREQ_405		202500000
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define PIXEL_RATE_WITH_405M_10BIT	(SC2336_LINK_FREQ_405 * 2 * \
42*4882a593Smuzhiyun 					SC2336_LANES / SC2336_BITS_PER_SAMPLE)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define CHIP_ID				0xcb3a
45*4882a593Smuzhiyun #define SC2336_REG_CHIP_ID		0x3107
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define SC2336_REG_CTRL_MODE		0x0100
48*4882a593Smuzhiyun #define SC2336_MODE_SW_STANDBY		0x0
49*4882a593Smuzhiyun #define SC2336_MODE_STREAMING		BIT(0)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define SC2336_REG_EXPOSURE_H		0x3e00
52*4882a593Smuzhiyun #define SC2336_REG_EXPOSURE_M		0x3e01
53*4882a593Smuzhiyun #define SC2336_REG_EXPOSURE_L		0x3e02
54*4882a593Smuzhiyun #define	SC2336_EXPOSURE_MIN		1
55*4882a593Smuzhiyun #define	SC2336_EXPOSURE_STEP		1
56*4882a593Smuzhiyun #define SC2336_VTS_MAX			0x7fff
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define SC2336_REG_DIG_GAIN		0x3e06
59*4882a593Smuzhiyun #define SC2336_REG_DIG_FINE_GAIN	0x3e07
60*4882a593Smuzhiyun #define SC2336_REG_ANA_GAIN		0x3e09
61*4882a593Smuzhiyun #define SC2336_GAIN_MIN			0x0020
62*4882a593Smuzhiyun #define SC2336_GAIN_MAX			(4096)	//32*4*32
63*4882a593Smuzhiyun #define SC2336_GAIN_STEP		1
64*4882a593Smuzhiyun #define SC2336_GAIN_DEFAULT		0x80
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define SC2336_REG_GROUP_HOLD		0x3812
68*4882a593Smuzhiyun #define SC2336_GROUP_HOLD_START		0x00
69*4882a593Smuzhiyun #define SC2336_GROUP_HOLD_END		0x30
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define SC2336_REG_TEST_PATTERN		0x4501
72*4882a593Smuzhiyun #define SC2336_TEST_PATTERN_BIT_MASK	BIT(3)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define SC2336_REG_VTS_H		0x320e
75*4882a593Smuzhiyun #define SC2336_REG_VTS_L		0x320f
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define SC2336_FLIP_MIRROR_REG		0x3221
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define SC2336_FETCH_EXP_H(VAL)		(((VAL) >> 12) & 0xF)
80*4882a593Smuzhiyun #define SC2336_FETCH_EXP_M(VAL)		(((VAL) >> 4) & 0xFF)
81*4882a593Smuzhiyun #define SC2336_FETCH_EXP_L(VAL)		(((VAL) & 0xF) << 4)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define SC2336_FETCH_AGAIN_H(VAL)	(((VAL) >> 8) & 0x03)
84*4882a593Smuzhiyun #define SC2336_FETCH_AGAIN_L(VAL)	((VAL) & 0xFF)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define SC2336_FETCH_MIRROR(VAL, ENABLE)	(ENABLE ? VAL | 0x06 : VAL & 0xf9)
87*4882a593Smuzhiyun #define SC2336_FETCH_FLIP(VAL, ENABLE)		(ENABLE ? VAL | 0x60 : VAL & 0x9f)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define REG_DELAY			0xFFFE
90*4882a593Smuzhiyun #define REG_NULL			0xFFFF
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define SC2336_REG_VALUE_08BIT		1
93*4882a593Smuzhiyun #define SC2336_REG_VALUE_16BIT		2
94*4882a593Smuzhiyun #define SC2336_REG_VALUE_24BIT		3
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT	"rockchip,camera_default"
97*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP	"rockchip,camera_sleep"
98*4882a593Smuzhiyun #define SC2336_NAME			"sc2336"
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun static const char * const sc2336_supply_names[] = {
101*4882a593Smuzhiyun 	"avdd",		/* Analog power */
102*4882a593Smuzhiyun 	"dovdd",	/* Digital I/O power */
103*4882a593Smuzhiyun 	"dvdd",		/* Digital core power */
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define SC2336_NUM_SUPPLIES ARRAY_SIZE(sc2336_supply_names)
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun struct regval {
109*4882a593Smuzhiyun 	u16 addr;
110*4882a593Smuzhiyun 	u8 val;
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun struct sc2336_mode {
114*4882a593Smuzhiyun 	u32 bus_fmt;
115*4882a593Smuzhiyun 	u32 width;
116*4882a593Smuzhiyun 	u32 height;
117*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
118*4882a593Smuzhiyun 	u32 hts_def;
119*4882a593Smuzhiyun 	u32 vts_def;
120*4882a593Smuzhiyun 	u32 exp_def;
121*4882a593Smuzhiyun 	const struct regval *reg_list;
122*4882a593Smuzhiyun 	u32 hdr_mode;
123*4882a593Smuzhiyun 	u32 xvclk_freq;
124*4882a593Smuzhiyun 	u32 link_freq_idx;
125*4882a593Smuzhiyun 	u32 vc[PAD_MAX];
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun struct sc2336 {
129*4882a593Smuzhiyun 	struct i2c_client	*client;
130*4882a593Smuzhiyun 	struct clk		*xvclk;
131*4882a593Smuzhiyun 	struct gpio_desc	*reset_gpio;
132*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[SC2336_NUM_SUPPLIES];
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	struct pinctrl		*pinctrl;
135*4882a593Smuzhiyun 	struct pinctrl_state	*pins_default;
136*4882a593Smuzhiyun 	struct pinctrl_state	*pins_sleep;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	struct v4l2_subdev	subdev;
139*4882a593Smuzhiyun 	struct media_pad	pad;
140*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
141*4882a593Smuzhiyun 	struct v4l2_ctrl	*exposure;
142*4882a593Smuzhiyun 	struct v4l2_ctrl	*anal_gain;
143*4882a593Smuzhiyun 	struct v4l2_ctrl	*digi_gain;
144*4882a593Smuzhiyun 	struct v4l2_ctrl	*hblank;
145*4882a593Smuzhiyun 	struct v4l2_ctrl	*vblank;
146*4882a593Smuzhiyun 	struct v4l2_ctrl	*pixel_rate;
147*4882a593Smuzhiyun 	struct v4l2_ctrl	*link_freq;
148*4882a593Smuzhiyun 	struct v4l2_ctrl	*test_pattern;
149*4882a593Smuzhiyun 	struct mutex		mutex;
150*4882a593Smuzhiyun 	bool			streaming;
151*4882a593Smuzhiyun 	bool			power_on;
152*4882a593Smuzhiyun 	const struct sc2336_mode *cur_mode;
153*4882a593Smuzhiyun 	u32			module_index;
154*4882a593Smuzhiyun 	const char		*module_facing;
155*4882a593Smuzhiyun 	const char		*module_name;
156*4882a593Smuzhiyun 	const char		*len_name;
157*4882a593Smuzhiyun 	u32			cur_vts;
158*4882a593Smuzhiyun 	bool			has_init_exp;
159*4882a593Smuzhiyun 	bool			is_thunderboot;
160*4882a593Smuzhiyun 	bool			is_first_streamoff;
161*4882a593Smuzhiyun 	struct preisp_hdrae_exp_s init_hdrae_exp;
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define to_sc2336(sd) container_of(sd, struct sc2336, subdev)
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun  * Xclk 24Mhz
168*4882a593Smuzhiyun  */
169*4882a593Smuzhiyun static const struct regval sc2336_global_regs[] = {
170*4882a593Smuzhiyun 	{REG_NULL, 0x00},
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun  * Xclk 24Mhz
175*4882a593Smuzhiyun  * max_framerate 30fps
176*4882a593Smuzhiyun  * mipi_datarate per lane 405Mbps, 2lane
177*4882a593Smuzhiyun  */
178*4882a593Smuzhiyun static const struct regval sc2336_linear_10_1920x1080_30fps_regs[] = {
179*4882a593Smuzhiyun 	{0x0103, 0x01},
180*4882a593Smuzhiyun 	{0x0100, 0x00},
181*4882a593Smuzhiyun 	{0x36e9, 0x80},
182*4882a593Smuzhiyun 	{0x37f9, 0x80},
183*4882a593Smuzhiyun 	{0x301f, 0x02},
184*4882a593Smuzhiyun 	{0x3106, 0x05},
185*4882a593Smuzhiyun 	{0x320c, 0x08},
186*4882a593Smuzhiyun 	{0x320d, 0xca},
187*4882a593Smuzhiyun 	{0x320e, 0x04},
188*4882a593Smuzhiyun 	{0x320f, 0xb0},
189*4882a593Smuzhiyun 	{0x3248, 0x04},
190*4882a593Smuzhiyun 	{0x3249, 0x0b},
191*4882a593Smuzhiyun 	{0x3253, 0x08},
192*4882a593Smuzhiyun 	{0x3301, 0x09},
193*4882a593Smuzhiyun 	{0x3302, 0xff},
194*4882a593Smuzhiyun 	{0x3303, 0x10},
195*4882a593Smuzhiyun 	{0x3306, 0x60},
196*4882a593Smuzhiyun 	{0x3307, 0x02},
197*4882a593Smuzhiyun 	{0x330a, 0x01},
198*4882a593Smuzhiyun 	{0x330b, 0x10},
199*4882a593Smuzhiyun 	{0x330c, 0x16},
200*4882a593Smuzhiyun 	{0x330d, 0xff},
201*4882a593Smuzhiyun 	{0x3318, 0x02},
202*4882a593Smuzhiyun 	{0x3321, 0x0a},
203*4882a593Smuzhiyun 	{0x3327, 0x0e},
204*4882a593Smuzhiyun 	{0x332b, 0x12},
205*4882a593Smuzhiyun 	{0x3333, 0x10},
206*4882a593Smuzhiyun 	{0x3334, 0x40},
207*4882a593Smuzhiyun 	{0x335e, 0x06},
208*4882a593Smuzhiyun 	{0x335f, 0x0a},
209*4882a593Smuzhiyun 	{0x3364, 0x1f},
210*4882a593Smuzhiyun 	{0x337c, 0x02},
211*4882a593Smuzhiyun 	{0x337d, 0x0e},
212*4882a593Smuzhiyun 	{0x3390, 0x09},
213*4882a593Smuzhiyun 	{0x3391, 0x0f},
214*4882a593Smuzhiyun 	{0x3392, 0x1f},
215*4882a593Smuzhiyun 	{0x3393, 0x20},
216*4882a593Smuzhiyun 	{0x3394, 0x20},
217*4882a593Smuzhiyun 	{0x3395, 0xff},
218*4882a593Smuzhiyun 	{0x33a2, 0x04},
219*4882a593Smuzhiyun 	{0x33b1, 0x80},
220*4882a593Smuzhiyun 	{0x33b2, 0x68},
221*4882a593Smuzhiyun 	{0x33b3, 0x42},
222*4882a593Smuzhiyun 	{0x33f9, 0x70},
223*4882a593Smuzhiyun 	{0x33fb, 0xd0},
224*4882a593Smuzhiyun 	{0x33fc, 0x0f},
225*4882a593Smuzhiyun 	{0x33fd, 0x1f},
226*4882a593Smuzhiyun 	{0x349f, 0x03},
227*4882a593Smuzhiyun 	{0x34a6, 0x0f},
228*4882a593Smuzhiyun 	{0x34a7, 0x1f},
229*4882a593Smuzhiyun 	{0x34a8, 0x42},
230*4882a593Smuzhiyun 	{0x34a9, 0x06},
231*4882a593Smuzhiyun 	{0x34aa, 0x01},
232*4882a593Smuzhiyun 	{0x34ab, 0x23},
233*4882a593Smuzhiyun 	{0x34ac, 0x01},
234*4882a593Smuzhiyun 	{0x34ad, 0x84},
235*4882a593Smuzhiyun 	{0x3630, 0xf4},
236*4882a593Smuzhiyun 	{0x3633, 0x22},
237*4882a593Smuzhiyun 	{0x3639, 0xf4},
238*4882a593Smuzhiyun 	{0x363c, 0x47},
239*4882a593Smuzhiyun 	{0x3670, 0x09},
240*4882a593Smuzhiyun 	{0x3674, 0xf4},
241*4882a593Smuzhiyun 	{0x3675, 0xfb},
242*4882a593Smuzhiyun 	{0x3676, 0xed},
243*4882a593Smuzhiyun 	{0x367c, 0x09},
244*4882a593Smuzhiyun 	{0x367d, 0x0f},
245*4882a593Smuzhiyun 	{0x3690, 0x33},
246*4882a593Smuzhiyun 	{0x3691, 0x33},
247*4882a593Smuzhiyun 	{0x3692, 0x43},
248*4882a593Smuzhiyun 	{0x3698, 0x89},
249*4882a593Smuzhiyun 	{0x3699, 0x96},
250*4882a593Smuzhiyun 	{0x369a, 0xd0},
251*4882a593Smuzhiyun 	{0x369b, 0xd0},
252*4882a593Smuzhiyun 	{0x369c, 0x09},
253*4882a593Smuzhiyun 	{0x369d, 0x0f},
254*4882a593Smuzhiyun 	{0x36a2, 0x09},
255*4882a593Smuzhiyun 	{0x36a3, 0x0f},
256*4882a593Smuzhiyun 	{0x36a4, 0x1f},
257*4882a593Smuzhiyun 	{0x36d0, 0x01},
258*4882a593Smuzhiyun 	{0x36ea, 0x09},
259*4882a593Smuzhiyun 	{0x36eb, 0x0c},
260*4882a593Smuzhiyun 	{0x36ec, 0x1c},
261*4882a593Smuzhiyun 	{0x36ed, 0x28},
262*4882a593Smuzhiyun 	{0x3722, 0xe1},
263*4882a593Smuzhiyun 	{0x3724, 0x41},
264*4882a593Smuzhiyun 	{0x3725, 0xc1},
265*4882a593Smuzhiyun 	{0x3728, 0x20},
266*4882a593Smuzhiyun 	{0x37fa, 0x09},
267*4882a593Smuzhiyun 	{0x37fb, 0x32},
268*4882a593Smuzhiyun 	{0x37fc, 0x11},
269*4882a593Smuzhiyun 	{0x37fd, 0x37},
270*4882a593Smuzhiyun 	{0x3900, 0x0d},
271*4882a593Smuzhiyun 	{0x3905, 0x98},
272*4882a593Smuzhiyun 	{0x391b, 0x81},
273*4882a593Smuzhiyun 	{0x391c, 0x10},
274*4882a593Smuzhiyun 	{0x3933, 0x81},
275*4882a593Smuzhiyun 	{0x3934, 0xc5},
276*4882a593Smuzhiyun 	{0x3940, 0x68},
277*4882a593Smuzhiyun 	{0x3941, 0x00},
278*4882a593Smuzhiyun 	{0x3942, 0x01},
279*4882a593Smuzhiyun 	{0x3943, 0xc6},
280*4882a593Smuzhiyun 	{0x3952, 0x02},
281*4882a593Smuzhiyun 	{0x3953, 0x0f},
282*4882a593Smuzhiyun 	{0x3e01, 0x4a},
283*4882a593Smuzhiyun 	{0x3e02, 0xa0},
284*4882a593Smuzhiyun 	{0x3e08, 0x1f},
285*4882a593Smuzhiyun 	{0x3e1b, 0x14},
286*4882a593Smuzhiyun 	{0x440e, 0x02},
287*4882a593Smuzhiyun 	{0x4509, 0x38},
288*4882a593Smuzhiyun 	{0x4819, 0x06},
289*4882a593Smuzhiyun 	{0x481b, 0x03},
290*4882a593Smuzhiyun 	{0x481d, 0x0b},
291*4882a593Smuzhiyun 	{0x481f, 0x03},
292*4882a593Smuzhiyun 	{0x4821, 0x08},
293*4882a593Smuzhiyun 	{0x4823, 0x03},
294*4882a593Smuzhiyun 	{0x4825, 0x03},
295*4882a593Smuzhiyun 	{0x4827, 0x03},
296*4882a593Smuzhiyun 	{0x4829, 0x05},
297*4882a593Smuzhiyun 	{0x5799, 0x06},
298*4882a593Smuzhiyun 	{0x5ae0, 0xfe},
299*4882a593Smuzhiyun 	{0x5ae1, 0x40},
300*4882a593Smuzhiyun 	{0x5ae2, 0x30},
301*4882a593Smuzhiyun 	{0x5ae3, 0x28},
302*4882a593Smuzhiyun 	{0x5ae4, 0x20},
303*4882a593Smuzhiyun 	{0x5ae5, 0x30},
304*4882a593Smuzhiyun 	{0x5ae6, 0x28},
305*4882a593Smuzhiyun 	{0x5ae7, 0x20},
306*4882a593Smuzhiyun 	{0x5ae8, 0x3c},
307*4882a593Smuzhiyun 	{0x5ae9, 0x30},
308*4882a593Smuzhiyun 	{0x5aea, 0x28},
309*4882a593Smuzhiyun 	{0x5aeb, 0x3c},
310*4882a593Smuzhiyun 	{0x5aec, 0x30},
311*4882a593Smuzhiyun 	{0x5aed, 0x28},
312*4882a593Smuzhiyun 	{0x5aee, 0xfe},
313*4882a593Smuzhiyun 	{0x5aef, 0x40},
314*4882a593Smuzhiyun 	{0x5af4, 0x30},
315*4882a593Smuzhiyun 	{0x5af5, 0x28},
316*4882a593Smuzhiyun 	{0x5af6, 0x20},
317*4882a593Smuzhiyun 	{0x5af7, 0x30},
318*4882a593Smuzhiyun 	{0x5af8, 0x28},
319*4882a593Smuzhiyun 	{0x5af9, 0x20},
320*4882a593Smuzhiyun 	{0x5afa, 0x3c},
321*4882a593Smuzhiyun 	{0x5afb, 0x30},
322*4882a593Smuzhiyun 	{0x5afc, 0x28},
323*4882a593Smuzhiyun 	{0x5afd, 0x3c},
324*4882a593Smuzhiyun 	{0x5afe, 0x30},
325*4882a593Smuzhiyun 	{0x5aff, 0x28},
326*4882a593Smuzhiyun 	{0x36e9, 0x53},
327*4882a593Smuzhiyun 	{0x37f9, 0x53},
328*4882a593Smuzhiyun 	{REG_NULL, 0x00},
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun static const struct sc2336_mode supported_modes[] = {
332*4882a593Smuzhiyun 	{
333*4882a593Smuzhiyun 		.width = 1920,
334*4882a593Smuzhiyun 		.height = 1080,
335*4882a593Smuzhiyun 		.max_fps = {
336*4882a593Smuzhiyun 			.numerator = 10000,
337*4882a593Smuzhiyun 			.denominator = 300000,
338*4882a593Smuzhiyun 		},
339*4882a593Smuzhiyun 		.exp_def = 0x080,
340*4882a593Smuzhiyun 		.hts_def = 0x08ca,
341*4882a593Smuzhiyun 		.vts_def = 0x04b0,
342*4882a593Smuzhiyun 		.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
343*4882a593Smuzhiyun 		.reg_list = sc2336_linear_10_1920x1080_30fps_regs,
344*4882a593Smuzhiyun 		.hdr_mode = NO_HDR,
345*4882a593Smuzhiyun 		.xvclk_freq = 24000000,
346*4882a593Smuzhiyun 		.link_freq_idx = 0,
347*4882a593Smuzhiyun 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
348*4882a593Smuzhiyun 	},
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
352*4882a593Smuzhiyun 	SC2336_LINK_FREQ_405,
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static const char * const sc2336_test_pattern_menu[] = {
356*4882a593Smuzhiyun 	"Disabled",
357*4882a593Smuzhiyun 	"Vertical Color Bar Type 1",
358*4882a593Smuzhiyun 	"Vertical Color Bar Type 2",
359*4882a593Smuzhiyun 	"Vertical Color Bar Type 3",
360*4882a593Smuzhiyun 	"Vertical Color Bar Type 4",
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun /* Write registers up to 4 at a time */
sc2336_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)364*4882a593Smuzhiyun static int sc2336_write_reg(struct i2c_client *client, u16 reg,
365*4882a593Smuzhiyun 			    u32 len, u32 val)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	u32 buf_i, val_i;
368*4882a593Smuzhiyun 	u8 buf[6];
369*4882a593Smuzhiyun 	u8 *val_p;
370*4882a593Smuzhiyun 	__be32 val_be;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (len > 4)
373*4882a593Smuzhiyun 		return -EINVAL;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	buf[0] = reg >> 8;
376*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	val_be = cpu_to_be32(val);
379*4882a593Smuzhiyun 	val_p = (u8 *)&val_be;
380*4882a593Smuzhiyun 	buf_i = 2;
381*4882a593Smuzhiyun 	val_i = 4 - len;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	while (val_i < 4)
384*4882a593Smuzhiyun 		buf[buf_i++] = val_p[val_i++];
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2)
387*4882a593Smuzhiyun 		return -EIO;
388*4882a593Smuzhiyun 	return 0;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun 
sc2336_write_array(struct i2c_client * client,const struct regval * regs)391*4882a593Smuzhiyun static int sc2336_write_array(struct i2c_client *client,
392*4882a593Smuzhiyun 			       const struct regval *regs)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	u32 i;
395*4882a593Smuzhiyun 	int ret = 0;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
398*4882a593Smuzhiyun 		ret = sc2336_write_reg(client, regs[i].addr,
399*4882a593Smuzhiyun 					SC2336_REG_VALUE_08BIT, regs[i].val);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	return ret;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun /* Read registers up to 4 at a time */
sc2336_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)405*4882a593Smuzhiyun static int sc2336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
406*4882a593Smuzhiyun 			    u32 *val)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
409*4882a593Smuzhiyun 	u8 *data_be_p;
410*4882a593Smuzhiyun 	__be32 data_be = 0;
411*4882a593Smuzhiyun 	__be16 reg_addr_be = cpu_to_be16(reg);
412*4882a593Smuzhiyun 	int ret;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	if (len > 4 || !len)
415*4882a593Smuzhiyun 		return -EINVAL;
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	data_be_p = (u8 *)&data_be;
418*4882a593Smuzhiyun 	/* Write register address */
419*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
420*4882a593Smuzhiyun 	msgs[0].flags = 0;
421*4882a593Smuzhiyun 	msgs[0].len = 2;
422*4882a593Smuzhiyun 	msgs[0].buf = (u8 *)&reg_addr_be;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* Read data from register */
425*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
426*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
427*4882a593Smuzhiyun 	msgs[1].len = len;
428*4882a593Smuzhiyun 	msgs[1].buf = &data_be_p[4 - len];
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
431*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
432*4882a593Smuzhiyun 		return -EIO;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	*val = be32_to_cpu(data_be);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	return 0;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun 
sc2336_set_gain_reg(struct sc2336 * sc2336,u32 gain)439*4882a593Smuzhiyun static int sc2336_set_gain_reg(struct sc2336 *sc2336, u32 gain)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun 	u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
442*4882a593Smuzhiyun 	u32 gain_factor;
443*4882a593Smuzhiyun 	int ret = 0;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	gain_factor = gain * 1000 / 32;
446*4882a593Smuzhiyun 	if (gain_factor < 1000) {
447*4882a593Smuzhiyun 		coarse_again = 0x00;
448*4882a593Smuzhiyun 		coarse_dgain = 0x00;
449*4882a593Smuzhiyun 		fine_dgain = 0x80;
450*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 2) {			/*1x ~ 2x gain*/
451*4882a593Smuzhiyun 		coarse_again = 0x00;
452*4882a593Smuzhiyun 		coarse_dgain = 0x00;
453*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000;
454*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 4) {			/*2x ~ 4x gain*/
455*4882a593Smuzhiyun 		coarse_again = 0x01;
456*4882a593Smuzhiyun 		coarse_dgain = 0x00;
457*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 2;
458*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 8) {			/*4x ~ 8x gain*/
459*4882a593Smuzhiyun 		coarse_again = 0x03;
460*4882a593Smuzhiyun 		coarse_dgain = 0x00;
461*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 4;
462*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 16) {			/*8x ~ 16x gain*/
463*4882a593Smuzhiyun 		coarse_again = 0x07;
464*4882a593Smuzhiyun 		coarse_dgain = 0x00;
465*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 8;
466*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 32) {			/*16x ~ 32x gain*/
467*4882a593Smuzhiyun 		coarse_again = 0x0f;
468*4882a593Smuzhiyun 		coarse_dgain = 0x00;
469*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 16;
470*4882a593Smuzhiyun 	//open dgain begin  max digital gain 4X
471*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 64) {			/*32x ~ 64x gain*/
472*4882a593Smuzhiyun 		coarse_again = 0x1f;
473*4882a593Smuzhiyun 		coarse_dgain = 0x00;
474*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 32;
475*4882a593Smuzhiyun 	} else if (gain_factor < 1000 * 128) {			/*64x ~ 128x gain*/
476*4882a593Smuzhiyun 		coarse_again = 0x1f;
477*4882a593Smuzhiyun 		coarse_dgain = 0x01;
478*4882a593Smuzhiyun 		fine_dgain = gain_factor * 128 / 1000 / 64;
479*4882a593Smuzhiyun 	} else {						/*max 128x gain*/
480*4882a593Smuzhiyun 		coarse_again = 0x1f;
481*4882a593Smuzhiyun 		coarse_dgain = 0x03;
482*4882a593Smuzhiyun 		fine_dgain = 0x80;
483*4882a593Smuzhiyun 	}
484*4882a593Smuzhiyun 	dev_dbg(&sc2336->client->dev,
485*4882a593Smuzhiyun 		"total_gain: 0x%x, d_gain: 0x%x, d_fine_gain: 0x%x, c_gain: 0x%x\n",
486*4882a593Smuzhiyun 		gain, coarse_dgain, fine_dgain, coarse_again);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	ret = sc2336_write_reg(sc2336->client,
489*4882a593Smuzhiyun 				SC2336_REG_DIG_GAIN,
490*4882a593Smuzhiyun 				SC2336_REG_VALUE_08BIT,
491*4882a593Smuzhiyun 				coarse_dgain);
492*4882a593Smuzhiyun 	ret |= sc2336_write_reg(sc2336->client,
493*4882a593Smuzhiyun 				 SC2336_REG_DIG_FINE_GAIN,
494*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT,
495*4882a593Smuzhiyun 				 fine_dgain);
496*4882a593Smuzhiyun 	ret |= sc2336_write_reg(sc2336->client,
497*4882a593Smuzhiyun 				 SC2336_REG_ANA_GAIN,
498*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT,
499*4882a593Smuzhiyun 				 coarse_again);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	return ret;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
sc2336_get_reso_dist(const struct sc2336_mode * mode,struct v4l2_mbus_framefmt * framefmt)504*4882a593Smuzhiyun static int sc2336_get_reso_dist(const struct sc2336_mode *mode,
505*4882a593Smuzhiyun 				 struct v4l2_mbus_framefmt *framefmt)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun 	return abs(mode->width - framefmt->width) +
508*4882a593Smuzhiyun 	       abs(mode->height - framefmt->height);
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun static const struct sc2336_mode *
sc2336_find_best_fit(struct v4l2_subdev_format * fmt)512*4882a593Smuzhiyun sc2336_find_best_fit(struct v4l2_subdev_format *fmt)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
515*4882a593Smuzhiyun 	int dist;
516*4882a593Smuzhiyun 	int cur_best_fit = 0;
517*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
518*4882a593Smuzhiyun 	unsigned int i;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
521*4882a593Smuzhiyun 		dist = sc2336_get_reso_dist(&supported_modes[i], framefmt);
522*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
523*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
524*4882a593Smuzhiyun 			cur_best_fit = i;
525*4882a593Smuzhiyun 		}
526*4882a593Smuzhiyun 	}
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	return &supported_modes[cur_best_fit];
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
sc2336_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)531*4882a593Smuzhiyun static int sc2336_set_fmt(struct v4l2_subdev *sd,
532*4882a593Smuzhiyun 			   struct v4l2_subdev_pad_config *cfg,
533*4882a593Smuzhiyun 			   struct v4l2_subdev_format *fmt)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
536*4882a593Smuzhiyun 	const struct sc2336_mode *mode;
537*4882a593Smuzhiyun 	s64 h_blank, vblank_def;
538*4882a593Smuzhiyun 	u64 dst_link_freq = 0;
539*4882a593Smuzhiyun 	u64 dst_pixel_rate = 0;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	mutex_lock(&sc2336->mutex);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	mode = sc2336_find_best_fit(fmt);
544*4882a593Smuzhiyun 	fmt->format.code = mode->bus_fmt;
545*4882a593Smuzhiyun 	fmt->format.width = mode->width;
546*4882a593Smuzhiyun 	fmt->format.height = mode->height;
547*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
548*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
549*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
550*4882a593Smuzhiyun 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
551*4882a593Smuzhiyun #else
552*4882a593Smuzhiyun 		mutex_unlock(&sc2336->mutex);
553*4882a593Smuzhiyun 		return -ENOTTY;
554*4882a593Smuzhiyun #endif
555*4882a593Smuzhiyun 	} else {
556*4882a593Smuzhiyun 		sc2336->cur_mode = mode;
557*4882a593Smuzhiyun 		h_blank = mode->hts_def - mode->width;
558*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(sc2336->hblank, h_blank,
559*4882a593Smuzhiyun 					 h_blank, 1, h_blank);
560*4882a593Smuzhiyun 		vblank_def = mode->vts_def - mode->height;
561*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(sc2336->vblank, vblank_def,
562*4882a593Smuzhiyun 					 SC2336_VTS_MAX - mode->height,
563*4882a593Smuzhiyun 					 1, vblank_def);
564*4882a593Smuzhiyun 		dst_link_freq = mode->link_freq_idx;
565*4882a593Smuzhiyun 		dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
566*4882a593Smuzhiyun 						 SC2336_BITS_PER_SAMPLE * 2 * SC2336_LANES;
567*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl_int64(sc2336->pixel_rate,
568*4882a593Smuzhiyun 					 dst_pixel_rate);
569*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl(sc2336->link_freq,
570*4882a593Smuzhiyun 				   dst_link_freq);
571*4882a593Smuzhiyun 	}
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	mutex_unlock(&sc2336->mutex);
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	return 0;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
sc2336_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)578*4882a593Smuzhiyun static int sc2336_get_fmt(struct v4l2_subdev *sd,
579*4882a593Smuzhiyun 			   struct v4l2_subdev_pad_config *cfg,
580*4882a593Smuzhiyun 			   struct v4l2_subdev_format *fmt)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
583*4882a593Smuzhiyun 	const struct sc2336_mode *mode = sc2336->cur_mode;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	mutex_lock(&sc2336->mutex);
586*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
587*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
588*4882a593Smuzhiyun 		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
589*4882a593Smuzhiyun #else
590*4882a593Smuzhiyun 		mutex_unlock(&sc2336->mutex);
591*4882a593Smuzhiyun 		return -ENOTTY;
592*4882a593Smuzhiyun #endif
593*4882a593Smuzhiyun 	} else {
594*4882a593Smuzhiyun 		fmt->format.width = mode->width;
595*4882a593Smuzhiyun 		fmt->format.height = mode->height;
596*4882a593Smuzhiyun 		fmt->format.code = mode->bus_fmt;
597*4882a593Smuzhiyun 		fmt->format.field = V4L2_FIELD_NONE;
598*4882a593Smuzhiyun 		/* format info: width/height/data type/virctual channel */
599*4882a593Smuzhiyun 		if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
600*4882a593Smuzhiyun 			fmt->reserved[0] = mode->vc[fmt->pad];
601*4882a593Smuzhiyun 		else
602*4882a593Smuzhiyun 			fmt->reserved[0] = mode->vc[PAD0];
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun 	mutex_unlock(&sc2336->mutex);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
sc2336_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)609*4882a593Smuzhiyun static int sc2336_enum_mbus_code(struct v4l2_subdev *sd,
610*4882a593Smuzhiyun 				  struct v4l2_subdev_pad_config *cfg,
611*4882a593Smuzhiyun 				  struct v4l2_subdev_mbus_code_enum *code)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	if (code->index != 0)
616*4882a593Smuzhiyun 		return -EINVAL;
617*4882a593Smuzhiyun 	code->code = sc2336->cur_mode->bus_fmt;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	return 0;
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun 
sc2336_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)622*4882a593Smuzhiyun static int sc2336_enum_frame_sizes(struct v4l2_subdev *sd,
623*4882a593Smuzhiyun 				    struct v4l2_subdev_pad_config *cfg,
624*4882a593Smuzhiyun 				    struct v4l2_subdev_frame_size_enum *fse)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
627*4882a593Smuzhiyun 		return -EINVAL;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	if (fse->code != supported_modes[0].bus_fmt)
630*4882a593Smuzhiyun 		return -EINVAL;
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	fse->min_width  = supported_modes[fse->index].width;
633*4882a593Smuzhiyun 	fse->max_width  = supported_modes[fse->index].width;
634*4882a593Smuzhiyun 	fse->max_height = supported_modes[fse->index].height;
635*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	return 0;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun 
sc2336_enable_test_pattern(struct sc2336 * sc2336,u32 pattern)640*4882a593Smuzhiyun static int sc2336_enable_test_pattern(struct sc2336 *sc2336, u32 pattern)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun 	u32 val = 0;
643*4882a593Smuzhiyun 	int ret = 0;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	ret = sc2336_read_reg(sc2336->client, SC2336_REG_TEST_PATTERN,
646*4882a593Smuzhiyun 			       SC2336_REG_VALUE_08BIT, &val);
647*4882a593Smuzhiyun 	if (pattern)
648*4882a593Smuzhiyun 		val |= SC2336_TEST_PATTERN_BIT_MASK;
649*4882a593Smuzhiyun 	else
650*4882a593Smuzhiyun 		val &= ~SC2336_TEST_PATTERN_BIT_MASK;
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	ret |= sc2336_write_reg(sc2336->client, SC2336_REG_TEST_PATTERN,
653*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT, val);
654*4882a593Smuzhiyun 	return ret;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun 
sc2336_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)657*4882a593Smuzhiyun static int sc2336_g_frame_interval(struct v4l2_subdev *sd,
658*4882a593Smuzhiyun 				    struct v4l2_subdev_frame_interval *fi)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
661*4882a593Smuzhiyun 	const struct sc2336_mode *mode = sc2336->cur_mode;
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	return 0;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun 
sc2336_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)668*4882a593Smuzhiyun static int sc2336_g_mbus_config(struct v4l2_subdev *sd,
669*4882a593Smuzhiyun 				unsigned int pad_id,
670*4882a593Smuzhiyun 				struct v4l2_mbus_config *config)
671*4882a593Smuzhiyun {
672*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
673*4882a593Smuzhiyun 	const struct sc2336_mode *mode = sc2336->cur_mode;
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	u32 val = 1 << (SC2336_LANES - 1) |
676*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CHANNEL_0 |
677*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	if (mode->hdr_mode != NO_HDR)
680*4882a593Smuzhiyun 		val |= V4L2_MBUS_CSI2_CHANNEL_1;
681*4882a593Smuzhiyun 	if (mode->hdr_mode == HDR_X3)
682*4882a593Smuzhiyun 		val |= V4L2_MBUS_CSI2_CHANNEL_2;
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	config->type = V4L2_MBUS_CSI2_DPHY;
685*4882a593Smuzhiyun 	config->flags = val;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	return 0;
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun 
sc2336_get_module_inf(struct sc2336 * sc2336,struct rkmodule_inf * inf)690*4882a593Smuzhiyun static void sc2336_get_module_inf(struct sc2336 *sc2336,
691*4882a593Smuzhiyun 				   struct rkmodule_inf *inf)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
694*4882a593Smuzhiyun 	strscpy(inf->base.sensor, SC2336_NAME, sizeof(inf->base.sensor));
695*4882a593Smuzhiyun 	strscpy(inf->base.module, sc2336->module_name,
696*4882a593Smuzhiyun 		sizeof(inf->base.module));
697*4882a593Smuzhiyun 	strscpy(inf->base.lens, sc2336->len_name, sizeof(inf->base.lens));
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
sc2336_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)700*4882a593Smuzhiyun static long sc2336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
703*4882a593Smuzhiyun 	struct rkmodule_hdr_cfg *hdr;
704*4882a593Smuzhiyun 	u32 i, h, w;
705*4882a593Smuzhiyun 	long ret = 0;
706*4882a593Smuzhiyun 	u32 stream = 0;
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	switch (cmd) {
709*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
710*4882a593Smuzhiyun 		sc2336_get_module_inf(sc2336, (struct rkmodule_inf *)arg);
711*4882a593Smuzhiyun 		break;
712*4882a593Smuzhiyun 	case RKMODULE_GET_HDR_CFG:
713*4882a593Smuzhiyun 		hdr = (struct rkmodule_hdr_cfg *)arg;
714*4882a593Smuzhiyun 		hdr->esp.mode = HDR_NORMAL_VC;
715*4882a593Smuzhiyun 		hdr->hdr_mode = sc2336->cur_mode->hdr_mode;
716*4882a593Smuzhiyun 		break;
717*4882a593Smuzhiyun 	case RKMODULE_SET_HDR_CFG:
718*4882a593Smuzhiyun 		hdr = (struct rkmodule_hdr_cfg *)arg;
719*4882a593Smuzhiyun 		w = sc2336->cur_mode->width;
720*4882a593Smuzhiyun 		h = sc2336->cur_mode->height;
721*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
722*4882a593Smuzhiyun 			if (w == supported_modes[i].width &&
723*4882a593Smuzhiyun 			    h == supported_modes[i].height &&
724*4882a593Smuzhiyun 			    supported_modes[i].hdr_mode == hdr->hdr_mode) {
725*4882a593Smuzhiyun 				sc2336->cur_mode = &supported_modes[i];
726*4882a593Smuzhiyun 				break;
727*4882a593Smuzhiyun 			}
728*4882a593Smuzhiyun 		}
729*4882a593Smuzhiyun 		if (i == ARRAY_SIZE(supported_modes)) {
730*4882a593Smuzhiyun 			dev_err(&sc2336->client->dev,
731*4882a593Smuzhiyun 				"not find hdr mode:%d %dx%d config\n",
732*4882a593Smuzhiyun 				hdr->hdr_mode, w, h);
733*4882a593Smuzhiyun 			ret = -EINVAL;
734*4882a593Smuzhiyun 		} else {
735*4882a593Smuzhiyun 			w = sc2336->cur_mode->hts_def - sc2336->cur_mode->width;
736*4882a593Smuzhiyun 			h = sc2336->cur_mode->vts_def - sc2336->cur_mode->height;
737*4882a593Smuzhiyun 			__v4l2_ctrl_modify_range(sc2336->hblank, w, w, 1, w);
738*4882a593Smuzhiyun 			__v4l2_ctrl_modify_range(sc2336->vblank, h,
739*4882a593Smuzhiyun 						 SC2336_VTS_MAX - sc2336->cur_mode->height, 1, h);
740*4882a593Smuzhiyun 		}
741*4882a593Smuzhiyun 		break;
742*4882a593Smuzhiyun 	case PREISP_CMD_SET_HDRAE_EXP:
743*4882a593Smuzhiyun 		break;
744*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 		stream = *((u32 *)arg);
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 		if (stream)
749*4882a593Smuzhiyun 			ret = sc2336_write_reg(sc2336->client, SC2336_REG_CTRL_MODE,
750*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT, SC2336_MODE_STREAMING);
751*4882a593Smuzhiyun 		else
752*4882a593Smuzhiyun 			ret = sc2336_write_reg(sc2336->client, SC2336_REG_CTRL_MODE,
753*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT, SC2336_MODE_SW_STANDBY);
754*4882a593Smuzhiyun 		break;
755*4882a593Smuzhiyun 	default:
756*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
757*4882a593Smuzhiyun 		break;
758*4882a593Smuzhiyun 	}
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	return ret;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
sc2336_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)764*4882a593Smuzhiyun static long sc2336_compat_ioctl32(struct v4l2_subdev *sd,
765*4882a593Smuzhiyun 				   unsigned int cmd, unsigned long arg)
766*4882a593Smuzhiyun {
767*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
768*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
769*4882a593Smuzhiyun 	struct rkmodule_hdr_cfg *hdr;
770*4882a593Smuzhiyun 	struct preisp_hdrae_exp_s *hdrae;
771*4882a593Smuzhiyun 	long ret;
772*4882a593Smuzhiyun 	u32 stream = 0;
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	switch (cmd) {
775*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
776*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
777*4882a593Smuzhiyun 		if (!inf) {
778*4882a593Smuzhiyun 			ret = -ENOMEM;
779*4882a593Smuzhiyun 			return ret;
780*4882a593Smuzhiyun 		}
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 		ret = sc2336_ioctl(sd, cmd, inf);
783*4882a593Smuzhiyun 		if (!ret) {
784*4882a593Smuzhiyun 			if (copy_to_user(up, inf, sizeof(*inf)))
785*4882a593Smuzhiyun 				ret = -EFAULT;
786*4882a593Smuzhiyun 		}
787*4882a593Smuzhiyun 		kfree(inf);
788*4882a593Smuzhiyun 		break;
789*4882a593Smuzhiyun 	case RKMODULE_GET_HDR_CFG:
790*4882a593Smuzhiyun 		hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
791*4882a593Smuzhiyun 		if (!hdr) {
792*4882a593Smuzhiyun 			ret = -ENOMEM;
793*4882a593Smuzhiyun 			return ret;
794*4882a593Smuzhiyun 		}
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 		ret = sc2336_ioctl(sd, cmd, hdr);
797*4882a593Smuzhiyun 		if (!ret) {
798*4882a593Smuzhiyun 			if (copy_to_user(up, hdr, sizeof(*hdr)))
799*4882a593Smuzhiyun 				ret = -EFAULT;
800*4882a593Smuzhiyun 		}
801*4882a593Smuzhiyun 		kfree(hdr);
802*4882a593Smuzhiyun 		break;
803*4882a593Smuzhiyun 	case RKMODULE_SET_HDR_CFG:
804*4882a593Smuzhiyun 		hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
805*4882a593Smuzhiyun 		if (!hdr) {
806*4882a593Smuzhiyun 			ret = -ENOMEM;
807*4882a593Smuzhiyun 			return ret;
808*4882a593Smuzhiyun 		}
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 		ret = copy_from_user(hdr, up, sizeof(*hdr));
811*4882a593Smuzhiyun 		if (!ret)
812*4882a593Smuzhiyun 			ret = sc2336_ioctl(sd, cmd, hdr);
813*4882a593Smuzhiyun 		else
814*4882a593Smuzhiyun 			ret = -EFAULT;
815*4882a593Smuzhiyun 		kfree(hdr);
816*4882a593Smuzhiyun 		break;
817*4882a593Smuzhiyun 	case PREISP_CMD_SET_HDRAE_EXP:
818*4882a593Smuzhiyun 		hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
819*4882a593Smuzhiyun 		if (!hdrae) {
820*4882a593Smuzhiyun 			ret = -ENOMEM;
821*4882a593Smuzhiyun 			return ret;
822*4882a593Smuzhiyun 		}
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 		ret = copy_from_user(hdrae, up, sizeof(*hdrae));
825*4882a593Smuzhiyun 		if (!ret)
826*4882a593Smuzhiyun 			ret = sc2336_ioctl(sd, cmd, hdrae);
827*4882a593Smuzhiyun 		else
828*4882a593Smuzhiyun 			ret = -EFAULT;
829*4882a593Smuzhiyun 		kfree(hdrae);
830*4882a593Smuzhiyun 		break;
831*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
832*4882a593Smuzhiyun 		ret = copy_from_user(&stream, up, sizeof(u32));
833*4882a593Smuzhiyun 		if (!ret)
834*4882a593Smuzhiyun 			ret = sc2336_ioctl(sd, cmd, &stream);
835*4882a593Smuzhiyun 		else
836*4882a593Smuzhiyun 			ret = -EFAULT;
837*4882a593Smuzhiyun 		break;
838*4882a593Smuzhiyun 	default:
839*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
840*4882a593Smuzhiyun 		break;
841*4882a593Smuzhiyun 	}
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	return ret;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun #endif
846*4882a593Smuzhiyun 
__sc2336_start_stream(struct sc2336 * sc2336)847*4882a593Smuzhiyun static int __sc2336_start_stream(struct sc2336 *sc2336)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun 	int ret;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	if (!sc2336->is_thunderboot) {
852*4882a593Smuzhiyun 		ret = sc2336_write_array(sc2336->client, sc2336->cur_mode->reg_list);
853*4882a593Smuzhiyun 		if (ret)
854*4882a593Smuzhiyun 			return ret;
855*4882a593Smuzhiyun 		/* In case these controls are set before streaming */
856*4882a593Smuzhiyun 		ret = __v4l2_ctrl_handler_setup(&sc2336->ctrl_handler);
857*4882a593Smuzhiyun 		if (ret)
858*4882a593Smuzhiyun 			return ret;
859*4882a593Smuzhiyun 		if (sc2336->has_init_exp && sc2336->cur_mode->hdr_mode != NO_HDR) {
860*4882a593Smuzhiyun 			ret = sc2336_ioctl(&sc2336->subdev, PREISP_CMD_SET_HDRAE_EXP,
861*4882a593Smuzhiyun 				&sc2336->init_hdrae_exp);
862*4882a593Smuzhiyun 			if (ret) {
863*4882a593Smuzhiyun 				dev_err(&sc2336->client->dev,
864*4882a593Smuzhiyun 					"init exp fail in hdr mode\n");
865*4882a593Smuzhiyun 				return ret;
866*4882a593Smuzhiyun 			}
867*4882a593Smuzhiyun 		}
868*4882a593Smuzhiyun 	}
869*4882a593Smuzhiyun 	ret = sc2336_write_reg(sc2336->client, SC2336_REG_CTRL_MODE,
870*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT, SC2336_MODE_STREAMING);
871*4882a593Smuzhiyun 	return ret;
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun 
__sc2336_stop_stream(struct sc2336 * sc2336)874*4882a593Smuzhiyun static int __sc2336_stop_stream(struct sc2336 *sc2336)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun 	sc2336->has_init_exp = false;
877*4882a593Smuzhiyun 	if (sc2336->is_thunderboot) {
878*4882a593Smuzhiyun 		sc2336->is_first_streamoff = true;
879*4882a593Smuzhiyun 		pm_runtime_put(&sc2336->client->dev);
880*4882a593Smuzhiyun 	}
881*4882a593Smuzhiyun 	return sc2336_write_reg(sc2336->client, SC2336_REG_CTRL_MODE,
882*4882a593Smuzhiyun 				 SC2336_REG_VALUE_08BIT, SC2336_MODE_SW_STANDBY);
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun static int __sc2336_power_on(struct sc2336 *sc2336);
sc2336_s_stream(struct v4l2_subdev * sd,int on)886*4882a593Smuzhiyun static int sc2336_s_stream(struct v4l2_subdev *sd, int on)
887*4882a593Smuzhiyun {
888*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
889*4882a593Smuzhiyun 	struct i2c_client *client = sc2336->client;
890*4882a593Smuzhiyun 	int ret = 0;
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun 	mutex_lock(&sc2336->mutex);
893*4882a593Smuzhiyun 	on = !!on;
894*4882a593Smuzhiyun 	if (on == sc2336->streaming)
895*4882a593Smuzhiyun 		goto unlock_and_return;
896*4882a593Smuzhiyun 	if (on) {
897*4882a593Smuzhiyun 		if (sc2336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
898*4882a593Smuzhiyun 			sc2336->is_thunderboot = false;
899*4882a593Smuzhiyun 			__sc2336_power_on(sc2336);
900*4882a593Smuzhiyun 		}
901*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
902*4882a593Smuzhiyun 		if (ret < 0) {
903*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
904*4882a593Smuzhiyun 			goto unlock_and_return;
905*4882a593Smuzhiyun 		}
906*4882a593Smuzhiyun 		ret = __sc2336_start_stream(sc2336);
907*4882a593Smuzhiyun 		if (ret) {
908*4882a593Smuzhiyun 			v4l2_err(sd, "start stream failed while write regs\n");
909*4882a593Smuzhiyun 			pm_runtime_put(&client->dev);
910*4882a593Smuzhiyun 			goto unlock_and_return;
911*4882a593Smuzhiyun 		}
912*4882a593Smuzhiyun 	} else {
913*4882a593Smuzhiyun 		__sc2336_stop_stream(sc2336);
914*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
915*4882a593Smuzhiyun 	}
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	sc2336->streaming = on;
918*4882a593Smuzhiyun unlock_and_return:
919*4882a593Smuzhiyun 	mutex_unlock(&sc2336->mutex);
920*4882a593Smuzhiyun 	return ret;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
sc2336_s_power(struct v4l2_subdev * sd,int on)923*4882a593Smuzhiyun static int sc2336_s_power(struct v4l2_subdev *sd, int on)
924*4882a593Smuzhiyun {
925*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
926*4882a593Smuzhiyun 	struct i2c_client *client = sc2336->client;
927*4882a593Smuzhiyun 	int ret = 0;
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	mutex_lock(&sc2336->mutex);
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun 	/* If the power state is not modified - no work to do. */
932*4882a593Smuzhiyun 	if (sc2336->power_on == !!on)
933*4882a593Smuzhiyun 		goto unlock_and_return;
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun 	if (on) {
936*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
937*4882a593Smuzhiyun 		if (ret < 0) {
938*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
939*4882a593Smuzhiyun 			goto unlock_and_return;
940*4882a593Smuzhiyun 		}
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 		if (!sc2336->is_thunderboot) {
943*4882a593Smuzhiyun 			ret = sc2336_write_array(sc2336->client, sc2336_global_regs);
944*4882a593Smuzhiyun 			if (ret) {
945*4882a593Smuzhiyun 				v4l2_err(sd, "could not set init registers\n");
946*4882a593Smuzhiyun 				pm_runtime_put_noidle(&client->dev);
947*4882a593Smuzhiyun 				goto unlock_and_return;
948*4882a593Smuzhiyun 			}
949*4882a593Smuzhiyun 		}
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 		sc2336->power_on = true;
952*4882a593Smuzhiyun 	} else {
953*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
954*4882a593Smuzhiyun 		sc2336->power_on = false;
955*4882a593Smuzhiyun 	}
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun unlock_and_return:
958*4882a593Smuzhiyun 	mutex_unlock(&sc2336->mutex);
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 	return ret;
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
sc2336_cal_delay(u32 cycles,struct sc2336 * sc2336)964*4882a593Smuzhiyun static inline u32 sc2336_cal_delay(u32 cycles, struct sc2336 *sc2336)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun 	return DIV_ROUND_UP(cycles, sc2336->cur_mode->xvclk_freq / 1000 / 1000);
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun 
__sc2336_power_on(struct sc2336 * sc2336)969*4882a593Smuzhiyun static int __sc2336_power_on(struct sc2336 *sc2336)
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun 	int ret;
972*4882a593Smuzhiyun 	u32 delay_us;
973*4882a593Smuzhiyun 	struct device *dev = &sc2336->client->dev;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	if (!IS_ERR_OR_NULL(sc2336->pins_default)) {
976*4882a593Smuzhiyun 		ret = pinctrl_select_state(sc2336->pinctrl,
977*4882a593Smuzhiyun 					   sc2336->pins_default);
978*4882a593Smuzhiyun 		if (ret < 0)
979*4882a593Smuzhiyun 			dev_err(dev, "could not set pins\n");
980*4882a593Smuzhiyun 	}
981*4882a593Smuzhiyun 	ret = clk_set_rate(sc2336->xvclk, sc2336->cur_mode->xvclk_freq);
982*4882a593Smuzhiyun 	if (ret < 0)
983*4882a593Smuzhiyun 		dev_warn(dev, "Failed to set xvclk rate (%dHz)\n", sc2336->cur_mode->xvclk_freq);
984*4882a593Smuzhiyun 	if (clk_get_rate(sc2336->xvclk) != sc2336->cur_mode->xvclk_freq)
985*4882a593Smuzhiyun 		dev_warn(dev, "xvclk mismatched, modes are based on %dHz\n",
986*4882a593Smuzhiyun 			 sc2336->cur_mode->xvclk_freq);
987*4882a593Smuzhiyun 	ret = clk_prepare_enable(sc2336->xvclk);
988*4882a593Smuzhiyun 	if (ret < 0) {
989*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable xvclk\n");
990*4882a593Smuzhiyun 		return ret;
991*4882a593Smuzhiyun 	}
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	if (sc2336->is_thunderboot)
994*4882a593Smuzhiyun 		return 0;
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	if (!IS_ERR(sc2336->reset_gpio))
997*4882a593Smuzhiyun 		gpiod_set_value_cansleep(sc2336->reset_gpio, 0);
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	ret = regulator_bulk_enable(SC2336_NUM_SUPPLIES, sc2336->supplies);
1000*4882a593Smuzhiyun 	if (ret < 0) {
1001*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable regulators\n");
1002*4882a593Smuzhiyun 		goto disable_clk;
1003*4882a593Smuzhiyun 	}
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	if (!IS_ERR(sc2336->reset_gpio))
1006*4882a593Smuzhiyun 		gpiod_set_value_cansleep(sc2336->reset_gpio, 1);
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	usleep_range(500, 1000);
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	if (!IS_ERR(sc2336->reset_gpio))
1011*4882a593Smuzhiyun 		usleep_range(6000, 8000);
1012*4882a593Smuzhiyun 	else
1013*4882a593Smuzhiyun 		usleep_range(12000, 16000);
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun 	/* 8192 cycles prior to first SCCB transaction */
1016*4882a593Smuzhiyun 	delay_us = sc2336_cal_delay(8192, sc2336);
1017*4882a593Smuzhiyun 	usleep_range(delay_us, delay_us * 2);
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun 	return 0;
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun disable_clk:
1022*4882a593Smuzhiyun 	clk_disable_unprepare(sc2336->xvclk);
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	return ret;
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun 
__sc2336_power_off(struct sc2336 * sc2336)1027*4882a593Smuzhiyun static void __sc2336_power_off(struct sc2336 *sc2336)
1028*4882a593Smuzhiyun {
1029*4882a593Smuzhiyun 	int ret;
1030*4882a593Smuzhiyun 	struct device *dev = &sc2336->client->dev;
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	clk_disable_unprepare(sc2336->xvclk);
1033*4882a593Smuzhiyun 	if (sc2336->is_thunderboot) {
1034*4882a593Smuzhiyun 		if (sc2336->is_first_streamoff) {
1035*4882a593Smuzhiyun 			sc2336->is_thunderboot = false;
1036*4882a593Smuzhiyun 			sc2336->is_first_streamoff = false;
1037*4882a593Smuzhiyun 		} else {
1038*4882a593Smuzhiyun 			return;
1039*4882a593Smuzhiyun 		}
1040*4882a593Smuzhiyun 	}
1041*4882a593Smuzhiyun 
1042*4882a593Smuzhiyun 	if (!IS_ERR(sc2336->reset_gpio))
1043*4882a593Smuzhiyun 		gpiod_set_value_cansleep(sc2336->reset_gpio, 0);
1044*4882a593Smuzhiyun 	if (!IS_ERR_OR_NULL(sc2336->pins_sleep)) {
1045*4882a593Smuzhiyun 		ret = pinctrl_select_state(sc2336->pinctrl,
1046*4882a593Smuzhiyun 					   sc2336->pins_sleep);
1047*4882a593Smuzhiyun 		if (ret < 0)
1048*4882a593Smuzhiyun 			dev_dbg(dev, "could not set pins\n");
1049*4882a593Smuzhiyun 	}
1050*4882a593Smuzhiyun 	regulator_bulk_disable(SC2336_NUM_SUPPLIES, sc2336->supplies);
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun 
sc2336_runtime_resume(struct device * dev)1053*4882a593Smuzhiyun static int sc2336_runtime_resume(struct device *dev)
1054*4882a593Smuzhiyun {
1055*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1056*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1057*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	return __sc2336_power_on(sc2336);
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun 
sc2336_runtime_suspend(struct device * dev)1062*4882a593Smuzhiyun static int sc2336_runtime_suspend(struct device *dev)
1063*4882a593Smuzhiyun {
1064*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1065*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1066*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	__sc2336_power_off(sc2336);
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	return 0;
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc2336_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1074*4882a593Smuzhiyun static int sc2336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1075*4882a593Smuzhiyun {
1076*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
1077*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1078*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1079*4882a593Smuzhiyun 	const struct sc2336_mode *def_mode = &supported_modes[0];
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	mutex_lock(&sc2336->mutex);
1082*4882a593Smuzhiyun 	/* Initialize try_fmt */
1083*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1084*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1085*4882a593Smuzhiyun 	try_fmt->code = def_mode->bus_fmt;
1086*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	mutex_unlock(&sc2336->mutex);
1089*4882a593Smuzhiyun 	/* No crop or compose */
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	return 0;
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun #endif
1094*4882a593Smuzhiyun 
sc2336_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1095*4882a593Smuzhiyun static int sc2336_enum_frame_interval(struct v4l2_subdev *sd,
1096*4882a593Smuzhiyun 				       struct v4l2_subdev_pad_config *cfg,
1097*4882a593Smuzhiyun 				       struct v4l2_subdev_frame_interval_enum *fie)
1098*4882a593Smuzhiyun {
1099*4882a593Smuzhiyun 	if (fie->index >= ARRAY_SIZE(supported_modes))
1100*4882a593Smuzhiyun 		return -EINVAL;
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	fie->code = supported_modes[fie->index].bus_fmt;
1103*4882a593Smuzhiyun 	fie->width = supported_modes[fie->index].width;
1104*4882a593Smuzhiyun 	fie->height = supported_modes[fie->index].height;
1105*4882a593Smuzhiyun 	fie->interval = supported_modes[fie->index].max_fps;
1106*4882a593Smuzhiyun 	fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1107*4882a593Smuzhiyun 	return 0;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun static const struct dev_pm_ops sc2336_pm_ops = {
1111*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(sc2336_runtime_suspend,
1112*4882a593Smuzhiyun 			   sc2336_runtime_resume, NULL)
1113*4882a593Smuzhiyun };
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1116*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops sc2336_internal_ops = {
1117*4882a593Smuzhiyun 	.open = sc2336_open,
1118*4882a593Smuzhiyun };
1119*4882a593Smuzhiyun #endif
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops sc2336_core_ops = {
1122*4882a593Smuzhiyun 	.s_power = sc2336_s_power,
1123*4882a593Smuzhiyun 	.ioctl = sc2336_ioctl,
1124*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1125*4882a593Smuzhiyun 	.compat_ioctl32 = sc2336_compat_ioctl32,
1126*4882a593Smuzhiyun #endif
1127*4882a593Smuzhiyun };
1128*4882a593Smuzhiyun 
1129*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops sc2336_video_ops = {
1130*4882a593Smuzhiyun 	.s_stream = sc2336_s_stream,
1131*4882a593Smuzhiyun 	.g_frame_interval = sc2336_g_frame_interval,
1132*4882a593Smuzhiyun };
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops sc2336_pad_ops = {
1135*4882a593Smuzhiyun 	.enum_mbus_code = sc2336_enum_mbus_code,
1136*4882a593Smuzhiyun 	.enum_frame_size = sc2336_enum_frame_sizes,
1137*4882a593Smuzhiyun 	.enum_frame_interval = sc2336_enum_frame_interval,
1138*4882a593Smuzhiyun 	.get_fmt = sc2336_get_fmt,
1139*4882a593Smuzhiyun 	.set_fmt = sc2336_set_fmt,
1140*4882a593Smuzhiyun 	.get_mbus_config = sc2336_g_mbus_config,
1141*4882a593Smuzhiyun };
1142*4882a593Smuzhiyun 
1143*4882a593Smuzhiyun static const struct v4l2_subdev_ops sc2336_subdev_ops = {
1144*4882a593Smuzhiyun 	.core	= &sc2336_core_ops,
1145*4882a593Smuzhiyun 	.video	= &sc2336_video_ops,
1146*4882a593Smuzhiyun 	.pad	= &sc2336_pad_ops,
1147*4882a593Smuzhiyun };
1148*4882a593Smuzhiyun 
sc2336_set_ctrl(struct v4l2_ctrl * ctrl)1149*4882a593Smuzhiyun static int sc2336_set_ctrl(struct v4l2_ctrl *ctrl)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun 	struct sc2336 *sc2336 = container_of(ctrl->handler,
1152*4882a593Smuzhiyun 					       struct sc2336, ctrl_handler);
1153*4882a593Smuzhiyun 	struct i2c_client *client = sc2336->client;
1154*4882a593Smuzhiyun 	s64 max;
1155*4882a593Smuzhiyun 	int ret = 0;
1156*4882a593Smuzhiyun 	u32 val = 0;
1157*4882a593Smuzhiyun 
1158*4882a593Smuzhiyun 	/* Propagate change of current control to all related controls */
1159*4882a593Smuzhiyun 	switch (ctrl->id) {
1160*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1161*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
1162*4882a593Smuzhiyun 		max = sc2336->cur_mode->height + ctrl->val - 8;
1163*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(sc2336->exposure,
1164*4882a593Smuzhiyun 					 sc2336->exposure->minimum, max,
1165*4882a593Smuzhiyun 					 sc2336->exposure->step,
1166*4882a593Smuzhiyun 					 sc2336->exposure->default_value);
1167*4882a593Smuzhiyun 		break;
1168*4882a593Smuzhiyun 	}
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
1171*4882a593Smuzhiyun 		return 0;
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 	switch (ctrl->id) {
1174*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
1175*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1176*4882a593Smuzhiyun 		if (sc2336->cur_mode->hdr_mode == NO_HDR) {
1177*4882a593Smuzhiyun 			val = ctrl->val;
1178*4882a593Smuzhiyun 			/* 4 least significant bits of expsoure are fractional part */
1179*4882a593Smuzhiyun 			ret = sc2336_write_reg(sc2336->client,
1180*4882a593Smuzhiyun 						SC2336_REG_EXPOSURE_H,
1181*4882a593Smuzhiyun 						SC2336_REG_VALUE_08BIT,
1182*4882a593Smuzhiyun 						SC2336_FETCH_EXP_H(val));
1183*4882a593Smuzhiyun 			ret |= sc2336_write_reg(sc2336->client,
1184*4882a593Smuzhiyun 						 SC2336_REG_EXPOSURE_M,
1185*4882a593Smuzhiyun 						 SC2336_REG_VALUE_08BIT,
1186*4882a593Smuzhiyun 						 SC2336_FETCH_EXP_M(val));
1187*4882a593Smuzhiyun 			ret |= sc2336_write_reg(sc2336->client,
1188*4882a593Smuzhiyun 						 SC2336_REG_EXPOSURE_L,
1189*4882a593Smuzhiyun 						 SC2336_REG_VALUE_08BIT,
1190*4882a593Smuzhiyun 						 SC2336_FETCH_EXP_L(val));
1191*4882a593Smuzhiyun 		}
1192*4882a593Smuzhiyun 		break;
1193*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
1194*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
1195*4882a593Smuzhiyun 		if (sc2336->cur_mode->hdr_mode == NO_HDR)
1196*4882a593Smuzhiyun 			ret = sc2336_set_gain_reg(sc2336, ctrl->val);
1197*4882a593Smuzhiyun 		break;
1198*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1199*4882a593Smuzhiyun 		dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1200*4882a593Smuzhiyun 		ret = sc2336_write_reg(sc2336->client,
1201*4882a593Smuzhiyun 					SC2336_REG_VTS_H,
1202*4882a593Smuzhiyun 					SC2336_REG_VALUE_08BIT,
1203*4882a593Smuzhiyun 					(ctrl->val + sc2336->cur_mode->height)
1204*4882a593Smuzhiyun 					>> 8);
1205*4882a593Smuzhiyun 		ret |= sc2336_write_reg(sc2336->client,
1206*4882a593Smuzhiyun 					 SC2336_REG_VTS_L,
1207*4882a593Smuzhiyun 					 SC2336_REG_VALUE_08BIT,
1208*4882a593Smuzhiyun 					 (ctrl->val + sc2336->cur_mode->height)
1209*4882a593Smuzhiyun 					 & 0xff);
1210*4882a593Smuzhiyun 		sc2336->cur_vts = ctrl->val + sc2336->cur_mode->height;
1211*4882a593Smuzhiyun 		break;
1212*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
1213*4882a593Smuzhiyun 		ret = sc2336_enable_test_pattern(sc2336, ctrl->val);
1214*4882a593Smuzhiyun 		break;
1215*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
1216*4882a593Smuzhiyun 		ret = sc2336_read_reg(sc2336->client, SC2336_FLIP_MIRROR_REG,
1217*4882a593Smuzhiyun 				       SC2336_REG_VALUE_08BIT, &val);
1218*4882a593Smuzhiyun 		ret |= sc2336_write_reg(sc2336->client, SC2336_FLIP_MIRROR_REG,
1219*4882a593Smuzhiyun 					 SC2336_REG_VALUE_08BIT,
1220*4882a593Smuzhiyun 					 SC2336_FETCH_MIRROR(val, ctrl->val));
1221*4882a593Smuzhiyun 		break;
1222*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
1223*4882a593Smuzhiyun 		ret = sc2336_read_reg(sc2336->client, SC2336_FLIP_MIRROR_REG,
1224*4882a593Smuzhiyun 				       SC2336_REG_VALUE_08BIT, &val);
1225*4882a593Smuzhiyun 		ret |= sc2336_write_reg(sc2336->client, SC2336_FLIP_MIRROR_REG,
1226*4882a593Smuzhiyun 					 SC2336_REG_VALUE_08BIT,
1227*4882a593Smuzhiyun 					 SC2336_FETCH_FLIP(val, ctrl->val));
1228*4882a593Smuzhiyun 		break;
1229*4882a593Smuzhiyun 	default:
1230*4882a593Smuzhiyun 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1231*4882a593Smuzhiyun 			 __func__, ctrl->id, ctrl->val);
1232*4882a593Smuzhiyun 		break;
1233*4882a593Smuzhiyun 	}
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	return ret;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sc2336_ctrl_ops = {
1241*4882a593Smuzhiyun 	.s_ctrl = sc2336_set_ctrl,
1242*4882a593Smuzhiyun };
1243*4882a593Smuzhiyun 
sc2336_initialize_controls(struct sc2336 * sc2336)1244*4882a593Smuzhiyun static int sc2336_initialize_controls(struct sc2336 *sc2336)
1245*4882a593Smuzhiyun {
1246*4882a593Smuzhiyun 	const struct sc2336_mode *mode;
1247*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler;
1248*4882a593Smuzhiyun 	s64 exposure_max, vblank_def;
1249*4882a593Smuzhiyun 	u32 h_blank;
1250*4882a593Smuzhiyun 	int ret;
1251*4882a593Smuzhiyun 	u64 dst_link_freq = 0;
1252*4882a593Smuzhiyun 	u64 dst_pixel_rate = 0;
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 	handler = &sc2336->ctrl_handler;
1255*4882a593Smuzhiyun 	mode = sc2336->cur_mode;
1256*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(handler, 9);
1257*4882a593Smuzhiyun 	if (ret)
1258*4882a593Smuzhiyun 		return ret;
1259*4882a593Smuzhiyun 	handler->lock = &sc2336->mutex;
1260*4882a593Smuzhiyun 
1261*4882a593Smuzhiyun 	sc2336->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1262*4882a593Smuzhiyun 			V4L2_CID_LINK_FREQ,
1263*4882a593Smuzhiyun 			ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
1264*4882a593Smuzhiyun 	if (sc2336->link_freq)
1265*4882a593Smuzhiyun 		sc2336->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1266*4882a593Smuzhiyun 
1267*4882a593Smuzhiyun 	dst_link_freq = mode->link_freq_idx;
1268*4882a593Smuzhiyun 	dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1269*4882a593Smuzhiyun 					 SC2336_BITS_PER_SAMPLE * 2 * SC2336_LANES;
1270*4882a593Smuzhiyun 	sc2336->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1271*4882a593Smuzhiyun 			  0, PIXEL_RATE_WITH_405M_10BIT, 1, dst_pixel_rate);
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl(sc2336->link_freq, dst_link_freq);
1274*4882a593Smuzhiyun 
1275*4882a593Smuzhiyun 	h_blank = mode->hts_def - mode->width;
1276*4882a593Smuzhiyun 	sc2336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1277*4882a593Smuzhiyun 					    h_blank, h_blank, 1, h_blank);
1278*4882a593Smuzhiyun 	if (sc2336->hblank)
1279*4882a593Smuzhiyun 		sc2336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1280*4882a593Smuzhiyun 	vblank_def = mode->vts_def - mode->height;
1281*4882a593Smuzhiyun 	sc2336->vblank = v4l2_ctrl_new_std(handler, &sc2336_ctrl_ops,
1282*4882a593Smuzhiyun 					    V4L2_CID_VBLANK, vblank_def,
1283*4882a593Smuzhiyun 					    SC2336_VTS_MAX - mode->height,
1284*4882a593Smuzhiyun 					    1, vblank_def);
1285*4882a593Smuzhiyun 	exposure_max = mode->vts_def - 8;
1286*4882a593Smuzhiyun 	sc2336->exposure = v4l2_ctrl_new_std(handler, &sc2336_ctrl_ops,
1287*4882a593Smuzhiyun 					      V4L2_CID_EXPOSURE, SC2336_EXPOSURE_MIN,
1288*4882a593Smuzhiyun 					      exposure_max, SC2336_EXPOSURE_STEP,
1289*4882a593Smuzhiyun 					      mode->exp_def);
1290*4882a593Smuzhiyun 	sc2336->anal_gain = v4l2_ctrl_new_std(handler, &sc2336_ctrl_ops,
1291*4882a593Smuzhiyun 					       V4L2_CID_ANALOGUE_GAIN, SC2336_GAIN_MIN,
1292*4882a593Smuzhiyun 					       SC2336_GAIN_MAX, SC2336_GAIN_STEP,
1293*4882a593Smuzhiyun 					       SC2336_GAIN_DEFAULT);
1294*4882a593Smuzhiyun 	sc2336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1295*4882a593Smuzhiyun 							    &sc2336_ctrl_ops,
1296*4882a593Smuzhiyun 					V4L2_CID_TEST_PATTERN,
1297*4882a593Smuzhiyun 					ARRAY_SIZE(sc2336_test_pattern_menu) - 1,
1298*4882a593Smuzhiyun 					0, 0, sc2336_test_pattern_menu);
1299*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, &sc2336_ctrl_ops,
1300*4882a593Smuzhiyun 				V4L2_CID_HFLIP, 0, 1, 1, 0);
1301*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, &sc2336_ctrl_ops,
1302*4882a593Smuzhiyun 				V4L2_CID_VFLIP, 0, 1, 1, 0);
1303*4882a593Smuzhiyun 	if (handler->error) {
1304*4882a593Smuzhiyun 		ret = handler->error;
1305*4882a593Smuzhiyun 		dev_err(&sc2336->client->dev,
1306*4882a593Smuzhiyun 			"Failed to init controls(%d)\n", ret);
1307*4882a593Smuzhiyun 		goto err_free_handler;
1308*4882a593Smuzhiyun 	}
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	sc2336->subdev.ctrl_handler = handler;
1311*4882a593Smuzhiyun 	sc2336->has_init_exp = false;
1312*4882a593Smuzhiyun 
1313*4882a593Smuzhiyun 	return 0;
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun err_free_handler:
1316*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(handler);
1317*4882a593Smuzhiyun 
1318*4882a593Smuzhiyun 	return ret;
1319*4882a593Smuzhiyun }
1320*4882a593Smuzhiyun 
sc2336_check_sensor_id(struct sc2336 * sc2336,struct i2c_client * client)1321*4882a593Smuzhiyun static int sc2336_check_sensor_id(struct sc2336 *sc2336,
1322*4882a593Smuzhiyun 				   struct i2c_client *client)
1323*4882a593Smuzhiyun {
1324*4882a593Smuzhiyun 	struct device *dev = &sc2336->client->dev;
1325*4882a593Smuzhiyun 	u32 id = 0;
1326*4882a593Smuzhiyun 	int ret;
1327*4882a593Smuzhiyun 
1328*4882a593Smuzhiyun 	if (sc2336->is_thunderboot) {
1329*4882a593Smuzhiyun 		dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1330*4882a593Smuzhiyun 		return 0;
1331*4882a593Smuzhiyun 	}
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun 	ret = sc2336_read_reg(client, SC2336_REG_CHIP_ID,
1334*4882a593Smuzhiyun 			       SC2336_REG_VALUE_16BIT, &id);
1335*4882a593Smuzhiyun 	if (id != CHIP_ID) {
1336*4882a593Smuzhiyun 		dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1337*4882a593Smuzhiyun 		return -ENODEV;
1338*4882a593Smuzhiyun 	}
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1341*4882a593Smuzhiyun 
1342*4882a593Smuzhiyun 	return 0;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun 
sc2336_configure_regulators(struct sc2336 * sc2336)1345*4882a593Smuzhiyun static int sc2336_configure_regulators(struct sc2336 *sc2336)
1346*4882a593Smuzhiyun {
1347*4882a593Smuzhiyun 	unsigned int i;
1348*4882a593Smuzhiyun 
1349*4882a593Smuzhiyun 	for (i = 0; i < SC2336_NUM_SUPPLIES; i++)
1350*4882a593Smuzhiyun 		sc2336->supplies[i].supply = sc2336_supply_names[i];
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&sc2336->client->dev,
1353*4882a593Smuzhiyun 				       SC2336_NUM_SUPPLIES,
1354*4882a593Smuzhiyun 				       sc2336->supplies);
1355*4882a593Smuzhiyun }
1356*4882a593Smuzhiyun 
sc2336_probe(struct i2c_client * client,const struct i2c_device_id * id)1357*4882a593Smuzhiyun static int sc2336_probe(struct i2c_client *client,
1358*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
1359*4882a593Smuzhiyun {
1360*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1361*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1362*4882a593Smuzhiyun 	struct sc2336 *sc2336;
1363*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1364*4882a593Smuzhiyun 	char facing[2];
1365*4882a593Smuzhiyun 	int ret;
1366*4882a593Smuzhiyun 	int i, hdr_mode = 0;
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1369*4882a593Smuzhiyun 		 DRIVER_VERSION >> 16,
1370*4882a593Smuzhiyun 		 (DRIVER_VERSION & 0xff00) >> 8,
1371*4882a593Smuzhiyun 		 DRIVER_VERSION & 0x00ff);
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun 	sc2336 = devm_kzalloc(dev, sizeof(*sc2336), GFP_KERNEL);
1374*4882a593Smuzhiyun 	if (!sc2336)
1375*4882a593Smuzhiyun 		return -ENOMEM;
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1378*4882a593Smuzhiyun 				   &sc2336->module_index);
1379*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1380*4882a593Smuzhiyun 				       &sc2336->module_facing);
1381*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1382*4882a593Smuzhiyun 				       &sc2336->module_name);
1383*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1384*4882a593Smuzhiyun 				       &sc2336->len_name);
1385*4882a593Smuzhiyun 	if (ret) {
1386*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1387*4882a593Smuzhiyun 		return -EINVAL;
1388*4882a593Smuzhiyun 	}
1389*4882a593Smuzhiyun 
1390*4882a593Smuzhiyun 	sc2336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun 	sc2336->client = client;
1393*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1394*4882a593Smuzhiyun 		if (hdr_mode == supported_modes[i].hdr_mode) {
1395*4882a593Smuzhiyun 			sc2336->cur_mode = &supported_modes[i];
1396*4882a593Smuzhiyun 			break;
1397*4882a593Smuzhiyun 		}
1398*4882a593Smuzhiyun 	}
1399*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(supported_modes))
1400*4882a593Smuzhiyun 		sc2336->cur_mode = &supported_modes[0];
1401*4882a593Smuzhiyun 
1402*4882a593Smuzhiyun 	sc2336->xvclk = devm_clk_get(dev, "xvclk");
1403*4882a593Smuzhiyun 	if (IS_ERR(sc2336->xvclk)) {
1404*4882a593Smuzhiyun 		dev_err(dev, "Failed to get xvclk\n");
1405*4882a593Smuzhiyun 		return -EINVAL;
1406*4882a593Smuzhiyun 	}
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	if (sc2336->is_thunderboot) {
1409*4882a593Smuzhiyun 		sc2336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1410*4882a593Smuzhiyun 		if (IS_ERR(sc2336->reset_gpio))
1411*4882a593Smuzhiyun 			dev_warn(dev, "Failed to get reset-gpios\n");
1412*4882a593Smuzhiyun 	} else {
1413*4882a593Smuzhiyun 		sc2336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1414*4882a593Smuzhiyun 		if (IS_ERR(sc2336->reset_gpio))
1415*4882a593Smuzhiyun 			dev_warn(dev, "Failed to get reset-gpios\n");
1416*4882a593Smuzhiyun 	}
1417*4882a593Smuzhiyun 
1418*4882a593Smuzhiyun 	sc2336->pinctrl = devm_pinctrl_get(dev);
1419*4882a593Smuzhiyun 	if (!IS_ERR(sc2336->pinctrl)) {
1420*4882a593Smuzhiyun 		sc2336->pins_default =
1421*4882a593Smuzhiyun 			pinctrl_lookup_state(sc2336->pinctrl,
1422*4882a593Smuzhiyun 					     OF_CAMERA_PINCTRL_STATE_DEFAULT);
1423*4882a593Smuzhiyun 		if (IS_ERR(sc2336->pins_default))
1424*4882a593Smuzhiyun 			dev_err(dev, "could not get default pinstate\n");
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun 		sc2336->pins_sleep =
1427*4882a593Smuzhiyun 			pinctrl_lookup_state(sc2336->pinctrl,
1428*4882a593Smuzhiyun 					     OF_CAMERA_PINCTRL_STATE_SLEEP);
1429*4882a593Smuzhiyun 		if (IS_ERR(sc2336->pins_sleep))
1430*4882a593Smuzhiyun 			dev_err(dev, "could not get sleep pinstate\n");
1431*4882a593Smuzhiyun 	} else {
1432*4882a593Smuzhiyun 		dev_err(dev, "no pinctrl\n");
1433*4882a593Smuzhiyun 	}
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun 	ret = sc2336_configure_regulators(sc2336);
1436*4882a593Smuzhiyun 	if (ret) {
1437*4882a593Smuzhiyun 		dev_err(dev, "Failed to get power regulators\n");
1438*4882a593Smuzhiyun 		return ret;
1439*4882a593Smuzhiyun 	}
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	mutex_init(&sc2336->mutex);
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	sd = &sc2336->subdev;
1444*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &sc2336_subdev_ops);
1445*4882a593Smuzhiyun 	ret = sc2336_initialize_controls(sc2336);
1446*4882a593Smuzhiyun 	if (ret)
1447*4882a593Smuzhiyun 		goto err_destroy_mutex;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	ret = __sc2336_power_on(sc2336);
1450*4882a593Smuzhiyun 	if (ret)
1451*4882a593Smuzhiyun 		goto err_free_handler;
1452*4882a593Smuzhiyun 
1453*4882a593Smuzhiyun 	ret = sc2336_check_sensor_id(sc2336, client);
1454*4882a593Smuzhiyun 	if (ret)
1455*4882a593Smuzhiyun 		goto err_power_off;
1456*4882a593Smuzhiyun 
1457*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1458*4882a593Smuzhiyun 	sd->internal_ops = &sc2336_internal_ops;
1459*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1460*4882a593Smuzhiyun 		     V4L2_SUBDEV_FL_HAS_EVENTS;
1461*4882a593Smuzhiyun #endif
1462*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1463*4882a593Smuzhiyun 	sc2336->pad.flags = MEDIA_PAD_FL_SOURCE;
1464*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1465*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &sc2336->pad);
1466*4882a593Smuzhiyun 	if (ret < 0)
1467*4882a593Smuzhiyun 		goto err_power_off;
1468*4882a593Smuzhiyun #endif
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1471*4882a593Smuzhiyun 	if (strcmp(sc2336->module_facing, "back") == 0)
1472*4882a593Smuzhiyun 		facing[0] = 'b';
1473*4882a593Smuzhiyun 	else
1474*4882a593Smuzhiyun 		facing[0] = 'f';
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1477*4882a593Smuzhiyun 		 sc2336->module_index, facing,
1478*4882a593Smuzhiyun 		 SC2336_NAME, dev_name(sd->dev));
1479*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(sd);
1480*4882a593Smuzhiyun 	if (ret) {
1481*4882a593Smuzhiyun 		dev_err(dev, "v4l2 async register subdev failed\n");
1482*4882a593Smuzhiyun 		goto err_clean_entity;
1483*4882a593Smuzhiyun 	}
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
1486*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1487*4882a593Smuzhiyun 	if (sc2336->is_thunderboot)
1488*4882a593Smuzhiyun 		pm_runtime_get_sync(dev);
1489*4882a593Smuzhiyun 	else
1490*4882a593Smuzhiyun 		pm_runtime_idle(dev);
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	return 0;
1493*4882a593Smuzhiyun 
1494*4882a593Smuzhiyun err_clean_entity:
1495*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1496*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1497*4882a593Smuzhiyun #endif
1498*4882a593Smuzhiyun err_power_off:
1499*4882a593Smuzhiyun 	__sc2336_power_off(sc2336);
1500*4882a593Smuzhiyun err_free_handler:
1501*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&sc2336->ctrl_handler);
1502*4882a593Smuzhiyun err_destroy_mutex:
1503*4882a593Smuzhiyun 	mutex_destroy(&sc2336->mutex);
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun 	return ret;
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun 
sc2336_remove(struct i2c_client * client)1508*4882a593Smuzhiyun static int sc2336_remove(struct i2c_client *client)
1509*4882a593Smuzhiyun {
1510*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1511*4882a593Smuzhiyun 	struct sc2336 *sc2336 = to_sc2336(sd);
1512*4882a593Smuzhiyun 
1513*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1514*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1515*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1516*4882a593Smuzhiyun #endif
1517*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&sc2336->ctrl_handler);
1518*4882a593Smuzhiyun 	mutex_destroy(&sc2336->mutex);
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1521*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&client->dev))
1522*4882a593Smuzhiyun 		__sc2336_power_off(sc2336);
1523*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
1524*4882a593Smuzhiyun 
1525*4882a593Smuzhiyun 	return 0;
1526*4882a593Smuzhiyun }
1527*4882a593Smuzhiyun 
1528*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1529*4882a593Smuzhiyun static const struct of_device_id sc2336_of_match[] = {
1530*4882a593Smuzhiyun 	{ .compatible = "smartsens,sc2336" },
1531*4882a593Smuzhiyun 	{},
1532*4882a593Smuzhiyun };
1533*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sc2336_of_match);
1534*4882a593Smuzhiyun #endif
1535*4882a593Smuzhiyun 
1536*4882a593Smuzhiyun static const struct i2c_device_id sc2336_match_id[] = {
1537*4882a593Smuzhiyun 	{ "smartsens,sc2336", 0 },
1538*4882a593Smuzhiyun 	{ },
1539*4882a593Smuzhiyun };
1540*4882a593Smuzhiyun 
1541*4882a593Smuzhiyun static struct i2c_driver sc2336_i2c_driver = {
1542*4882a593Smuzhiyun 	.driver = {
1543*4882a593Smuzhiyun 		.name = SC2336_NAME,
1544*4882a593Smuzhiyun 		.pm = &sc2336_pm_ops,
1545*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(sc2336_of_match),
1546*4882a593Smuzhiyun 	},
1547*4882a593Smuzhiyun 	.probe		= &sc2336_probe,
1548*4882a593Smuzhiyun 	.remove		= &sc2336_remove,
1549*4882a593Smuzhiyun 	.id_table	= sc2336_match_id,
1550*4882a593Smuzhiyun };
1551*4882a593Smuzhiyun 
sensor_mod_init(void)1552*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1553*4882a593Smuzhiyun {
1554*4882a593Smuzhiyun 	return i2c_add_driver(&sc2336_i2c_driver);
1555*4882a593Smuzhiyun }
1556*4882a593Smuzhiyun 
sensor_mod_exit(void)1557*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1558*4882a593Smuzhiyun {
1559*4882a593Smuzhiyun 	i2c_del_driver(&sc2336_i2c_driver);
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1563*4882a593Smuzhiyun subsys_initcall(sensor_mod_init);
1564*4882a593Smuzhiyun #else
1565*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1566*4882a593Smuzhiyun #endif
1567*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun MODULE_DESCRIPTION("smartsens sc2336 sensor driver");
1570*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1571