1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc2232 driver
4 *
5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version,adjust sc2232.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/version.h>
21 #include <linux/rk-camera-module.h>
22 #include <media/media-entity.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-subdev.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/rk-preisp.h>
28
29 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
30
31 #ifndef V4L2_CID_DIGITAL_GAIN
32 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
33 #endif
34
35 #define MIPI_FREQ_186M 186000000
36 #define SC2232_MAX_PIXEL_RATE (MIPI_FREQ_186M * 2 / 10 * 2)
37
38 #define SC2232_XVCLK_FREQ 27000000
39
40 #define CHIP_ID 0x2238
41 #define SC2232_REG_CHIP_ID 0x3107
42
43 #define SC2232_REG_CTRL_MODE 0x0100
44 #define SC2232_MODE_SW_STANDBY 0x0
45 #define SC2232_MODE_STREAMING BIT(0)
46
47 #define SC2232_EXPOSURE_MIN 3
48 #define SC2232_EXPOSURE_STEP 1
49 #define SC2232_VTS_MAX 0xffff
50
51 #define SC2232_REG_EXP_LONG_H 0x3e00 //[3:0]
52 #define SC2232_REG_EXP_LONG_M 0x3e01 //[7:0]
53 #define SC2232_REG_EXP_LONG_L 0x3e02 //[7:4]
54
55 #define SC2232_REG_AGAIN 0x3e08
56 #define SC2232_REG_AGAIN_FINE 0x3e09
57
58 #define SC2232_REG_DGAIN 0x3e06
59 #define SC2232_REG_DGAIN_FINE 0x3e07
60
61 #define SC2232_GAIN_MIN 0x40
62 #define SC2232_GAIN_MAX 0x4000
63 #define SC2232_GAIN_STEP 1
64 #define SC2232_GAIN_DEFAULT 0x40
65
66 #define SC2232_SOFTWARE_RESET_REG 0x0103
67
68 #define SC2232_REG_VTS 0x320e
69 #define SC2232_REG_HTS 0x320c
70
71 #define SC2232_FLIP_REG 0x3221
72 #define SC2232_FLIP_MASK 0x60
73 #define SC2232_MIRROR_MASK 0x06
74 #define REG_NULL 0xFFFF
75
76 #define SC2232_REG_VALUE_08BIT 1
77 #define SC2232_REG_VALUE_16BIT 2
78 #define SC2232_REG_VALUE_24BIT 3
79
80 #define SC2232_LANES 2
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
85
86 #define SC2232_NAME "sc2232"
87
88 static const char * const sc2232_supply_names[] = {
89 "avdd", /* Analog power */
90 "dovdd", /* Digital I/O power */
91 "dvdd", /* Digital core power */
92 };
93
94 #define SC2232_NUM_SUPPLIES ARRAY_SIZE(sc2232_supply_names)
95
96 struct regval {
97 u16 addr;
98 u8 val;
99 };
100
101 struct sc2232_mode {
102 u32 bus_fmt;
103 u32 width;
104 u32 height;
105 struct v4l2_fract max_fps;
106 u32 hts_def;
107 u32 vts_def;
108 u32 exp_def;
109 const struct regval *reg_list;
110 u32 hdr_mode;
111 u32 mipi_freq_idx;
112 u32 bpp;
113 u32 vc[PAD_MAX];
114 };
115
116 struct sc2232 {
117 struct i2c_client *client;
118 struct clk *xvclk;
119 struct gpio_desc *reset_gpio;
120 struct gpio_desc *pwdn_gpio;
121 struct regulator_bulk_data supplies[SC2232_NUM_SUPPLIES];
122 struct pinctrl *pinctrl;
123 struct pinctrl_state *pins_default;
124 struct pinctrl_state *pins_sleep;
125 struct v4l2_subdev subdev;
126 struct media_pad pad;
127 struct v4l2_ctrl_handler ctrl_handler;
128 struct v4l2_ctrl *exposure;
129 struct v4l2_ctrl *anal_gain;
130 struct v4l2_ctrl *digi_gain;
131 struct v4l2_ctrl *hblank;
132 struct v4l2_ctrl *vblank;
133 struct v4l2_ctrl *pixel_rate;
134 struct v4l2_ctrl *link_freq;
135 struct mutex mutex;
136 struct v4l2_fract cur_fps;
137 bool streaming;
138 bool power_on;
139 const struct sc2232_mode *cur_mode;
140 u32 cfg_num;
141 u32 module_index;
142 const char *module_facing;
143 const char *module_name;
144 const char *len_name;
145 bool has_init_exp;
146 u32 cur_vts;
147 struct preisp_hdrae_exp_s init_hdrae_exp;
148 };
149
150 #define to_sc2232(sd) container_of(sd, struct sc2232, subdev)
151
152 static const struct regval sc2232_linear10bit_1920x1080_regs[] = {
153 {0x0103,0x01},
154 {0x0100,0x00},
155 {0x3034,0x81},//pll2 bypass
156 {0x3039,0xa2},//pll1 bypass
157 {0x3624,0x08},
158 {0x337f,0x03},
159 {0x3368,0x04},
160 {0x3369,0x00},
161 {0x336a,0x00},
162 {0x336b,0x00},
163 {0x3367,0x08},
164 {0x330e,0x30},
165 {0x3366,0x7c},
166 {0x3302,0x1f},
167 {0x3907,0x00},
168 {0x3902,0x45},
169 {0x3908,0x11},
170 {0x335e,0x01},
171 {0x335f,0x03},
172 {0x337c,0x04},
173 {0x337d,0x06},
174 {0x33a0,0x05},
175 {0x3633,0x4f},
176 {0x3622,0x06},
177 {0x3631,0x84},
178 {0x366e,0x08},
179 {0x3326,0x00},
180 {0x3303,0x20},
181 {0x3638,0x1f},
182 {0x3636,0x25},
183 {0x3625,0x02},
184 {0x331b,0x83},
185 {0x3333,0x30},
186 {0x3635,0xa0},
187 {0x363c,0x05},
188 {0x3038,0xff},
189 {0x3639,0x09},
190 {0x3621,0x28},
191 {0x3211,0x0c},
192 {0x3320,0x01},
193 {0x331e,0x19},
194 {0x3620,0x28},
195 {0x3309,0x60},
196 {0x331f,0x59},
197 {0x3308,0x10},
198 {0x3f00,0x07},
199 {0x3802,0x01}, //0x01 for over 2fps update
200 {0x33aa,0x10},
201 {0x3677,0x86},
202 {0x3678,0x88},
203 {0x3679,0x88},
204 {0x367e,0x08},
205 {0x367f,0x28},
206 {0x3670,0x0c},
207 {0x3690,0x33},
208 {0x3691,0x11},
209 {0x3692,0x43},
210 {0x369c,0x08},
211 {0x369d,0x28},
212 {0x360f,0x01},
213 {0x3671,0xc6},
214 {0x3672,0x06},
215 {0x3673,0x16},
216 {0x367a,0x28},
217 {0x367b,0x3f},
218 {0x320c,0x08},
219 {0x320d,0x98},
220 {0x320e,0x04},
221 {0x320f,0x65},
222 {0x3f04,0x04},
223 {0x3f05,0x28},
224 {0x3235,0x08},
225 {0x3236,0xc8},
226 {0x3222,0x29},
227 {0x3901,0x02},
228 {0x3905,0x98},
229 {0x3e1e,0x34},
230 {0x3900,0x19},
231 {0x391d,0x04},
232 {0x391e,0x00},
233 {0x3641,0x01},
234 {0x3213,0x04},
235 {0x3614,0x80},
236 {0x363a,0x9f},
237 {0x3630,0x9c},
238 {0x3306,0x48},
239 {0x330b,0xcd},
240 {0x3018,0x33},
241 {0x3031,0x0a},
242 {0x3037,0x20},
243 {0x3001,0xfe},
244 {0x4603,0x00},
245 {0x4827,0x48},
246 {0x301c,0x78},
247 {0x4809,0x01},
248 {0x3314,0x04},
249 {0x303c,0x0e},
250 {0x4837,0x35},
251 {0x3933,0x0a},
252 {0x3934,0x10},
253 {0x3940,0x60},
254 {0x3942,0x02},
255 {0x3943,0x1f},
256 {0x3960,0xba},
257 {0x3961,0xae},
258 {0x3966,0xba},
259 {0x3980,0xa0},
260 {0x3981,0x40},
261 {0x3982,0x18},
262 {0x3903,0x08},
263 {0x3984,0x08},
264 {0x3985,0x20},
265 {0x3986,0x50},
266 {0x3987,0xb0},
267 {0x3988,0x08},
268 {0x3989,0x10},
269 {0x398a,0x20},
270 {0x398b,0x30},
271 {0x398c,0x60},
272 {0x398d,0x20},
273 {0x398e,0x10},
274 {0x398f,0x08},
275 {0x3990,0x60},
276 {0x3991,0x24},
277 {0x3992,0x15},
278 {0x3993,0x08},
279 {0x3994,0x0a},
280 {0x3995,0x20},
281 {0x3996,0x38},
282 {0x3997,0xa0},
283 {0x3998,0x08},
284 {0x3999,0x10},
285 {0x399a,0x18},
286 {0x399b,0x30},
287 {0x399c,0x30},
288 {0x399d,0x18},
289 {0x399e,0x10},
290 {0x399f,0x08},
291 {0x3637,0x55},
292 {0x363b,0x06},
293 {0x366f,0x2c},
294 {0x5000,0x06},
295 {0x5780,0x7f},
296 {0x5781,0x04},
297 {0x5782,0x03},
298 {0x5783,0x02},
299 {0x5784,0x01},
300 {0x5785,0x18},
301 {0x5786,0x10},
302 {0x5787,0x08},
303 {0x5788,0x02},
304 {0x57a0,0x00},
305 {0x57a1,0x71},
306 {0x57a2,0x01},
307 {0x57a3,0xf1},
308 {0x395e,0xc0},
309 {0x3962,0x89},
310 {0x3e00,0x00},
311 {0x3e01,0x8c},
312 {0x3e02,0x60},
313 {0x3e03,0x0b},
314 {0x3e06,0x00},
315 {0x3e07,0x80},
316 {0x3e08,0x03},
317 {0x3e09,0x10},
318 {0x3301,0x0f},
319 {0x3632,0x08},
320 {0x3034,0x01},
321 {0x3039,0x22},
322 {0x0100,0x01},
323 {REG_NULL, 0x00},
324 };
325
326 /*
327 * The width and height must be configured to be
328 * the same as the current output resolution of the sensor.
329 * The input width of the isp needs to be 16 aligned.
330 * The input height of the isp needs to be 8 aligned.
331 * If the width or height does not meet the alignment rules,
332 * you can configure the cropping parameters with the following function to
333 * crop out the appropriate resolution.
334 * struct v4l2_subdev_pad_ops {
335 * .get_selection
336 * }
337 */
338 static const struct sc2232_mode supported_modes[] = {
339 {
340 /* linear modes */
341 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
342 .width = 1920,
343 .height = 1080,
344 .max_fps = {
345 .numerator = 10000,
346 .denominator = 300000,
347 },
348 .exp_def = 0x0463,
349 .hts_def = 0x0898 * 2,
350 .vts_def = 0x0465,
351 .reg_list = sc2232_linear10bit_1920x1080_regs,
352 .hdr_mode = NO_HDR,
353 .mipi_freq_idx = 0,
354 .bpp = 10,
355 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
356 },
357 };
358
359 static const s64 link_freq_items[] = {
360 MIPI_FREQ_186M,
361 };
362
363 /* Write registers up to 4 at a time */
sc2232_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)364 static int sc2232_write_reg(struct i2c_client *client, u16 reg,
365 u32 len, u32 val)
366 {
367 u32 buf_i, val_i;
368 u8 buf[6];
369 u8 *val_p;
370 __be32 val_be;
371
372 if (len > 4)
373 return -EINVAL;
374
375 buf[0] = reg >> 8;
376 buf[1] = reg & 0xff;
377
378 val_be = cpu_to_be32(val);
379 val_p = (u8 *)&val_be;
380 buf_i = 2;
381 val_i = 4 - len;
382
383 while (val_i < 4)
384 buf[buf_i++] = val_p[val_i++];
385
386 if (i2c_master_send(client, buf, len + 2) != len + 2)
387 return -EIO;
388
389 return 0;
390 }
391
sc2232_write_array(struct i2c_client * client,const struct regval * regs)392 static int sc2232_write_array(struct i2c_client *client,
393 const struct regval *regs)
394 {
395 u32 i;
396 int ret = 0;
397
398 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
399 ret |= sc2232_write_reg(client, regs[i].addr,
400 SC2232_REG_VALUE_08BIT, regs[i].val);
401 }
402 return ret;
403 }
404
405 /* Read registers up to 4 at a time */
sc2232_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)406 static int sc2232_read_reg(struct i2c_client *client,
407 u16 reg,
408 unsigned int len,
409 u32 *val)
410 {
411 struct i2c_msg msgs[2];
412 u8 *data_be_p;
413 __be32 data_be = 0;
414 __be16 reg_addr_be = cpu_to_be16(reg);
415 int ret;
416
417 if (len > 4 || !len)
418 return -EINVAL;
419
420 data_be_p = (u8 *)&data_be;
421 /* Write register address */
422 msgs[0].addr = client->addr;
423 msgs[0].flags = 0;
424 msgs[0].len = 2;
425 msgs[0].buf = (u8 *)®_addr_be;
426
427 /* Read data from register */
428 msgs[1].addr = client->addr;
429 msgs[1].flags = I2C_M_RD;
430 msgs[1].len = len;
431 msgs[1].buf = &data_be_p[4 - len];
432
433 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
434 if (ret != ARRAY_SIZE(msgs))
435 return -EIO;
436
437 *val = be32_to_cpu(data_be);
438
439 return 0;
440 }
441
sc2232_get_reso_dist(const struct sc2232_mode * mode,struct v4l2_mbus_framefmt * framefmt)442 static int sc2232_get_reso_dist(const struct sc2232_mode *mode,
443 struct v4l2_mbus_framefmt *framefmt)
444 {
445 return abs(mode->width - framefmt->width) +
446 abs(mode->height - framefmt->height);
447 }
448
449 static const struct sc2232_mode *
sc2232_find_best_fit(struct sc2232 * sc2232,struct v4l2_subdev_format * fmt)450 sc2232_find_best_fit(struct sc2232 *sc2232, struct v4l2_subdev_format *fmt)
451 {
452 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
453 int dist;
454 int cur_best_fit = 0;
455 int cur_best_fit_dist = -1;
456 unsigned int i;
457
458 for (i = 0; i < sc2232->cfg_num; i++) {
459 dist = sc2232_get_reso_dist(&supported_modes[i], framefmt);
460 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
461 (supported_modes[i].bus_fmt == framefmt->code)) {
462 cur_best_fit_dist = dist;
463 cur_best_fit = i;
464 }
465 }
466
467 return &supported_modes[cur_best_fit];
468 }
469
sc2232_change_mode(struct sc2232 * sc2232,const struct sc2232_mode * mode)470 static void sc2232_change_mode(struct sc2232 *sc2232, const struct sc2232_mode *mode)
471 {
472 sc2232->cur_mode = mode;
473 sc2232->cur_vts = sc2232->cur_mode->vts_def;
474 dev_info(&sc2232->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
475 mode->width, mode->height, mode->hdr_mode);
476 }
477
sc2232_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)478 static int sc2232_set_fmt(struct v4l2_subdev *sd,
479 struct v4l2_subdev_pad_config *cfg,
480 struct v4l2_subdev_format *fmt)
481 {
482 struct sc2232 *sc2232 = to_sc2232(sd);
483 const struct sc2232_mode *mode;
484 s64 h_blank, vblank_def;
485 u64 pixel_rate = 0;
486
487 mutex_lock(&sc2232->mutex);
488
489 mode = sc2232_find_best_fit(sc2232, fmt);
490 fmt->format.code = mode->bus_fmt;
491 fmt->format.width = mode->width;
492 fmt->format.height = mode->height;
493 fmt->format.field = V4L2_FIELD_NONE;
494 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
495 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
496 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
497 #else
498 mutex_unlock(&sc2232->mutex);
499 return -ENOTTY;
500 #endif
501 } else {
502 sc2232_change_mode(sc2232, mode);
503 h_blank = mode->hts_def - mode->width;
504 __v4l2_ctrl_modify_range(sc2232->hblank, h_blank,
505 h_blank, 1, h_blank);
506 vblank_def = mode->vts_def - mode->height;
507 __v4l2_ctrl_modify_range(sc2232->vblank, vblank_def,
508 SC2232_VTS_MAX - mode->height,
509 1, vblank_def);
510 __v4l2_ctrl_s_ctrl(sc2232->link_freq, mode->mipi_freq_idx);
511 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
512 mode->bpp * 2 * SC2232_LANES;
513 __v4l2_ctrl_s_ctrl_int64(sc2232->pixel_rate, pixel_rate);
514 sc2232->cur_fps = mode->max_fps;
515 sc2232->cur_vts = mode->vts_def;
516 }
517
518 mutex_unlock(&sc2232->mutex);
519
520 return 0;
521 }
522
sc2232_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)523 static int sc2232_get_fmt(struct v4l2_subdev *sd,
524 struct v4l2_subdev_pad_config *cfg,
525 struct v4l2_subdev_format *fmt)
526 {
527 struct sc2232 *sc2232 = to_sc2232(sd);
528 const struct sc2232_mode *mode = sc2232->cur_mode;
529
530 mutex_lock(&sc2232->mutex);
531 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
532 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
533 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
534 #else
535 mutex_unlock(&sc2232->mutex);
536 return -ENOTTY;
537 #endif
538 } else {
539 fmt->format.width = mode->width;
540 fmt->format.height = mode->height;
541 fmt->format.code = mode->bus_fmt;
542 fmt->format.field = V4L2_FIELD_NONE;
543 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
544 fmt->reserved[0] = mode->vc[fmt->pad];
545 else
546 fmt->reserved[0] = mode->vc[PAD0];
547 }
548 mutex_unlock(&sc2232->mutex);
549
550 return 0;
551 }
552
sc2232_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)553 static int sc2232_enum_mbus_code(struct v4l2_subdev *sd,
554 struct v4l2_subdev_pad_config *cfg,
555 struct v4l2_subdev_mbus_code_enum *code)
556 {
557 struct sc2232 *sc2232 = to_sc2232(sd);
558
559 if (code->index != 0)
560 return -EINVAL;
561 code->code = sc2232->cur_mode->bus_fmt;
562
563 return 0;
564 }
565
sc2232_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)566 static int sc2232_enum_frame_sizes(struct v4l2_subdev *sd,
567 struct v4l2_subdev_pad_config *cfg,
568 struct v4l2_subdev_frame_size_enum *fse)
569 {
570 struct sc2232 *sc2232 = to_sc2232(sd);
571
572 if (fse->index >= sc2232->cfg_num)
573 return -EINVAL;
574
575 if (fse->code != supported_modes[fse->index].bus_fmt)
576 return -EINVAL;
577
578 fse->min_width = supported_modes[fse->index].width;
579 fse->max_width = supported_modes[fse->index].width;
580 fse->max_height = supported_modes[fse->index].height;
581 fse->min_height = supported_modes[fse->index].height;
582
583 return 0;
584 }
585
sc2232_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)586 static int sc2232_g_frame_interval(struct v4l2_subdev *sd,
587 struct v4l2_subdev_frame_interval *fi)
588 {
589 struct sc2232 *sc2232 = to_sc2232(sd);
590 const struct sc2232_mode *mode = sc2232->cur_mode;
591
592 if (sc2232->streaming)
593 fi->interval = sc2232->cur_fps;
594 else
595 fi->interval = mode->max_fps;
596
597 return 0;
598 }
599
sc2232_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)600 static int sc2232_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
601 struct v4l2_mbus_config *config)
602 {
603 struct sc2232 *sc2232 = to_sc2232(sd);
604 const struct sc2232_mode *mode = sc2232->cur_mode;
605 u32 val = 0;
606
607 if (mode->hdr_mode == NO_HDR)
608 val = 1 << (SC2232_LANES - 1) |
609 V4L2_MBUS_CSI2_CHANNEL_0 |
610 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
611 if (mode->hdr_mode == HDR_X2)
612 val = 1 << (SC2232_LANES - 1) |
613 V4L2_MBUS_CSI2_CHANNEL_0 |
614 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
615 V4L2_MBUS_CSI2_CHANNEL_1;
616
617 config->type = V4L2_MBUS_CSI2_DPHY;
618 config->flags = val;
619
620 return 0;
621 }
622
sc2232_get_module_inf(struct sc2232 * sc2232,struct rkmodule_inf * inf)623 static void sc2232_get_module_inf(struct sc2232 *sc2232,
624 struct rkmodule_inf *inf)
625 {
626 memset(inf, 0, sizeof(*inf));
627 strlcpy(inf->base.sensor, SC2232_NAME, sizeof(inf->base.sensor));
628 strlcpy(inf->base.module, sc2232->module_name,
629 sizeof(inf->base.module));
630 strlcpy(inf->base.lens, sc2232->len_name, sizeof(inf->base.lens));
631 }
632
sc2232_set_gain(struct sc2232 * sc2232,u32 total_gain)633 static int sc2232_set_gain(struct sc2232 *sc2232, u32 total_gain)
634 {
635 u32 again = 0, again_fine = 0;
636 u32 dgain = 0, dgain_fine = 0;
637 u32 step = 0;
638 u32 val = 0;
639 int ret = 0;
640
641 if (total_gain < 0x80) {/* 1x gain ~ 2x gain */
642 step = (total_gain - 0x40) >> 2;
643
644 again = 0x0;
645 again_fine = step + 0x10;
646 dgain = 0x0;
647 dgain_fine = 0x80;
648
649 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x0f);
650 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
651
652 } else if (total_gain < 0x100) {/* 2x gain ~ 4x gain */
653 step = (total_gain - 0x80) >> 3;
654
655 again = 0x1;
656 again_fine = step + 0x10;
657 dgain = 0x0;
658 dgain_fine = 0x80;
659
660 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x20);
661 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
662
663 } else if (total_gain < 0x200) {/* 4x gain ~ 8x gain */
664 step = (total_gain - 0x100) >> 4;
665
666 again = 0x3;
667 again_fine = step + 0x10;
668 dgain = 0x0;
669 dgain_fine = 0x80;
670
671 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x28);
672 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
673
674 } else if (total_gain < 0x400) {/* 8x gain ~ 16x gain */
675 step = (total_gain - 0x200) >> 5;
676
677 again = 0x7;
678 again_fine = step + 0x10;
679 dgain = 0x0;
680 dgain_fine = 0x80;
681
682 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
683 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
684
685 } else if (total_gain < 0x800) { /* 16x gain ~ 32x gain */
686 step = (total_gain - 0x400) >> 6;
687
688 again = 0x7;
689 again_fine = 0x1f;
690 dgain = 0x0;
691 dgain_fine = step * 8 + 0x80;
692
693 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
694 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
695 } else if (total_gain < 0x1000) { /* 32x gain ~ 64x gain */
696 step = (total_gain - 0x800) >> 7;
697
698 again = 0x7;
699 again_fine = 0x1f;
700 dgain = 0x1;
701 dgain_fine = step * 8 + 0x80;
702
703 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
704 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
705 } else if (total_gain < 0x2000) { /* 64x gain ~ 128x gain */
706 step = (total_gain - 0x1000) >> 8;
707
708 again = 0x7;
709 again_fine = 0x1f;
710 dgain = 0x3;
711 dgain_fine = step * 8 + 0x80;
712
713 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
714 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
715 } else if (total_gain <= 0x4000) { /* 128x gain ~ 256x gain */
716 step = (total_gain - 0x2000) >> 9;
717 step = (step >= 16) ? 0xf : step;
718
719 again = 0x7;
720 again_fine = 0x1f;
721 dgain = 0x7;
722 dgain_fine = step * 8 + 0x80;
723
724 ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
725 ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
726 }
727
728 ret |= sc2232_write_reg(sc2232->client, 0x3812, SC2232_REG_VALUE_08BIT, 0x30);
729
730 dev_dbg(&sc2232->client->dev, "total_gain:%d again 0x%x, again_fine 0x%x, dgain 0x%x, dgain_fine 0x%x\n",
731 total_gain, again, again_fine, dgain, dgain_fine);
732
733 ret |= sc2232_read_reg(sc2232->client, SC2232_REG_AGAIN,SC2232_REG_VALUE_08BIT, &val);
734 ret |= sc2232_write_reg(sc2232->client, SC2232_REG_AGAIN,SC2232_REG_VALUE_08BIT, (val & 0xE3) | (again << 2));
735 ret |= sc2232_read_reg(sc2232->client, SC2232_REG_DGAIN,SC2232_REG_VALUE_08BIT, &val);
736 ret |= sc2232_write_reg(sc2232->client, SC2232_REG_DGAIN,SC2232_REG_VALUE_08BIT,(val & 0xF0) | dgain);
737
738 ret |= sc2232_write_reg(sc2232->client, SC2232_REG_AGAIN_FINE, SC2232_REG_VALUE_08BIT, again_fine);
739 ret |= sc2232_write_reg(sc2232->client, SC2232_REG_DGAIN_FINE, SC2232_REG_VALUE_08BIT, dgain_fine);
740 return ret;
741 }
742
sc2232_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)743 static long sc2232_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
744 {
745 struct sc2232 *sc2232 = to_sc2232(sd);
746 struct rkmodule_hdr_cfg *hdr_cfg;
747 long ret = 0;
748 u32 stream;
749
750 switch (cmd) {
751 case PREISP_CMD_SET_HDRAE_EXP:
752 break;
753 case RKMODULE_SET_HDR_CFG:
754 break;
755 case RKMODULE_GET_MODULE_INFO:
756 sc2232_get_module_inf(sc2232, (struct rkmodule_inf *)arg);
757 break;
758 case RKMODULE_GET_HDR_CFG:
759 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
760 hdr_cfg->esp.mode = HDR_NORMAL_VC;
761 hdr_cfg->hdr_mode = sc2232->cur_mode->hdr_mode;
762 break;
763 case RKMODULE_SET_QUICK_STREAM:
764 stream = *((u32 *)arg);
765 if (stream)
766 ret = sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
767 SC2232_REG_VALUE_08BIT, SC2232_MODE_STREAMING);
768 else
769 ret = sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
770 SC2232_REG_VALUE_08BIT, SC2232_MODE_SW_STANDBY);
771 break;
772 default:
773 ret = -ENOIOCTLCMD;
774 break;
775 }
776
777 return ret;
778 }
779
780 #ifdef CONFIG_COMPAT
sc2232_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)781 static long sc2232_compat_ioctl32(struct v4l2_subdev *sd,
782 unsigned int cmd, unsigned long arg)
783 {
784 void __user *up = compat_ptr(arg);
785 struct rkmodule_inf *inf;
786 struct rkmodule_awb_cfg *cfg;
787 struct rkmodule_hdr_cfg *hdr;
788 struct preisp_hdrae_exp_s *hdrae;
789 long ret = 0;
790 u32 cg = 0;
791 u32 stream = 0;
792
793 switch (cmd) {
794 case RKMODULE_GET_MODULE_INFO:
795 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
796 if (!inf) {
797 ret = -ENOMEM;
798 return ret;
799 }
800
801 ret = sc2232_ioctl(sd, cmd, inf);
802 if (!ret) {
803 ret = copy_to_user(up, inf, sizeof(*inf));
804 if (ret)
805 ret = -EFAULT;
806 }
807 kfree(inf);
808 break;
809 case RKMODULE_AWB_CFG:
810 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
811 if (!cfg) {
812 ret = -ENOMEM;
813 return ret;
814 }
815
816 ret = copy_from_user(cfg, up, sizeof(*cfg));
817 if (!ret)
818 ret = sc2232_ioctl(sd, cmd, cfg);
819 else
820 ret = -EFAULT;
821 kfree(cfg);
822 break;
823 case RKMODULE_GET_HDR_CFG:
824 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
825 if (!hdr) {
826 ret = -ENOMEM;
827 return ret;
828 }
829
830 ret = sc2232_ioctl(sd, cmd, hdr);
831 if (!ret) {
832 ret = copy_to_user(up, hdr, sizeof(*hdr));
833 if (ret)
834 ret = -EFAULT;
835 }
836 kfree(hdr);
837 break;
838 case RKMODULE_SET_HDR_CFG:
839 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
840 if (!hdr) {
841 ret = -ENOMEM;
842 return ret;
843 }
844
845 ret = copy_from_user(hdr, up, sizeof(*hdr));
846 if (!ret)
847 ret = sc2232_ioctl(sd, cmd, hdr);
848 else
849 ret = -EFAULT;
850 kfree(hdr);
851 break;
852 case PREISP_CMD_SET_HDRAE_EXP:
853 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
854 if (!hdrae) {
855 ret = -ENOMEM;
856 return ret;
857 }
858
859 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
860 if (!ret)
861 ret = sc2232_ioctl(sd, cmd, hdrae);
862 else
863 ret = -EFAULT;
864 kfree(hdrae);
865 break;
866 case RKMODULE_SET_CONVERSION_GAIN:
867 ret = copy_from_user(&cg, up, sizeof(cg));
868 if (!ret)
869 ret = sc2232_ioctl(sd, cmd, &cg);
870 else
871 ret = -EFAULT;
872 break;
873 case RKMODULE_SET_QUICK_STREAM:
874 ret = copy_from_user(&stream, up, sizeof(u32));
875 if (!ret)
876 ret = sc2232_ioctl(sd, cmd, &stream);
877 else
878 ret = -EFAULT;
879 break;
880 default:
881 ret = -ENOIOCTLCMD;
882 break;
883 }
884
885 return ret;
886 }
887 #endif
888
__sc2232_start_stream(struct sc2232 * sc2232)889 static int __sc2232_start_stream(struct sc2232 *sc2232)
890 {
891 int ret;
892
893 ret = sc2232_write_array(sc2232->client, sc2232->cur_mode->reg_list);
894 if (ret)
895 return ret;
896
897 ret = __v4l2_ctrl_handler_setup(&sc2232->ctrl_handler);
898 if (ret)
899 return ret;
900
901 /* In case these controls are set before streaming */
902 if (sc2232->has_init_exp && sc2232->cur_mode->hdr_mode != NO_HDR) {
903 ret = sc2232_ioctl(&sc2232->subdev, PREISP_CMD_SET_HDRAE_EXP,
904 &sc2232->init_hdrae_exp);
905 if (ret) {
906 dev_err(&sc2232->client->dev,
907 "init exp fail in hdr mode\n");
908 return ret;
909 }
910 }
911
912 return sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
913 SC2232_REG_VALUE_08BIT, SC2232_MODE_STREAMING);
914 }
915
__sc2232_stop_stream(struct sc2232 * sc2232)916 static int __sc2232_stop_stream(struct sc2232 *sc2232)
917 {
918 sc2232->has_init_exp = false;
919 return sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
920 SC2232_REG_VALUE_08BIT, SC2232_MODE_SW_STANDBY);
921 }
922
sc2232_s_stream(struct v4l2_subdev * sd,int on)923 static int sc2232_s_stream(struct v4l2_subdev *sd, int on)
924 {
925 struct sc2232 *sc2232 = to_sc2232(sd);
926 struct i2c_client *client = sc2232->client;
927 int ret = 0;
928
929 mutex_lock(&sc2232->mutex);
930 on = !!on;
931 if (on == sc2232->streaming)
932 goto unlock_and_return;
933
934 if (on) {
935 ret = pm_runtime_get_sync(&client->dev);
936 if (ret < 0) {
937 pm_runtime_put_noidle(&client->dev);
938 goto unlock_and_return;
939 }
940
941 ret = __sc2232_start_stream(sc2232);
942 if (ret) {
943 v4l2_err(sd, "start stream failed while write regs\n");
944 pm_runtime_put(&client->dev);
945 goto unlock_and_return;
946 }
947 } else {
948 __sc2232_stop_stream(sc2232);
949 pm_runtime_put(&client->dev);
950 }
951
952 sc2232->streaming = on;
953
954 unlock_and_return:
955 mutex_unlock(&sc2232->mutex);
956
957 return ret;
958 }
959
sc2232_s_power(struct v4l2_subdev * sd,int on)960 static int sc2232_s_power(struct v4l2_subdev *sd, int on)
961 {
962 struct sc2232 *sc2232 = to_sc2232(sd);
963 struct i2c_client *client = sc2232->client;
964 int ret = 0;
965
966 mutex_lock(&sc2232->mutex);
967
968 /* If the power state is not modified - no work to do. */
969 if (sc2232->power_on == !!on)
970 goto unlock_and_return;
971
972 if (on) {
973 ret = pm_runtime_get_sync(&client->dev);
974 if (ret < 0) {
975 pm_runtime_put_noidle(&client->dev);
976 goto unlock_and_return;
977 }
978
979 ret |= sc2232_write_reg(sc2232->client,
980 SC2232_SOFTWARE_RESET_REG,
981 SC2232_REG_VALUE_08BIT,
982 0x01);
983 usleep_range(100, 200);
984
985 sc2232->power_on = true;
986 } else {
987 pm_runtime_put(&client->dev);
988 sc2232->power_on = false;
989 }
990
991 unlock_and_return:
992 mutex_unlock(&sc2232->mutex);
993
994 return ret;
995 }
996
__sc2232_power_on(struct sc2232 * sc2232)997 static int __sc2232_power_on(struct sc2232 *sc2232)
998 {
999 int ret;
1000 struct device *dev = &sc2232->client->dev;
1001
1002 if (!IS_ERR_OR_NULL(sc2232->pins_default)) {
1003 ret = pinctrl_select_state(sc2232->pinctrl,
1004 sc2232->pins_default);
1005 if (ret < 0)
1006 dev_err(dev, "could not set pins\n");
1007 }
1008 ret = clk_set_rate(sc2232->xvclk, SC2232_XVCLK_FREQ);
1009 if (ret < 0)
1010 dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
1011 if (clk_get_rate(sc2232->xvclk) != SC2232_XVCLK_FREQ)
1012 dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
1013 ret = clk_prepare_enable(sc2232->xvclk);
1014 if (ret < 0) {
1015 dev_err(dev, "Failed to enable xvclk\n");
1016 return ret;
1017 }
1018 if (!IS_ERR(sc2232->reset_gpio))
1019 gpiod_set_value_cansleep(sc2232->reset_gpio, 1);
1020
1021 ret = regulator_bulk_enable(SC2232_NUM_SUPPLIES, sc2232->supplies);
1022 if (ret < 0) {
1023 dev_err(dev, "Failed to enable regulators\n");
1024 goto disable_clk;
1025 }
1026
1027 if (!IS_ERR(sc2232->reset_gpio))
1028 gpiod_set_value_cansleep(sc2232->reset_gpio, 0);
1029
1030 usleep_range(500, 1000);
1031 if (!IS_ERR(sc2232->pwdn_gpio))
1032 gpiod_set_value_cansleep(sc2232->pwdn_gpio, 1);
1033 usleep_range(2000, 4000);
1034
1035 return 0;
1036
1037 disable_clk:
1038 clk_disable_unprepare(sc2232->xvclk);
1039
1040 return ret;
1041 }
1042
__sc2232_power_off(struct sc2232 * sc2232)1043 static void __sc2232_power_off(struct sc2232 *sc2232)
1044 {
1045 int ret;
1046 struct device *dev = &sc2232->client->dev;
1047
1048 if (!IS_ERR(sc2232->pwdn_gpio))
1049 gpiod_set_value_cansleep(sc2232->pwdn_gpio, 0);
1050 clk_disable_unprepare(sc2232->xvclk);
1051 if (!IS_ERR(sc2232->reset_gpio))
1052 gpiod_set_value_cansleep(sc2232->reset_gpio, 1);
1053 if (!IS_ERR_OR_NULL(sc2232->pins_sleep)) {
1054 ret = pinctrl_select_state(sc2232->pinctrl,
1055 sc2232->pins_sleep);
1056 if (ret < 0)
1057 dev_dbg(dev, "could not set pins\n");
1058 }
1059 regulator_bulk_disable(SC2232_NUM_SUPPLIES, sc2232->supplies);
1060 }
1061
sc2232_runtime_resume(struct device * dev)1062 static int sc2232_runtime_resume(struct device *dev)
1063 {
1064 struct i2c_client *client = to_i2c_client(dev);
1065 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1066 struct sc2232 *sc2232 = to_sc2232(sd);
1067
1068 return __sc2232_power_on(sc2232);
1069 }
1070
sc2232_runtime_suspend(struct device * dev)1071 static int sc2232_runtime_suspend(struct device *dev)
1072 {
1073 struct i2c_client *client = to_i2c_client(dev);
1074 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1075 struct sc2232 *sc2232 = to_sc2232(sd);
1076
1077 __sc2232_power_off(sc2232);
1078
1079 return 0;
1080 }
1081
1082 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc2232_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1083 static int sc2232_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1084 {
1085 struct sc2232 *sc2232 = to_sc2232(sd);
1086 struct v4l2_mbus_framefmt *try_fmt =
1087 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1088 const struct sc2232_mode *def_mode = &supported_modes[0];
1089
1090 mutex_lock(&sc2232->mutex);
1091 /* Initialize try_fmt */
1092 try_fmt->width = def_mode->width;
1093 try_fmt->height = def_mode->height;
1094 try_fmt->code = def_mode->bus_fmt;
1095 try_fmt->field = V4L2_FIELD_NONE;
1096
1097 mutex_unlock(&sc2232->mutex);
1098 /* No crop or compose */
1099
1100 return 0;
1101 }
1102 #endif
1103
sc2232_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1104 static int sc2232_enum_frame_interval(struct v4l2_subdev *sd,
1105 struct v4l2_subdev_pad_config *cfg,
1106 struct v4l2_subdev_frame_interval_enum *fie)
1107 {
1108 struct sc2232 *sc2232 = to_sc2232(sd);
1109
1110 if (fie->index >= sc2232->cfg_num)
1111 return -EINVAL;
1112
1113 fie->code = supported_modes[fie->index].bus_fmt;
1114 fie->width = supported_modes[fie->index].width;
1115 fie->height = supported_modes[fie->index].height;
1116 fie->interval = supported_modes[fie->index].max_fps;
1117 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1118 return 0;
1119 }
1120
1121 static const struct dev_pm_ops sc2232_pm_ops = {
1122 SET_RUNTIME_PM_OPS(sc2232_runtime_suspend,
1123 sc2232_runtime_resume, NULL)
1124 };
1125
1126 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1127 static const struct v4l2_subdev_internal_ops sc2232_internal_ops = {
1128 .open = sc2232_open,
1129 };
1130 #endif
1131
1132 static const struct v4l2_subdev_core_ops sc2232_core_ops = {
1133 .s_power = sc2232_s_power,
1134 .ioctl = sc2232_ioctl,
1135 #ifdef CONFIG_COMPAT
1136 .compat_ioctl32 = sc2232_compat_ioctl32,
1137 #endif
1138 };
1139
1140 static const struct v4l2_subdev_video_ops sc2232_video_ops = {
1141 .s_stream = sc2232_s_stream,
1142 .g_frame_interval = sc2232_g_frame_interval,
1143 };
1144
1145 static const struct v4l2_subdev_pad_ops sc2232_pad_ops = {
1146 .enum_mbus_code = sc2232_enum_mbus_code,
1147 .enum_frame_size = sc2232_enum_frame_sizes,
1148 .enum_frame_interval = sc2232_enum_frame_interval,
1149 .get_fmt = sc2232_get_fmt,
1150 .set_fmt = sc2232_set_fmt,
1151 .get_mbus_config = sc2232_g_mbus_config,
1152 };
1153
1154 static const struct v4l2_subdev_ops sc2232_subdev_ops = {
1155 .core = &sc2232_core_ops, /* v4l2_subdev_core_ops sc2232_core_ops */
1156 .video = &sc2232_video_ops, /* */
1157 .pad = &sc2232_pad_ops, /* */
1158 };
1159
sc2232_modify_fps_info(struct sc2232 * sc2232)1160 static void sc2232_modify_fps_info(struct sc2232 *sc2232)
1161 {
1162 const struct sc2232_mode *mode = sc2232->cur_mode;
1163
1164 sc2232->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1165 sc2232->cur_vts;
1166 }
1167
sc2232_set_ctrl(struct v4l2_ctrl * ctrl)1168 static int sc2232_set_ctrl(struct v4l2_ctrl *ctrl)
1169 {
1170 struct sc2232 *sc2232 = container_of(ctrl->handler,
1171 struct sc2232, ctrl_handler);
1172 struct i2c_client *client = sc2232->client;
1173 s64 max;
1174 int ret = 0;
1175 u32 val;
1176
1177 /* Propagate change of current control to all related controls */
1178 switch (ctrl->id) {
1179 case V4L2_CID_VBLANK:
1180 /* Update max exposure while meeting expected vblanking */
1181 max = sc2232->cur_mode->height + ctrl->val - 2;
1182 __v4l2_ctrl_modify_range(sc2232->exposure,
1183 sc2232->exposure->minimum, max,
1184 sc2232->exposure->step,
1185 sc2232->exposure->default_value);
1186 break;
1187 }
1188
1189 if (!pm_runtime_get_if_in_use(&client->dev))
1190 return 0;
1191
1192 switch (ctrl->id) {
1193 case V4L2_CID_EXPOSURE:
1194 if (sc2232->cur_mode->hdr_mode != NO_HDR)
1195 goto ctrl_end;
1196 val = ctrl->val << 1;
1197 ret = sc2232_write_reg(sc2232->client,
1198 SC2232_REG_EXP_LONG_L,
1199 SC2232_REG_VALUE_08BIT,
1200 (val << 4 & 0XF0));
1201 ret |= sc2232_write_reg(sc2232->client,
1202 SC2232_REG_EXP_LONG_M,
1203 SC2232_REG_VALUE_08BIT,
1204 (val >> 4 & 0XFF));
1205 ret |= sc2232_write_reg(sc2232->client,
1206 SC2232_REG_EXP_LONG_H,
1207 SC2232_REG_VALUE_08BIT,
1208 (val >> 12 & 0X0F));
1209 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1210 break;
1211 case V4L2_CID_ANALOGUE_GAIN:
1212 if (sc2232->cur_mode->hdr_mode != NO_HDR)
1213 goto ctrl_end;
1214 ret = sc2232_set_gain(sc2232, ctrl->val);
1215 break;
1216 case V4L2_CID_VBLANK:
1217 ret = sc2232_write_reg(sc2232->client, SC2232_REG_VTS,
1218 SC2232_REG_VALUE_16BIT,
1219 ctrl->val + sc2232->cur_mode->height);
1220 if (!ret)
1221 sc2232->cur_vts = ctrl->val + sc2232->cur_mode->height;
1222 sc2232_modify_fps_info(sc2232);
1223 dev_dbg(&client->dev, "set vblank 0x%x\n",
1224 ctrl->val);
1225 break;
1226 case V4L2_CID_TEST_PATTERN:
1227 break;
1228 case V4L2_CID_HFLIP:
1229 ret = sc2232_read_reg(sc2232->client, SC2232_FLIP_REG,
1230 SC2232_REG_VALUE_08BIT, &val);
1231 if (ret)
1232 break;
1233 if (ctrl->val)
1234 val |= SC2232_MIRROR_MASK;
1235 else
1236 val &= ~SC2232_MIRROR_MASK;
1237 ret |= sc2232_write_reg(sc2232->client, SC2232_FLIP_REG,
1238 SC2232_REG_VALUE_08BIT, val);
1239 break;
1240 case V4L2_CID_VFLIP:
1241 ret = sc2232_read_reg(sc2232->client, SC2232_FLIP_REG,
1242 SC2232_REG_VALUE_08BIT, &val);
1243 if (ret)
1244 break;
1245 if (ctrl->val)
1246 val |= SC2232_FLIP_MASK;
1247 else
1248 val &= ~SC2232_FLIP_MASK;
1249 ret |= sc2232_write_reg(sc2232->client, SC2232_FLIP_REG,
1250 SC2232_REG_VALUE_08BIT, val);
1251 break;
1252 default:
1253 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1254 __func__, ctrl->id, ctrl->val);
1255 break;
1256 }
1257
1258 ctrl_end:
1259 pm_runtime_put(&client->dev);
1260 return ret;
1261 }
1262
1263 static const struct v4l2_ctrl_ops sc2232_ctrl_ops = {
1264 .s_ctrl = sc2232_set_ctrl,
1265 };
1266
sc2232_initialize_controls(struct sc2232 * sc2232)1267 static int sc2232_initialize_controls(struct sc2232 *sc2232)
1268 {
1269 const struct sc2232_mode *mode;
1270 struct v4l2_ctrl_handler *handler;
1271 s64 exposure_max, vblank_def;
1272 u32 h_blank;
1273 int ret;
1274 u64 pixel_rate = 0;
1275
1276 handler = &sc2232->ctrl_handler;
1277 mode = sc2232->cur_mode;
1278 ret = v4l2_ctrl_handler_init(handler, 9);
1279 if (ret)
1280 return ret;
1281 handler->lock = &sc2232->mutex;
1282
1283 sc2232->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1284 V4L2_CID_LINK_FREQ,
1285 ARRAY_SIZE(link_freq_items) - 1, 0,
1286 link_freq_items);
1287 __v4l2_ctrl_s_ctrl(sc2232->link_freq, mode->mipi_freq_idx);
1288
1289 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1290 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC2232_LANES;
1291 sc2232->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1292 V4L2_CID_PIXEL_RATE, 0, SC2232_MAX_PIXEL_RATE,
1293 1, pixel_rate);
1294
1295 h_blank = mode->hts_def - mode->width;
1296 sc2232->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1297 h_blank, h_blank, 1, h_blank);
1298 if (sc2232->hblank)
1299 sc2232->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1300
1301 vblank_def = mode->vts_def - mode->height;
1302 sc2232->vblank = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
1303 V4L2_CID_VBLANK, vblank_def,
1304 SC2232_VTS_MAX - mode->height,
1305 1, vblank_def);
1306
1307 exposure_max = mode->vts_def - 2;
1308 sc2232->exposure = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
1309 V4L2_CID_EXPOSURE, SC2232_EXPOSURE_MIN,
1310 exposure_max, SC2232_EXPOSURE_STEP,
1311 mode->exp_def);
1312
1313 sc2232->anal_gain = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
1314 V4L2_CID_ANALOGUE_GAIN, SC2232_GAIN_MIN,
1315 SC2232_GAIN_MAX, SC2232_GAIN_STEP,
1316 SC2232_GAIN_DEFAULT);
1317
1318 v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1319 v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1320
1321 if (handler->error) {
1322 ret = handler->error;
1323 dev_err(&sc2232->client->dev,
1324 "Failed to init controls(%d)\n", ret);
1325 goto err_free_handler;
1326 }
1327
1328 sc2232->subdev.ctrl_handler = handler;
1329 sc2232->has_init_exp = false;
1330 sc2232->cur_vts = mode->vts_def;
1331 sc2232->cur_fps = mode->max_fps;
1332
1333 return 0;
1334
1335 err_free_handler:
1336 v4l2_ctrl_handler_free(handler);
1337
1338 return ret;
1339 }
1340
sc2232_check_sensor_id(struct sc2232 * sc2232,struct i2c_client * client)1341 static int sc2232_check_sensor_id(struct sc2232 *sc2232,
1342 struct i2c_client *client)
1343 {
1344 struct device *dev = &sc2232->client->dev;
1345 u32 id = 0;
1346 int ret;
1347
1348 ret = sc2232_read_reg(client, SC2232_REG_CHIP_ID,
1349 SC2232_REG_VALUE_16BIT, &id);
1350 if (id != CHIP_ID) {
1351 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1352 return -ENODEV;
1353 }
1354
1355 dev_info(dev, "Detected SC%04x sensor\n", CHIP_ID);
1356 return 0;
1357 }
1358
sc2232_configure_regulators(struct sc2232 * sc2232)1359 static int sc2232_configure_regulators(struct sc2232 *sc2232)
1360 {
1361 unsigned int i;
1362
1363 for (i = 0; i < SC2232_NUM_SUPPLIES; i++)
1364 sc2232->supplies[i].supply = sc2232_supply_names[i];
1365
1366 return devm_regulator_bulk_get(&sc2232->client->dev,
1367 SC2232_NUM_SUPPLIES,
1368 sc2232->supplies);
1369 }
1370
sc2232_probe(struct i2c_client * client,const struct i2c_device_id * id)1371 static int sc2232_probe(struct i2c_client *client,
1372 const struct i2c_device_id *id)
1373 {
1374 struct device *dev = &client->dev;
1375 struct device_node *node = dev->of_node;
1376 struct sc2232 *sc2232;
1377 struct v4l2_subdev *sd;
1378 char facing[2];
1379 int ret;
1380 u32 i, hdr_mode = 0;
1381
1382 dev_info(dev, "driver version: %02x.%02x.%02x",
1383 DRIVER_VERSION >> 16,
1384 (DRIVER_VERSION & 0xff00) >> 8,
1385 DRIVER_VERSION & 0x00ff);
1386
1387 sc2232 = devm_kzalloc(dev, sizeof(*sc2232), GFP_KERNEL);
1388 if (!sc2232)
1389 return -ENOMEM;
1390
1391 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1392 &sc2232->module_index);
1393 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1394 &sc2232->module_facing);
1395 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1396 &sc2232->module_name);
1397 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1398 &sc2232->len_name);
1399 if (ret) {
1400 dev_err(dev, "could not get module information!\n");
1401 return -EINVAL;
1402 }
1403
1404 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
1405 &hdr_mode);
1406
1407 if (ret) {
1408 hdr_mode = NO_HDR;
1409 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1410 }
1411
1412 sc2232->cfg_num = ARRAY_SIZE(supported_modes);
1413 for (i = 0; i < sc2232->cfg_num; i++) {
1414 if (hdr_mode == supported_modes[i].hdr_mode) {
1415 sc2232->cur_mode = &supported_modes[i];
1416 break;
1417 }
1418 }
1419 sc2232->client = client;
1420
1421 sc2232->xvclk = devm_clk_get(dev, "xvclk");
1422 if (IS_ERR(sc2232->xvclk)) {
1423 dev_err(dev, "Failed to get xvclk\n");
1424 return -EINVAL;
1425 }
1426
1427 sc2232->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1428 if (IS_ERR(sc2232->reset_gpio))
1429 dev_warn(dev, "Failed to get reset-gpios\n");
1430
1431 sc2232->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1432 if (IS_ERR(sc2232->pwdn_gpio))
1433 dev_warn(dev, "Failed to get pwdn-gpios\n");
1434
1435 sc2232->pinctrl = devm_pinctrl_get(dev);
1436 if (!IS_ERR(sc2232->pinctrl)) {
1437 sc2232->pins_default =
1438 pinctrl_lookup_state(sc2232->pinctrl,
1439 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1440 if (IS_ERR(sc2232->pins_default))
1441 dev_err(dev, "could not get default pinstate\n");
1442
1443 sc2232->pins_sleep =
1444 pinctrl_lookup_state(sc2232->pinctrl,
1445 OF_CAMERA_PINCTRL_STATE_SLEEP);
1446 if (IS_ERR(sc2232->pins_sleep))
1447 dev_err(dev, "could not get sleep pinstate\n");
1448 } else {
1449 dev_err(dev, "no pinctrl\n");
1450 }
1451
1452 ret = sc2232_configure_regulators(sc2232);
1453 if (ret) {
1454 dev_err(dev, "Failed to get power regulators\n");
1455 return ret;
1456 }
1457
1458 mutex_init(&sc2232->mutex);
1459
1460 sd = &sc2232->subdev;
1461 v4l2_i2c_subdev_init(sd, client, &sc2232_subdev_ops);
1462 ret = sc2232_initialize_controls(sc2232);
1463 if (ret)
1464 goto err_destroy_mutex;
1465
1466 ret = __sc2232_power_on(sc2232);
1467 if (ret)
1468 goto err_free_handler;
1469
1470 ret = sc2232_check_sensor_id(sc2232, client);
1471 if (ret)
1472 goto err_power_off;
1473
1474 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1475 sd->internal_ops = &sc2232_internal_ops;
1476 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1477 #endif
1478 #if defined(CONFIG_MEDIA_CONTROLLER)
1479 sc2232->pad.flags = MEDIA_PAD_FL_SOURCE;
1480 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1481 ret = media_entity_pads_init(&sd->entity, 1, &sc2232->pad);
1482 if (ret < 0)
1483 goto err_power_off;
1484 #endif
1485
1486 memset(facing, 0, sizeof(facing));
1487 if (strcmp(sc2232->module_facing, "back") == 0)
1488 facing[0] = 'b';
1489 else
1490 facing[0] = 'f';
1491
1492 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1493 sc2232->module_index, facing,
1494 SC2232_NAME, dev_name(sd->dev));
1495 ret = v4l2_async_register_subdev_sensor_common(sd);
1496 if (ret) {
1497 dev_err(dev, "v4l2 async register subdev failed\n");
1498 goto err_clean_entity;
1499 }
1500
1501 pm_runtime_set_active(dev);
1502 pm_runtime_enable(dev);
1503 pm_runtime_idle(dev);
1504 #ifdef USED_SYS_DEBUG
1505 add_sysfs_interfaces(dev);
1506 #endif
1507 return 0;
1508
1509 err_clean_entity:
1510 #if defined(CONFIG_MEDIA_CONTROLLER)
1511 media_entity_cleanup(&sd->entity);
1512 #endif
1513 err_power_off:
1514 __sc2232_power_off(sc2232);
1515 err_free_handler:
1516 v4l2_ctrl_handler_free(&sc2232->ctrl_handler);
1517 err_destroy_mutex:
1518 mutex_destroy(&sc2232->mutex);
1519
1520 return ret;
1521 }
1522
sc2232_remove(struct i2c_client * client)1523 static int sc2232_remove(struct i2c_client *client)
1524 {
1525 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1526 struct sc2232 *sc2232 = to_sc2232(sd);
1527
1528 v4l2_async_unregister_subdev(sd);
1529 #if defined(CONFIG_MEDIA_CONTROLLER)
1530 media_entity_cleanup(&sd->entity);
1531 #endif
1532 v4l2_ctrl_handler_free(&sc2232->ctrl_handler);
1533 mutex_destroy(&sc2232->mutex);
1534
1535 pm_runtime_disable(&client->dev);
1536 if (!pm_runtime_status_suspended(&client->dev))
1537 __sc2232_power_off(sc2232);
1538 pm_runtime_set_suspended(&client->dev);
1539
1540 return 0;
1541 }
1542
1543 #if IS_ENABLED(CONFIG_OF)
1544 static const struct of_device_id sc2232_of_match[] = {
1545 { .compatible = "smartsens,sc2232" },
1546 { },
1547 };
1548 MODULE_DEVICE_TABLE(of, sc2232_of_match);
1549 #endif
1550
1551 static const struct i2c_device_id sc2232_match_id[] = {
1552 { "smartsens,sc2232", 0 },
1553 { },
1554 };
1555
1556 static struct i2c_driver sc2232_i2c_driver = {
1557 .driver = {
1558 .name = SC2232_NAME,
1559 .pm = &sc2232_pm_ops,
1560 .of_match_table = of_match_ptr(sc2232_of_match),
1561 },
1562 .probe = &sc2232_probe,
1563 .remove = &sc2232_remove,
1564 .id_table = sc2232_match_id,
1565 };
1566
1567 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
1568 module_i2c_driver(sc2232_i2c_driver);
1569 #else
sensor_mod_init(void)1570 static int __init sensor_mod_init(void)
1571 {
1572 return i2c_add_driver(&sc2232_i2c_driver);
1573 }
1574
sensor_mod_exit(void)1575 static void __exit sensor_mod_exit(void)
1576 {
1577 i2c_del_driver(&sc2232_i2c_driver);
1578 }
1579
1580 device_initcall_sync(sensor_mod_init);
1581 module_exit(sensor_mod_exit);
1582 #endif
1583
1584 MODULE_DESCRIPTION("Smartsens sc2232 sensor driver");
1585 MODULE_LICENSE("GPL v2");
1586