1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc200ai driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 add quick stream on/off.
12 * V0.0X01.0X06 fix set vflip/hflip failed bug.
13 * V0.0X01.0X07
14 * 1. fix set double times exposue value failed issue.
15 * 2. add some debug info.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/i2c.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/sysfs.h>
27 #include <linux/slab.h>
28 #include <linux/version.h>
29 #include <linux/rk-camera-module.h>
30 #include <linux/rk-preisp.h>
31 #include <media/media-entity.h>
32 #include <media/v4l2-async.h>
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-subdev.h>
35 #include <linux/pinctrl/consumer.h>
36 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
37
38 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
39
40 #ifndef V4L2_CID_DIGITAL_GAIN
41 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
42 #endif
43
44 #define SC200AI_LANES 2
45 #define SC200AI_BITS_PER_SAMPLE 10
46 #define SC200AI_LINK_FREQ_371 371250000// 742.5Mbps
47
48 #define PIXEL_RATE_WITH_371M_10BIT (SC200AI_LINK_FREQ_371 * 2 * \
49 SC200AI_LANES / SC200AI_BITS_PER_SAMPLE)
50
51 #define SC200AI_XVCLK_FREQ 27000000
52
53 #define CHIP_ID 0xcb1c
54 #define SC200AI_REG_CHIP_ID 0x3107
55
56 #define SC200AI_REG_CTRL_MODE 0x0100
57 #define SC200AI_MODE_SW_STANDBY 0x0
58 #define SC200AI_MODE_STREAMING BIT(0)
59
60 #define SC200AI_REG_EXPOSURE_H 0x3e00
61 #define SC200AI_REG_EXPOSURE_M 0x3e01
62 #define SC200AI_REG_EXPOSURE_L 0x3e02
63 #define SC200AI_REG_SEXPOSURE_H 0x3e22
64 #define SC200AI_REG_SEXPOSURE_M 0x3e04
65 #define SC200AI_REG_SEXPOSURE_L 0x3e05
66 #define SC200AI_EXPOSURE_MIN 1
67 #define SC200AI_EXPOSURE_STEP 1
68 #define SC200AI_VTS_MAX 0x7fff
69
70 #define SC200AI_REG_DIG_GAIN 0x3e06
71 #define SC200AI_REG_DIG_FINE_GAIN 0x3e07
72 #define SC200AI_REG_ANA_GAIN 0x3e08
73 #define SC200AI_REG_ANA_FINE_GAIN 0x3e09
74 #define SC200AI_REG_SDIG_GAIN 0x3e10
75 #define SC200AI_REG_SDIG_FINE_GAIN 0x3e11
76 #define SC200AI_REG_SANA_GAIN 0x3e12
77 #define SC200AI_REG_SANA_FINE_GAIN 0x3e13
78 #define SC200AI_GAIN_MIN 0x0040
79 #define SC200AI_GAIN_MAX (54 * 32 * 64) //53.975*31.75*64
80 #define SC200AI_GAIN_STEP 1
81 #define SC200AI_GAIN_DEFAULT 0x0800
82 #define SC200AI_LGAIN 0
83 #define SC200AI_SGAIN 1
84
85 #define SC200AI_REG_GROUP_HOLD 0x3812
86 #define SC200AI_GROUP_HOLD_START 0x00
87 #define SC200AI_GROUP_HOLD_END 0x30
88
89 #define SC200AI_REG_HIGH_TEMP_H 0x3974
90 #define SC200AI_REG_HIGH_TEMP_L 0x3975
91
92 #define SC200AI_REG_TEST_PATTERN 0x4501
93 #define SC200AI_TEST_PATTERN_BIT_MASK BIT(3)
94
95 #define SC200AI_REG_VTS_H 0x320e
96 #define SC200AI_REG_VTS_L 0x320f
97
98 #define SC200AI_FLIP_MIRROR_REG 0x3221
99
100 #define SC200AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
101 #define SC200AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
102 #define SC200AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
103
104 #define SC200AI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
105 #define SC200AI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
106
107 #define SC200AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
108 #define SC200AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
109
110 #define REG_DELAY 0xFFFE
111 #define REG_NULL 0xFFFF
112
113 #define SC200AI_REG_VALUE_08BIT 1
114 #define SC200AI_REG_VALUE_16BIT 2
115 #define SC200AI_REG_VALUE_24BIT 3
116
117 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
118 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
119 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
120 #define SC200AI_NAME "sc200ai"
121
122 static const char * const sc200ai_supply_names[] = {
123 "avdd", /* Analog power */
124 "dovdd", /* Digital I/O power */
125 "dvdd", /* Digital core power */
126 };
127
128 #define SC200AI_NUM_SUPPLIES ARRAY_SIZE(sc200ai_supply_names)
129
130 struct regval {
131 u16 addr;
132 u8 val;
133 };
134
135 struct sc200ai_mode {
136 u32 bus_fmt;
137 u32 width;
138 u32 height;
139 struct v4l2_fract max_fps;
140 u32 hts_def;
141 u32 vts_def;
142 u32 exp_def;
143 const struct regval *reg_list;
144 u32 hdr_mode;
145 u32 vc[PAD_MAX];
146 };
147
148 struct sc200ai {
149 struct i2c_client *client;
150 struct clk *xvclk;
151 struct gpio_desc *reset_gpio;
152 struct gpio_desc *pwdn_gpio;
153 struct regulator_bulk_data supplies[SC200AI_NUM_SUPPLIES];
154
155 struct pinctrl *pinctrl;
156 struct pinctrl_state *pins_default;
157 struct pinctrl_state *pins_sleep;
158
159 struct v4l2_subdev subdev;
160 struct media_pad pad;
161 struct v4l2_ctrl_handler ctrl_handler;
162 struct v4l2_ctrl *exposure;
163 struct v4l2_ctrl *anal_gain;
164 struct v4l2_ctrl *digi_gain;
165 struct v4l2_ctrl *hblank;
166 struct v4l2_ctrl *vblank;
167 struct v4l2_ctrl *test_pattern;
168 struct mutex mutex;
169 struct v4l2_fract cur_fps;
170 bool streaming;
171 bool power_on;
172 const struct sc200ai_mode *cur_mode;
173 u32 module_index;
174 const char *module_facing;
175 const char *module_name;
176 const char *len_name;
177 u32 cur_vts;
178 bool has_init_exp;
179 bool is_thunderboot;
180 bool is_first_streamoff;
181 struct preisp_hdrae_exp_s init_hdrae_exp;
182 };
183
184 #define to_sc200ai(sd) container_of(sd, struct sc200ai, subdev)
185
186 /*
187 * Xclk 24Mhz
188 */
189 static const struct regval sc200ai_global_regs[] = {
190 {REG_NULL, 0x00},
191 };
192
193 /*
194 * Xclk 24Mhz
195 * max_framerate 60fps
196 * mipi_datarate per lane 1008Mbps, 4lane
197 */
198 static const struct regval sc200ai_linear_10_1920x1080_60fps_regs[] = {
199 {0x0103, 0x01},
200 {0x0100, 0x00},
201 {0x36e9, 0x80},
202 {0x36f9, 0x80},
203 {0x301f, 0x01},
204 {0x3243, 0x01},
205 {0x3248, 0x02},
206 {0x3249, 0x09},
207 {0x3253, 0x08},
208 {0x3271, 0x0a},
209 {0x3301, 0x06},
210 {0x3302, 0x0c},
211 {0x3303, 0x08},
212 {0x3304, 0x60},
213 {0x3306, 0x30},
214 {0x3308, 0x10},
215 {0x3309, 0x70},
216 {0x330b, 0x80},
217 {0x330d, 0x16},
218 {0x330e, 0x1c},
219 {0x330f, 0x02},
220 {0x3310, 0x02},
221 {0x331c, 0x04},
222 {0x331e, 0x51},
223 {0x331f, 0x61},
224 {0x3320, 0x07},
225 {0x3333, 0x10},
226 {0x334c, 0x08},
227 {0x3356, 0x09},
228 {0x3364, 0x17},
229 {0x3390, 0x08},
230 {0x3391, 0x18},
231 {0x3392, 0x38},
232 {0x3393, 0x06},
233 {0x3394, 0x06},
234 {0x3395, 0x06},
235 {0x3396, 0x08},
236 {0x3397, 0x18},
237 {0x3398, 0x38},
238 {0x3399, 0x06},
239 {0x339a, 0x0a},
240 {0x339b, 0x10},
241 {0x339c, 0x20},
242 {0x33ac, 0x08},
243 {0x33ae, 0x10},
244 {0x33af, 0x19},
245 {0x3621, 0xe8},
246 {0x3622, 0x16},
247 {0x3630, 0xa0},
248 {0x3637, 0x36},
249 {0x363a, 0x1f},
250 {0x363b, 0xc6},
251 {0x363c, 0x0e},
252 {0x3670, 0x0a},
253 {0x3674, 0x82},
254 {0x3675, 0x76},
255 {0x3676, 0x78},
256 {0x367c, 0x48},
257 {0x367d, 0x58},
258 {0x3690, 0x34},
259 {0x3691, 0x33},
260 {0x3692, 0x44},
261 {0x369c, 0x40},
262 {0x369d, 0x48},
263 {0x36eb, 0x0c},
264 {0x36ec, 0x0c},
265 {0x36fd, 0x14},
266 {0x3901, 0x02},
267 {0x3904, 0x04},
268 {0x3908, 0x41},
269 {0x391f, 0x10},
270 {0x3e01, 0x8c},
271 {0x3e02, 0x20},
272 {0x3e16, 0x00},
273 {0x3e17, 0x80},
274 {0x3f09, 0x48},
275 {0x4819, 0x09},
276 {0x481b, 0x05},
277 {0x481d, 0x14},
278 {0x481f, 0x04},
279 {0x4821, 0x0a},
280 {0x4823, 0x05},
281 {0x4825, 0x04},
282 {0x4827, 0x05},
283 {0x4829, 0x08},
284 {0x5787, 0x10},
285 {0x5788, 0x06},
286 {0x578a, 0x10},
287 {0x578b, 0x06},
288 {0x5790, 0x10},
289 {0x5791, 0x10},
290 {0x5792, 0x00},
291 {0x5793, 0x10},
292 {0x5794, 0x10},
293 {0x5795, 0x00},
294 {0x5799, 0x00},
295 {0x57c7, 0x10},
296 {0x57c8, 0x06},
297 {0x57ca, 0x10},
298 {0x57cb, 0x06},
299 {0x57d1, 0x10},
300 {0x57d4, 0x10},
301 {0x57d9, 0x00},
302 {0x59e0, 0x60},
303 {0x59e1, 0x08},
304 {0x59e2, 0x3f},
305 {0x59e3, 0x18},
306 {0x59e4, 0x18},
307 {0x59e5, 0x3f},
308 {0x59e6, 0x06},
309 {0x59e7, 0x02},
310 {0x59e8, 0x38},
311 {0x59e9, 0x10},
312 {0x59ea, 0x0c},
313 {0x59eb, 0x10},
314 {0x59ec, 0x04},
315 {0x59ed, 0x02},
316 {0x59ee, 0xa0},
317 {0x59ef, 0x08},
318 {0x59f4, 0x18},
319 {0x59f5, 0x10},
320 {0x59f6, 0x0c},
321 {0x59f7, 0x10},
322 {0x59f8, 0x06},
323 {0x59f9, 0x02},
324 {0x59fa, 0x18},
325 {0x59fb, 0x10},
326 {0x59fc, 0x0c},
327 {0x59fd, 0x10},
328 {0x59fe, 0x04},
329 {0x59ff, 0x02},
330 {0x36e9, 0x20},
331 {0x36f9, 0x24},
332 {REG_NULL, 0x00},
333 };
334
335 /*
336 * Xclk 27Mhz
337 * max_framerate 30fps
338 * mipi_datarate per lane 371.25Mbps, 2lane
339 */
340 static const struct regval sc200ai_linear_10_1920x1080_30fps_regs[] = {
341 {0x0103, 0x01},
342 {0x0100, 0x00},
343 {0x36e9, 0x80},
344 {0x36f9, 0x80},
345 {0x301f, 0x03},
346 //HTS=1100*2=2200
347 {0x320c, 0x04},
348 {0x320d, 0x4c},
349 //VTS=1125
350 {0x320e, 0x04},
351 {0x320f, 0x65},
352 {0x3243, 0x01},
353 {0x3248, 0x02},
354 {0x3249, 0x09},
355 {0x3253, 0x08},
356 {0x3271, 0x0a},
357 {0x3301, 0x20},
358 {0x3304, 0x40},
359 {0x3306, 0x32},
360 {0x330b, 0x88},
361 {0x330f, 0x02},
362 {0x331e, 0x39},
363 {0x3333, 0x10},
364 {0x3621, 0xe8},
365 {0x3622, 0x16},
366 {0x3637, 0x1b},
367 {0x363a, 0x1f},
368 {0x363b, 0xc6},
369 {0x363c, 0x0e},
370 {0x3670, 0x0a},
371 {0x3674, 0x82},
372 {0x3675, 0x76},
373 {0x3676, 0x78},
374 {0x367c, 0x48},
375 {0x367d, 0x58},
376 {0x3690, 0x34},
377 {0x3691, 0x33},
378 {0x3692, 0x44},
379 {0x369c, 0x40},
380 {0x369d, 0x48},
381 {0x3901, 0x02},
382 {0x3904, 0x04},
383 {0x3908, 0x41},
384 {0x391d, 0x14},
385 {0x391f, 0x18},
386 {0x3e01, 0x8c},
387 {0x3e02, 0x20},
388 {0x3e16, 0x00},
389 {0x3e17, 0x80},
390 {0x3f09, 0x48},
391 {0x5787, 0x10},
392 {0x5788, 0x06},
393 {0x578a, 0x10},
394 {0x578b, 0x06},
395 {0x5790, 0x10},
396 {0x5791, 0x10},
397 {0x5792, 0x00},
398 {0x5793, 0x10},
399 {0x5794, 0x10},
400 {0x5795, 0x00},
401 {0x5799, 0x00},
402 {0x57c7, 0x10},
403 {0x57c8, 0x06},
404 {0x57ca, 0x10},
405 {0x57cb, 0x06},
406 {0x57d1, 0x10},
407 {0x57d4, 0x10},
408 {0x57d9, 0x00},
409 {0x59e0, 0x60},
410 {0x59e1, 0x08},
411 {0x59e2, 0x3f},
412 {0x59e3, 0x18},
413 {0x59e4, 0x18},
414 {0x59e5, 0x3f},
415 {0x59e6, 0x06},
416 {0x59e7, 0x02},
417 {0x59e8, 0x38},
418 {0x59e9, 0x10},
419 {0x59ea, 0x0c},
420 {0x59eb, 0x10},
421 {0x59ec, 0x04},
422 {0x59ed, 0x02},
423 {0x59ee, 0xa0},
424 {0x59ef, 0x08},
425 {0x59f4, 0x18},
426 {0x59f5, 0x10},
427 {0x59f6, 0x0c},
428 {0x59f7, 0x10},
429 {0x59f8, 0x06},
430 {0x59f9, 0x02},
431 {0x59fa, 0x18},
432 {0x59fb, 0x10},
433 {0x59fc, 0x0c},
434 {0x59fd, 0x10},
435 {0x59fe, 0x04},
436 {0x59ff, 0x02},
437 {0x36e9, 0x20},
438 {0x36f9, 0x27},
439 {REG_NULL, 0x00},
440 };
441
442 /*
443 * Xclk 27Mhz
444 * max_framerate 30fps
445 * mipi_datarate per lane 742.5Mbps, HDR 2lane
446 */
447 static const struct regval sc200ai_hdr_10_1920x1080_regs[] = {
448 {0x0103, 0x01},
449 {0x0100, 0x00},
450 {0x36e9, 0x80},
451 {0x36f9, 0x80},
452 {0x301f, 0x02},
453 //HTS=1100*2=2200
454 {0x320c, 0x04},
455 {0x320d, 0x4c},
456 //VTS =2252
457 {0x320e, 0x08},
458 {0x320f, 0xcc},
459 {0x3220, 0x53},
460 {0x3243, 0x01},
461 {0x3248, 0x02},
462 {0x3249, 0x09},
463 {0x3250, 0x3f},
464 {0x3253, 0x08},
465 {0x3271, 0x0a},
466 {0x3301, 0x06},
467 {0x3302, 0x0c},
468 {0x3303, 0x08},
469 {0x3304, 0x60},
470 {0x3306, 0x30},
471 {0x3308, 0x10},
472 {0x3309, 0x70},
473 {0x330b, 0x80},
474 {0x330d, 0x16},
475 {0x330e, 0x1c},
476 {0x330f, 0x02},
477 {0x3310, 0x02},
478 {0x331c, 0x04},
479 {0x331e, 0x51},
480 {0x331f, 0x61},
481 {0x3320, 0x07},
482 {0x3333, 0x10},
483 {0x3347, 0x77},
484 {0x334c, 0x08},
485 {0x3356, 0x09},
486 {0x3364, 0x17},
487 {0x336c, 0xcc},
488 {0x3390, 0x08},
489 {0x3391, 0x18},
490 {0x3392, 0x38},
491 {0x3393, 0x06},
492 {0x3394, 0x06},
493 {0x3395, 0x06},
494 {0x3396, 0x08},
495 {0x3397, 0x18},
496 {0x3398, 0x38},
497 {0x3399, 0x06},
498 {0x339a, 0x0a},
499 {0x339b, 0x10},
500 {0x339c, 0x20},
501 {0x33ac, 0x08},
502 {0x33ae, 0x10},
503 {0x33af, 0x19},
504 {0x3621, 0xe8},
505 {0x3622, 0x16},
506 {0x3630, 0xa0},
507 {0x3637, 0x36},
508 {0x363a, 0x1f},
509 {0x363b, 0xc6},
510 {0x363c, 0x0e},
511 {0x3670, 0x0a},
512 {0x3674, 0x82},
513 {0x3675, 0x76},
514 {0x3676, 0x78},
515 {0x367c, 0x48},
516 {0x367d, 0x58},
517 {0x3690, 0x34},
518 {0x3691, 0x33},
519 {0x3692, 0x44},
520 {0x369c, 0x40},
521 {0x369d, 0x48},
522 {0x36eb, 0x0c},
523 {0x36ec, 0x0c},
524 {0x36fd, 0x14},
525 {0x3901, 0x02},
526 {0x3904, 0x04},
527 {0x3908, 0x41},
528 {0x391f, 0x10},
529 {0x3e00, 0x01},
530 {0x3e01, 0x06},
531 {0x3e02, 0x00},
532 {0x3e04, 0x10},
533 {0x3e05, 0x60},
534 {0x3e06, 0x00},
535 {0x3e07, 0x80},
536 {0x3e08, 0x03},
537 {0x3e09, 0x40},
538 {0x3e10, 0x00},
539 {0x3e11, 0x80},
540 {0x3e12, 0x03},
541 {0x3e13, 0x40},
542 {0x3e16, 0x00},
543 {0x3e17, 0x80},
544 {0x3e23, 0x01},
545 {0x3e24, 0x9e},
546 {0x3f09, 0x48},
547 {0x4816, 0xb1},
548 {0x4819, 0x09},
549 {0x481b, 0x05},
550 {0x481d, 0x14},
551 {0x481f, 0x04},
552 {0x4821, 0x0a},
553 {0x4823, 0x05},
554 {0x4825, 0x04},
555 {0x4827, 0x05},
556 {0x4829, 0x08},
557 {0x5787, 0x10},
558 {0x5788, 0x06},
559 {0x578a, 0x10},
560 {0x578b, 0x06},
561 {0x5790, 0x10},
562 {0x5791, 0x10},
563 {0x5792, 0x00},
564 {0x5793, 0x10},
565 {0x5794, 0x10},
566 {0x5795, 0x00},
567 {0x5799, 0x00},
568 {0x57c7, 0x10},
569 {0x57c8, 0x06},
570 {0x57ca, 0x10},
571 {0x57cb, 0x06},
572 {0x57d1, 0x10},
573 {0x57d4, 0x10},
574 {0x57d9, 0x00},
575 {0x59e0, 0x60},
576 {0x59e1, 0x08},
577 {0x59e2, 0x3f},
578 {0x59e3, 0x18},
579 {0x59e4, 0x18},
580 {0x59e5, 0x3f},
581 {0x59e6, 0x06},
582 {0x59e7, 0x02},
583 {0x59e8, 0x38},
584 {0x59e9, 0x10},
585 {0x59ea, 0x0c},
586 {0x59eb, 0x10},
587 {0x59ec, 0x04},
588 {0x59ed, 0x02},
589 {0x59ee, 0xa0},
590 {0x59ef, 0x08},
591 {0x59f4, 0x18},
592 {0x59f5, 0x10},
593 {0x59f6, 0x0c},
594 {0x59f7, 0x10},
595 {0x59f8, 0x06},
596 {0x59f9, 0x02},
597 {0x59fa, 0x18},
598 {0x59fb, 0x10},
599 {0x59fc, 0x0c},
600 {0x59fd, 0x10},
601 {0x59fe, 0x04},
602 {0x59ff, 0x02},
603 {0x36e9, 0x20},
604 {0x36f9, 0x24},
605 {REG_NULL, 0x00},
606 };
607
608 static const struct sc200ai_mode supported_modes[] = {
609 {
610 .width = 1920,
611 .height = 1080,
612 .max_fps = {
613 .numerator = 10000,
614 .denominator = 300000,
615 },
616 .exp_def = 0x0080,
617 .hts_def = 0x44C * 2,
618 .vts_def = 0x0465,
619 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
620 .reg_list = sc200ai_linear_10_1920x1080_30fps_regs,
621 .hdr_mode = NO_HDR,
622 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
623 }, {
624 .width = 1920,
625 .height = 1080,
626 .max_fps = {
627 .numerator = 10000,
628 .denominator = 600000,
629 },
630 .exp_def = 0x0080,
631 .hts_def = 0x44C * 2,
632 .vts_def = 0x0465,
633 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
634 .reg_list = sc200ai_linear_10_1920x1080_60fps_regs,
635 .hdr_mode = NO_HDR,
636 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
637 }, {
638 .width = 1920,
639 .height = 1080,
640 .max_fps = {
641 .numerator = 10000,
642 .denominator = 300000,
643 },
644 .exp_def = 0x0080,
645 .hts_def = 0x44C * 2,
646 .vts_def = 0x08CC,
647 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
648 .reg_list = sc200ai_hdr_10_1920x1080_regs,
649 .hdr_mode = HDR_X2,
650 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
651 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
652 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
653 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
654 },
655 };
656
657 static const s64 link_freq_menu_items[] = {
658 SC200AI_LINK_FREQ_371
659 };
660
661 static const char * const sc200ai_test_pattern_menu[] = {
662 "Disabled",
663 "Vertical Color Bar Type 1",
664 "Vertical Color Bar Type 2",
665 "Vertical Color Bar Type 3",
666 "Vertical Color Bar Type 4"
667 };
668
669 /* Write registers up to 4 at a time */
sc200ai_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)670 static int sc200ai_write_reg(struct i2c_client *client, u16 reg,
671 u32 len, u32 val)
672 {
673 u32 buf_i, val_i;
674 u8 buf[6];
675 u8 *val_p;
676 __be32 val_be;
677
678 if (len > 4)
679 return -EINVAL;
680
681 buf[0] = reg >> 8;
682 buf[1] = reg & 0xff;
683
684 val_be = cpu_to_be32(val);
685 val_p = (u8 *)&val_be;
686 buf_i = 2;
687 val_i = 4 - len;
688
689 while (val_i < 4)
690 buf[buf_i++] = val_p[val_i++];
691
692 if (i2c_master_send(client, buf, len + 2) != len + 2)
693 return -EIO;
694
695 return 0;
696 }
697
sc200ai_write_array(struct i2c_client * client,const struct regval * regs)698 static int sc200ai_write_array(struct i2c_client *client,
699 const struct regval *regs)
700 {
701 u32 i;
702 int ret = 0;
703
704 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
705 ret = sc200ai_write_reg(client, regs[i].addr,
706 SC200AI_REG_VALUE_08BIT, regs[i].val);
707
708 return ret;
709 }
710
711 /* Read registers up to 4 at a time */
sc200ai_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)712 static int sc200ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
713 u32 *val)
714 {
715 struct i2c_msg msgs[2];
716 u8 *data_be_p;
717 __be32 data_be = 0;
718 __be16 reg_addr_be = cpu_to_be16(reg);
719 int ret;
720
721 if (len > 4 || !len)
722 return -EINVAL;
723
724 data_be_p = (u8 *)&data_be;
725 /* Write register address */
726 msgs[0].addr = client->addr;
727 msgs[0].flags = 0;
728 msgs[0].len = 2;
729 msgs[0].buf = (u8 *)®_addr_be;
730
731 /* Read data from register */
732 msgs[1].addr = client->addr;
733 msgs[1].flags = I2C_M_RD;
734 msgs[1].len = len;
735 msgs[1].buf = &data_be_p[4 - len];
736
737 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
738 if (ret != ARRAY_SIZE(msgs))
739 return -EIO;
740
741 *val = be32_to_cpu(data_be);
742
743 return 0;
744 }
745
746 /* mode: 0 = lgain 1 = sgain */
sc200ai_set_gain_reg(struct sc200ai * sc200ai,u32 gain,int mode)747 static int sc200ai_set_gain_reg(struct sc200ai *sc200ai, u32 gain, int mode)
748 {
749 u8 Coarse_gain = 1, DIG_gain = 1;
750 u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1;
751 u8 Coarse_gain_reg = 0, DIG_gain_reg = 0;
752 u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80;
753 int ret = 0;
754
755 gain = gain * 16;
756 if (gain <= 1024)
757 gain = 1024;
758 else if (gain > SC200AI_GAIN_MAX * 16)
759 gain = SC200AI_GAIN_MAX * 16;
760
761 if (gain < 2 * 1024) { // start again
762 Dcg_gainx100 = 100;
763 Coarse_gain = 1;
764 DIG_gain = 1;
765 Coarse_gain_reg = 0x03;
766 DIG_gain_reg = 0x0;
767 DIG_Fine_gain_reg = 0x80;
768 } else if (gain <= 3456) {
769 Dcg_gainx100 = 100;
770 Coarse_gain = 2;
771 DIG_gain = 1;
772 Coarse_gain_reg = 0x07;
773 DIG_gain_reg = 0x0;
774 DIG_Fine_gain_reg = 0x80;
775 } else if (gain <= 6908) {
776 Dcg_gainx100 = 340;
777 Coarse_gain = 1;
778 DIG_gain = 1;
779 Coarse_gain_reg = 0x23;
780 DIG_gain_reg = 0x0;
781 DIG_Fine_gain_reg = 0x80;
782 } else if (gain <= 13817) {
783 Dcg_gainx100 = 340;
784 Coarse_gain = 2;
785 DIG_gain = 1;
786 Coarse_gain_reg = 0x27;
787 DIG_gain_reg = 0x0;
788 DIG_Fine_gain_reg = 0x80;
789 } else if (gain <= 27635) {
790 Dcg_gainx100 = 340;
791 Coarse_gain = 4;
792 DIG_gain = 1;
793 Coarse_gain_reg = 0x2f;
794 DIG_gain_reg = 0x0;
795 DIG_Fine_gain_reg = 0x80;
796 } else if (gain <= 55270) { // end again
797 Dcg_gainx100 = 340;
798 Coarse_gain = 8;
799 DIG_gain = 1;
800 Coarse_gain_reg = 0x3f;
801 DIG_gain_reg = 0x0;
802 DIG_Fine_gain_reg = 0x80;
803 } else if (gain < 55270 * 2) { // start dgain
804 Dcg_gainx100 = 340;
805 Coarse_gain = 8;
806 DIG_gain = 1;
807 ANA_Fine_gainx64 = 127;
808 Coarse_gain_reg = 0x3f;
809 DIG_gain_reg = 0x0;
810 ANA_Fine_gain_reg = 0x7f;
811 } else if (gain < 55270 * 4) {
812 Dcg_gainx100 = 340;
813 Coarse_gain = 8;
814 DIG_gain = 2;
815 ANA_Fine_gainx64 = 127;
816 Coarse_gain_reg = 0x3f;
817 DIG_gain_reg = 0x1;
818 ANA_Fine_gain_reg = 0x7f;
819 } else if (gain < 55270 * 8) {
820 Dcg_gainx100 = 340;
821 Coarse_gain = 8;
822 DIG_gain = 4;
823 ANA_Fine_gainx64 = 127;
824 Coarse_gain_reg = 0x3f;
825 DIG_gain_reg = 0x3;
826 ANA_Fine_gain_reg = 0x7f;
827 } else if (gain < 55270 * 16) {
828 Dcg_gainx100 = 340;
829 Coarse_gain = 8;
830 DIG_gain = 8;
831 ANA_Fine_gainx64 = 127;
832 Coarse_gain_reg = 0x3f;
833 DIG_gain_reg = 0x7;
834 ANA_Fine_gain_reg = 0x7f;
835 } else if (gain <= 1754822) {
836 Dcg_gainx100 = 340;
837 Coarse_gain = 8;
838 DIG_gain = 16;
839 ANA_Fine_gainx64 = 127;
840 Coarse_gain_reg = 0x3f;
841 DIG_gain_reg = 0xF;
842 ANA_Fine_gain_reg = 0x7f;
843 }
844
845 if (gain < 3456)
846 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
847 else if (gain == 3456)
848 ANA_Fine_gain_reg = 0x6C;
849 else if (gain < 55270)
850 ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
851 else
852 DIG_Fine_gain_reg = abs(800 * gain / (Dcg_gainx100 * Coarse_gain *
853 DIG_gain) / ANA_Fine_gainx64);
854
855 if (mode == SC200AI_LGAIN) {
856 ret = sc200ai_write_reg(sc200ai->client,
857 SC200AI_REG_DIG_GAIN,
858 SC200AI_REG_VALUE_08BIT,
859 DIG_gain_reg & 0xF);
860 ret |= sc200ai_write_reg(sc200ai->client,
861 SC200AI_REG_DIG_FINE_GAIN,
862 SC200AI_REG_VALUE_08BIT,
863 DIG_Fine_gain_reg);
864 ret |= sc200ai_write_reg(sc200ai->client,
865 SC200AI_REG_ANA_GAIN,
866 SC200AI_REG_VALUE_08BIT,
867 Coarse_gain_reg);
868 ret |= sc200ai_write_reg(sc200ai->client,
869 SC200AI_REG_ANA_FINE_GAIN,
870 SC200AI_REG_VALUE_08BIT,
871 ANA_Fine_gain_reg);
872 } else {
873 ret = sc200ai_write_reg(sc200ai->client,
874 SC200AI_REG_SDIG_GAIN,
875 SC200AI_REG_VALUE_08BIT,
876 DIG_gain_reg & 0xF);
877 ret |= sc200ai_write_reg(sc200ai->client,
878 SC200AI_REG_SDIG_FINE_GAIN,
879 SC200AI_REG_VALUE_08BIT,
880 DIG_Fine_gain_reg);
881 ret |= sc200ai_write_reg(sc200ai->client,
882 SC200AI_REG_SANA_GAIN,
883 SC200AI_REG_VALUE_08BIT,
884 Coarse_gain_reg);
885 ret |= sc200ai_write_reg(sc200ai->client,
886 SC200AI_REG_SANA_FINE_GAIN,
887 SC200AI_REG_VALUE_08BIT,
888 ANA_Fine_gain_reg);
889 }
890
891 if (gain <= 20 * 1024)
892 ret |= sc200ai_write_reg(sc200ai->client,
893 0x5799,
894 SC200AI_REG_VALUE_08BIT,
895 0x0);
896 else if (gain >= 30 * 1024)
897 ret |= sc200ai_write_reg(sc200ai->client,
898 0x5799,
899 SC200AI_REG_VALUE_08BIT,
900 0x07);
901
902 return ret;
903 }
904
sc200ai_set_hdrae(struct sc200ai * sc200ai,struct preisp_hdrae_exp_s * ae)905 static int sc200ai_set_hdrae(struct sc200ai *sc200ai,
906 struct preisp_hdrae_exp_s *ae)
907 {
908 int ret = 0;
909 u32 l_exp_time, m_exp_time, s_exp_time;
910 u32 l_a_gain, m_a_gain, s_a_gain;
911
912 if (!sc200ai->has_init_exp && !sc200ai->streaming) {
913 sc200ai->init_hdrae_exp = *ae;
914 sc200ai->has_init_exp = true;
915 dev_dbg(&sc200ai->client->dev, "sc200ai don't stream, record exp for hdr!\n");
916 return ret;
917 }
918 l_exp_time = ae->long_exp_reg;
919 m_exp_time = ae->middle_exp_reg;
920 s_exp_time = ae->short_exp_reg;
921 l_a_gain = ae->long_gain_reg;
922 m_a_gain = ae->middle_gain_reg;
923 s_a_gain = ae->short_gain_reg;
924
925 dev_dbg(&sc200ai->client->dev,
926 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
927 l_exp_time, m_exp_time, s_exp_time,
928 l_a_gain, m_a_gain, s_a_gain);
929
930 if (sc200ai->cur_mode->hdr_mode == HDR_X2) {
931 //2 stagger
932 l_a_gain = m_a_gain;
933 l_exp_time = m_exp_time;
934 }
935
936 //set exposure
937 l_exp_time = l_exp_time * 2;
938 s_exp_time = s_exp_time * 2;
939 if (l_exp_time > 4362) //(2250 - 64 - 5) * 2
940 l_exp_time = 4362;
941 if (s_exp_time > 404) //(64 - 5) * 2
942 s_exp_time = 404;
943
944 ret = sc200ai_write_reg(sc200ai->client,
945 SC200AI_REG_EXPOSURE_H,
946 SC200AI_REG_VALUE_08BIT,
947 SC200AI_FETCH_EXP_H(l_exp_time));
948 ret |= sc200ai_write_reg(sc200ai->client,
949 SC200AI_REG_EXPOSURE_M,
950 SC200AI_REG_VALUE_08BIT,
951 SC200AI_FETCH_EXP_M(l_exp_time));
952 ret |= sc200ai_write_reg(sc200ai->client,
953 SC200AI_REG_EXPOSURE_L,
954 SC200AI_REG_VALUE_08BIT,
955 SC200AI_FETCH_EXP_L(l_exp_time));
956 ret |= sc200ai_write_reg(sc200ai->client,
957 SC200AI_REG_SEXPOSURE_M,
958 SC200AI_REG_VALUE_08BIT,
959 SC200AI_FETCH_EXP_M(s_exp_time));
960 ret |= sc200ai_write_reg(sc200ai->client,
961 SC200AI_REG_SEXPOSURE_L,
962 SC200AI_REG_VALUE_08BIT,
963 SC200AI_FETCH_EXP_L(s_exp_time));
964
965 ret |= sc200ai_set_gain_reg(sc200ai, l_a_gain, SC200AI_LGAIN);
966 ret |= sc200ai_set_gain_reg(sc200ai, s_a_gain, SC200AI_SGAIN);
967 return ret;
968 }
969
sc200ai_get_reso_dist(const struct sc200ai_mode * mode,struct v4l2_mbus_framefmt * framefmt)970 static int sc200ai_get_reso_dist(const struct sc200ai_mode *mode,
971 struct v4l2_mbus_framefmt *framefmt)
972 {
973 return abs(mode->width - framefmt->width) +
974 abs(mode->height - framefmt->height);
975 }
976
977 static const struct sc200ai_mode *
sc200ai_find_best_fit(struct v4l2_subdev_format * fmt)978 sc200ai_find_best_fit(struct v4l2_subdev_format *fmt)
979 {
980 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
981 int dist;
982 int cur_best_fit = 0;
983 int cur_best_fit_dist = -1;
984 unsigned int i;
985
986 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
987 dist = sc200ai_get_reso_dist(&supported_modes[i], framefmt);
988 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
989 cur_best_fit_dist = dist;
990 cur_best_fit = i;
991 }
992 }
993
994 return &supported_modes[cur_best_fit];
995 }
996
sc200ai_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)997 static int sc200ai_set_fmt(struct v4l2_subdev *sd,
998 struct v4l2_subdev_pad_config *cfg,
999 struct v4l2_subdev_format *fmt)
1000 {
1001 struct sc200ai *sc200ai = to_sc200ai(sd);
1002 const struct sc200ai_mode *mode;
1003 s64 h_blank, vblank_def;
1004
1005 mutex_lock(&sc200ai->mutex);
1006
1007 mode = sc200ai_find_best_fit(fmt);
1008 fmt->format.code = mode->bus_fmt;
1009 fmt->format.width = mode->width;
1010 fmt->format.height = mode->height;
1011 fmt->format.field = V4L2_FIELD_NONE;
1012 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1013 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1014 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1015 #else
1016 mutex_unlock(&sc200ai->mutex);
1017 return -ENOTTY;
1018 #endif
1019 } else {
1020 sc200ai->cur_mode = mode;
1021 h_blank = mode->hts_def - mode->width;
1022 __v4l2_ctrl_modify_range(sc200ai->hblank, h_blank,
1023 h_blank, 1, h_blank);
1024 vblank_def = mode->vts_def - mode->height;
1025 __v4l2_ctrl_modify_range(sc200ai->vblank, vblank_def,
1026 SC200AI_VTS_MAX - mode->height,
1027 1, vblank_def);
1028 sc200ai->cur_fps = mode->max_fps;
1029 sc200ai->cur_vts = mode->vts_def;
1030 }
1031
1032 mutex_unlock(&sc200ai->mutex);
1033
1034 return 0;
1035 }
1036
sc200ai_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1037 static int sc200ai_get_fmt(struct v4l2_subdev *sd,
1038 struct v4l2_subdev_pad_config *cfg,
1039 struct v4l2_subdev_format *fmt)
1040 {
1041 struct sc200ai *sc200ai = to_sc200ai(sd);
1042 const struct sc200ai_mode *mode = sc200ai->cur_mode;
1043
1044 mutex_lock(&sc200ai->mutex);
1045 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1046 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1047 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1048 #else
1049 mutex_unlock(&sc200ai->mutex);
1050 return -ENOTTY;
1051 #endif
1052 } else {
1053 fmt->format.width = mode->width;
1054 fmt->format.height = mode->height;
1055 fmt->format.code = mode->bus_fmt;
1056 fmt->format.field = V4L2_FIELD_NONE;
1057 /* format info: width/height/data type/virctual channel */
1058 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1059 fmt->reserved[0] = mode->vc[fmt->pad];
1060 else
1061 fmt->reserved[0] = mode->vc[PAD0];
1062 }
1063 mutex_unlock(&sc200ai->mutex);
1064
1065 return 0;
1066 }
1067
sc200ai_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1068 static int sc200ai_enum_mbus_code(struct v4l2_subdev *sd,
1069 struct v4l2_subdev_pad_config *cfg,
1070 struct v4l2_subdev_mbus_code_enum *code)
1071 {
1072 struct sc200ai *sc200ai = to_sc200ai(sd);
1073
1074 if (code->index != 0)
1075 return -EINVAL;
1076 code->code = sc200ai->cur_mode->bus_fmt;
1077
1078 return 0;
1079 }
1080
sc200ai_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1081 static int sc200ai_enum_frame_sizes(struct v4l2_subdev *sd,
1082 struct v4l2_subdev_pad_config *cfg,
1083 struct v4l2_subdev_frame_size_enum *fse)
1084 {
1085 if (fse->index >= ARRAY_SIZE(supported_modes))
1086 return -EINVAL;
1087
1088 if (fse->code != supported_modes[0].bus_fmt)
1089 return -EINVAL;
1090
1091 fse->min_width = supported_modes[fse->index].width;
1092 fse->max_width = supported_modes[fse->index].width;
1093 fse->max_height = supported_modes[fse->index].height;
1094 fse->min_height = supported_modes[fse->index].height;
1095
1096 return 0;
1097 }
1098
sc200ai_enable_test_pattern(struct sc200ai * sc200ai,u32 pattern)1099 static int sc200ai_enable_test_pattern(struct sc200ai *sc200ai, u32 pattern)
1100 {
1101 u32 val = 0;
1102 int ret = 0;
1103
1104 ret = sc200ai_read_reg(sc200ai->client, SC200AI_REG_TEST_PATTERN,
1105 SC200AI_REG_VALUE_08BIT, &val);
1106 if (pattern)
1107 val |= SC200AI_TEST_PATTERN_BIT_MASK;
1108 else
1109 val &= ~SC200AI_TEST_PATTERN_BIT_MASK;
1110
1111 ret |= sc200ai_write_reg(sc200ai->client, SC200AI_REG_TEST_PATTERN,
1112 SC200AI_REG_VALUE_08BIT, val);
1113 return ret;
1114 }
1115
sc200ai_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1116 static int sc200ai_g_frame_interval(struct v4l2_subdev *sd,
1117 struct v4l2_subdev_frame_interval *fi)
1118 {
1119 struct sc200ai *sc200ai = to_sc200ai(sd);
1120 const struct sc200ai_mode *mode = sc200ai->cur_mode;
1121
1122 if (sc200ai->streaming)
1123 fi->interval = sc200ai->cur_fps;
1124 else
1125 fi->interval = mode->max_fps;
1126
1127 return 0;
1128 }
1129
sc200ai_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1130 static int sc200ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1131 struct v4l2_mbus_config *config)
1132 {
1133 struct sc200ai *sc200ai = to_sc200ai(sd);
1134 const struct sc200ai_mode *mode = sc200ai->cur_mode;
1135 u32 val = 1 << (SC200AI_LANES - 1) |
1136 V4L2_MBUS_CSI2_CHANNEL_0 |
1137 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1138
1139 if (mode->hdr_mode != NO_HDR)
1140 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1141 if (mode->hdr_mode == HDR_X3)
1142 val |= V4L2_MBUS_CSI2_CHANNEL_2;
1143
1144 config->type = V4L2_MBUS_CSI2_DPHY;
1145 config->flags = val;
1146
1147 return 0;
1148 }
1149
sc200ai_get_module_inf(struct sc200ai * sc200ai,struct rkmodule_inf * inf)1150 static void sc200ai_get_module_inf(struct sc200ai *sc200ai,
1151 struct rkmodule_inf *inf)
1152 {
1153 memset(inf, 0, sizeof(*inf));
1154 strlcpy(inf->base.sensor, SC200AI_NAME, sizeof(inf->base.sensor));
1155 strlcpy(inf->base.module, sc200ai->module_name,
1156 sizeof(inf->base.module));
1157 strlcpy(inf->base.lens, sc200ai->len_name, sizeof(inf->base.lens));
1158 }
1159
sc200ai_get_channel_info(struct sc200ai * sc200ai,struct rkmodule_channel_info * ch_info)1160 static int sc200ai_get_channel_info(struct sc200ai *sc200ai, struct rkmodule_channel_info *ch_info)
1161 {
1162 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1163 return -EINVAL;
1164 ch_info->vc = sc200ai->cur_mode->vc[ch_info->index];
1165 ch_info->width = sc200ai->cur_mode->width;
1166 ch_info->height = sc200ai->cur_mode->height;
1167 ch_info->bus_fmt = sc200ai->cur_mode->bus_fmt;
1168 return 0;
1169 }
1170
sc200ai_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1171 static long sc200ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1172 {
1173 struct sc200ai *sc200ai = to_sc200ai(sd);
1174 struct rkmodule_hdr_cfg *hdr;
1175 struct rkmodule_channel_info *ch_info;
1176 u32 i, h, w;
1177 long ret = 0;
1178 u32 stream = 0;
1179
1180 switch (cmd) {
1181 case RKMODULE_GET_MODULE_INFO:
1182 sc200ai_get_module_inf(sc200ai, (struct rkmodule_inf *)arg);
1183 break;
1184 case RKMODULE_GET_HDR_CFG:
1185 hdr = (struct rkmodule_hdr_cfg *)arg;
1186 hdr->esp.mode = HDR_NORMAL_VC;
1187 hdr->hdr_mode = sc200ai->cur_mode->hdr_mode;
1188 break;
1189 case RKMODULE_SET_HDR_CFG:
1190 hdr = (struct rkmodule_hdr_cfg *)arg;
1191 w = sc200ai->cur_mode->width;
1192 h = sc200ai->cur_mode->height;
1193 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1194 if (w == supported_modes[i].width &&
1195 h == supported_modes[i].height &&
1196 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1197 sc200ai->cur_mode = &supported_modes[i];
1198 break;
1199 }
1200 }
1201 if (i == ARRAY_SIZE(supported_modes)) {
1202 dev_err(&sc200ai->client->dev,
1203 "not find hdr mode:%d %dx%d config\n",
1204 hdr->hdr_mode, w, h);
1205 ret = -EINVAL;
1206 } else {
1207 w = sc200ai->cur_mode->hts_def - sc200ai->cur_mode->width;
1208 h = sc200ai->cur_mode->vts_def - sc200ai->cur_mode->height;
1209 __v4l2_ctrl_modify_range(sc200ai->hblank, w, w, 1, w);
1210 __v4l2_ctrl_modify_range(sc200ai->vblank, h,
1211 SC200AI_VTS_MAX - sc200ai->cur_mode->height, 1, h);
1212 sc200ai->cur_fps = sc200ai->cur_mode->max_fps;
1213 sc200ai->cur_vts = sc200ai->cur_mode->vts_def;
1214 }
1215 break;
1216 case PREISP_CMD_SET_HDRAE_EXP:
1217 sc200ai_set_hdrae(sc200ai, arg);
1218 break;
1219 case RKMODULE_SET_QUICK_STREAM:
1220
1221 stream = *((u32 *)arg);
1222
1223 if (stream)
1224 ret = sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
1225 SC200AI_REG_VALUE_08BIT, SC200AI_MODE_STREAMING);
1226 else
1227 ret = sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
1228 SC200AI_REG_VALUE_08BIT, SC200AI_MODE_SW_STANDBY);
1229 break;
1230 case RKMODULE_GET_CHANNEL_INFO:
1231 ch_info = (struct rkmodule_channel_info *)arg;
1232 ret = sc200ai_get_channel_info(sc200ai, ch_info);
1233 break;
1234 default:
1235 ret = -ENOIOCTLCMD;
1236 break;
1237 }
1238
1239 return ret;
1240 }
1241
1242 #ifdef CONFIG_COMPAT
sc200ai_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1243 static long sc200ai_compat_ioctl32(struct v4l2_subdev *sd,
1244 unsigned int cmd, unsigned long arg)
1245 {
1246 void __user *up = compat_ptr(arg);
1247 struct rkmodule_inf *inf;
1248 struct rkmodule_awb_cfg *cfg;
1249 struct rkmodule_hdr_cfg *hdr;
1250 struct preisp_hdrae_exp_s *hdrae;
1251 struct rkmodule_channel_info *ch_info;
1252 long ret;
1253 u32 stream = 0;
1254
1255 switch (cmd) {
1256 case RKMODULE_GET_MODULE_INFO:
1257 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1258 if (!inf) {
1259 ret = -ENOMEM;
1260 return ret;
1261 }
1262
1263 ret = sc200ai_ioctl(sd, cmd, inf);
1264 if (!ret) {
1265 ret = copy_to_user(up, inf, sizeof(*inf));
1266 if (ret)
1267 ret = -EFAULT;
1268 }
1269 kfree(inf);
1270 break;
1271 case RKMODULE_AWB_CFG:
1272 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1273 if (!cfg) {
1274 ret = -ENOMEM;
1275 return ret;
1276 }
1277
1278 ret = copy_from_user(cfg, up, sizeof(*cfg));
1279 if (!ret)
1280 ret = sc200ai_ioctl(sd, cmd, cfg);
1281 else
1282 ret = -EFAULT;
1283 kfree(cfg);
1284 break;
1285 case RKMODULE_GET_HDR_CFG:
1286 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1287 if (!hdr) {
1288 ret = -ENOMEM;
1289 return ret;
1290 }
1291
1292 ret = sc200ai_ioctl(sd, cmd, hdr);
1293 if (!ret) {
1294 ret = copy_to_user(up, hdr, sizeof(*hdr));
1295 if (ret)
1296 ret = -EFAULT;
1297 }
1298 kfree(hdr);
1299 break;
1300 case RKMODULE_SET_HDR_CFG:
1301 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1302 if (!hdr) {
1303 ret = -ENOMEM;
1304 return ret;
1305 }
1306
1307 ret = copy_from_user(hdr, up, sizeof(*hdr));
1308 if (!ret)
1309 ret = sc200ai_ioctl(sd, cmd, hdr);
1310 else
1311 ret = -EFAULT;
1312 kfree(hdr);
1313 break;
1314 case PREISP_CMD_SET_HDRAE_EXP:
1315 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1316 if (!hdrae) {
1317 ret = -ENOMEM;
1318 return ret;
1319 }
1320
1321 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1322 if (!ret)
1323 ret = sc200ai_ioctl(sd, cmd, hdrae);
1324 else
1325 ret = -EFAULT;
1326 kfree(hdrae);
1327 break;
1328 case RKMODULE_SET_QUICK_STREAM:
1329 ret = copy_from_user(&stream, up, sizeof(u32));
1330 if (!ret)
1331 ret = sc200ai_ioctl(sd, cmd, &stream);
1332 else
1333 ret = -EFAULT;
1334 break;
1335 case RKMODULE_GET_CHANNEL_INFO:
1336 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1337 if (!ch_info) {
1338 ret = -ENOMEM;
1339 return ret;
1340 }
1341
1342 ret = sc200ai_ioctl(sd, cmd, ch_info);
1343 if (!ret) {
1344 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1345 if (ret)
1346 ret = -EFAULT;
1347 }
1348 kfree(ch_info);
1349 break;
1350 default:
1351 ret = -ENOIOCTLCMD;
1352 break;
1353 }
1354
1355 return ret;
1356 }
1357 #endif
1358
__sc200ai_start_stream(struct sc200ai * sc200ai)1359 static int __sc200ai_start_stream(struct sc200ai *sc200ai)
1360 {
1361 int ret;
1362
1363 dev_info(&sc200ai->client->dev,
1364 "%dx%d@%d, mode %d, vts 0x%x\n",
1365 sc200ai->cur_mode->width,
1366 sc200ai->cur_mode->height,
1367 sc200ai->cur_fps.denominator / sc200ai->cur_fps.numerator,
1368 sc200ai->cur_mode->hdr_mode,
1369 sc200ai->cur_vts);
1370 if (!sc200ai->is_thunderboot) {
1371 ret = sc200ai_write_array(sc200ai->client, sc200ai->cur_mode->reg_list);
1372 if (ret)
1373 return ret;
1374
1375 /* In case these controls are set before streaming */
1376 ret = __v4l2_ctrl_handler_setup(&sc200ai->ctrl_handler);
1377 if (ret)
1378 return ret;
1379 if (sc200ai->has_init_exp && sc200ai->cur_mode->hdr_mode != NO_HDR) {
1380 ret = sc200ai_ioctl(&sc200ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
1381 &sc200ai->init_hdrae_exp);
1382 if (ret) {
1383 dev_err(&sc200ai->client->dev,
1384 "init exp fail in hdr mode\n");
1385 return ret;
1386 }
1387 }
1388 }
1389
1390 return sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
1391 SC200AI_REG_VALUE_08BIT, SC200AI_MODE_STREAMING);
1392 }
1393
__sc200ai_stop_stream(struct sc200ai * sc200ai)1394 static int __sc200ai_stop_stream(struct sc200ai *sc200ai)
1395 {
1396 sc200ai->has_init_exp = false;
1397 if (sc200ai->is_thunderboot) {
1398 sc200ai->is_first_streamoff = true;
1399 pm_runtime_put(&sc200ai->client->dev);
1400 }
1401 return sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
1402 SC200AI_REG_VALUE_08BIT, SC200AI_MODE_SW_STANDBY);
1403 }
1404
1405 static int __sc200ai_power_on(struct sc200ai *sc200ai);
sc200ai_s_stream(struct v4l2_subdev * sd,int on)1406 static int sc200ai_s_stream(struct v4l2_subdev *sd, int on)
1407 {
1408 struct sc200ai *sc200ai = to_sc200ai(sd);
1409 struct i2c_client *client = sc200ai->client;
1410 int ret = 0;
1411
1412 mutex_lock(&sc200ai->mutex);
1413 on = !!on;
1414 if (on == sc200ai->streaming)
1415 goto unlock_and_return;
1416
1417 if (on) {
1418 if (sc200ai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1419 sc200ai->is_thunderboot = false;
1420 __sc200ai_power_on(sc200ai);
1421 }
1422 ret = pm_runtime_get_sync(&client->dev);
1423 if (ret < 0) {
1424 pm_runtime_put_noidle(&client->dev);
1425 goto unlock_and_return;
1426 }
1427
1428 ret = __sc200ai_start_stream(sc200ai);
1429 if (ret) {
1430 v4l2_err(sd, "start stream failed while write regs\n");
1431 pm_runtime_put(&client->dev);
1432 goto unlock_and_return;
1433 }
1434 } else {
1435 __sc200ai_stop_stream(sc200ai);
1436 pm_runtime_put(&client->dev);
1437 }
1438
1439 sc200ai->streaming = on;
1440
1441 unlock_and_return:
1442 mutex_unlock(&sc200ai->mutex);
1443
1444 return ret;
1445 }
1446
sc200ai_s_power(struct v4l2_subdev * sd,int on)1447 static int sc200ai_s_power(struct v4l2_subdev *sd, int on)
1448 {
1449 struct sc200ai *sc200ai = to_sc200ai(sd);
1450 struct i2c_client *client = sc200ai->client;
1451 int ret = 0;
1452
1453 mutex_lock(&sc200ai->mutex);
1454
1455 /* If the power state is not modified - no work to do. */
1456 if (sc200ai->power_on == !!on)
1457 goto unlock_and_return;
1458
1459 if (on) {
1460 ret = pm_runtime_get_sync(&client->dev);
1461 if (ret < 0) {
1462 pm_runtime_put_noidle(&client->dev);
1463 goto unlock_and_return;
1464 }
1465
1466 if (!sc200ai->is_thunderboot) {
1467 ret = sc200ai_write_array(sc200ai->client, sc200ai_global_regs);
1468 if (ret) {
1469 v4l2_err(sd, "could not set init registers\n");
1470 pm_runtime_put_noidle(&client->dev);
1471 goto unlock_and_return;
1472 }
1473 }
1474
1475 sc200ai->power_on = true;
1476 } else {
1477 pm_runtime_put(&client->dev);
1478 sc200ai->power_on = false;
1479 }
1480
1481 unlock_and_return:
1482 mutex_unlock(&sc200ai->mutex);
1483
1484 return ret;
1485 }
1486
1487 /* Calculate the delay in us by clock rate and clock cycles */
sc200ai_cal_delay(u32 cycles)1488 static inline u32 sc200ai_cal_delay(u32 cycles)
1489 {
1490 return DIV_ROUND_UP(cycles, SC200AI_XVCLK_FREQ / 1000 / 1000);
1491 }
1492
__sc200ai_power_on(struct sc200ai * sc200ai)1493 static int __sc200ai_power_on(struct sc200ai *sc200ai)
1494 {
1495 int ret;
1496 u32 delay_us;
1497 struct device *dev = &sc200ai->client->dev;
1498
1499 if (!IS_ERR_OR_NULL(sc200ai->pins_default)) {
1500 ret = pinctrl_select_state(sc200ai->pinctrl,
1501 sc200ai->pins_default);
1502 if (ret < 0)
1503 dev_err(dev, "could not set pins\n");
1504 }
1505 ret = clk_set_rate(sc200ai->xvclk, SC200AI_XVCLK_FREQ);
1506 if (ret < 0)
1507 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1508 if (clk_get_rate(sc200ai->xvclk) != SC200AI_XVCLK_FREQ)
1509 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1510 ret = clk_prepare_enable(sc200ai->xvclk);
1511 if (ret < 0) {
1512 dev_err(dev, "Failed to enable xvclk\n");
1513 return ret;
1514 }
1515 if (sc200ai->is_thunderboot)
1516 return 0;
1517
1518 if (!IS_ERR(sc200ai->reset_gpio))
1519 gpiod_set_value_cansleep(sc200ai->reset_gpio, 0);
1520
1521 ret = regulator_bulk_enable(SC200AI_NUM_SUPPLIES, sc200ai->supplies);
1522 if (ret < 0) {
1523 dev_err(dev, "Failed to enable regulators\n");
1524 goto disable_clk;
1525 }
1526
1527 if (!IS_ERR(sc200ai->reset_gpio))
1528 gpiod_set_value_cansleep(sc200ai->reset_gpio, 1);
1529
1530 usleep_range(500, 1000);
1531 if (!IS_ERR(sc200ai->pwdn_gpio))
1532 gpiod_set_value_cansleep(sc200ai->pwdn_gpio, 1);
1533
1534 if (!IS_ERR(sc200ai->reset_gpio))
1535 usleep_range(6000, 8000);
1536 else
1537 usleep_range(12000, 16000);
1538
1539 /* 8192 cycles prior to first SCCB transaction */
1540 delay_us = sc200ai_cal_delay(8192);
1541 usleep_range(delay_us, delay_us * 2);
1542
1543 return 0;
1544
1545 disable_clk:
1546 clk_disable_unprepare(sc200ai->xvclk);
1547
1548 return ret;
1549 }
1550
__sc200ai_power_off(struct sc200ai * sc200ai)1551 static void __sc200ai_power_off(struct sc200ai *sc200ai)
1552 {
1553 int ret;
1554 struct device *dev = &sc200ai->client->dev;
1555
1556 clk_disable_unprepare(sc200ai->xvclk);
1557 if (sc200ai->is_thunderboot) {
1558 if (sc200ai->is_first_streamoff) {
1559 sc200ai->is_thunderboot = false;
1560 sc200ai->is_first_streamoff = false;
1561 } else {
1562 return;
1563 }
1564 }
1565 if (!IS_ERR(sc200ai->pwdn_gpio))
1566 gpiod_set_value_cansleep(sc200ai->pwdn_gpio, 0);
1567 clk_disable_unprepare(sc200ai->xvclk);
1568 if (!IS_ERR(sc200ai->reset_gpio))
1569 gpiod_set_value_cansleep(sc200ai->reset_gpio, 0);
1570 if (!IS_ERR_OR_NULL(sc200ai->pins_sleep)) {
1571 ret = pinctrl_select_state(sc200ai->pinctrl,
1572 sc200ai->pins_sleep);
1573 if (ret < 0)
1574 dev_dbg(dev, "could not set pins\n");
1575 }
1576 regulator_bulk_disable(SC200AI_NUM_SUPPLIES, sc200ai->supplies);
1577 }
1578
sc200ai_runtime_resume(struct device * dev)1579 static int sc200ai_runtime_resume(struct device *dev)
1580 {
1581 struct i2c_client *client = to_i2c_client(dev);
1582 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1583 struct sc200ai *sc200ai = to_sc200ai(sd);
1584
1585 return __sc200ai_power_on(sc200ai);
1586 }
1587
sc200ai_runtime_suspend(struct device * dev)1588 static int sc200ai_runtime_suspend(struct device *dev)
1589 {
1590 struct i2c_client *client = to_i2c_client(dev);
1591 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1592 struct sc200ai *sc200ai = to_sc200ai(sd);
1593
1594 __sc200ai_power_off(sc200ai);
1595
1596 return 0;
1597 }
1598
1599 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc200ai_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1600 static int sc200ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1601 {
1602 struct sc200ai *sc200ai = to_sc200ai(sd);
1603 struct v4l2_mbus_framefmt *try_fmt =
1604 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1605 const struct sc200ai_mode *def_mode = &supported_modes[0];
1606
1607 mutex_lock(&sc200ai->mutex);
1608 /* Initialize try_fmt */
1609 try_fmt->width = def_mode->width;
1610 try_fmt->height = def_mode->height;
1611 try_fmt->code = def_mode->bus_fmt;
1612 try_fmt->field = V4L2_FIELD_NONE;
1613
1614 mutex_unlock(&sc200ai->mutex);
1615 /* No crop or compose */
1616
1617 return 0;
1618 }
1619 #endif
1620
sc200ai_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1621 static int sc200ai_enum_frame_interval(struct v4l2_subdev *sd,
1622 struct v4l2_subdev_pad_config *cfg,
1623 struct v4l2_subdev_frame_interval_enum *fie)
1624 {
1625 if (fie->index >= ARRAY_SIZE(supported_modes))
1626 return -EINVAL;
1627
1628 fie->code = supported_modes[fie->index].bus_fmt;
1629 fie->width = supported_modes[fie->index].width;
1630 fie->height = supported_modes[fie->index].height;
1631 fie->interval = supported_modes[fie->index].max_fps;
1632 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1633 return 0;
1634 }
1635
1636 static const struct dev_pm_ops sc200ai_pm_ops = {
1637 SET_RUNTIME_PM_OPS(sc200ai_runtime_suspend,
1638 sc200ai_runtime_resume, NULL)
1639 };
1640
1641 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1642 static const struct v4l2_subdev_internal_ops sc200ai_internal_ops = {
1643 .open = sc200ai_open,
1644 };
1645 #endif
1646
1647 static const struct v4l2_subdev_core_ops sc200ai_core_ops = {
1648 .s_power = sc200ai_s_power,
1649 .ioctl = sc200ai_ioctl,
1650 #ifdef CONFIG_COMPAT
1651 .compat_ioctl32 = sc200ai_compat_ioctl32,
1652 #endif
1653 };
1654
1655 static const struct v4l2_subdev_video_ops sc200ai_video_ops = {
1656 .s_stream = sc200ai_s_stream,
1657 .g_frame_interval = sc200ai_g_frame_interval,
1658 };
1659
1660 static const struct v4l2_subdev_pad_ops sc200ai_pad_ops = {
1661 .enum_mbus_code = sc200ai_enum_mbus_code,
1662 .enum_frame_size = sc200ai_enum_frame_sizes,
1663 .enum_frame_interval = sc200ai_enum_frame_interval,
1664 .get_fmt = sc200ai_get_fmt,
1665 .set_fmt = sc200ai_set_fmt,
1666 .get_mbus_config = sc200ai_g_mbus_config,
1667 };
1668
1669 static const struct v4l2_subdev_ops sc200ai_subdev_ops = {
1670 .core = &sc200ai_core_ops,
1671 .video = &sc200ai_video_ops,
1672 .pad = &sc200ai_pad_ops,
1673 };
1674
sc200ai_modify_fps_info(struct sc200ai * sc200ai)1675 static void sc200ai_modify_fps_info(struct sc200ai *sc200ai)
1676 {
1677 const struct sc200ai_mode *mode = sc200ai->cur_mode;
1678
1679 sc200ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def/
1680 sc200ai->cur_vts;
1681 }
1682
sc200ai_set_ctrl(struct v4l2_ctrl * ctrl)1683 static int sc200ai_set_ctrl(struct v4l2_ctrl *ctrl)
1684 {
1685 struct sc200ai *sc200ai = container_of(ctrl->handler,
1686 struct sc200ai, ctrl_handler);
1687 struct i2c_client *client = sc200ai->client;
1688 s64 max;
1689 int ret = 0;
1690 u32 val = 0;
1691 s32 temp = 0;
1692
1693 /* Propagate change of current control to all related controls */
1694 switch (ctrl->id) {
1695 case V4L2_CID_VBLANK:
1696 /* Update max exposure while meeting expected vblanking */
1697 max = sc200ai->cur_mode->height + ctrl->val - 4;
1698 __v4l2_ctrl_modify_range(sc200ai->exposure,
1699 sc200ai->exposure->minimum, max,
1700 sc200ai->exposure->step,
1701 sc200ai->exposure->default_value);
1702 break;
1703 }
1704
1705 if (!pm_runtime_get_if_in_use(&client->dev))
1706 return 0;
1707
1708 switch (ctrl->id) {
1709 case V4L2_CID_EXPOSURE:
1710 dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
1711 if (sc200ai->cur_mode->hdr_mode == NO_HDR) {
1712 temp = ctrl->val * 2;
1713 /* 4 least significant bits of expsoure are fractional part */
1714 ret = sc200ai_write_reg(sc200ai->client,
1715 SC200AI_REG_EXPOSURE_H,
1716 SC200AI_REG_VALUE_08BIT,
1717 SC200AI_FETCH_EXP_H(temp));
1718 ret |= sc200ai_write_reg(sc200ai->client,
1719 SC200AI_REG_EXPOSURE_M,
1720 SC200AI_REG_VALUE_08BIT,
1721 SC200AI_FETCH_EXP_M(temp));
1722 ret |= sc200ai_write_reg(sc200ai->client,
1723 SC200AI_REG_EXPOSURE_L,
1724 SC200AI_REG_VALUE_08BIT,
1725 SC200AI_FETCH_EXP_L(temp));
1726 }
1727 break;
1728 case V4L2_CID_ANALOGUE_GAIN:
1729 dev_dbg(&client->dev, "set gain value 0x%x\n", ctrl->val);
1730 if (sc200ai->cur_mode->hdr_mode == NO_HDR)
1731 ret = sc200ai_set_gain_reg(sc200ai, ctrl->val, SC200AI_LGAIN);
1732 break;
1733 case V4L2_CID_VBLANK:
1734 dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val);
1735 ret = sc200ai_write_reg(sc200ai->client,
1736 SC200AI_REG_VTS_H,
1737 SC200AI_REG_VALUE_08BIT,
1738 (ctrl->val + sc200ai->cur_mode->height)
1739 >> 8);
1740 ret |= sc200ai_write_reg(sc200ai->client,
1741 SC200AI_REG_VTS_L,
1742 SC200AI_REG_VALUE_08BIT,
1743 (ctrl->val + sc200ai->cur_mode->height)
1744 & 0xff);
1745 if (!ret)
1746 sc200ai->cur_vts = ctrl->val + sc200ai->cur_mode->height;
1747 sc200ai_modify_fps_info(sc200ai);
1748 break;
1749 case V4L2_CID_TEST_PATTERN:
1750 ret = sc200ai_enable_test_pattern(sc200ai, ctrl->val);
1751 break;
1752 case V4L2_CID_HFLIP:
1753 ret = sc200ai_read_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
1754 SC200AI_REG_VALUE_08BIT, &val);
1755 ret |= sc200ai_write_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
1756 SC200AI_REG_VALUE_08BIT,
1757 SC200AI_FETCH_MIRROR(val, ctrl->val));
1758 break;
1759 case V4L2_CID_VFLIP:
1760 ret = sc200ai_read_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
1761 SC200AI_REG_VALUE_08BIT, &val);
1762 ret |= sc200ai_write_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
1763 SC200AI_REG_VALUE_08BIT,
1764 SC200AI_FETCH_FLIP(val, ctrl->val));
1765 break;
1766 default:
1767 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1768 __func__, ctrl->id, ctrl->val);
1769 break;
1770 }
1771
1772 pm_runtime_put(&client->dev);
1773
1774 return ret;
1775 }
1776
1777 static const struct v4l2_ctrl_ops sc200ai_ctrl_ops = {
1778 .s_ctrl = sc200ai_set_ctrl,
1779 };
1780
sc200ai_initialize_controls(struct sc200ai * sc200ai)1781 static int sc200ai_initialize_controls(struct sc200ai *sc200ai)
1782 {
1783 const struct sc200ai_mode *mode;
1784 struct v4l2_ctrl_handler *handler;
1785 struct v4l2_ctrl *ctrl;
1786 s64 exposure_max, vblank_def;
1787 u32 h_blank;
1788 int ret;
1789
1790 handler = &sc200ai->ctrl_handler;
1791 mode = sc200ai->cur_mode;
1792 ret = v4l2_ctrl_handler_init(handler, 9);
1793 if (ret)
1794 return ret;
1795 handler->lock = &sc200ai->mutex;
1796
1797 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1798 0, 0, link_freq_menu_items);
1799 if (ctrl)
1800 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1801
1802 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1803 0, PIXEL_RATE_WITH_371M_10BIT, 1, PIXEL_RATE_WITH_371M_10BIT);
1804
1805 h_blank = mode->hts_def - mode->width;
1806 sc200ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1807 h_blank, h_blank, 1, h_blank);
1808 if (sc200ai->hblank)
1809 sc200ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1810 sc200ai->cur_fps = mode->max_fps;
1811 vblank_def = mode->vts_def - mode->height;
1812 sc200ai->cur_vts = mode->vts_def;
1813 sc200ai->vblank = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
1814 V4L2_CID_VBLANK, vblank_def,
1815 SC200AI_VTS_MAX - mode->height,
1816 1, vblank_def);
1817 exposure_max = 2 * mode->vts_def - 8;
1818 sc200ai->exposure = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
1819 V4L2_CID_EXPOSURE, SC200AI_EXPOSURE_MIN,
1820 exposure_max, SC200AI_EXPOSURE_STEP,
1821 mode->exp_def);
1822 sc200ai->anal_gain = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
1823 V4L2_CID_ANALOGUE_GAIN, SC200AI_GAIN_MIN,
1824 SC200AI_GAIN_MAX, SC200AI_GAIN_STEP,
1825 SC200AI_GAIN_DEFAULT);
1826 sc200ai->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1827 &sc200ai_ctrl_ops,
1828 V4L2_CID_TEST_PATTERN,
1829 ARRAY_SIZE(sc200ai_test_pattern_menu) - 1,
1830 0, 0, sc200ai_test_pattern_menu);
1831 v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
1832 V4L2_CID_HFLIP, 0, 1, 1, 0);
1833
1834 v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
1835 V4L2_CID_VFLIP, 0, 1, 1, 0);
1836
1837 if (handler->error) {
1838 ret = handler->error;
1839 dev_err(&sc200ai->client->dev,
1840 "Failed to init controls(%d)\n", ret);
1841 goto err_free_handler;
1842 }
1843
1844 sc200ai->subdev.ctrl_handler = handler;
1845 sc200ai->has_init_exp = false;
1846
1847 return 0;
1848
1849 err_free_handler:
1850 v4l2_ctrl_handler_free(handler);
1851
1852 return ret;
1853 }
1854
sc200ai_check_sensor_id(struct sc200ai * sc200ai,struct i2c_client * client)1855 static int sc200ai_check_sensor_id(struct sc200ai *sc200ai,
1856 struct i2c_client *client)
1857 {
1858 struct device *dev = &sc200ai->client->dev;
1859 u32 id = 0;
1860 int ret;
1861
1862 if (sc200ai->is_thunderboot) {
1863 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1864 return 0;
1865 }
1866
1867 ret = sc200ai_read_reg(client, SC200AI_REG_CHIP_ID,
1868 SC200AI_REG_VALUE_16BIT, &id);
1869 if (id != CHIP_ID) {
1870 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1871 return -ENODEV;
1872 }
1873
1874 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1875
1876 return 0;
1877 }
1878
sc200ai_configure_regulators(struct sc200ai * sc200ai)1879 static int sc200ai_configure_regulators(struct sc200ai *sc200ai)
1880 {
1881 unsigned int i;
1882
1883 for (i = 0; i < SC200AI_NUM_SUPPLIES; i++)
1884 sc200ai->supplies[i].supply = sc200ai_supply_names[i];
1885
1886 return devm_regulator_bulk_get(&sc200ai->client->dev,
1887 SC200AI_NUM_SUPPLIES,
1888 sc200ai->supplies);
1889 }
1890
1891 #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
1892 static u32 rk_cam_hdr;
1893 static u32 rk_cam_w;
1894 static u32 rk_cam_h;
1895 static u32 rk_cam_fps;
1896
rk_cam_hdr_setup(char * str)1897 static int __init __maybe_unused rk_cam_hdr_setup(char *str)
1898 {
1899 int ret = 0;
1900 unsigned long val = 0;
1901
1902 ret = kstrtoul(str, 0, &val);
1903 if (!ret)
1904 rk_cam_hdr = (u32)val;
1905 else
1906 pr_err("get rk_cam_hdr fail\n");
1907 return 1;
1908 }
1909
rk_cam_w_setup(char * str)1910 static int __init __maybe_unused rk_cam_w_setup(char *str)
1911 {
1912 int ret = 0;
1913 unsigned long val = 0;
1914
1915 ret = kstrtoul(str, 0, &val);
1916 if (!ret)
1917 rk_cam_w = (u32)val;
1918 else
1919 pr_err("get rk_cam_w fail\n");
1920 return 1;
1921 }
1922
rk_cam_h_setup(char * str)1923 static int __init __maybe_unused rk_cam_h_setup(char *str)
1924 {
1925 int ret = 0;
1926 unsigned long val = 0;
1927
1928 ret = kstrtoul(str, 0, &val);
1929 if (!ret)
1930 rk_cam_h = (u32)val;
1931 else
1932 pr_err("get rk_cam_h fail\n");
1933 return 1;
1934 }
1935
rk_cam_fps_setup(char * str)1936 static int __init __maybe_unused rk_cam_fps_setup(char *str)
1937 {
1938 int ret = 0;
1939 unsigned long val = 0;
1940
1941 ret = kstrtoul(str, 0, &val);
1942 if (!ret)
1943 rk_cam_fps = (u32)val;
1944 else
1945 pr_err("get rk_cam_fps fail\n");
1946 return 1;
1947 }
1948
1949 __setup("rk_cam_hdr=", rk_cam_hdr_setup);
1950 __setup("rk_cam_w=", rk_cam_w_setup);
1951 __setup("rk_cam_h=", rk_cam_h_setup);
1952 __setup("rk_cam_fps=", rk_cam_fps_setup);
1953
find_terminal_resolution(struct sc200ai * sc200ai)1954 static void find_terminal_resolution(struct sc200ai *sc200ai)
1955 {
1956 int i = 0;
1957 const struct sc200ai_mode *mode = NULL;
1958 const struct sc200ai_mode *fit_mode = NULL;
1959 u32 cur_fps = 0;
1960 u32 dst_fps = 0;
1961 u32 tmp_fps = 0;
1962
1963 if (rk_cam_w == 0 || rk_cam_h == 0 ||
1964 rk_cam_fps == 0)
1965 goto err_find_res;
1966
1967 dst_fps = rk_cam_fps;
1968 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1969 mode = &supported_modes[i];
1970 cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
1971 if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
1972 mode->hdr_mode == rk_cam_hdr) {
1973 if (cur_fps == dst_fps) {
1974 sc200ai->cur_mode = mode;
1975 return;
1976 }
1977 if (cur_fps >= dst_fps) {
1978 if (fit_mode) {
1979 tmp_fps = fit_mode->max_fps.denominator / fit_mode->max_fps.numerator;
1980 if (tmp_fps - dst_fps > cur_fps - dst_fps)
1981 fit_mode = mode;
1982 } else {
1983 fit_mode = mode;
1984 }
1985 }
1986 }
1987 }
1988 if (fit_mode) {
1989 sc200ai->cur_mode = fit_mode;
1990 return;
1991 }
1992 err_find_res:
1993 dev_err(&sc200ai->client->dev, "not match %dx%d@%dfps mode %d\n!",
1994 rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
1995 sc200ai->cur_mode = &supported_modes[0];
1996 }
1997 #else
find_terminal_resolution(struct sc200ai * sc200ai)1998 static void find_terminal_resolution(struct sc200ai *sc200ai)
1999 {
2000 u32 hdr_mode = 0;
2001 struct device_node *node = sc200ai->client->dev.of_node;
2002 int i = 0;
2003
2004 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
2005 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
2006 if (hdr_mode == supported_modes[i].hdr_mode) {
2007 sc200ai->cur_mode = &supported_modes[i];
2008 break;
2009 }
2010 }
2011 if (i == ARRAY_SIZE(supported_modes))
2012 sc200ai->cur_mode = &supported_modes[0];
2013
2014 }
2015 #endif
2016
sc200ai_probe(struct i2c_client * client,const struct i2c_device_id * id)2017 static int sc200ai_probe(struct i2c_client *client,
2018 const struct i2c_device_id *id)
2019 {
2020 struct device *dev = &client->dev;
2021 struct device_node *node = dev->of_node;
2022 struct sc200ai *sc200ai;
2023 struct v4l2_subdev *sd;
2024 char facing[2];
2025 int ret;
2026
2027 dev_info(dev, "driver version: %02x.%02x.%02x",
2028 DRIVER_VERSION >> 16,
2029 (DRIVER_VERSION & 0xff00) >> 8,
2030 DRIVER_VERSION & 0x00ff);
2031
2032 sc200ai = devm_kzalloc(dev, sizeof(*sc200ai), GFP_KERNEL);
2033 if (!sc200ai)
2034 return -ENOMEM;
2035
2036 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2037 &sc200ai->module_index);
2038 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2039 &sc200ai->module_facing);
2040 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2041 &sc200ai->module_name);
2042 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2043 &sc200ai->len_name);
2044 if (ret) {
2045 dev_err(dev, "could not get module information!\n");
2046 return -EINVAL;
2047 }
2048
2049 sc200ai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
2050 sc200ai->client = client;
2051
2052 find_terminal_resolution(sc200ai);
2053
2054 sc200ai->xvclk = devm_clk_get(dev, "xvclk");
2055 if (IS_ERR(sc200ai->xvclk)) {
2056 dev_err(dev, "Failed to get xvclk\n");
2057 return -EINVAL;
2058 }
2059
2060 sc200ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
2061 if (IS_ERR(sc200ai->reset_gpio))
2062 dev_warn(dev, "Failed to get reset-gpios\n");
2063
2064 sc200ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
2065 if (IS_ERR(sc200ai->pwdn_gpio))
2066 dev_warn(dev, "Failed to get pwdn-gpios\n");
2067
2068 sc200ai->pinctrl = devm_pinctrl_get(dev);
2069 if (!IS_ERR(sc200ai->pinctrl)) {
2070 sc200ai->pins_default =
2071 pinctrl_lookup_state(sc200ai->pinctrl,
2072 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2073 if (IS_ERR(sc200ai->pins_default))
2074 dev_err(dev, "could not get default pinstate\n");
2075
2076 sc200ai->pins_sleep =
2077 pinctrl_lookup_state(sc200ai->pinctrl,
2078 OF_CAMERA_PINCTRL_STATE_SLEEP);
2079 if (IS_ERR(sc200ai->pins_sleep))
2080 dev_err(dev, "could not get sleep pinstate\n");
2081 } else {
2082 dev_err(dev, "no pinctrl\n");
2083 }
2084
2085 ret = sc200ai_configure_regulators(sc200ai);
2086 if (ret) {
2087 dev_err(dev, "Failed to get power regulators\n");
2088 return ret;
2089 }
2090
2091 mutex_init(&sc200ai->mutex);
2092
2093 sd = &sc200ai->subdev;
2094 v4l2_i2c_subdev_init(sd, client, &sc200ai_subdev_ops);
2095 ret = sc200ai_initialize_controls(sc200ai);
2096 if (ret)
2097 goto err_destroy_mutex;
2098
2099 ret = __sc200ai_power_on(sc200ai);
2100 if (ret)
2101 goto err_free_handler;
2102
2103 ret = sc200ai_check_sensor_id(sc200ai, client);
2104 if (ret)
2105 goto err_power_off;
2106
2107 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2108 sd->internal_ops = &sc200ai_internal_ops;
2109 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2110 V4L2_SUBDEV_FL_HAS_EVENTS;
2111 #endif
2112 #if defined(CONFIG_MEDIA_CONTROLLER)
2113 sc200ai->pad.flags = MEDIA_PAD_FL_SOURCE;
2114 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2115 ret = media_entity_pads_init(&sd->entity, 1, &sc200ai->pad);
2116 if (ret < 0)
2117 goto err_power_off;
2118 #endif
2119
2120 memset(facing, 0, sizeof(facing));
2121 if (strcmp(sc200ai->module_facing, "back") == 0)
2122 facing[0] = 'b';
2123 else
2124 facing[0] = 'f';
2125
2126 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2127 sc200ai->module_index, facing,
2128 SC200AI_NAME, dev_name(sd->dev));
2129 ret = v4l2_async_register_subdev_sensor_common(sd);
2130 if (ret) {
2131 dev_err(dev, "v4l2 async register subdev failed\n");
2132 goto err_clean_entity;
2133 }
2134
2135 pm_runtime_set_active(dev);
2136 pm_runtime_enable(dev);
2137 if (sc200ai->is_thunderboot)
2138 pm_runtime_get_sync(dev);
2139 else
2140 pm_runtime_idle(dev);
2141
2142 return 0;
2143
2144 err_clean_entity:
2145 #if defined(CONFIG_MEDIA_CONTROLLER)
2146 media_entity_cleanup(&sd->entity);
2147 #endif
2148 err_power_off:
2149 __sc200ai_power_off(sc200ai);
2150 err_free_handler:
2151 v4l2_ctrl_handler_free(&sc200ai->ctrl_handler);
2152 err_destroy_mutex:
2153 mutex_destroy(&sc200ai->mutex);
2154
2155 return ret;
2156 }
2157
sc200ai_remove(struct i2c_client * client)2158 static int sc200ai_remove(struct i2c_client *client)
2159 {
2160 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2161 struct sc200ai *sc200ai = to_sc200ai(sd);
2162
2163 v4l2_async_unregister_subdev(sd);
2164 #if defined(CONFIG_MEDIA_CONTROLLER)
2165 media_entity_cleanup(&sd->entity);
2166 #endif
2167 v4l2_ctrl_handler_free(&sc200ai->ctrl_handler);
2168 mutex_destroy(&sc200ai->mutex);
2169
2170 pm_runtime_disable(&client->dev);
2171 if (!pm_runtime_status_suspended(&client->dev))
2172 __sc200ai_power_off(sc200ai);
2173 pm_runtime_set_suspended(&client->dev);
2174
2175 return 0;
2176 }
2177
2178 #if IS_ENABLED(CONFIG_OF)
2179 static const struct of_device_id sc200ai_of_match[] = {
2180 { .compatible = "smartsens,sc200ai" },
2181 {},
2182 };
2183 MODULE_DEVICE_TABLE(of, sc200ai_of_match);
2184 #endif
2185
2186 static const struct i2c_device_id sc200ai_match_id[] = {
2187 { "smartsens,sc200ai", 0 },
2188 { },
2189 };
2190
2191 static struct i2c_driver sc200ai_i2c_driver = {
2192 .driver = {
2193 .name = SC200AI_NAME,
2194 .pm = &sc200ai_pm_ops,
2195 .of_match_table = of_match_ptr(sc200ai_of_match),
2196 },
2197 .probe = &sc200ai_probe,
2198 .remove = &sc200ai_remove,
2199 .id_table = sc200ai_match_id,
2200 };
2201
sensor_mod_init(void)2202 static int __init sensor_mod_init(void)
2203 {
2204 return i2c_add_driver(&sc200ai_i2c_driver);
2205 }
2206
sensor_mod_exit(void)2207 static void __exit sensor_mod_exit(void)
2208 {
2209 i2c_del_driver(&sc200ai_i2c_driver);
2210 }
2211
2212 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
2213 subsys_initcall(sensor_mod_init);
2214 #else
2215 device_initcall_sync(sensor_mod_init);
2216 #endif
2217 module_exit(sensor_mod_exit);
2218
2219 MODULE_DESCRIPTION("smartsens sc200ai sensor driver");
2220 MODULE_LICENSE("GPL");
2221