1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc132gs driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 * V0.1.0: MIPI is ok.
7 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
8 * V0.0X01.0X03 add enum_frame_interval function.
9 * V0.0X01.0X04 add quick stream on/off
10 * V0.0X01.0X05 add function g_mbus_config
11 * V0.0X01.0X06 add function reset gpio control
12 * V0.0X01.0X06 add 2-lane mode as default
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/version.h>
26 #include <linux/rk-camera-module.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-async.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-subdev.h>
31 #include <linux/pinctrl/consumer.h>
32
33 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define MIPI_FREQ_180M 180000000
39 #define MIPI_FREQ_360M 360000000
40
41 #define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10 * 2)
42 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 8 * 1)
43
44 #define SC132GS_XVCLK_FREQ 24000000
45
46 #define CHIP_ID 0x0132
47 #define SC132GS_REG_CHIP_ID 0x3107
48
49 #define SC132GS_REG_CTRL_MODE 0x0100
50 #define SC132GS_MODE_SW_STANDBY 0x0
51 #define SC132GS_MODE_STREAMING BIT(0)
52
53 #define SC132GS_REG_EXPOSURE 0x3e01
54 #define SC132GS_EXPOSURE_MIN 6
55 #define SC132GS_EXPOSURE_STEP 1
56 #define SC132GS_VTS_MAX 0xffff
57
58 #define SC132GS_REG_COARSE_AGAIN 0x3e08
59 #define SC132GS_REG_FINE_AGAIN 0x3e09
60 #define ANALOG_GAIN_MIN 0x20
61 #define ANALOG_GAIN_MAX 0x391
62 #define ANALOG_GAIN_STEP 1
63 #define ANALOG_GAIN_DEFAULT 0x20
64
65 #define SC132GS_REG_TEST_PATTERN 0x4501
66 #define SC132GS_TEST_PATTERN_ENABLE 0xcc
67 #define SC132GS_TEST_PATTERN_DISABLE 0xc4
68
69 #define SC132GS_REG_VTS 0x320e
70
71 #define REG_NULL 0xFFFF
72
73 #define SC132GS_REG_VALUE_08BIT 1
74 #define SC132GS_REG_VALUE_16BIT 2
75 #define SC132GS_REG_VALUE_24BIT 3
76
77 #define SC132GS_NAME "sc132gs"
78
79 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
80 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
81
82 static const char * const sc132gs_supply_names[] = {
83 "avdd", /* Analog power */
84 "dovdd", /* Digital I/O power */
85 "dvdd", /* Digital core power */
86 };
87
88 #define SC132GS_NUM_SUPPLIES ARRAY_SIZE(sc132gs_supply_names)
89
90 enum {
91 LINK_FREQ_180M_INDEX,
92 LINK_FREQ_360M_INDEX,
93 };
94
95 struct regval {
96 u16 addr;
97 u8 val;
98 };
99
100 struct sc132gs_mode {
101 u32 width;
102 u32 height;
103 struct v4l2_fract max_fps;
104 u32 hts_def;
105 u32 vts_def;
106 u32 exp_def;
107 u32 link_freq_index;
108 u64 pixel_rate;
109 const struct regval *reg_list;
110 u32 lanes;
111 u32 bus_fmt;
112 };
113
114 struct sc132gs {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *reset_gpio;
118 struct gpio_desc *pwdn_gpio;
119 struct regulator_bulk_data supplies[SC132GS_NUM_SUPPLIES];
120 struct pinctrl *pinctrl;
121 struct pinctrl_state *pins_default;
122 struct pinctrl_state *pins_sleep;
123 struct v4l2_subdev subdev;
124 struct media_pad pad;
125 struct v4l2_ctrl_handler ctrl_handler;
126 struct v4l2_ctrl *exposure;
127 struct v4l2_ctrl *anal_gain;
128 struct v4l2_ctrl *digi_gain;
129 struct v4l2_ctrl *hblank;
130 struct v4l2_ctrl *vblank;
131 struct v4l2_ctrl *test_pattern;
132 struct v4l2_ctrl *pixel_rate;
133 struct v4l2_ctrl *link_freq;
134 struct mutex mutex;
135 struct v4l2_fract cur_fps;
136 u32 cur_vts;
137 bool streaming;
138 bool power_on;
139 const struct sc132gs_mode *cur_mode;
140 u32 module_index;
141 const char *module_facing;
142 const char *module_name;
143 const char *len_name;
144 };
145
146 #define to_sc132gs(sd) container_of(sd, struct sc132gs, subdev)
147
148 /*
149 * Xclk 24Mhz
150 * Pclk 90Mhz
151 * linelength 1696(0x06a0)
152 * framelength 2122(0x084a)
153 * grabwindow_width 1080
154 * grabwindow_height 1280
155 * mipi 1 lane
156 * max_framerate 30fps
157 * mipi_datarate per lane 720Mbps
158 */
159 static const struct regval sc132gs_1lane_8bit_regs[] = {
160 {0x0103, 0x01},
161 {0x0100, 0x00},
162
163 //PLL bypass
164 {0x36e9, 0x80},
165 {0x36f9, 0x80},
166
167 {0x3018, 0x12},
168 {0x3019, 0x0e},
169 {0x301a, 0xb4},
170 {0x3031, 0x08},
171 {0x3032, 0x60},
172 {0x3038, 0x44},
173 {0x3207, 0x17},
174 {0x320c, 0x06},
175 {0x320d, 0xa0},
176 {0x320e, 0x08},
177 {0x320f, 0x4a},
178 {0x3250, 0xcc},
179 {0x3251, 0x02},
180 {0x3252, 0x08},
181 {0x3253, 0x45},
182 {0x3254, 0x05},
183 {0x3255, 0x3b},
184 {0x3306, 0x78},
185 {0x330a, 0x00},
186 {0x330b, 0xc8},
187 {0x330f, 0x24},
188 {0x3314, 0x80},
189 {0x3315, 0x40},
190 {0x3317, 0xf0},
191 {0x331f, 0x12},
192 {0x3364, 0x00},
193 {0x3385, 0x41},
194 {0x3387, 0x41},
195 {0x3389, 0x09},
196 {0x33ab, 0x00},
197 {0x33ac, 0x00},
198 {0x33b1, 0x03},
199 {0x33b2, 0x12},
200 {0x33f8, 0x02},
201 {0x33fa, 0x01},
202 {0x3409, 0x08},
203 {0x34f0, 0xc0},
204 {0x34f1, 0x20},
205 {0x34f2, 0x03},
206 {0x3622, 0xf5},
207 {0x3630, 0x5c},
208 {0x3631, 0x80},
209 {0x3632, 0xc8},
210 {0x3633, 0x32},
211 {0x3638, 0x2a},
212 {0x3639, 0x07},
213 {0x363b, 0x48},
214 {0x363c, 0x83},
215 {0x363d, 0x10},
216 {0x36ea, 0x3a},
217 {0x36fa, 0x25},
218 {0x36fb, 0x05},
219 {0x36fd, 0x04},
220 {0x3900, 0x11},
221 {0x3901, 0x05},
222 {0x3902, 0xc5},
223 {0x3904, 0x04},
224 {0x3908, 0x91},
225 {0x391e, 0x00},
226 {0x3e01, 0x53},
227 {0x3e02, 0xe0},
228 {0x3e09, 0x20},
229 {0x3e0e, 0xd2},
230 {0x3e14, 0xb0},
231 {0x3e1e, 0x7c},
232 {0x3e26, 0x20},
233 {0x4418, 0x38},
234 {0x4503, 0x10},
235 {0x4837, 0x14},
236 {0x5000, 0x0e},
237 {0x540c, 0x51},
238 {0x550f, 0x38},
239 {0x5780, 0x67},
240 {0x5784, 0x10},
241 {0x5785, 0x06},
242 {0x5787, 0x02},
243 {0x5788, 0x00},
244 {0x5789, 0x00},
245 {0x578a, 0x02},
246 {0x578b, 0x00},
247 {0x578c, 0x00},
248 {0x5790, 0x00},
249 {0x5791, 0x00},
250 {0x5792, 0x00},
251 {0x5793, 0x00},
252 {0x5794, 0x00},
253 {0x5795, 0x00},
254 {0x5799, 0x04},
255
256 {0x3037, 0x00},
257
258 //PLL set
259 {0x36e9, 0x24},
260 {0x36f9, 0x24},
261
262 {0x0100, 0x01},
263 {REG_NULL, 0x00},
264 };
265
266 /*
267 * Xclk 24Mhz
268 * Pclk 72Mhz
269 * linelength 1696(0x06a0)
270 * framelength 2122(0x084a)
271 * grabwindow_width 1080
272 * grabwindow_height 1280
273 * mipi 2 lane
274 * max_framerate 30fps
275 * mipi_datarate per lane 360Mbps
276 */
277 static const struct regval sc132gs_2lane_10bit_regs[] = {
278 {0x0103, 0x01},
279 {0x0100, 0x00},
280
281 //PLL bypass
282 {0x36e9, 0x80},
283 {0x36f9, 0x80},
284
285 {0x3018, 0x32},
286 {0x3019, 0x0c},
287 {0x301a, 0xb4},
288 {0x3031, 0x0a},
289 {0x3032, 0x60},
290 {0x3038, 0x44},
291 {0x3207, 0x17},
292 {0x320c, 0x05},
293 {0x320d, 0xdc},
294 {0x320e, 0x09},
295 {0x320f, 0x60},
296 {0x3250, 0xcc},
297 {0x3251, 0x02},
298 {0x3252, 0x09},
299 {0x3253, 0x5b},
300 {0x3254, 0x05},
301 {0x3255, 0x3b},
302 {0x3306, 0x78},
303 {0x330a, 0x00},
304 {0x330b, 0xc8},
305 {0x330f, 0x24},
306 {0x3314, 0x80},
307 {0x3315, 0x40},
308 {0x3317, 0xf0},
309 {0x331f, 0x12},
310 {0x3364, 0x00},
311 {0x3385, 0x41},
312 {0x3387, 0x41},
313 {0x3389, 0x09},
314 {0x33ab, 0x00},
315 {0x33ac, 0x00},
316 {0x33b1, 0x03},
317 {0x33b2, 0x12},
318 {0x33f8, 0x02},
319 {0x33fa, 0x01},
320 {0x3409, 0x08},
321 {0x34f0, 0xc0},
322 {0x34f1, 0x20},
323 {0x34f2, 0x03},
324 {0x3622, 0xf5},
325 {0x3630, 0x5c},
326 {0x3631, 0x80},
327 {0x3632, 0xc8},
328 {0x3633, 0x32},
329 {0x3638, 0x2a},
330 {0x3639, 0x07},
331 {0x363b, 0x48},
332 {0x363c, 0x83},
333 {0x363d, 0x10},
334 {0x36ea, 0x38},
335 {0x36fa, 0x25},
336 {0x36fb, 0x05},
337 {0x36fd, 0x04},
338 {0x3900, 0x11},
339 {0x3901, 0x05},
340 {0x3902, 0xc5},
341 {0x3904, 0x04},
342 {0x3908, 0x91},
343 {0x391e, 0x00},
344 {0x3e01, 0x11},
345 {0x3e02, 0x20},
346 {0x3e09, 0x20},
347 {0x3e0e, 0xd2},
348 {0x3e14, 0xb0},
349 {0x3e1e, 0x7c},
350 {0x3e26, 0x20},
351 {0x4418, 0x38},
352 {0x4503, 0x10},
353 {0x4837, 0x21},
354 {0x5000, 0x0e},
355 {0x540c, 0x51},
356 {0x550f, 0x38},
357 {0x5780, 0x67},
358 {0x5784, 0x10},
359 {0x5785, 0x06},
360 {0x5787, 0x02},
361 {0x5788, 0x00},
362 {0x5789, 0x00},
363 {0x578a, 0x02},
364 {0x578b, 0x00},
365 {0x578c, 0x00},
366 {0x5790, 0x00},
367 {0x5791, 0x00},
368 {0x5792, 0x00},
369 {0x5793, 0x00},
370 {0x5794, 0x00},
371 {0x5795, 0x00},
372 {0x5799, 0x04},
373
374 //flip
375 //{0x3221, (0x3 << 5)},
376
377 //mirror
378 {0x3221, (0x3 << 1)},
379
380 //flip & mirror
381 //{0x3221, ((0x3 << 1)|(0x3 << 5))},
382
383 //PLL set
384 {0x36e9, 0x20},
385 {0x36f9, 0x24},
386
387 {REG_NULL, 0x00},
388 };
389
390 static const struct sc132gs_mode supported_modes[] = {
391 {
392 .width = 1080,
393 .height = 1280,
394 .max_fps = {
395 .numerator = 10000,
396 .denominator = 300000,
397 },
398 .exp_def = 0x0148,
399 .hts_def = 0x06a0,
400 .vts_def = 0x084a,
401 .link_freq_index = LINK_FREQ_180M_INDEX,
402 .pixel_rate = PIXEL_RATE_WITH_180M,
403 .reg_list = sc132gs_2lane_10bit_regs,
404 .lanes = 2,
405 .bus_fmt = MEDIA_BUS_FMT_Y10_1X10,
406 },
407
408 {
409 .width = 1080,
410 .height = 1280,
411 .max_fps = {
412 .numerator = 10000,
413 .denominator = 300000,
414 },
415 .exp_def = 0x0148,
416 .hts_def = 0x06a0,
417 .vts_def = 0x084a,
418 .link_freq_index = LINK_FREQ_360M_INDEX,
419 .pixel_rate = PIXEL_RATE_WITH_360M,
420 .reg_list = sc132gs_1lane_8bit_regs,
421 .lanes = 1,
422 .bus_fmt = MEDIA_BUS_FMT_Y8_1X8,
423 },
424 };
425
426 static const char * const sc132gs_test_pattern_menu[] = {
427 "Disabled",
428 "Vertical Color Bar Type 1",
429 "Vertical Color Bar Type 2",
430 "Vertical Color Bar Type 3",
431 "Vertical Color Bar Type 4"
432 };
433
434 static const s64 link_freq_menu_items[] = {
435 MIPI_FREQ_180M,
436 MIPI_FREQ_360M,
437 };
438
439 /* Write registers up to 4 at a time */
sc132gs_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)440 static int sc132gs_write_reg(struct i2c_client *client,
441 u16 reg, u32 len, u32 val)
442 {
443 u32 buf_i, val_i;
444 u8 buf[6];
445 u8 *val_p;
446 __be32 val_be;
447 u32 ret;
448
449 if (len > 4)
450 return -EINVAL;
451
452 buf[0] = reg >> 8;
453 buf[1] = reg & 0xff;
454
455 val_be = cpu_to_be32(val);
456 val_p = (u8 *)&val_be;
457 buf_i = 2;
458 val_i = 4 - len;
459
460 while (val_i < 4)
461 buf[buf_i++] = val_p[val_i++];
462
463 ret = i2c_master_send(client, buf, len + 2);
464 if (ret != len + 2)
465 return -EIO;
466
467 return 0;
468 }
469
sc132gs_write_array(struct i2c_client * client,const struct regval * regs)470 static int sc132gs_write_array(struct i2c_client *client,
471 const struct regval *regs)
472 {
473 u32 i;
474 int ret = 0;
475
476 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
477 ret = sc132gs_write_reg(client, regs[i].addr,
478 SC132GS_REG_VALUE_08BIT, regs[i].val);
479 }
480
481 return ret;
482 }
483
484 /* Read registers up to 4 at a time */
sc132gs_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)485 static int sc132gs_read_reg(struct i2c_client *client,
486 u16 reg, unsigned int len, u32 *val)
487 {
488 struct i2c_msg msgs[2];
489 u8 *data_be_p;
490 __be32 data_be = 0;
491 __be16 reg_addr_be = cpu_to_be16(reg);
492 int ret;
493
494 if (len > 4 || !len)
495 return -EINVAL;
496
497 data_be_p = (u8 *)&data_be;
498 /* Write register address */
499 msgs[0].addr = client->addr;
500 msgs[0].flags = 0;
501 msgs[0].len = 2;
502 msgs[0].buf = (u8 *)®_addr_be;
503
504 /* Read data from register */
505 msgs[1].addr = client->addr;
506 msgs[1].flags = I2C_M_RD;
507 msgs[1].len = len;
508 msgs[1].buf = &data_be_p[4 - len];
509
510 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
511 if (ret != ARRAY_SIZE(msgs))
512 return -EIO;
513
514 *val = be32_to_cpu(data_be);
515
516 return 0;
517 }
518
sc132gs_get_reso_dist(const struct sc132gs_mode * mode,struct v4l2_mbus_framefmt * framefmt)519 static int sc132gs_get_reso_dist(const struct sc132gs_mode *mode,
520 struct v4l2_mbus_framefmt *framefmt)
521 {
522 return abs(mode->width - framefmt->width) +
523 abs(mode->height - framefmt->height);
524 }
525
526 static const struct sc132gs_mode *
sc132gs_find_best_fit(struct v4l2_subdev_format * fmt)527 sc132gs_find_best_fit(struct v4l2_subdev_format *fmt)
528 {
529 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
530 int dist;
531 int cur_best_fit = 0;
532 int cur_best_fit_dist = -1;
533 unsigned int i;
534
535 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
536 dist = sc132gs_get_reso_dist(&supported_modes[i], framefmt);
537 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
538 (supported_modes[i].bus_fmt == framefmt->code)) {
539 cur_best_fit_dist = dist;
540 cur_best_fit = i;
541 }
542 }
543 return &supported_modes[cur_best_fit];
544 }
545
sc132gs_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)546 static int sc132gs_set_fmt(struct v4l2_subdev *sd,
547 struct v4l2_subdev_pad_config *cfg,
548 struct v4l2_subdev_format *fmt)
549 {
550 struct sc132gs *sc132gs = to_sc132gs(sd);
551 const struct sc132gs_mode *mode;
552 s64 h_blank, vblank_def;
553
554 mutex_lock(&sc132gs->mutex);
555
556 mode = sc132gs_find_best_fit(fmt);
557 fmt->format.code = mode->bus_fmt;
558 fmt->format.width = mode->width;
559 fmt->format.height = mode->height;
560 fmt->format.field = V4L2_FIELD_NONE;
561 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
562 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
563 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
564 #else
565 mutex_unlock(&sc132gs->mutex);
566 return -ENOTTY;
567 #endif
568 } else {
569 sc132gs->cur_mode = mode;
570 h_blank = mode->hts_def - mode->width;
571 __v4l2_ctrl_modify_range(sc132gs->hblank, h_blank,
572 h_blank, 1, h_blank);
573 vblank_def = mode->vts_def - mode->height;
574 __v4l2_ctrl_modify_range(sc132gs->vblank, vblank_def,
575 SC132GS_VTS_MAX - mode->height,
576 1, vblank_def);
577 __v4l2_ctrl_s_ctrl_int64(sc132gs->pixel_rate, mode->pixel_rate);
578 __v4l2_ctrl_s_ctrl(sc132gs->link_freq, mode->link_freq_index);
579 sc132gs->cur_fps = mode->max_fps;
580 sc132gs->cur_vts = mode->vts_def;
581 }
582
583 mutex_unlock(&sc132gs->mutex);
584
585 return 0;
586 }
587
sc132gs_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)588 static int sc132gs_get_fmt(struct v4l2_subdev *sd,
589 struct v4l2_subdev_pad_config *cfg,
590 struct v4l2_subdev_format *fmt)
591 {
592 struct sc132gs *sc132gs = to_sc132gs(sd);
593 const struct sc132gs_mode *mode = sc132gs->cur_mode;
594
595 mutex_lock(&sc132gs->mutex);
596 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
597 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
598 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
599 #else
600 mutex_unlock(&sc132gs->mutex);
601 return -ENOTTY;
602 #endif
603 } else {
604 fmt->format.width = mode->width;
605 fmt->format.height = mode->height;
606 fmt->format.code = mode->bus_fmt;
607 fmt->format.field = V4L2_FIELD_NONE;
608 }
609 mutex_unlock(&sc132gs->mutex);
610
611 return 0;
612 }
613
sc132gs_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)614 static int sc132gs_enum_mbus_code(struct v4l2_subdev *sd,
615 struct v4l2_subdev_pad_config *cfg,
616 struct v4l2_subdev_mbus_code_enum *code)
617 {
618 struct sc132gs *sc132gs = to_sc132gs(sd);
619
620 if (code->index != 0)
621 return -EINVAL;
622 code->code = sc132gs->cur_mode->bus_fmt;
623
624 return 0;
625 }
626
sc132gs_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)627 static int sc132gs_enum_frame_sizes(struct v4l2_subdev *sd,
628 struct v4l2_subdev_pad_config *cfg,
629 struct v4l2_subdev_frame_size_enum *fse)
630 {
631 if (fse->index >= ARRAY_SIZE(supported_modes))
632 return -EINVAL;
633
634 if (fse->code != supported_modes[fse->index].bus_fmt)
635 return -EINVAL;
636
637 fse->min_width = supported_modes[fse->index].width;
638 fse->max_width = supported_modes[fse->index].width;
639 fse->max_height = supported_modes[fse->index].height;
640 fse->min_height = supported_modes[fse->index].height;
641
642 return 0;
643 }
644
sc132gs_enable_test_pattern(struct sc132gs * sc132gs,u32 pattern)645 static int sc132gs_enable_test_pattern(struct sc132gs *sc132gs, u32 pattern)
646 {
647 u32 val;
648
649 if (pattern)
650 val = (pattern - 1) | SC132GS_TEST_PATTERN_ENABLE;
651 else
652 val = SC132GS_TEST_PATTERN_DISABLE;
653
654 return sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN,
655 SC132GS_REG_VALUE_08BIT, val);
656 }
657
sc132gs_get_module_inf(struct sc132gs * sc132gs,struct rkmodule_inf * inf)658 static void sc132gs_get_module_inf(struct sc132gs *sc132gs,
659 struct rkmodule_inf *inf)
660 {
661 memset(inf, 0, sizeof(*inf));
662 strlcpy(inf->base.sensor, SC132GS_NAME, sizeof(inf->base.sensor));
663 strlcpy(inf->base.module, sc132gs->module_name,
664 sizeof(inf->base.module));
665 strlcpy(inf->base.lens, sc132gs->len_name, sizeof(inf->base.lens));
666 }
667
sc132gs_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)668 static long sc132gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
669 {
670 struct sc132gs *sc132gs = to_sc132gs(sd);
671 long ret = 0;
672 u32 stream = 0;
673
674 switch (cmd) {
675 case RKMODULE_GET_MODULE_INFO:
676 sc132gs_get_module_inf(sc132gs, (struct rkmodule_inf *)arg);
677 break;
678 case RKMODULE_SET_QUICK_STREAM:
679
680 stream = *((u32 *)arg);
681
682 if (stream)
683 ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
684 SC132GS_REG_VALUE_08BIT, SC132GS_MODE_STREAMING);
685 else
686 ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
687 SC132GS_REG_VALUE_08BIT, SC132GS_MODE_SW_STANDBY);
688 break;
689 default:
690 ret = -ENOIOCTLCMD;
691 break;
692 }
693
694 return ret;
695 }
696
697 #ifdef CONFIG_COMPAT
sc132gs_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)698 static long sc132gs_compat_ioctl32(struct v4l2_subdev *sd,
699 unsigned int cmd, unsigned long arg)
700 {
701 void __user *up = compat_ptr(arg);
702 struct rkmodule_inf *inf;
703 long ret = 0;
704 u32 stream = 0;
705
706 switch (cmd) {
707 case RKMODULE_GET_MODULE_INFO:
708 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
709 if (!inf) {
710 ret = -ENOMEM;
711 return ret;
712 }
713
714 ret = sc132gs_ioctl(sd, cmd, inf);
715 if (!ret) {
716 ret = copy_to_user(up, inf, sizeof(*inf));
717 if (ret)
718 ret = -EFAULT;
719 }
720 kfree(inf);
721 break;
722 case RKMODULE_SET_QUICK_STREAM:
723 if (copy_from_user(&stream, up, sizeof(u32)))
724 return -EFAULT;
725
726 ret = sc132gs_ioctl(sd, cmd, &stream);
727 break;
728 default:
729 ret = -ENOIOCTLCMD;
730 break;
731 }
732
733 return ret;
734 }
735 #endif
736
sc132gs_set_ctrl_gain(struct sc132gs * sc132gs,u32 a_gain)737 static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain)
738 {
739 int ret = 0;
740 u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
741
742 if (a_gain < 0x20)
743 a_gain = 0x20;
744 if (a_gain > 0x391)
745 a_gain = 0x391;
746
747 if (a_gain < 0x3a) {/*1x~1.813*/
748 fine_again = a_gain;
749 coarse_again = 0x03;
750 fine_again_reg = fine_again & 0x3f;
751 coarse_again_reg = coarse_again & 0x3F;
752 if (fine_again_reg >= 0x39)
753 fine_again_reg = 0x39;
754 } else if (a_gain < 0x72) {/*1.813~3.568x*/
755 fine_again = (a_gain - 0x3a) * 1000 / 1755 + 0x20;
756 coarse_again = 0x23;
757 if (fine_again > 0x3f)
758 fine_again = 0x3f;
759 fine_again_reg = fine_again & 0x3f;
760 coarse_again_reg = coarse_again & 0x3F;
761 } else if (a_gain < 0xe8) { /*3.568x~7.250x*/
762 fine_again = (a_gain - 0x72) * 1000 / 3682 + 0x20;
763 coarse_again = 0x27;
764 if (fine_again > 0x3f)
765 fine_again = 0x3f;
766 fine_again_reg = fine_again & 0x3f;
767 coarse_again_reg = coarse_again & 0x3F;
768 } else if (a_gain < 0x1d0) { /*7.250x~14.5x*/
769 fine_again = (a_gain - 0xe8) * 100 / 725 + 0x20;
770 coarse_again = 0x2f;
771 if (fine_again > 0x3f)
772 fine_again = 0x3f;
773 fine_again_reg = fine_again & 0x3f;
774 coarse_again_reg = coarse_again & 0x3F;
775 } else { /*14.5x~28.547*/
776 fine_again = (a_gain - 0x1d0) * 1000 / 14047 + 0x20;
777 coarse_again = 0x3f;
778 if (fine_again > 0x3f)
779 fine_again = 0x3f;
780 fine_again_reg = fine_again & 0x3f;
781 coarse_again_reg = coarse_again & 0x3F;
782 }
783 ret |= sc132gs_write_reg(sc132gs->client,
784 SC132GS_REG_COARSE_AGAIN,
785 SC132GS_REG_VALUE_08BIT,
786 coarse_again_reg);
787 ret |= sc132gs_write_reg(sc132gs->client,
788 SC132GS_REG_FINE_AGAIN,
789 SC132GS_REG_VALUE_08BIT,
790 fine_again_reg);
791 return ret;
792 }
793
__sc132gs_start_stream(struct sc132gs * sc132gs)794 static int __sc132gs_start_stream(struct sc132gs *sc132gs)
795 {
796 int ret;
797
798 ret = sc132gs_write_array(sc132gs->client, sc132gs->cur_mode->reg_list);
799 if (ret)
800 return ret;
801
802 /* In case these controls are set before streaming */
803 mutex_unlock(&sc132gs->mutex);
804 ret = v4l2_ctrl_handler_setup(&sc132gs->ctrl_handler);
805 mutex_lock(&sc132gs->mutex);
806 if (ret)
807 return ret;
808
809 return sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
810 SC132GS_REG_VALUE_08BIT, SC132GS_MODE_STREAMING);
811 }
812
__sc132gs_stop_stream(struct sc132gs * sc132gs)813 static int __sc132gs_stop_stream(struct sc132gs *sc132gs)
814 {
815 return sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
816 SC132GS_REG_VALUE_08BIT, SC132GS_MODE_SW_STANDBY);
817 }
818
sc132gs_s_stream(struct v4l2_subdev * sd,int on)819 static int sc132gs_s_stream(struct v4l2_subdev *sd, int on)
820 {
821 struct sc132gs *sc132gs = to_sc132gs(sd);
822 struct i2c_client *client = sc132gs->client;
823 unsigned int fps;
824 int ret = 0;
825
826 mutex_lock(&sc132gs->mutex);
827 on = !!on;
828 if (on == sc132gs->streaming)
829 goto unlock_and_return;
830
831 fps = DIV_ROUND_CLOSEST(sc132gs->cur_mode->max_fps.denominator,
832 sc132gs->cur_mode->max_fps.numerator);
833
834 dev_info(&sc132gs->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
835 sc132gs->cur_mode->width,
836 sc132gs->cur_mode->height,
837 fps);
838
839 if (on) {
840 ret = pm_runtime_get_sync(&client->dev);
841 if (ret < 0) {
842 pm_runtime_put_noidle(&client->dev);
843 goto unlock_and_return;
844 }
845
846 ret = __sc132gs_start_stream(sc132gs);
847 if (ret) {
848 v4l2_err(sd, "start stream failed while write regs\n");
849 pm_runtime_put(&client->dev);
850 goto unlock_and_return;
851 }
852 } else {
853 __sc132gs_stop_stream(sc132gs);
854 pm_runtime_put(&client->dev);
855 }
856
857 sc132gs->streaming = on;
858
859 unlock_and_return:
860 mutex_unlock(&sc132gs->mutex);
861
862 return ret;
863 }
864
sc132gs_s_power(struct v4l2_subdev * sd,int on)865 static int sc132gs_s_power(struct v4l2_subdev *sd, int on)
866 {
867 struct sc132gs *sc132gs = to_sc132gs(sd);
868 struct i2c_client *client = sc132gs->client;
869 int ret = 0;
870
871 mutex_lock(&sc132gs->mutex);
872
873 /* If the power state is not modified - no work to do. */
874 if (sc132gs->power_on == !!on)
875 goto unlock_and_return;
876
877 if (on) {
878 ret = pm_runtime_get_sync(&client->dev);
879 if (ret < 0) {
880 pm_runtime_put_noidle(&client->dev);
881 goto unlock_and_return;
882 }
883 sc132gs->power_on = true;
884 } else {
885 pm_runtime_put(&client->dev);
886 sc132gs->power_on = false;
887 }
888
889 unlock_and_return:
890 mutex_unlock(&sc132gs->mutex);
891
892 return ret;
893 }
894
sc132gs_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)895 static int sc132gs_g_frame_interval(struct v4l2_subdev *sd,
896 struct v4l2_subdev_frame_interval *fi)
897 {
898 struct sc132gs *sc132gs = to_sc132gs(sd);
899 const struct sc132gs_mode *mode = sc132gs->cur_mode;
900
901 if (sc132gs->streaming)
902 fi->interval = sc132gs->cur_fps;
903 else
904 fi->interval = mode->max_fps;
905
906 return 0;
907 }
908
909 /* Calculate the delay in us by clock rate and clock cycles */
sc132gs_cal_delay(u32 cycles)910 static inline u32 sc132gs_cal_delay(u32 cycles)
911 {
912 return DIV_ROUND_UP(cycles, SC132GS_XVCLK_FREQ / 1000 / 1000);
913 }
914
__sc132gs_power_on(struct sc132gs * sc132gs)915 static int __sc132gs_power_on(struct sc132gs *sc132gs)
916 {
917 int ret;
918 u32 delay_us;
919 struct device *dev = &sc132gs->client->dev;
920
921 if (!IS_ERR_OR_NULL(sc132gs->pins_default)) {
922 ret = pinctrl_select_state(sc132gs->pinctrl,
923 sc132gs->pins_default);
924 if (ret < 0)
925 dev_err(dev, "could not set pins\n");
926 }
927
928 ret = clk_set_rate(sc132gs->xvclk, SC132GS_XVCLK_FREQ);
929 if (ret < 0)
930 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
931 if (clk_get_rate(sc132gs->xvclk) != SC132GS_XVCLK_FREQ)
932 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
933 ret = clk_prepare_enable(sc132gs->xvclk);
934 if (ret < 0) {
935 dev_err(dev, "Failed to enable xvclk\n");
936 return ret;
937 }
938
939 ret = regulator_bulk_enable(SC132GS_NUM_SUPPLIES, sc132gs->supplies);
940 if (ret < 0) {
941 dev_err(dev, "Failed to enable regulators\n");
942 goto disable_clk;
943 }
944
945 if (!IS_ERR(sc132gs->reset_gpio))
946 gpiod_set_value_cansleep(sc132gs->reset_gpio, 1);
947
948 usleep_range(1000, 2000);
949
950 if (!IS_ERR(sc132gs->pwdn_gpio))
951 gpiod_set_value_cansleep(sc132gs->pwdn_gpio, 1);
952
953 if (!IS_ERR(sc132gs->reset_gpio))
954 gpiod_set_value_cansleep(sc132gs->reset_gpio, 0);
955
956 /* 8192 cycles prior to first SCCB transaction */
957 delay_us = sc132gs_cal_delay(8192);
958 usleep_range(delay_us, delay_us * 2);
959
960 return 0;
961
962 disable_clk:
963 clk_disable_unprepare(sc132gs->xvclk);
964
965 return ret;
966 }
967
__sc132gs_power_off(struct sc132gs * sc132gs)968 static void __sc132gs_power_off(struct sc132gs *sc132gs)
969 {
970 int ret;
971
972 if (!IS_ERR(sc132gs->reset_gpio))
973 gpiod_set_value_cansleep(sc132gs->reset_gpio, 1);
974
975 if (!IS_ERR(sc132gs->pwdn_gpio))
976 gpiod_set_value_cansleep(sc132gs->pwdn_gpio, 0);
977 clk_disable_unprepare(sc132gs->xvclk);
978 if (!IS_ERR_OR_NULL(sc132gs->pins_sleep)) {
979 ret = pinctrl_select_state(sc132gs->pinctrl,
980 sc132gs->pins_sleep);
981 if (ret < 0)
982 dev_dbg(&sc132gs->client->dev, "could not set pins\n");
983 }
984 regulator_bulk_disable(SC132GS_NUM_SUPPLIES, sc132gs->supplies);
985 }
986
sc132gs_runtime_resume(struct device * dev)987 static int sc132gs_runtime_resume(struct device *dev)
988 {
989 struct i2c_client *client = to_i2c_client(dev);
990 struct v4l2_subdev *sd = i2c_get_clientdata(client);
991 struct sc132gs *sc132gs = to_sc132gs(sd);
992
993 return __sc132gs_power_on(sc132gs);
994 }
995
sc132gs_runtime_suspend(struct device * dev)996 static int sc132gs_runtime_suspend(struct device *dev)
997 {
998 struct i2c_client *client = to_i2c_client(dev);
999 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1000 struct sc132gs *sc132gs = to_sc132gs(sd);
1001
1002 __sc132gs_power_off(sc132gs);
1003
1004 return 0;
1005 }
1006
1007 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc132gs_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1008 static int sc132gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1009 {
1010 struct sc132gs *sc132gs = to_sc132gs(sd);
1011 struct v4l2_mbus_framefmt *try_fmt =
1012 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1013 const struct sc132gs_mode *def_mode = &supported_modes[0];
1014
1015 mutex_lock(&sc132gs->mutex);
1016 /* Initialize try_fmt */
1017 try_fmt->width = def_mode->width;
1018 try_fmt->height = def_mode->height;
1019 try_fmt->code = def_mode->bus_fmt;
1020 try_fmt->field = V4L2_FIELD_NONE;
1021
1022 mutex_unlock(&sc132gs->mutex);
1023 /* No crop or compose */
1024
1025 return 0;
1026 }
1027 #endif
1028
sc132gs_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1029 static int sc132gs_enum_frame_interval(struct v4l2_subdev *sd,
1030 struct v4l2_subdev_pad_config *cfg,
1031 struct v4l2_subdev_frame_interval_enum *fie)
1032 {
1033 if (fie->index >= ARRAY_SIZE(supported_modes))
1034 return -EINVAL;
1035
1036 fie->code = supported_modes[fie->index].bus_fmt;
1037 fie->width = supported_modes[fie->index].width;
1038 fie->height = supported_modes[fie->index].height;
1039 fie->interval = supported_modes[fie->index].max_fps;
1040 return 0;
1041 }
1042
sc132gs_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1043 static int sc132gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1044 struct v4l2_mbus_config *config)
1045 {
1046 u32 val = 0;
1047 struct sc132gs *sc132gs = to_sc132gs(sd);
1048
1049 val = 1 << (sc132gs->cur_mode->lanes - 1) |
1050 V4L2_MBUS_CSI2_CHANNEL_0 |
1051 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1052 config->type = V4L2_MBUS_CSI2_DPHY;
1053 config->flags = val;
1054
1055 return 0;
1056 }
1057
1058 static const struct dev_pm_ops sc132gs_pm_ops = {
1059 SET_RUNTIME_PM_OPS(sc132gs_runtime_suspend,
1060 sc132gs_runtime_resume, NULL)
1061 };
1062
1063 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1064 static const struct v4l2_subdev_internal_ops sc132gs_internal_ops = {
1065 .open = sc132gs_open,
1066 };
1067 #endif
1068
1069 static const struct v4l2_subdev_core_ops sc132gs_core_ops = {
1070 .s_power = sc132gs_s_power,
1071 .ioctl = sc132gs_ioctl,
1072 #ifdef CONFIG_COMPAT
1073 .compat_ioctl32 = sc132gs_compat_ioctl32,
1074 #endif
1075 };
1076
1077 static const struct v4l2_subdev_video_ops sc132gs_video_ops = {
1078 .s_stream = sc132gs_s_stream,
1079 .g_frame_interval = sc132gs_g_frame_interval,
1080 };
1081
1082 static const struct v4l2_subdev_pad_ops sc132gs_pad_ops = {
1083 .enum_mbus_code = sc132gs_enum_mbus_code,
1084 .enum_frame_size = sc132gs_enum_frame_sizes,
1085 .enum_frame_interval = sc132gs_enum_frame_interval,
1086 .get_fmt = sc132gs_get_fmt,
1087 .set_fmt = sc132gs_set_fmt,
1088 .get_mbus_config = sc132gs_g_mbus_config,
1089 };
1090
1091 static const struct v4l2_subdev_ops sc132gs_subdev_ops = {
1092 .core = &sc132gs_core_ops,
1093 .video = &sc132gs_video_ops,
1094 .pad = &sc132gs_pad_ops,
1095 };
1096
sc132gs_modify_fps_info(struct sc132gs * sc132gs)1097 static void sc132gs_modify_fps_info(struct sc132gs *sc132gs)
1098 {
1099 const struct sc132gs_mode *mode = sc132gs->cur_mode;
1100
1101 sc132gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1102 sc132gs->cur_vts;
1103 }
1104
sc132gs_set_ctrl(struct v4l2_ctrl * ctrl)1105 static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
1106 {
1107 struct sc132gs *sc132gs = container_of(ctrl->handler,
1108 struct sc132gs, ctrl_handler);
1109 struct i2c_client *client = sc132gs->client;
1110 s64 max;
1111 int ret = 0;
1112
1113 /* Propagate change of current control to all related controls */
1114 switch (ctrl->id) {
1115 case V4L2_CID_VBLANK:
1116 /* Update max exposure while meeting expected vblanking */
1117 max = sc132gs->cur_mode->height + ctrl->val - 6;
1118 __v4l2_ctrl_modify_range(sc132gs->exposure,
1119 sc132gs->exposure->minimum, max,
1120 sc132gs->exposure->step,
1121 sc132gs->exposure->default_value);
1122 break;
1123 }
1124
1125 if (!pm_runtime_get_if_in_use(&client->dev))
1126 return 0;
1127
1128 switch (ctrl->id) {
1129 case V4L2_CID_EXPOSURE:
1130 /* 4 least significant bits of expsoure are fractional part */
1131 ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_EXPOSURE,
1132 SC132GS_REG_VALUE_16BIT, ctrl->val << 4);
1133 break;
1134 case V4L2_CID_ANALOGUE_GAIN:
1135 ret = sc132gs_set_ctrl_gain(sc132gs, ctrl->val);
1136 break;
1137 case V4L2_CID_VBLANK:
1138 ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_VTS,
1139 SC132GS_REG_VALUE_16BIT,
1140 ctrl->val + sc132gs->cur_mode->height);
1141 if (!ret)
1142 sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height;
1143 sc132gs_modify_fps_info(sc132gs);
1144 break;
1145 break;
1146 case V4L2_CID_TEST_PATTERN:
1147 ret = sc132gs_enable_test_pattern(sc132gs, ctrl->val);
1148 break;
1149 default:
1150 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1151 __func__, ctrl->id, ctrl->val);
1152 break;
1153 }
1154
1155 pm_runtime_put(&client->dev);
1156
1157 return ret;
1158 }
1159
1160 static const struct v4l2_ctrl_ops sc132gs_ctrl_ops = {
1161 .s_ctrl = sc132gs_set_ctrl,
1162 };
1163
sc132gs_initialize_controls(struct sc132gs * sc132gs)1164 static int sc132gs_initialize_controls(struct sc132gs *sc132gs)
1165 {
1166 const struct sc132gs_mode *mode;
1167 struct v4l2_ctrl_handler *handler;
1168 s64 exposure_max, vblank_def;
1169 u32 h_blank;
1170 int ret;
1171
1172 handler = &sc132gs->ctrl_handler;
1173 mode = sc132gs->cur_mode;
1174 ret = v4l2_ctrl_handler_init(handler, 8);
1175 if (ret)
1176 return ret;
1177 handler->lock = &sc132gs->mutex;
1178
1179 sc132gs->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1180 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1181 link_freq_menu_items);
1182
1183 sc132gs->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1184 V4L2_CID_PIXEL_RATE,
1185 0, PIXEL_RATE_WITH_360M,
1186 1, mode->pixel_rate);
1187
1188 __v4l2_ctrl_s_ctrl(sc132gs->link_freq, mode->pixel_rate);
1189
1190 h_blank = mode->hts_def - mode->width;
1191 sc132gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1192 h_blank, h_blank, 1, h_blank);
1193 if (sc132gs->hblank)
1194 sc132gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1195
1196 vblank_def = mode->vts_def - mode->height;
1197 sc132gs->vblank = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
1198 V4L2_CID_VBLANK, vblank_def,
1199 SC132GS_VTS_MAX - mode->height,
1200 1, vblank_def);
1201
1202 exposure_max = mode->vts_def - 6;
1203 sc132gs->exposure = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
1204 V4L2_CID_EXPOSURE, SC132GS_EXPOSURE_MIN,
1205 exposure_max, SC132GS_EXPOSURE_STEP,
1206 mode->exp_def);
1207
1208 sc132gs->anal_gain = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
1209 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1210 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1211 ANALOG_GAIN_DEFAULT);
1212
1213 sc132gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1214 &sc132gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
1215 ARRAY_SIZE(sc132gs_test_pattern_menu) - 1,
1216 0, 0, sc132gs_test_pattern_menu);
1217
1218 if (handler->error) {
1219 ret = handler->error;
1220 dev_err(&sc132gs->client->dev,
1221 "Failed to init controls(%d)\n", ret);
1222 goto err_free_handler;
1223 }
1224 sc132gs->cur_fps = mode->max_fps;
1225 sc132gs->cur_vts = mode->vts_def;
1226 sc132gs->subdev.ctrl_handler = handler;
1227
1228 return 0;
1229
1230 err_free_handler:
1231 v4l2_ctrl_handler_free(handler);
1232
1233 return ret;
1234 }
1235
sc132gs_check_sensor_id(struct sc132gs * sc132gs,struct i2c_client * client)1236 static int sc132gs_check_sensor_id(struct sc132gs *sc132gs,
1237 struct i2c_client *client)
1238 {
1239 struct device *dev = &sc132gs->client->dev;
1240 u32 id = 0;
1241 int ret;
1242
1243 ret = sc132gs_read_reg(client, SC132GS_REG_CHIP_ID,
1244 SC132GS_REG_VALUE_16BIT, &id);
1245 if (id != CHIP_ID) {
1246 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1247 return -ENODEV;
1248 }
1249
1250 dev_info(dev, "Detected SC132GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
1251
1252 return 0;
1253 }
1254
sc132gs_configure_regulators(struct sc132gs * sc132gs)1255 static int sc132gs_configure_regulators(struct sc132gs *sc132gs)
1256 {
1257 unsigned int i;
1258
1259 for (i = 0; i < SC132GS_NUM_SUPPLIES; i++)
1260 sc132gs->supplies[i].supply = sc132gs_supply_names[i];
1261
1262 return devm_regulator_bulk_get(&sc132gs->client->dev,
1263 SC132GS_NUM_SUPPLIES,
1264 sc132gs->supplies);
1265 }
1266
sc132gs_probe(struct i2c_client * client,const struct i2c_device_id * id)1267 static int sc132gs_probe(struct i2c_client *client,
1268 const struct i2c_device_id *id)
1269 {
1270 struct device *dev = &client->dev;
1271 struct device_node *node = dev->of_node;
1272 struct sc132gs *sc132gs;
1273 struct v4l2_subdev *sd;
1274 char facing[2];
1275 int ret;
1276
1277 dev_info(dev, "driver version: %02x.%02x.%02x",
1278 DRIVER_VERSION >> 16,
1279 (DRIVER_VERSION & 0xff00) >> 8,
1280 DRIVER_VERSION & 0x00ff);
1281
1282 sc132gs = devm_kzalloc(dev, sizeof(*sc132gs), GFP_KERNEL);
1283 if (!sc132gs)
1284 return -ENOMEM;
1285
1286 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1287 &sc132gs->module_index);
1288 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1289 &sc132gs->module_facing);
1290 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1291 &sc132gs->module_name);
1292 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1293 &sc132gs->len_name);
1294 if (ret) {
1295 dev_err(dev, "could not get module information!\n");
1296 return -EINVAL;
1297 }
1298 sc132gs->client = client;
1299 sc132gs->cur_mode = &supported_modes[0];
1300
1301 sc132gs->xvclk = devm_clk_get(dev, "xvclk");
1302 if (IS_ERR(sc132gs->xvclk)) {
1303 dev_err(dev, "Failed to get xvclk\n");
1304 return -EINVAL;
1305 }
1306
1307 sc132gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1308 if (IS_ERR(sc132gs->reset_gpio))
1309 dev_warn(dev, "Failed to get reset-gpios\n");
1310
1311 sc132gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1312 if (IS_ERR(sc132gs->pwdn_gpio))
1313 dev_warn(dev, "Failed to get pwdn-gpios\n");
1314 ret = sc132gs_configure_regulators(sc132gs);
1315 if (ret) {
1316 dev_err(dev, "Failed to get power regulators\n");
1317 return ret;
1318 }
1319
1320 sc132gs->pinctrl = devm_pinctrl_get(dev);
1321 if (!IS_ERR(sc132gs->pinctrl)) {
1322 sc132gs->pins_default =
1323 pinctrl_lookup_state(sc132gs->pinctrl,
1324 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1325 if (IS_ERR(sc132gs->pins_default))
1326 dev_err(dev, "could not get default pinstate\n");
1327
1328 sc132gs->pins_sleep =
1329 pinctrl_lookup_state(sc132gs->pinctrl,
1330 OF_CAMERA_PINCTRL_STATE_SLEEP);
1331 if (IS_ERR(sc132gs->pins_sleep))
1332 dev_err(dev, "could not get sleep pinstate\n");
1333 }
1334 mutex_init(&sc132gs->mutex);
1335
1336 sd = &sc132gs->subdev;
1337 v4l2_i2c_subdev_init(sd, client, &sc132gs_subdev_ops);
1338 ret = sc132gs_initialize_controls(sc132gs);
1339 if (ret)
1340 goto err_destroy_mutex;
1341
1342 ret = __sc132gs_power_on(sc132gs);
1343 if (ret)
1344 goto err_free_handler;
1345
1346 ret = sc132gs_check_sensor_id(sc132gs, client);
1347 if (ret)
1348 goto err_power_off;
1349
1350 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1351 sd->internal_ops = &sc132gs_internal_ops;
1352 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1353 V4L2_SUBDEV_FL_HAS_EVENTS;
1354 #endif
1355 #if defined(CONFIG_MEDIA_CONTROLLER)
1356 sc132gs->pad.flags = MEDIA_PAD_FL_SOURCE;
1357 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1358 ret = media_entity_pads_init(&sd->entity, 1, &sc132gs->pad);
1359 if (ret < 0)
1360 goto err_power_off;
1361 #endif
1362
1363 memset(facing, 0, sizeof(facing));
1364 if (strcmp(sc132gs->module_facing, "back") == 0)
1365 facing[0] = 'b';
1366 else
1367 facing[0] = 'f';
1368
1369 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1370 sc132gs->module_index, facing,
1371 SC132GS_NAME, dev_name(sd->dev));
1372 ret = v4l2_async_register_subdev_sensor_common(sd);
1373 if (ret) {
1374 dev_err(dev, "v4l2 async register subdev failed\n");
1375 goto err_clean_entity;
1376 }
1377
1378 pm_runtime_set_active(dev);
1379 pm_runtime_enable(dev);
1380 pm_runtime_idle(dev);
1381
1382 return 0;
1383
1384 err_clean_entity:
1385 #if defined(CONFIG_MEDIA_CONTROLLER)
1386 media_entity_cleanup(&sd->entity);
1387 #endif
1388 err_power_off:
1389 __sc132gs_power_off(sc132gs);
1390 err_free_handler:
1391 v4l2_ctrl_handler_free(&sc132gs->ctrl_handler);
1392 err_destroy_mutex:
1393 mutex_destroy(&sc132gs->mutex);
1394
1395 return ret;
1396 }
1397
sc132gs_remove(struct i2c_client * client)1398 static int sc132gs_remove(struct i2c_client *client)
1399 {
1400 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1401 struct sc132gs *sc132gs = to_sc132gs(sd);
1402
1403 v4l2_async_unregister_subdev(sd);
1404 #if defined(CONFIG_MEDIA_CONTROLLER)
1405 media_entity_cleanup(&sd->entity);
1406 #endif
1407 v4l2_ctrl_handler_free(&sc132gs->ctrl_handler);
1408 mutex_destroy(&sc132gs->mutex);
1409
1410 pm_runtime_disable(&client->dev);
1411 if (!pm_runtime_status_suspended(&client->dev))
1412 __sc132gs_power_off(sc132gs);
1413 pm_runtime_set_suspended(&client->dev);
1414
1415 return 0;
1416 }
1417
1418 #if IS_ENABLED(CONFIG_OF)
1419 static const struct of_device_id sc132gs_of_match[] = {
1420 { .compatible = "smartsens,sc132gs" },
1421 {},
1422 };
1423 MODULE_DEVICE_TABLE(of, sc132gs_of_match);
1424 #endif
1425
1426 static const struct i2c_device_id sc132gs_match_id[] = {
1427 { "smartsens,sc132gs", 0 },
1428 { },
1429 };
1430
1431 static struct i2c_driver sc132gs_i2c_driver = {
1432 .driver = {
1433 .name = SC132GS_NAME,
1434 .pm = &sc132gs_pm_ops,
1435 .of_match_table = of_match_ptr(sc132gs_of_match),
1436 },
1437 .probe = &sc132gs_probe,
1438 .remove = &sc132gs_remove,
1439 .id_table = sc132gs_match_id,
1440 };
1441
sensor_mod_init(void)1442 static int __init sensor_mod_init(void)
1443 {
1444 return i2c_add_driver(&sc132gs_i2c_driver);
1445 }
1446
sensor_mod_exit(void)1447 static void __exit sensor_mod_exit(void)
1448 {
1449 i2c_del_driver(&sc132gs_i2c_driver);
1450 }
1451
1452 device_initcall_sync(sensor_mod_init);
1453 module_exit(sensor_mod_exit);
1454
1455 MODULE_DESCRIPTION("Smartsens sc132gs sensor driver");
1456 MODULE_LICENSE("GPL v2");
1457