1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc035gs driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 * V0.1.0: MIPI is ok.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/sysfs.h>
18 #include <linux/slab.h>
19 #include <linux/version.h>
20 #include <linux/rk-camera-module.h>
21 #include <media/media-entity.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-subdev.h>
25 #include <linux/pinctrl/consumer.h>
26
27 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
28 #ifndef V4L2_CID_DIGITAL_GAIN
29 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
30 #endif
31
32 #define MIPI_FREQ_180M 180000000
33 #define MIPI_FREQ_300M 300000000
34
35 #define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10 * 2)
36 #define PIXEL_RATE_WITH_300M (MIPI_FREQ_300M * 2 / 8 * 1)
37
38 #define SC035GS_XVCLK_FREQ 24000000
39
40 #define CHIP_ID 0x0108
41 #define SC132GS_REG_CHIP_ID 0x300A
42
43 #define SC035GS_REG_CTRL_MODE 0x0100
44 #define SC035GS_MODE_SW_STANDBY 0x0
45 #define SC035GS_MODE_STREAMING BIT(0)
46
47 #define SC035GS_REG_EXPOSURE 0x3e01
48 #define SC035GS_EXPOSURE_MIN 6
49 #define SC035GS_EXPOSURE_STEP 1
50 #define SC035GS_VTS_MAX 0xffff
51
52 #define SC035GS_REG_COARSE_AGAIN 0x3e08
53 #define SC035GS_REG_FINE_AGAIN 0x3e09
54 #define ANALOG_GAIN_MIN 0x01
55 #define ANALOG_GAIN_MAX 0xF8
56 #define ANALOG_GAIN_STEP 1
57 #define ANALOG_GAIN_DEFAULT 0x1f
58
59 #define SC035GS_REG_TEST_PATTERN 0x4501
60 #define SC035GS_TEST_PATTERN_ENABLE 0xcc
61 #define SC035GS_TEST_PATTERN_DISABLE 0xc4
62
63 #define SC035GS_REG_VTS 0x320e
64
65 #define REG_NULL 0xFFFF
66
67 #define SC035GS_REG_VALUE_08BIT 1
68 #define SC035GS_REG_VALUE_16BIT 2
69 #define SC035GS_REG_VALUE_24BIT 3
70
71 #define SC035GS_NAME "sc035gs"
72
73 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
74 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
75
76 static const char *const sc035gs_supply_names[] = {
77 "avdd", /* Analog power */
78 "dovdd", /* Digital I/O power */
79 "dvdd", /* Digital core power */
80 };
81
82 #define SC035GS_NUM_SUPPLIES ARRAY_SIZE(sc035gs_supply_names)
83
84 enum {
85 LINK_FREQ_180M_INDEX,
86 LINK_FREQ_300M_INDEX,
87 };
88
89 struct regval {
90 u16 addr;
91 u8 val;
92 };
93
94 struct sc035gs_mode {
95 u32 width;
96 u32 height;
97 struct v4l2_fract max_fps;
98 u32 hts_def;
99 u32 vts_def;
100 u32 exp_def;
101 u32 link_freq_index;
102 u64 pixel_rate;
103 const struct regval *reg_list;
104 u32 lanes;
105 u32 bus_fmt;
106 };
107
108 struct sc035gs {
109 struct i2c_client *client;
110 struct clk *xvclk;
111 struct gpio_desc *reset_gpio;
112 struct gpio_desc *pwdn_gpio;
113 struct regulator_bulk_data supplies[SC035GS_NUM_SUPPLIES];
114 struct pinctrl *pinctrl;
115 struct pinctrl_state *pins_default;
116 struct pinctrl_state *pins_sleep;
117 struct v4l2_subdev subdev;
118 struct media_pad pad;
119 struct v4l2_ctrl_handler ctrl_handler;
120 struct v4l2_ctrl *exposure;
121 struct v4l2_ctrl *anal_gain;
122 struct v4l2_ctrl *digi_gain;
123 struct v4l2_ctrl *hblank;
124 struct v4l2_ctrl *vblank;
125 struct v4l2_ctrl *test_pattern;
126 struct v4l2_ctrl *pixel_rate;
127 struct v4l2_ctrl *link_freq;
128 struct mutex mutex;
129 struct v4l2_fract cur_fps;
130 u32 cur_vts;
131 bool streaming;
132 bool power_on;
133 const struct sc035gs_mode *cur_mode;
134 u32 module_index;
135 const char *module_facing;
136 const char *module_name;
137 const char *len_name;
138 };
139
140 #define to_sc035gs(sd) container_of(sd, struct sc035gs, subdev)
141
142 /*
143 * Xclk 24Mhz
144 * Pclk 72Mhz
145 * linelength 1600(0x06a0)
146 * framelength 1250(0x04e2)
147 * grabwindow_width 640
148 * grabwindow_height 480
149 * mipi 2 lane
150 * max_framerate 30fps
151 * mipi_datarate per lane 360Mbps
152 */
153 static const struct regval sc035gs_2lane_10bit_regs[] = {
154 {0x0103, 0x01},
155 {0x0100, 0x00},
156 {0x36e9, 0x80},
157 {0x36f9, 0x80},
158 {0x3000, 0x00},
159 {0x3001, 0x00},
160 {0x300f, 0x0f},
161 {0x3018, 0x33},
162 {0x3019, 0xfc},
163 {0x301c, 0x78},
164 {0x301f, 0x9c},
165 {0x3031, 0x0a},
166 {0x3037, 0x20},
167 {0x303f, 0x01},
168 {0x320c, 0x06},
169 {0x320d, 0x40},
170 {0x320e, 0x04},
171 {0x320f, 0xe2},
172 {0x3217, 0x00},
173 {0x3218, 0x00},
174 {0x3220, 0x10},
175 {0x3223, 0x48},
176 {0x3226, 0x74},
177 {0x3227, 0x07},
178 {0x323b, 0x00},
179 {0x3250, 0xf0},
180 {0x3251, 0x02},
181 {0x3252, 0x02},
182 {0x3253, 0x08},
183 {0x3254, 0x02},
184 {0x3255, 0x07},
185 {0x3304, 0x48},
186 {0x3305, 0x00},
187 {0x3306, 0x98},
188 {0x3309, 0x50},
189 {0x330a, 0x01},
190 {0x330b, 0x18},
191 {0x330c, 0x18},
192 {0x330f, 0x40},
193 {0x3310, 0x10},
194 {0x3314, 0x68},
195 {0x3315, 0x30},
196 {0x3316, 0x68},
197 {0x3317, 0x14},
198 {0x3329, 0x5c},
199 {0x332d, 0x5c},
200 {0x332f, 0x60},
201 {0x3335, 0x64},
202 {0x3344, 0x64},
203 {0x335b, 0x80},
204 {0x335f, 0x80},
205 {0x3366, 0x06},
206 {0x3385, 0x41},
207 {0x3387, 0x49},
208 {0x3389, 0x01},
209 {0x33b1, 0x03},
210 {0x33b2, 0x06},
211 {0x33bd, 0xe0},
212 {0x33bf, 0x10},
213 {0x3621, 0xa4},
214 {0x3622, 0x05},
215 {0x3624, 0x47},
216 {0x3630, 0x4a},
217 {0x3631, 0x58},
218 {0x3633, 0x52},
219 {0x3635, 0x03},
220 {0x3636, 0x25},
221 {0x3637, 0x8a},
222 {0x3638, 0x0f},
223 {0x3639, 0x08},
224 {0x363a, 0x00},
225 {0x363b, 0x48},
226 {0x363c, 0x86},
227 {0x363e, 0xf8},
228 {0x3640, 0x00},
229 {0x3641, 0x01},
230 {0x36ea, 0x3b},
231 {0x36eb, 0x0e},
232 {0x36ec, 0x1e},
233 {0x36ed, 0x20},
234 {0x36fa, 0x3b},
235 {0x36fb, 0x10},
236 {0x36fc, 0x02},
237 {0x36fd, 0x00},
238 {0x3908, 0x91},
239 {0x391b, 0x81},
240 {0x3d08, 0x01},
241 {0x3e01, 0x18},
242 {0x3e02, 0xf0},
243
244 {0x3f04, 0x06},
245 {0x3f05, 0x20},
246 {0x4500, 0x59},
247 {0x4501, 0xc4},
248 {0x4603, 0x00},
249 {0x4800, 0x64},
250 {0x4809, 0x01},
251 {0x4810, 0x00},
252 {0x4811, 0x01},
253 {0x4837, 0x42},
254 {0x5011, 0x00},
255 {0x5988, 0x02},
256 {0x598e, 0x06},
257 {0x598f, 0x08},
258 {0x36e9, 0x24},
259 {0x36f9, 0x24},
260
261 //again adjust
262 {0x4418, 0x0a},
263 {0x363d, 0x10},
264 {0x4419, 0x80},
265
266 //mirror & flip
267 {0x3221, (0x03 << 1)},
268
269 //exposure 5ms
270 {0x3e01, 0x13},
271 {0x3e02, 0xc0},
272
273 //dgain 1
274 {0x3e06, 0x0c},
275 {0x3e07, 0x80},
276
277 //gain < 2
278 {0x3631, 0x58},
279 {0x3630, 0x4a},
280
281 //again 1
282 {0x3e08, 0x03},
283 {0x3e09, 0x10},
284
285 {REG_NULL, 0x00},
286 };
287
288 static const struct sc035gs_mode supported_modes[] = {
289 {
290 .width = 640,
291 .height = 480,
292 .max_fps = {
293 .numerator = 10000,
294 .denominator = 300000,
295 },
296 .exp_def = 0x0bb,
297 .hts_def = 0x640,
298 .vts_def = 0x4e2,
299 .link_freq_index = LINK_FREQ_300M_INDEX,
300 .pixel_rate = PIXEL_RATE_WITH_300M,
301 .reg_list = sc035gs_2lane_10bit_regs,
302 .lanes = 2,
303 .bus_fmt = MEDIA_BUS_FMT_Y10_1X10,
304 },
305 };
306
307 static const char *const sc035gs_test_pattern_menu[] = {
308 "Disabled",
309 "Vertical Color Bar Type 1",
310 "Vertical Color Bar Type 2",
311 "Vertical Color Bar Type 3",
312 "Vertical Color Bar Type 4"
313 };
314
315 static const s64 link_freq_menu_items[] = {
316 MIPI_FREQ_180M,
317 MIPI_FREQ_300M,
318 };
319
320 /* Write registers up to 4 at a time */
sc035gs_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)321 static int sc035gs_write_reg(struct i2c_client *client,
322 u16 reg, u32 len, u32 val)
323 {
324 u32 buf_i, val_i;
325 u8 buf[6];
326 u8 *val_p;
327 __be32 val_be;
328 u32 ret;
329
330 if (len > 4)
331 return -EINVAL;
332
333 buf[0] = reg >> 8;
334 buf[1] = reg & 0xff;
335
336 val_be = cpu_to_be32(val);
337 val_p = (u8 *)&val_be;
338 buf_i = 2;
339 val_i = 4 - len;
340
341 while (val_i < 4)
342 buf[buf_i++] = val_p[val_i++];
343
344 ret = i2c_master_send(client, buf, len + 2);
345 if (ret != len + 2)
346 return -EIO;
347
348 return 0;
349 }
350
sc035gs_write_array(struct i2c_client * client,const struct regval * regs)351 static int sc035gs_write_array(struct i2c_client *client,
352 const struct regval *regs)
353 {
354 u32 i;
355 int ret = 0;
356
357 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
358 ret = sc035gs_write_reg(client, regs[i].addr,
359 SC035GS_REG_VALUE_08BIT, regs[i].val);
360 }
361
362 return ret;
363 }
364
365 /* Read registers up to 4 at a time */
sc035gs_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)366 static int sc035gs_read_reg(struct i2c_client *client,
367 u16 reg, unsigned int len, u32 *val)
368 {
369 struct i2c_msg msgs[2];
370 u8 *data_be_p;
371 __be32 data_be = 0;
372 __be16 reg_addr_be = cpu_to_be16(reg);
373 int ret;
374
375 if (len > 4 || !len)
376 return -EINVAL;
377
378 data_be_p = (u8 *)&data_be;
379 /* Write register address */
380 msgs[0].addr = client->addr;
381 msgs[0].flags = 0;
382 msgs[0].len = 2;
383 msgs[0].buf = (u8 *)®_addr_be;
384
385 /* Read data from register */
386 msgs[1].addr = client->addr;
387 msgs[1].flags = I2C_M_RD;
388 msgs[1].len = len;
389 msgs[1].buf = &data_be_p[4 - len];
390
391 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
392 if (ret != ARRAY_SIZE(msgs))
393 return -EIO;
394
395 *val = be32_to_cpu(data_be);
396
397 return 0;
398 }
399
sc035gs_get_reso_dist(const struct sc035gs_mode * mode,struct v4l2_mbus_framefmt * framefmt)400 static int sc035gs_get_reso_dist(const struct sc035gs_mode *mode,
401 struct v4l2_mbus_framefmt *framefmt)
402 {
403 return abs(mode->width - framefmt->width) +
404 abs(mode->height - framefmt->height);
405 }
406
407 static const struct sc035gs_mode *
sc035gs_find_best_fit(struct v4l2_subdev_format * fmt)408 sc035gs_find_best_fit(struct v4l2_subdev_format *fmt)
409 {
410 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
411 int dist;
412 int cur_best_fit = 0;
413 int cur_best_fit_dist = -1;
414 unsigned int i;
415
416 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
417 dist = sc035gs_get_reso_dist(&supported_modes[i], framefmt);
418 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
419 (supported_modes[i].bus_fmt == framefmt->code)) {
420 cur_best_fit_dist = dist;
421 cur_best_fit = i;
422 }
423 }
424 return &supported_modes[cur_best_fit];
425 }
426
sc035gs_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)427 static int sc035gs_set_fmt(struct v4l2_subdev *sd,
428 struct v4l2_subdev_pad_config *cfg,
429 struct v4l2_subdev_format *fmt)
430 {
431 struct sc035gs *sc035gs = to_sc035gs(sd);
432 const struct sc035gs_mode *mode;
433 s64 h_blank, vblank_def;
434
435 mutex_lock(&sc035gs->mutex);
436
437 mode = sc035gs_find_best_fit(fmt);
438 fmt->format.code = mode->bus_fmt;
439 fmt->format.width = mode->width;
440 fmt->format.height = mode->height;
441 fmt->format.field = V4L2_FIELD_NONE;
442 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
443 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
444 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
445 #else
446 mutex_unlock(&sc035gs->mutex);
447 return -ENOTTY;
448 #endif
449 } else {
450 sc035gs->cur_mode = mode;
451 h_blank = mode->hts_def - mode->width;
452 __v4l2_ctrl_modify_range(sc035gs->hblank, h_blank,
453 h_blank, 1, h_blank);
454 vblank_def = mode->vts_def - mode->height;
455 __v4l2_ctrl_modify_range(sc035gs->vblank, vblank_def,
456 SC035GS_VTS_MAX - mode->height,
457 1, vblank_def);
458 __v4l2_ctrl_s_ctrl_int64(sc035gs->pixel_rate, mode->pixel_rate);
459 __v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->link_freq_index);
460 sc035gs->cur_vts = mode->vts_def;
461 sc035gs->cur_fps = mode->max_fps;
462 }
463
464 mutex_unlock(&sc035gs->mutex);
465
466 return 0;
467 }
468
sc035gs_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)469 static int sc035gs_get_fmt(struct v4l2_subdev *sd,
470 struct v4l2_subdev_pad_config *cfg,
471 struct v4l2_subdev_format *fmt)
472 {
473 struct sc035gs *sc035gs = to_sc035gs(sd);
474 const struct sc035gs_mode *mode = sc035gs->cur_mode;
475
476 mutex_lock(&sc035gs->mutex);
477 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
478 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
479 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
480 #else
481 mutex_unlock(&sc035gs->mutex);
482 return -ENOTTY;
483 #endif
484 } else {
485 fmt->format.width = mode->width;
486 fmt->format.height = mode->height;
487 fmt->format.code = mode->bus_fmt;
488 fmt->format.field = V4L2_FIELD_NONE;
489 }
490 mutex_unlock(&sc035gs->mutex);
491
492 return 0;
493 }
494
sc035gs_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)495 static int sc035gs_enum_mbus_code(struct v4l2_subdev *sd,
496 struct v4l2_subdev_pad_config *cfg,
497 struct v4l2_subdev_mbus_code_enum *code)
498 {
499 struct sc035gs *sc035gs = to_sc035gs(sd);
500
501 if (code->index != 0)
502 return -EINVAL;
503 code->code = sc035gs->cur_mode->bus_fmt;
504
505 return 0;
506 }
507
sc035gs_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)508 static int sc035gs_enum_frame_sizes(struct v4l2_subdev *sd,
509 struct v4l2_subdev_pad_config *cfg,
510 struct v4l2_subdev_frame_size_enum *fse)
511 {
512 if (fse->index >= ARRAY_SIZE(supported_modes))
513 return -EINVAL;
514
515 if (fse->code != supported_modes[fse->index].bus_fmt)
516 return -EINVAL;
517
518 fse->min_width = supported_modes[fse->index].width;
519 fse->max_width = supported_modes[fse->index].width;
520 fse->max_height = supported_modes[fse->index].height;
521 fse->min_height = supported_modes[fse->index].height;
522
523 return 0;
524 }
525
sc035gs_enable_test_pattern(struct sc035gs * sc035gs,u32 pattern)526 static int sc035gs_enable_test_pattern(struct sc035gs *sc035gs, u32 pattern)
527 {
528 u32 val;
529
530 if (pattern)
531 val = (pattern - 1) | SC035GS_TEST_PATTERN_ENABLE;
532 else
533 val = SC035GS_TEST_PATTERN_DISABLE;
534
535 return sc035gs_write_reg(sc035gs->client, SC035GS_REG_TEST_PATTERN,
536 SC035GS_REG_VALUE_08BIT, val);
537 }
538
sc035gs_get_module_inf(struct sc035gs * sc035gs,struct rkmodule_inf * inf)539 static void sc035gs_get_module_inf(struct sc035gs *sc035gs,
540 struct rkmodule_inf *inf)
541 {
542 memset(inf, 0, sizeof(*inf));
543 strscpy(inf->base.sensor, SC035GS_NAME, sizeof(inf->base.sensor));
544 strscpy(inf->base.module, sc035gs->module_name,
545 sizeof(inf->base.module));
546 strscpy(inf->base.lens, sc035gs->len_name, sizeof(inf->base.lens));
547 }
548
sc035gs_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)549 static long sc035gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
550 {
551 struct sc035gs *sc035gs = to_sc035gs(sd);
552 long ret = 0;
553 u32 stream = 0;
554
555 switch (cmd) {
556 case RKMODULE_GET_MODULE_INFO:
557 sc035gs_get_module_inf(sc035gs, (struct rkmodule_inf *)arg);
558 break;
559 case RKMODULE_SET_QUICK_STREAM:
560
561 stream = *((u32 *)arg);
562
563 if (stream)
564 ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
565 SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
566 else
567 ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
568 SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
569 break;
570 default:
571 ret = -ENOIOCTLCMD;
572 break;
573 }
574
575 return ret;
576 }
577
578 #ifdef CONFIG_COMPAT
sc035gs_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)579 static long sc035gs_compat_ioctl32(struct v4l2_subdev *sd,
580 unsigned int cmd, unsigned long arg)
581 {
582 void __user *up = compat_ptr(arg);
583 struct rkmodule_inf *inf;
584 long ret = 0;
585 u32 stream = 0;
586
587 switch (cmd) {
588 case RKMODULE_GET_MODULE_INFO:
589 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
590 if (!inf) {
591 ret = -ENOMEM;
592 return ret;
593 }
594
595 ret = sc035gs_ioctl(sd, cmd, inf);
596 if (!ret) {
597 ret = copy_to_user(up, inf, sizeof(*inf));
598 if (ret)
599 ret = -EFAULT;
600 }
601 kfree(inf);
602 break;
603 case RKMODULE_SET_QUICK_STREAM:
604 if (copy_from_user(&stream, up, sizeof(u32)))
605 return -EFAULT;
606
607 ret = sc035gs_ioctl(sd, cmd, &stream);
608 break;
609 default:
610 ret = -ENOIOCTLCMD;
611 break;
612 }
613
614 return ret;
615 }
616 #endif
617
sc035gs_set_ctrl_gain(struct sc035gs * sc035gs,u32 a_gain)618 static int sc035gs_set_ctrl_gain(struct sc035gs *sc035gs, u32 a_gain)
619 {
620 int ret = 0;
621 u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
622
623 /* (1.0 - 15.5) * 0x10 (fix point) */
624 if (a_gain < 0x10)
625 a_gain = 0x10;
626 if (a_gain > 0xf8)
627 a_gain = 0xf8;
628
629 if (a_gain < 0x20) { /*1x ~ 2x*/
630 coarse_again = 0x3;
631 fine_again = a_gain * 16 / 0x10;
632 } else if (a_gain < 0x40) { /*2x ~ 4x*/
633 coarse_again = 0x7;
634 fine_again = a_gain * 8 / 0x10;
635 } else if (a_gain < 0x80) { /*4x ~ 8x*/
636 coarse_again = 0xf;
637 fine_again = a_gain * 4 / 0x10;
638 } else { /*8x ~ 16x*/
639 coarse_again = 0x1f;
640 fine_again = a_gain * 2 / 0x10;
641 }
642
643 fine_again_reg = fine_again & 0x1F;
644 coarse_again_reg = coarse_again & 0x1F;
645
646 if (a_gain < 0x20) {
647 ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
648 SC035GS_REG_VALUE_08BIT, 0x58);
649 ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
650 SC035GS_REG_VALUE_08BIT, 0x4a);
651 } else {
652 ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
653 SC035GS_REG_VALUE_08BIT, 0x48);
654 ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
655 SC035GS_REG_VALUE_08BIT, 0x4c);
656 }
657
658 ret |= sc035gs_write_reg(sc035gs->client,
659 SC035GS_REG_COARSE_AGAIN,
660 SC035GS_REG_VALUE_08BIT,
661 coarse_again_reg);
662 ret |= sc035gs_write_reg(sc035gs->client,
663 SC035GS_REG_FINE_AGAIN,
664 SC035GS_REG_VALUE_08BIT,
665 fine_again_reg);
666
667 return ret;
668 }
669
670
__sc035gs_start_stream(struct sc035gs * sc035gs)671 static int __sc035gs_start_stream(struct sc035gs *sc035gs)
672 {
673 int ret;
674
675 ret = sc035gs_write_array(sc035gs->client, sc035gs->cur_mode->reg_list);
676 if (ret)
677 return ret;
678
679 /* In case these controls are set before streaming */
680 mutex_unlock(&sc035gs->mutex);
681 ret = v4l2_ctrl_handler_setup(&sc035gs->ctrl_handler);
682 mutex_lock(&sc035gs->mutex);
683 if (ret)
684 return ret;
685
686 ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
687 SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
688
689 usleep_range(10000, 12000);
690
691 ret |= sc035gs_write_reg(sc035gs->client, 0x4418,
692 SC035GS_REG_VALUE_08BIT, 0x0a);
693 ret |= sc035gs_write_reg(sc035gs->client, 0x4419,
694 SC035GS_REG_VALUE_08BIT, 0x80);
695 return ret;
696 }
697
__sc035gs_stop_stream(struct sc035gs * sc035gs)698 static int __sc035gs_stop_stream(struct sc035gs *sc035gs)
699 {
700 return sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
701 SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
702 }
703
sc035gs_s_stream(struct v4l2_subdev * sd,int on)704 static int sc035gs_s_stream(struct v4l2_subdev *sd, int on)
705 {
706 struct sc035gs *sc035gs = to_sc035gs(sd);
707 struct i2c_client *client = sc035gs->client;
708 unsigned int fps;
709 int ret = 0;
710
711 mutex_lock(&sc035gs->mutex);
712 on = !!on;
713 if (on == sc035gs->streaming)
714 goto unlock_and_return;
715
716 fps = DIV_ROUND_CLOSEST(sc035gs->cur_mode->max_fps.denominator,
717 sc035gs->cur_mode->max_fps.numerator);
718
719 dev_info(&sc035gs->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
720 sc035gs->cur_mode->width,
721 sc035gs->cur_mode->height,
722 fps);
723
724 if (on) {
725 ret = pm_runtime_get_sync(&client->dev);
726 if (ret < 0) {
727 pm_runtime_put_noidle(&client->dev);
728 goto unlock_and_return;
729 }
730
731 ret = __sc035gs_start_stream(sc035gs);
732 if (ret) {
733 v4l2_err(sd, "start stream failed while write regs\n");
734 pm_runtime_put(&client->dev);
735 goto unlock_and_return;
736 }
737 } else {
738 __sc035gs_stop_stream(sc035gs);
739 pm_runtime_put(&client->dev);
740 }
741
742 sc035gs->streaming = on;
743
744 unlock_and_return:
745 mutex_unlock(&sc035gs->mutex);
746
747 return ret;
748 }
749
sc035gs_s_power(struct v4l2_subdev * sd,int on)750 static int sc035gs_s_power(struct v4l2_subdev *sd, int on)
751 {
752 struct sc035gs *sc035gs = to_sc035gs(sd);
753 struct i2c_client *client = sc035gs->client;
754 int ret = 0;
755
756 mutex_lock(&sc035gs->mutex);
757
758 /* If the power state is not modified - no work to do. */
759 if (sc035gs->power_on == !!on)
760 goto unlock_and_return;
761
762 if (on) {
763 ret = pm_runtime_get_sync(&client->dev);
764 if (ret < 0) {
765 pm_runtime_put_noidle(&client->dev);
766 goto unlock_and_return;
767 }
768 sc035gs->power_on = true;
769 } else {
770 pm_runtime_put(&client->dev);
771 sc035gs->power_on = false;
772 }
773
774 unlock_and_return:
775 mutex_unlock(&sc035gs->mutex);
776
777 return ret;
778 }
779
sc035gs_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)780 static int sc035gs_g_frame_interval(struct v4l2_subdev *sd,
781 struct v4l2_subdev_frame_interval *fi)
782 {
783 struct sc035gs *sc035gs = to_sc035gs(sd);
784 const struct sc035gs_mode *mode = sc035gs->cur_mode;
785
786 if (sc035gs->streaming)
787 fi->interval = sc035gs->cur_fps;
788 else
789 fi->interval = mode->max_fps;
790
791 return 0;
792 }
793
794 /* Calculate the delay in us by clock rate and clock cycles */
sc035gs_cal_delay(u32 cycles)795 static inline u32 sc035gs_cal_delay(u32 cycles)
796 {
797 return DIV_ROUND_UP(cycles, SC035GS_XVCLK_FREQ / 1000 / 1000);
798 }
799
__sc035gs_power_on(struct sc035gs * sc035gs)800 static int __sc035gs_power_on(struct sc035gs *sc035gs)
801 {
802 int ret;
803 u32 delay_us;
804 struct device *dev = &sc035gs->client->dev;
805
806 if (!IS_ERR_OR_NULL(sc035gs->pins_default)) {
807 ret = pinctrl_select_state(sc035gs->pinctrl,
808 sc035gs->pins_default);
809 if (ret < 0)
810 dev_err(dev, "could not set pins\n");
811 }
812
813 ret = clk_set_rate(sc035gs->xvclk, SC035GS_XVCLK_FREQ);
814 if (ret < 0)
815 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
816 if (clk_get_rate(sc035gs->xvclk) != SC035GS_XVCLK_FREQ)
817 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
818 ret = clk_prepare_enable(sc035gs->xvclk);
819 if (ret < 0) {
820 dev_err(dev, "Failed to enable xvclk\n");
821 return ret;
822 }
823
824 ret = regulator_bulk_enable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
825 if (ret < 0) {
826 dev_err(dev, "Failed to enable regulators\n");
827 goto disable_clk;
828 }
829
830 if (!IS_ERR(sc035gs->reset_gpio))
831 gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
832
833 usleep_range(1000, 2000);
834
835 if (!IS_ERR(sc035gs->pwdn_gpio))
836 gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 1);
837
838 if (!IS_ERR(sc035gs->reset_gpio))
839 gpiod_set_value_cansleep(sc035gs->reset_gpio, 0);
840
841 /* 8192 cycles prior to first SCCB transaction */
842 delay_us = sc035gs_cal_delay(8192);
843 usleep_range(delay_us, delay_us * 2);
844
845 return 0;
846
847 disable_clk:
848 clk_disable_unprepare(sc035gs->xvclk);
849
850 return ret;
851 }
852
__sc035gs_power_off(struct sc035gs * sc035gs)853 static void __sc035gs_power_off(struct sc035gs *sc035gs)
854 {
855 int ret;
856
857 if (!IS_ERR(sc035gs->reset_gpio))
858 gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
859
860 if (!IS_ERR(sc035gs->pwdn_gpio))
861 gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 0);
862 clk_disable_unprepare(sc035gs->xvclk);
863 if (!IS_ERR_OR_NULL(sc035gs->pins_sleep)) {
864 ret = pinctrl_select_state(sc035gs->pinctrl,
865 sc035gs->pins_sleep);
866 if (ret < 0)
867 dev_dbg(&sc035gs->client->dev, "could not set pins\n");
868 }
869 regulator_bulk_disable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
870 }
871
sc035gs_runtime_resume(struct device * dev)872 static int sc035gs_runtime_resume(struct device *dev)
873 {
874 struct i2c_client *client = to_i2c_client(dev);
875 struct v4l2_subdev *sd = i2c_get_clientdata(client);
876 struct sc035gs *sc035gs = to_sc035gs(sd);
877
878 return __sc035gs_power_on(sc035gs);
879 }
880
sc035gs_runtime_suspend(struct device * dev)881 static int sc035gs_runtime_suspend(struct device *dev)
882 {
883 struct i2c_client *client = to_i2c_client(dev);
884 struct v4l2_subdev *sd = i2c_get_clientdata(client);
885 struct sc035gs *sc035gs = to_sc035gs(sd);
886
887 __sc035gs_power_off(sc035gs);
888
889 return 0;
890 }
891
892 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc035gs_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)893 static int sc035gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
894 {
895 struct sc035gs *sc035gs = to_sc035gs(sd);
896 struct v4l2_mbus_framefmt *try_fmt =
897 v4l2_subdev_get_try_format(sd, fh->pad, 0);
898 const struct sc035gs_mode *def_mode = &supported_modes[0];
899
900 mutex_lock(&sc035gs->mutex);
901 /* Initialize try_fmt */
902 try_fmt->width = def_mode->width;
903 try_fmt->height = def_mode->height;
904 try_fmt->code = def_mode->bus_fmt;
905 try_fmt->field = V4L2_FIELD_NONE;
906
907 mutex_unlock(&sc035gs->mutex);
908 /* No crop or compose */
909
910 return 0;
911 }
912 #endif
913
sc035gs_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)914 static int sc035gs_enum_frame_interval(struct v4l2_subdev *sd,
915 struct v4l2_subdev_pad_config *cfg,
916 struct v4l2_subdev_frame_interval_enum *fie)
917 {
918 if (fie->index >= ARRAY_SIZE(supported_modes))
919 return -EINVAL;
920
921 fie->code = supported_modes[fie->index].bus_fmt;
922 fie->width = supported_modes[fie->index].width;
923 fie->height = supported_modes[fie->index].height;
924 fie->interval = supported_modes[fie->index].max_fps;
925 return 0;
926 }
927
sc035gs_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)928 static int sc035gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
929 struct v4l2_mbus_config *config)
930 {
931 u32 val = 0;
932 struct sc035gs *sc035gs = to_sc035gs(sd);
933
934 val = 1 << (sc035gs->cur_mode->lanes - 1) |
935 V4L2_MBUS_CSI2_CHANNEL_0 |
936 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
937 config->type = V4L2_MBUS_CSI2_DPHY;
938 config->flags = val;
939
940 return 0;
941 }
942
943 static const struct dev_pm_ops sc035gs_pm_ops = {
944 SET_RUNTIME_PM_OPS(sc035gs_runtime_suspend,
945 sc035gs_runtime_resume, NULL)
946 };
947
948 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
949 static const struct v4l2_subdev_internal_ops sc035gs_internal_ops = {
950 .open = sc035gs_open,
951 };
952 #endif
953
954 static const struct v4l2_subdev_core_ops sc035gs_core_ops = {
955 .s_power = sc035gs_s_power,
956 .ioctl = sc035gs_ioctl,
957 #ifdef CONFIG_COMPAT
958 .compat_ioctl32 = sc035gs_compat_ioctl32,
959 #endif
960 };
961
962 static const struct v4l2_subdev_video_ops sc035gs_video_ops = {
963 .s_stream = sc035gs_s_stream,
964 .g_frame_interval = sc035gs_g_frame_interval,
965 };
966
967 static const struct v4l2_subdev_pad_ops sc035gs_pad_ops = {
968 .enum_mbus_code = sc035gs_enum_mbus_code,
969 .enum_frame_size = sc035gs_enum_frame_sizes,
970 .enum_frame_interval = sc035gs_enum_frame_interval,
971 .get_fmt = sc035gs_get_fmt,
972 .set_fmt = sc035gs_set_fmt,
973 .get_mbus_config = sc035gs_g_mbus_config,
974 };
975
976 static const struct v4l2_subdev_ops sc035gs_subdev_ops = {
977 .core = &sc035gs_core_ops,
978 .video = &sc035gs_video_ops,
979 .pad = &sc035gs_pad_ops,
980 };
981
sc035gs_modify_fps_info(struct sc035gs * sc035gs)982 static void sc035gs_modify_fps_info(struct sc035gs *sc035gs)
983 {
984 const struct sc035gs_mode *mode = sc035gs->cur_mode;
985
986 sc035gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
987 sc035gs->cur_vts;
988 }
989
sc035gs_set_ctrl(struct v4l2_ctrl * ctrl)990 static int sc035gs_set_ctrl(struct v4l2_ctrl *ctrl)
991 {
992 struct sc035gs *sc035gs = container_of(ctrl->handler,
993 struct sc035gs, ctrl_handler);
994 struct i2c_client *client = sc035gs->client;
995 s64 max;
996 int ret = 0;
997
998 /* Propagate change of current control to all related controls */
999 switch (ctrl->id) {
1000 case V4L2_CID_VBLANK:
1001 /* Update max exposure while meeting expected vblanking */
1002 max = sc035gs->cur_mode->height + ctrl->val - 6;
1003 __v4l2_ctrl_modify_range(sc035gs->exposure,
1004 sc035gs->exposure->minimum, max,
1005 sc035gs->exposure->step,
1006 sc035gs->exposure->default_value);
1007 break;
1008 }
1009
1010 if (!pm_runtime_get_if_in_use(&client->dev))
1011 return 0;
1012
1013 switch (ctrl->id) {
1014 case V4L2_CID_EXPOSURE:
1015 /* 4 least significant bits of expsoure are fractional part */
1016 ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_EXPOSURE,
1017 SC035GS_REG_VALUE_16BIT, ctrl->val << 4);
1018 break;
1019 case V4L2_CID_ANALOGUE_GAIN:
1020 ret = sc035gs_set_ctrl_gain(sc035gs, ctrl->val);
1021 break;
1022 case V4L2_CID_VBLANK:
1023 ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_VTS,
1024 SC035GS_REG_VALUE_16BIT,
1025 ctrl->val + sc035gs->cur_mode->height);
1026 if (!ret)
1027 sc035gs->cur_vts = ctrl->val + sc035gs->cur_mode->height;
1028 sc035gs_modify_fps_info(sc035gs);
1029 break;
1030 case V4L2_CID_TEST_PATTERN:
1031 ret = sc035gs_enable_test_pattern(sc035gs, ctrl->val);
1032 break;
1033 default:
1034 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1035 __func__, ctrl->id, ctrl->val);
1036 break;
1037 }
1038
1039 pm_runtime_put(&client->dev);
1040
1041 return ret;
1042 }
1043
1044 static const struct v4l2_ctrl_ops sc035gs_ctrl_ops = {
1045 .s_ctrl = sc035gs_set_ctrl,
1046 };
1047
sc035gs_initialize_controls(struct sc035gs * sc035gs)1048 static int sc035gs_initialize_controls(struct sc035gs *sc035gs)
1049 {
1050 const struct sc035gs_mode *mode;
1051 struct v4l2_ctrl_handler *handler;
1052 s64 exposure_max, vblank_def;
1053 u32 h_blank;
1054 int ret;
1055
1056 handler = &sc035gs->ctrl_handler;
1057 mode = sc035gs->cur_mode;
1058 ret = v4l2_ctrl_handler_init(handler, 8);
1059 if (ret)
1060 return ret;
1061 handler->lock = &sc035gs->mutex;
1062
1063 sc035gs->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1064 ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1065 link_freq_menu_items);
1066
1067 sc035gs->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1068 V4L2_CID_PIXEL_RATE,
1069 0, PIXEL_RATE_WITH_300M,
1070 1, mode->pixel_rate);
1071
1072 __v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->pixel_rate);
1073
1074 h_blank = mode->hts_def - mode->width;
1075 sc035gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1076 h_blank, h_blank, 1, h_blank);
1077 if (sc035gs->hblank)
1078 sc035gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1079
1080 vblank_def = mode->vts_def - mode->height;
1081 sc035gs->cur_vts = mode->vts_def;
1082 sc035gs->cur_fps = mode->max_fps;
1083 sc035gs->vblank = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
1084 V4L2_CID_VBLANK, vblank_def,
1085 SC035GS_VTS_MAX - mode->height,
1086 1, vblank_def);
1087
1088 exposure_max = mode->vts_def - 6;
1089 sc035gs->exposure = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
1090 V4L2_CID_EXPOSURE, SC035GS_EXPOSURE_MIN,
1091 exposure_max, SC035GS_EXPOSURE_STEP,
1092 mode->exp_def);
1093
1094 sc035gs->anal_gain = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
1095 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1096 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1097 ANALOG_GAIN_DEFAULT);
1098
1099 sc035gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1100 &sc035gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
1101 ARRAY_SIZE(sc035gs_test_pattern_menu) - 1,
1102 0, 0, sc035gs_test_pattern_menu);
1103
1104 if (handler->error) {
1105 ret = handler->error;
1106 dev_err(&sc035gs->client->dev,
1107 "Failed to init controls(%d)\n", ret);
1108 goto err_free_handler;
1109 }
1110
1111 sc035gs->subdev.ctrl_handler = handler;
1112
1113 return 0;
1114
1115 err_free_handler:
1116 v4l2_ctrl_handler_free(handler);
1117
1118 return ret;
1119 }
1120
sc035gs_check_sensor_id(struct sc035gs * sc035gs,struct i2c_client * client)1121 static int sc035gs_check_sensor_id(struct sc035gs *sc035gs,
1122 struct i2c_client *client)
1123 {
1124 struct device *dev = &sc035gs->client->dev;
1125 u32 id = 0;
1126 int ret;
1127
1128 ret = sc035gs_read_reg(client, SC132GS_REG_CHIP_ID,
1129 SC035GS_REG_VALUE_16BIT, &id);
1130 if (ret || id != CHIP_ID) {
1131 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1132 return -ENODEV;
1133 }
1134
1135 dev_info(dev, "Detected SC035GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
1136
1137 return 0;
1138 }
1139
sc035gs_configure_regulators(struct sc035gs * sc035gs)1140 static int sc035gs_configure_regulators(struct sc035gs *sc035gs)
1141 {
1142 unsigned int i;
1143
1144 for (i = 0; i < SC035GS_NUM_SUPPLIES; i++)
1145 sc035gs->supplies[i].supply = sc035gs_supply_names[i];
1146
1147 return devm_regulator_bulk_get(&sc035gs->client->dev,
1148 SC035GS_NUM_SUPPLIES,
1149 sc035gs->supplies);
1150 }
1151
sc035gs_probe(struct i2c_client * client,const struct i2c_device_id * id)1152 static int sc035gs_probe(struct i2c_client *client,
1153 const struct i2c_device_id *id)
1154 {
1155 struct device *dev = &client->dev;
1156 struct device_node *node = dev->of_node;
1157 struct sc035gs *sc035gs;
1158 struct v4l2_subdev *sd;
1159 char facing[2];
1160 int ret;
1161
1162 dev_info(dev, "driver version: %02x.%02x.%02x",
1163 DRIVER_VERSION >> 16,
1164 (DRIVER_VERSION & 0xff00) >> 8,
1165 DRIVER_VERSION & 0x00ff);
1166
1167 sc035gs = devm_kzalloc(dev, sizeof(*sc035gs), GFP_KERNEL);
1168 if (!sc035gs)
1169 return -ENOMEM;
1170
1171 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1172 &sc035gs->module_index);
1173 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1174 &sc035gs->module_facing);
1175 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1176 &sc035gs->module_name);
1177 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1178 &sc035gs->len_name);
1179 if (ret) {
1180 dev_err(dev, "could not get module information!\n");
1181 return -EINVAL;
1182 }
1183 sc035gs->client = client;
1184 sc035gs->cur_mode = &supported_modes[0];
1185
1186 sc035gs->xvclk = devm_clk_get(dev, "xvclk");
1187 if (IS_ERR(sc035gs->xvclk)) {
1188 dev_err(dev, "Failed to get xvclk\n");
1189 return -EINVAL;
1190 }
1191
1192 sc035gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1193 if (IS_ERR(sc035gs->reset_gpio))
1194 dev_warn(dev, "Failed to get reset-gpios\n");
1195
1196 sc035gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1197 if (IS_ERR(sc035gs->pwdn_gpio))
1198 dev_warn(dev, "Failed to get pwdn-gpios\n");
1199 ret = sc035gs_configure_regulators(sc035gs);
1200 if (ret) {
1201 dev_err(dev, "Failed to get power regulators\n");
1202 return ret;
1203 }
1204
1205 sc035gs->pinctrl = devm_pinctrl_get(dev);
1206 if (!IS_ERR(sc035gs->pinctrl)) {
1207 sc035gs->pins_default =
1208 pinctrl_lookup_state(sc035gs->pinctrl,
1209 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1210 if (IS_ERR(sc035gs->pins_default))
1211 dev_err(dev, "could not get default pinstate\n");
1212
1213 sc035gs->pins_sleep =
1214 pinctrl_lookup_state(sc035gs->pinctrl,
1215 OF_CAMERA_PINCTRL_STATE_SLEEP);
1216 if (IS_ERR(sc035gs->pins_sleep))
1217 dev_err(dev, "could not get sleep pinstate\n");
1218 }
1219 mutex_init(&sc035gs->mutex);
1220
1221 sd = &sc035gs->subdev;
1222 v4l2_i2c_subdev_init(sd, client, &sc035gs_subdev_ops);
1223 ret = sc035gs_initialize_controls(sc035gs);
1224 if (ret)
1225 goto err_destroy_mutex;
1226
1227 ret = __sc035gs_power_on(sc035gs);
1228 if (ret)
1229 goto err_free_handler;
1230
1231 ret = sc035gs_check_sensor_id(sc035gs, client);
1232 if (ret)
1233 goto err_power_off;
1234
1235 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1236 sd->internal_ops = &sc035gs_internal_ops;
1237 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1238 V4L2_SUBDEV_FL_HAS_EVENTS;
1239 #endif
1240 #if defined(CONFIG_MEDIA_CONTROLLER)
1241 sc035gs->pad.flags = MEDIA_PAD_FL_SOURCE;
1242 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1243 ret = media_entity_pads_init(&sd->entity, 1, &sc035gs->pad);
1244 if (ret < 0)
1245 goto err_power_off;
1246 #endif
1247
1248 memset(facing, 0, sizeof(facing));
1249 if (strcmp(sc035gs->module_facing, "back") == 0)
1250 facing[0] = 'b';
1251 else
1252 facing[0] = 'f';
1253
1254 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1255 sc035gs->module_index, facing,
1256 SC035GS_NAME, dev_name(sd->dev));
1257 ret = v4l2_async_register_subdev_sensor_common(sd);
1258 if (ret) {
1259 dev_err(dev, "v4l2 async register subdev failed\n");
1260 goto err_clean_entity;
1261 }
1262
1263 pm_runtime_set_active(dev);
1264 pm_runtime_enable(dev);
1265 pm_runtime_idle(dev);
1266
1267 return 0;
1268
1269 err_clean_entity:
1270 #if defined(CONFIG_MEDIA_CONTROLLER)
1271 media_entity_cleanup(&sd->entity);
1272 #endif
1273 err_power_off:
1274 __sc035gs_power_off(sc035gs);
1275 err_free_handler:
1276 v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
1277 err_destroy_mutex:
1278 mutex_destroy(&sc035gs->mutex);
1279
1280 return ret;
1281 }
1282
sc035gs_remove(struct i2c_client * client)1283 static int sc035gs_remove(struct i2c_client *client)
1284 {
1285 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1286 struct sc035gs *sc035gs = to_sc035gs(sd);
1287
1288 v4l2_async_unregister_subdev(sd);
1289 #if defined(CONFIG_MEDIA_CONTROLLER)
1290 media_entity_cleanup(&sd->entity);
1291 #endif
1292 v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
1293 mutex_destroy(&sc035gs->mutex);
1294
1295 pm_runtime_disable(&client->dev);
1296 if (!pm_runtime_status_suspended(&client->dev))
1297 __sc035gs_power_off(sc035gs);
1298 pm_runtime_set_suspended(&client->dev);
1299
1300 return 0;
1301 }
1302
1303 #if IS_ENABLED(CONFIG_OF)
1304 static const struct of_device_id sc035gs_of_match[] = {
1305 { .compatible = "smartsens,sc035gs" },
1306 {},
1307 };
1308 MODULE_DEVICE_TABLE(of, sc035gs_of_match);
1309 #endif
1310
1311 static const struct i2c_device_id sc035gs_match_id[] = {
1312 { "smartsens,sc035gs", 0 },
1313 { },
1314 };
1315
1316 static struct i2c_driver sc035gs_i2c_driver = {
1317 .driver = {
1318 .name = SC035GS_NAME,
1319 .pm = &sc035gs_pm_ops,
1320 .of_match_table = of_match_ptr(sc035gs_of_match),
1321 },
1322 .probe = &sc035gs_probe,
1323 .remove = &sc035gs_remove,
1324 .id_table = sc035gs_match_id,
1325 };
1326
sensor_mod_init(void)1327 static int __init sensor_mod_init(void)
1328 {
1329 return i2c_add_driver(&sc035gs_i2c_driver);
1330 }
1331
sensor_mod_exit(void)1332 static void __exit sensor_mod_exit(void)
1333 {
1334 i2c_del_driver(&sc035gs_i2c_driver);
1335 }
1336
1337 device_initcall_sync(sensor_mod_init);
1338 module_exit(sensor_mod_exit);
1339
1340 MODULE_DESCRIPTION("Smartsens sc035gs sensor driver");
1341 MODULE_LICENSE("GPL");
1342