1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * s5kjn1 driver
4 *
5 * Copyright (C) 2022 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 init version.
8 * V0.0X01.0X01 adjust supply sequence to suit spec
9 * V0.0X01.0X02
10 * 1. set binning output 32 pixel aligned.
11 * 2. fix channel info omitted copy from user issue.
12 * V0.0X01.0X03
13 * 1. add delays in setting to fix probability wrong reg write.
14 * 2. add register setting readback check support.
15 */
16 //#define DEBUG
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sysfs.h>
26 #include <linux/slab.h>
27 #include <linux/version.h>
28 #include <linux/rk-camera-module.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <media/v4l2-fwnode.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/rk-preisp.h>
36 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
37 #include <linux/of_graph.h>
38 #include "otp_eeprom.h"
39
40 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x03)
41
42 /* verify default register values */
43 //#define CHECK_REG_VALUE
44
45 #ifndef V4L2_CID_DIGITAL_GAIN
46 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
47 #endif
48
49 #define MIPI_FREQ_696M 696000000
50 #define MIPI_FREQ_828M 828000000
51
52 #define PIXEL_RATE_WITH_828M (MIPI_FREQ_828M / 10 * 4 * 2)
53
54 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
55
56 #define S5KJN1_XVCLK_FREQ 24000000
57
58 #define CHIP_ID 0x38E1
59 #define S5KJN1_REG_CHIP_ID 0x0000
60
61 #define S5KJN1_REG_CTRL_MODE 0x0100
62 #define S5KJN1_MODE_SW_STANDBY 0x0
63 #define S5KJN1_MODE_STREAMING BIT(0)
64
65 #define S5KJN1_EXPOSURE_MIN 8
66 #define S5KJN1_EXPOSURE_STEP 1
67 #define S5KJN1_VTS_MAX 0xffff
68
69 #define S5KJN1_REG_EXP_LONG_H 0x0202
70
71 #define S5KJN1_REG_AGAIN_LONG_H 0x0204
72 #define S5KJN1_GAIN_MIN 0x20
73 #define S5KJN1_GAIN_MAX 0x800
74 #define S5KJN1_FULL_SIZE_GAIN_MAX 0x200
75 #define S5KJN1_GAIN_STEP 1
76 #define S5KJN1_GAIN_DEFAULT 0xc0
77
78 #define S5KJN1_GROUP_UPDATE_ADDRESS 0x0104
79 #define S5KJN1_GROUP_UPDATE_START_DATA 0x01
80 #define S5KJN1_GROUP_UPDATE_END_LAUNCH 0x00
81
82 #define S5KJN1_SOFTWARE_RESET_REG 0x0103
83
84 #define S5KJN1_REG_TEST_PATTERN 0x0600
85 #define S5KJN1_TEST_PATTERN_ENABLE 0x01
86 #define S5KJN1_TEST_PATTERN_DISABLE 0x0
87
88 #define S5KJN1_REG_VTS 0x0340
89
90 #define REG_NULL 0xFFFF
91 #define DELAY_MS 0xEEEE /* Array delay token */
92
93 #define S5KJN1_REG_VALUE_08BIT 1
94 #define S5KJN1_REG_VALUE_16BIT 2
95 #define S5KJN1_REG_VALUE_24BIT 3
96
97 #define S5KJN1_LANES 4
98
99 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
100 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
101
102 #define S5KJN1_NAME "s5kjn1"
103
104 static const char * const s5kjn1_supply_names[] = {
105 "dovdd", /* Digital I/O power */
106 "dvdd", /* Digital core power */
107 "avdd", /* Analog power */
108 };
109
110 #define S5KJN1_NUM_SUPPLIES ARRAY_SIZE(s5kjn1_supply_names)
111
112 struct regval {
113 u16 addr;
114 u16 val;
115 };
116
117 struct other_data {
118 u32 width;
119 u32 height;
120 u32 bus_fmt;
121 u32 data_type;
122 u32 data_bit;
123 };
124
125 struct s5kjn1_mode {
126 u32 bus_fmt;
127 u32 width;
128 u32 height;
129 struct v4l2_fract max_fps;
130 u32 hts_def;
131 u32 vts_def;
132 u32 exp_def;
133 u32 mipi_freq_idx;
134 u32 bpp;
135 const struct regval *reg_list;
136 u32 hdr_mode;
137 const struct other_data *spd;
138 u32 vc[PAD_MAX];
139 };
140
141 struct s5kjn1 {
142 struct i2c_client *client;
143 struct clk *xvclk;
144 struct gpio_desc *reset_gpio;
145 struct gpio_desc *pwdn_gpio;
146 struct regulator_bulk_data supplies[S5KJN1_NUM_SUPPLIES];
147
148 struct pinctrl *pinctrl;
149 struct pinctrl_state *pins_default;
150 struct pinctrl_state *pins_sleep;
151
152 struct v4l2_subdev subdev;
153 struct media_pad pad;
154 struct v4l2_ctrl_handler ctrl_handler;
155 struct v4l2_ctrl *exposure;
156 struct v4l2_ctrl *anal_gain;
157 struct v4l2_ctrl *digi_gain;
158 struct v4l2_ctrl *hblank;
159 struct v4l2_ctrl *vblank;
160 struct v4l2_ctrl *test_pattern;
161 struct v4l2_ctrl *pixel_rate;
162 struct v4l2_ctrl *link_freq;
163 struct v4l2_ctrl *h_flip;
164 struct v4l2_ctrl *v_flip;
165 struct mutex mutex;
166 bool streaming;
167 bool power_on;
168 const struct s5kjn1_mode *cur_mode;
169 const struct s5kjn1_mode *support_modes;
170 u32 cfg_num;
171 u32 module_index;
172 const char *module_facing;
173 const char *module_name;
174 const char *len_name;
175 struct v4l2_fwnode_endpoint bus_cfg;
176 bool is_thunderboot;
177 bool is_thunderboot_ng;
178 bool is_first_streamoff;
179 struct otp_info *otp;
180 u32 spd_id;
181 };
182
183 #define to_s5kjn1(sd) container_of(sd, struct s5kjn1, subdev)
184
185 static const struct regval s5kjn1_10bit_4080x3072_dphy_30fps_regs[] = {
186 {0x6028, 0x4000}, // Page pointer HW
187 {0x0000, 0x0003}, // Setfile Version
188 {0x0000, 0x38E1}, // JN1( Sensor ID)
189 {0x001E, 0x0007}, // V07
190
191 {0x6028, 0x4000}, // Init setting
192 {0x6010, 0x0001},
193 {DELAY_MS, 5}, //Delay 5ms
194 {0x6226, 0x0001},
195 {DELAY_MS, 10}, //Delay 10ms
196
197 {0x6028, 0x2400}, //Global, Analog setting
198 {0x602A, 0x1354},
199 {0x6F12, 0x0100},
200 {0x6F12, 0x7017},
201 {0x602A, 0x13B2},
202 {0x6F12, 0x0000},
203 {0x602A, 0x1236},
204 {0x6F12, 0x0000},
205 {0x602A, 0x1A0A},
206 {0x6F12, 0x4C0A},
207 {0x602A, 0x2210},
208 {0x6F12, 0x3401},
209 {0x602A, 0x2176},
210 {0x6F12, 0x6400},
211 {0x602A, 0x222E},
212 {0x6F12, 0x0001},
213 {0x602A, 0x06B6},
214 {0x6F12, 0x0A00},
215 {0x602A, 0x06BC},
216 {0x6F12, 0x1001},
217 {0x602A, 0x2140},
218 {0x6F12, 0x0101},
219 {0x602A, 0x1A0E},
220 {0x6F12, 0x9600},
221 {0x6028, 0x4000},
222 {0xF44E, 0x0011},
223 {0xF44C, 0x0B0B},
224 {0xF44A, 0x0006},
225 {0x0118, 0x0002},
226 {0x011A, 0x0001},
227
228 {0x6028, 0x2400}, // Mode setting
229 {0x602A, 0x1A28},
230 {0x6F12, 0x4C00},
231 {0x602A, 0x065A},
232 {0x6F12, 0x0000},
233 {0x602A, 0x139E},
234 {0x6F12, 0x0100},
235 {0x602A, 0x139C},
236 {0x6F12, 0x0000},
237 {0x602A, 0x13A0},
238 {0x6F12, 0x0A00},
239 {0x6F12, 0x0120},
240 {0x602A, 0x2072},
241 {0x6F12, 0x0000},
242 {0x602A, 0x1A64},
243 {0x6F12, 0x0301},
244 {0x6F12, 0xFF00},
245 {0x602A, 0x19E6},
246 {0x6F12, 0x0200},
247 {0x602A, 0x1A30},
248 {0x6F12, 0x3401},
249 {0x602A, 0x19FC},
250 {0x6F12, 0x0B00},
251 {0x602A, 0x19F4},
252 {0x6F12, 0x0606},
253 {0x602A, 0x19F8},
254 {0x6F12, 0x1010},
255 {0x602A, 0x1B26},
256 {0x6F12, 0x6F80},
257 {0x6F12, 0xA060},
258 {0x602A, 0x1A3C},
259 {0x6F12, 0x6207},
260 {0x602A, 0x1A48},
261 {0x6F12, 0x6207},
262 {0x602A, 0x1444},
263 {0x6F12, 0x2000},
264 {0x6F12, 0x2000},
265 {0x602A, 0x144C},
266 {0x6F12, 0x3F00},
267 {0x6F12, 0x3F00},
268 {0x602A, 0x7F6C},
269 {0x6F12, 0x0100},
270 {0x6F12, 0x2F00},
271 {0x6F12, 0xFA00},
272 {0x6F12, 0x2400},
273 {0x6F12, 0xE500},
274 {0x602A, 0x0650},
275 {0x6F12, 0x0600},
276 {0x602A, 0x0654},
277 {0x6F12, 0x0000},
278 {0x602A, 0x1A46},
279 {0x6F12, 0x8A00},
280 {0x602A, 0x1A52},
281 {0x6F12, 0xBF00},
282 {0x602A, 0x0674},
283 {0x6F12, 0x0500},
284 {0x6F12, 0x0500},
285 {0x6F12, 0x0500},
286 {0x6F12, 0x0500},
287 {0x602A, 0x0668},
288 {0x6F12, 0x0800},
289 {0x6F12, 0x0800},
290 {0x6F12, 0x0800},
291 {0x6F12, 0x0800},
292 {0x602A, 0x0684},
293 {0x6F12, 0x4001},
294 {0x602A, 0x0688},
295 {0x6F12, 0x4001},
296 {0x602A, 0x147C},
297 {0x6F12, 0x1000},
298 {0x602A, 0x1480},
299 {0x6F12, 0x1000},
300 {0x602A, 0x19F6},
301 {0x6F12, 0x0904},
302 {0x602A, 0x0812},
303 {0x6F12, 0x0000},
304 {0x602A, 0x1A02},
305 {0x6F12, 0x1800},
306 {0x602A, 0x2148},
307 {0x6F12, 0x0100},
308 {0x602A, 0x2042},
309 {0x6F12, 0x1A00},
310 {0x602A, 0x0874},
311 {0x6F12, 0x0100},
312 {0x602A, 0x09C0},
313 {0x6F12, 0x2008},
314 {0x602A, 0x09C4},
315 {0x6F12, 0x2000},
316 {0x602A, 0x19FE},
317 {0x6F12, 0x0E1C},
318 {0x602A, 0x4D92},
319 {0x6F12, 0x0100},
320 {0x602A, 0x84C8},
321 {0x6F12, 0x0100},
322 {0x602A, 0x4D94},
323 {0x6F12, 0x0005},
324 {0x6F12, 0x000A},
325 {0x6F12, 0x0010},
326 {0x6F12, 0x0810},
327 {0x6F12, 0x000A},
328 {0x6F12, 0x0040},
329 {0x6F12, 0x0810},
330 {0x6F12, 0x0810},
331 {0x6F12, 0x8002},
332 {0x6F12, 0xFD03},
333 {0x6F12, 0x0010},
334 {0x6F12, 0x1510},
335 {0x602A, 0x3570},
336 {0x6F12, 0x0000},
337 {0x602A, 0x3574},
338 {0x6F12, 0x1201},
339 {0x602A, 0x21E4},
340 {0x6F12, 0x0400},
341 {0x602A, 0x21EC},
342 {0x6F12, 0x1F04},
343 {0x602A, 0x2080},
344 {0x6F12, 0x0101},
345 {0x6F12, 0xFF00},
346 {0x6F12, 0x7F01},
347 {0x6F12, 0x0001},
348 {0x6F12, 0x8001},
349 {0x6F12, 0xD244},
350 {0x6F12, 0xD244},
351 {0x6F12, 0x14F4},
352 {0x6F12, 0x0000},
353 {0x6F12, 0x0000},
354 {0x6F12, 0x0000},
355 {0x602A, 0x20BA},
356 {0x6F12, 0x141C},
357 {0x6F12, 0x111C},
358 {0x6F12, 0x54F4},
359 {0x602A, 0x120E},
360 {0x6F12, 0x1000},
361 {0x602A, 0x212E},
362 {0x6F12, 0x0200},
363 {0x602A, 0x13AE},
364 {0x6F12, 0x0101},
365 {0x602A, 0x0718},
366 {0x6F12, 0x0001},
367 {0x602A, 0x0710},
368 {0x6F12, 0x0002},
369 {0x6F12, 0x0804},
370 {0x6F12, 0x0100},
371 {0x602A, 0x1B5C},
372 {0x6F12, 0x0000},
373 {0x602A, 0x0786},
374 {0x6F12, 0x7701},
375 {0x602A, 0x2022},
376 {0x6F12, 0x0500},
377 {0x6F12, 0x0500},
378 {0x602A, 0x1360},
379 {0x6F12, 0x0100},
380 {0x602A, 0x1376},
381 {0x6F12, 0x0100},
382 {0x6F12, 0x6038},
383 {0x6F12, 0x7038},
384 {0x6F12, 0x8038},
385 {0x602A, 0x1386},
386 {0x6F12, 0x0B00},
387 {0x602A, 0x06FA},
388 {0x6F12, 0x1000},
389 {0x602A, 0x4A94},
390 {0x6F12, 0x0900},
391 {0x6F12, 0x0000},
392 {0x6F12, 0x0300},
393 {0x6F12, 0x0000},
394 {0x6F12, 0x0000},
395 {0x6F12, 0x0000},
396 {0x6F12, 0x0000},
397 {0x6F12, 0x0000},
398 {0x6F12, 0x0300},
399 {0x6F12, 0x0000},
400 {0x6F12, 0x0900},
401 {0x6F12, 0x0000},
402 {0x6F12, 0x0000},
403 {0x6F12, 0x0000},
404 {0x6F12, 0x0000},
405 {0x6F12, 0x0000},
406 {0x602A, 0x0A76},
407 {0x6F12, 0x1000},
408 {0x602A, 0x0AEE},
409 {0x6F12, 0x1000},
410 {0x602A, 0x0B66},
411 {0x6F12, 0x1000},
412 {0x602A, 0x0BDE},
413 {0x6F12, 0x1000},
414 {0x602A, 0x0BE8},
415 {0x6F12, 0x3000},
416 {0x6F12, 0x3000},
417 {0x602A, 0x0C56},
418 {0x6F12, 0x1000},
419 {0x602A, 0x0C60},
420 {0x6F12, 0x3000},
421 {0x6F12, 0x3000},
422 {0x602A, 0x0CB6},
423 {0x6F12, 0x0100},
424 {0x602A, 0x0CF2},
425 {0x6F12, 0x0001},
426 {0x602A, 0x0CF0},
427 {0x6F12, 0x0101},
428 {0x602A, 0x11B8},
429 {0x6F12, 0x0100},
430 {0x602A, 0x11F6},
431 {0x6F12, 0x0020},
432 {0x602A, 0x4A74},
433 {0x6F12, 0x0000},
434 {0x6F12, 0x0000},
435 {0x6F12, 0xD8FF},
436 {0x6F12, 0x0000},
437 {0x6F12, 0x0000},
438 {0x6F12, 0x0000},
439 {0x6F12, 0x0000},
440 {0x6F12, 0x0000},
441 {0x6F12, 0xD8FF},
442 {0x6F12, 0x0000},
443 {0x6F12, 0x0000},
444 {0x6F12, 0x0000},
445 {0x6F12, 0x0000},
446 {0x6F12, 0x0000},
447 {0x6F12, 0x0000},
448 {0x6F12, 0x0000},
449 {0x602A, 0x218E},
450 {0x6F12, 0x0000},
451 {0x602A, 0x2268},
452 {0x6F12, 0xF279},
453 {0x602A, 0x5006},
454 {0x6F12, 0x0000},
455 {0x602A, 0x500E},
456 {0x6F12, 0x0100},
457 {0x602A, 0x4E70},
458 {0x6F12, 0x2062},
459 {0x6F12, 0x5501},
460 {0x602A, 0x06DC},
461 {0x6F12, 0x0000},
462 {0x6F12, 0x0000},
463 {0x6F12, 0x0000},
464 {0x6F12, 0x0000},
465 {0x6028, 0x4000},
466 {0xF46A, 0xAE80},
467 {0x0344, 0x0000}, //x_addr_start
468 {0x0346, 0x0000}, //y_addr_start
469 {0x0348, 0x1FFF}, //x_addr_end
470 {0x034A, 0x181F}, //y_addr_end
471 {0x034C, 0x0FF0}, //output width
472 {0x034E, 0x0C00}, //output height
473 {0x0350, 0x0008},
474 {0x0352, 0x0008},
475 {0x0900, 0x0122},
476 {0x0380, 0x0002},
477 {0x0382, 0x0002},
478 {0x0384, 0x0002},
479 {0x0386, 0x0002},
480 {0x0110, 0x1002},
481 {0x0114, 0x0301},
482 {0x0116, 0x3000},
483 {0x0136, 0x1800},
484 {0x013E, 0x0000},
485 {0x0300, 0x0006},
486 {0x0302, 0x0001},
487 {0x0304, 0x0004},
488 {0x0306, 0x008C},
489 {0x0308, 0x0008},
490 {0x030A, 0x0001},
491 {0x030C, 0x0000},
492 {0x030E, 0x0004},
493 {0x0310, 0x008A},
494 {0x0312, 0x0000},
495 {0x080E, 0x0000},
496 {0x0340, 0x0FD6},
497 {0x0342, 0x11E8},
498 {0x0702, 0x0000},
499 {0x0202, 0x0f00},
500 {0x0200, 0x0100},
501 {0x0D00, 0x0101},
502 {0x0D02, 0x0101},
503 {0x0D04, 0x0102},
504 {0x6226, 0x0000},
505
506 //{0x0100, 0x0100}, // Streaming on
507 {REG_NULL, 0x00},
508 };
509
510 /* Attention: only support Tetra-Bayer pattern output*/
511 static const struct regval s5kjn1_10bit_8128x6144_dphy_10fps_regs[] = {
512 {0x6028, 0x4000}, // Page pointer HW
513 {0x0000, 0x0003}, // Setfile Version
514 {0x0000, 0x38E1}, // JN1( Sensor ID)
515 {0x001E, 0x0007}, // V07
516
517 {0x6028, 0x4000}, // Init setting
518 {0x6010, 0x0001},
519 {DELAY_MS, 5}, //Delay 5ms
520 {0x6226, 0x0001},
521 {DELAY_MS, 10}, //Delay 10ms
522 {0x6028, 0x2400}, //Global, Analog setting
523 {0x11d2, 0x00FF}, //Global, Analog setting
524
525 {0x602A, 0x1354},
526 {0x6F12, 0x0100},
527 {0x6F12, 0x7017},
528 {0x602A, 0x13B2},
529 {0x6F12, 0x0000},
530 {0x602A, 0x1236},
531 {0x6F12, 0x0000},
532 {0x602A, 0x1A0A},
533 {0x6F12, 0x4C0A},
534 {0x602A, 0x2210},
535 {0x6F12, 0x3401},
536 {0x602A, 0x2176},
537 {0x6F12, 0x6400},
538 {0x602A, 0x222E},
539 {0x6F12, 0x0001},
540 {0x602A, 0x06B6},
541 {0x6F12, 0x0A00},
542 {0x602A, 0x06BC},
543 {0x6F12, 0x1001},
544 {0x602A, 0x2140},
545 {0x6F12, 0x0101},
546 {0x602A, 0x1A0E},
547 {0x6F12, 0x9600},
548 {0x6028, 0x4000},
549 {0xF44E, 0x0011},
550 {0xF44C, 0x0B0B},
551 {0xF44A, 0x0006},
552 {0x0118, 0x0002},
553 {0x011A, 0x0001},
554
555 {0x6028, 0x2400}, // Mode setting
556 {0x602A, 0x1A28},
557 {0x6F12, 0x4C00},
558 {0x602A, 0x065A},
559 {0x6F12, 0x0000},
560 {0x602A, 0x139E},
561 {0x6F12, 0x0400},
562 {0x602A, 0x139C},
563 {0x6F12, 0x0100},
564 {0x602A, 0x13A0},
565 {0x6F12, 0x0500},
566 {0x6F12, 0x0120},
567 {0x602A, 0x2072},
568 {0x6F12, 0x0101},
569 {0x602A, 0x1A64},
570 {0x6F12, 0x0001},
571 {0x6F12, 0x0000},
572 {0x602A, 0x19E6},
573 {0x6F12, 0x0200},
574 {0x602A, 0x1A30},
575 {0x6F12, 0x3403},
576 {0x602A, 0x19FC},
577 {0x6F12, 0x0700},
578 {0x602A, 0x19F4},
579 {0x6F12, 0x0707},
580 {0x602A, 0x19F8},
581 {0x6F12, 0x0B0B},
582 {0x602A, 0x1B26},
583 {0x6F12, 0x6F80},
584 {0x6F12, 0xA060},
585 {0x602A, 0x1A3C},
586 {0x6F12, 0x8207},
587 {0x602A, 0x1A48},
588 {0x6F12, 0x8207},
589 {0x602A, 0x1444},
590 {0x6F12, 0x2000},
591 {0x6F12, 0x2000},
592 {0x602A, 0x144C},
593 {0x6F12, 0x3F00},
594 {0x6F12, 0x3F00},
595 {0x602A, 0x7F6C},
596 {0x6F12, 0x0100},
597 {0x6F12, 0x2F00},
598 {0x6F12, 0xFA00},
599 {0x6F12, 0x2400},
600 {0x6F12, 0xE500},
601 {0x602A, 0x0650},
602 {0x6F12, 0x0600},
603 {0x602A, 0x0654},
604 {0x6F12, 0x0000},
605 {0x602A, 0x1A46},
606 {0x6F12, 0x8500},
607 {0x602A, 0x1A52},
608 {0x6F12, 0x9800},
609 {0x602A, 0x0674},
610 {0x6F12, 0x0500},
611 {0x6F12, 0x0500},
612 {0x6F12, 0x0500},
613 {0x6F12, 0x0500},
614 {0x602A, 0x0668},
615 {0x6F12, 0x0800},
616 {0x6F12, 0x0800},
617 {0x6F12, 0x0800},
618 {0x6F12, 0x0800},
619 {0x602A, 0x0684},
620 {0x6F12, 0x4001},
621 {0x602A, 0x0688},
622 {0x6F12, 0x4001},
623 {0x602A, 0x147C},
624 {0x6F12, 0x0400},
625 {0x602A, 0x1480},
626 {0x6F12, 0x0400},
627 {0x602A, 0x19F6},
628 {0x6F12, 0x0404},
629 {0x602A, 0x0812},
630 {0x6F12, 0x0000},
631 {0x602A, 0x1A02},
632 {0x6F12, 0x1800},
633 {0x602A, 0x2148},
634 {0x6F12, 0x0100},
635 {0x602A, 0x2042},
636 {0x6F12, 0x1A00},
637 {0x602A, 0x0874},
638 {0x6F12, 0x0106},
639 {0x602A, 0x09C0},
640 {0x6F12, 0x4000},
641 {0x602A, 0x09C4},
642 {0x6F12, 0x4000},
643 {0x602A, 0x19FE},
644 {0x6F12, 0x0C1C},
645 {0x602A, 0x4D92},
646 {0x6F12, 0x0000},
647 {0x602A, 0x84C8},
648 {0x6F12, 0x0000},
649 {0x602A, 0x4D94},
650 {0x6F12, 0x0000},
651 {0x6F12, 0x0000},
652 {0x6F12, 0x0000},
653 {0x6F12, 0x0000},
654 {0x6F12, 0x0000},
655 {0x6F12, 0x0000},
656 {0x6F12, 0x0000},
657 {0x6F12, 0x0000},
658 {0x6F12, 0x0000},
659 {0x6F12, 0x0000},
660 {0x6F12, 0x0000},
661 {0x6F12, 0x0000},
662 {0x602A, 0x3570},
663 {0x6F12, 0x0000},
664 {0x602A, 0x3574},
665 {0x6F12, 0x7306},
666 {0x602A, 0x21E4},
667 {0x6F12, 0x0400},
668 {0x602A, 0x21EC},
669 {0x6F12, 0x6902},
670 {0x602A, 0x2080},
671 {0x6F12, 0x0100},
672 {0x6F12, 0xFF00},
673 {0x6F12, 0x0002},
674 {0x6F12, 0x0001},
675 {0x6F12, 0x0002},
676 {0x6F12, 0xD244},
677 {0x6F12, 0xD244},
678 {0x6F12, 0x14F4},
679 {0x6F12, 0x101C},
680 {0x6F12, 0x0D1C},
681 {0x6F12, 0x54F4},
682 {0x602A, 0x20BA},
683 {0x6F12, 0x0000},
684 {0x6F12, 0x0000},
685 {0x6F12, 0x0000},
686 {0x602A, 0x120E},
687 {0x6F12, 0x1000},
688 {0x602A, 0x212E},
689 {0x6F12, 0x0200},
690 {0x602A, 0x13AE},
691 {0x6F12, 0x0100},
692 {0x602A, 0x0718},
693 {0x6F12, 0x0000},
694 {0x602A, 0x0710},
695 {0x6F12, 0x0010},
696 {0x6F12, 0x0201},
697 {0x6F12, 0x0800},
698 {0x602A, 0x1B5C},
699 {0x6F12, 0x0000},
700 {0x602A, 0x0786},
701 {0x6F12, 0x1401},
702 {0x602A, 0x2022},
703 {0x6F12, 0x0500},
704 {0x6F12, 0x0500},
705 {0x602A, 0x1360},
706 {0x6F12, 0x0000},
707 {0x602A, 0x1376},
708 {0x6F12, 0x0000},
709 {0x6F12, 0x6038},
710 {0x6F12, 0x7038},
711 {0x6F12, 0x8038},
712 {0x602A, 0x1386},
713 {0x6F12, 0x0B00},
714 {0x602A, 0x06FA},
715 {0x6F12, 0x1000},
716 {0x602A, 0x4A94},
717 {0x6F12, 0x0400},
718 {0x6F12, 0x0400},
719 {0x6F12, 0x0400},
720 {0x6F12, 0x0400},
721 {0x6F12, 0x0800},
722 {0x6F12, 0x0800},
723 {0x6F12, 0x0800},
724 {0x6F12, 0x0800},
725 {0x6F12, 0x0400},
726 {0x6F12, 0x0400},
727 {0x6F12, 0x0400},
728 {0x6F12, 0x0400},
729 {0x6F12, 0x0800},
730 {0x6F12, 0x0800},
731 {0x6F12, 0x0800},
732 {0x6F12, 0x0800},
733 {0x602A, 0x0A76},
734 {0x6F12, 0x1000},
735 {0x602A, 0x0AEE},
736 {0x6F12, 0x1000},
737 {0x602A, 0x0B66},
738 {0x6F12, 0x1000},
739 {0x602A, 0x0BDE},
740 {0x6F12, 0x1000},
741 {0x602A, 0x0BE8},
742 {0x6F12, 0x5000},
743 {0x6F12, 0x5000},
744 {0x602A, 0x0C56},
745 {0x6F12, 0x1000},
746 {0x602A, 0x0C60},
747 {0x6F12, 0x5000},
748 {0x6F12, 0x5000},
749 {0x602A, 0x0CB6},
750 {0x6F12, 0x0000},
751 {0x602A, 0x0CF2},
752 {0x6F12, 0x0001},
753 {0x602A, 0x0CF0},
754 {0x6F12, 0x0101},
755 {0x602A, 0x11B8},
756 {0x6F12, 0x0000},
757 {0x602A, 0x11F6},
758 {0x6F12, 0x0010},
759 {0x602A, 0x4A74},
760 {0x6F12, 0x0000},
761 {0x6F12, 0x0000},
762 {0x6F12, 0x0000},
763 {0x6F12, 0x0000},
764 {0x6F12, 0x0000},
765 {0x6F12, 0x0000},
766 {0x6F12, 0x0000},
767 {0x6F12, 0x0000},
768 {0x6F12, 0x0000},
769 {0x6F12, 0x0000},
770 {0x6F12, 0x0000},
771 {0x6F12, 0x0000},
772 {0x6F12, 0x0000},
773 {0x6F12, 0x0000},
774 {0x6F12, 0x0000},
775 {0x6F12, 0x0000},
776 {0x602A, 0x218E},
777 {0x6F12, 0x0000},
778 {0x602A, 0x2268},
779 {0x6F12, 0xF279},
780 {0x602A, 0x5006},
781 {0x6F12, 0x0000},
782 {0x602A, 0x500E},
783 {0x6F12, 0x0100},
784 {0x602A, 0x4E70},
785 {0x6F12, 0x2062},
786 {0x6F12, 0x5501},
787 {0x602A, 0x06DC},
788 {0x6F12, 0x0000},
789 {0x6F12, 0x0000},
790 {0x6F12, 0x0000},
791 {0x6F12, 0x0000},
792 {0x6028, 0x4000},
793 {0xF46A, 0xAE80},
794 {0x0344, 0x0000}, //x_addr_start
795 {0x0346, 0x0000}, //y_addr_start
796 {0x0348, 0x1FFF}, //x_addr_end
797 {0x034A, 0x181F}, //y_addr_end
798 {0x034C, 0x1FC0}, //output width
799 {0x034E, 0x1800}, //output height
800 {0x0350, 0x0010},
801 {0x0352, 0x0010},
802 {0x0900, 0x0111},
803 {0x0380, 0x0001},
804 {0x0382, 0x0001},
805 {0x0384, 0x0001},
806 {0x0386, 0x0001},
807 {0x0110, 0x1002},
808 {0x0114, 0x0300},
809 {0x0116, 0x3000},
810 {0x0136, 0x1800},
811 {0x013E, 0x0000},
812 {0x0300, 0x0006},
813 {0x0302, 0x0001},
814 {0x0304, 0x0004},
815 {0x0306, 0x008C},
816 {0x0308, 0x0008},
817 {0x030A, 0x0001},
818 {0x030C, 0x0000},
819 {0x030E, 0x0004},
820 {0x0310, 0x0074},
821 {0x0312, 0x0000},
822 {0x080E, 0x0000},
823 {0x0340, 0x1900},
824 {0x0342, 0x21F0},
825 {0x0702, 0x0000},
826 {0x0202, 0x1800},
827 {0x0200, 0x0100},
828 {0x0D00, 0x0100},
829 {0x0D02, 0x0001},
830 {0x0D04, 0x0002},
831 {0x6226, 0x0000},
832
833 {REG_NULL, 0x00},
834 };
835
836 static const struct other_data s5kjn1_spd = {
837 .width = 508,
838 .height = 3056,
839 .bus_fmt = MEDIA_BUS_FMT_SPD_2X8,
840 .data_type = 0x30,
841 .data_bit = 10,
842 };
843
844 /*
845 * The width and height must be configured to be
846 * the same as the current output resolution of the sensor.
847 * The input width of the isp needs to be 16 aligned.
848 * The input height of the isp needs to be 8 aligned.
849 * If the width or height does not meet the alignment rules,
850 * you can configure the cropping parameters with the following function to
851 * crop out the appropriate resolution.
852 * struct v4l2_subdev_pad_ops {
853 * .get_selection
854 * }
855 */
856 static const struct s5kjn1_mode supported_modes_dphy[] = {
857 {
858 .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
859 .width = 4080,
860 .height = 3072,
861 .max_fps = {
862 .numerator = 10000,
863 .denominator = 300000,
864 },
865 .exp_def = 0x0f00,
866 .hts_def = 0x11e8,
867 .vts_def = 0x0fd6,
868 .mipi_freq_idx = 1,
869 .bpp = 10,
870 .reg_list = s5kjn1_10bit_4080x3072_dphy_30fps_regs,
871 .hdr_mode = NO_HDR,
872 .spd = &s5kjn1_spd,
873 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
874 },
875 {
876 .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
877 .width = 8128,
878 .height = 6144,
879 .max_fps = {
880 .numerator = 10000,
881 .denominator = 100000,
882 },
883 .exp_def = 0x1800,
884 .hts_def = 0x21f0,
885 .vts_def = 0x1900,
886 .mipi_freq_idx = 0,
887 .bpp = 10,
888 .reg_list = s5kjn1_10bit_8128x6144_dphy_10fps_regs,
889 .hdr_mode = NO_HDR,
890 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
891 },
892 };
893
894 static const s64 link_freq_items[] = {
895 MIPI_FREQ_696M,
896 MIPI_FREQ_828M
897 };
898
899 static const char * const s5kjn1_test_pattern_menu[] = {
900 "Disabled",
901 "solid colour",
902 "100% colour bars",
903 "fade to grey colour bars",
904 "PN9"
905 };
906
907 static int __s5kjn1_power_on(struct s5kjn1 *s5kjn1);
908
909 /* Write registers up to 4 at a time */
s5kjn1_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)910 static int s5kjn1_write_reg(struct i2c_client *client, u16 reg,
911 u32 len, u32 val)
912 {
913 u32 buf_i, val_i;
914 u8 buf[6];
915 u8 *val_p;
916 __be32 val_be;
917
918 if (len > 4)
919 return -EINVAL;
920
921 buf[0] = reg >> 8;
922 buf[1] = reg & 0xff;
923
924 val_be = cpu_to_be32(val);
925 val_p = (u8 *)&val_be;
926 buf_i = 2;
927 val_i = 4 - len;
928
929 while (val_i < 4)
930 buf[buf_i++] = val_p[val_i++];
931
932 if (i2c_master_send(client, buf, len + 2) != len + 2) {
933 dev_err(&client->dev, "Failed to write 0x%04x,0x%x\n", reg, val);
934 return -EIO;
935 }
936 return 0;
937 }
938
s5kjn1_write_array(struct i2c_client * client,const struct regval * regs)939 static int s5kjn1_write_array(struct i2c_client *client,
940 const struct regval *regs)
941 {
942 int i, delay_ms, ret = 0;
943
944 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
945 if (regs[i].addr == DELAY_MS) {
946 delay_ms = regs[i].val;
947 dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
948 usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
949 continue;
950 }
951 ret = s5kjn1_write_reg(client, regs[i].addr,
952 S5KJN1_REG_VALUE_16BIT, regs[i].val);
953 if (ret)
954 dev_err(&client->dev, "%s failed !\n", __func__);
955 }
956 return ret;
957 }
958
959 /* Read registers up to 4 at a time */
s5kjn1_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)960 static int s5kjn1_read_reg(struct i2c_client *client,
961 u16 reg,
962 unsigned int len,
963 u32 *val)
964 {
965 struct i2c_msg msgs[2];
966 u8 *data_be_p;
967 __be32 data_be = 0;
968 __be16 reg_addr_be = cpu_to_be16(reg);
969 int ret;
970
971 if (len > 4 || !len)
972 return -EINVAL;
973
974 data_be_p = (u8 *)&data_be;
975 /* Write register address */
976 msgs[0].addr = client->addr;
977 msgs[0].flags = 0;
978 msgs[0].len = 2;
979 msgs[0].buf = (u8 *)®_addr_be;
980
981 /* Read data from register */
982 msgs[1].addr = client->addr;
983 msgs[1].flags = I2C_M_RD;
984 msgs[1].len = len;
985 msgs[1].buf = &data_be_p[4 - len];
986
987 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
988 if (ret != ARRAY_SIZE(msgs))
989 return -EIO;
990
991 *val = be32_to_cpu(data_be);
992
993 return 0;
994 }
995
996 /* Check Register value */
997 #ifdef CHECK_REG_VALUE
s5kjn1_reg_verify(struct i2c_client * client,const struct regval * regs)998 static int s5kjn1_reg_verify(struct i2c_client *client,
999 const struct regval *regs)
1000 {
1001 u32 i;
1002 int ret = 0;
1003 u32 value;
1004
1005 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
1006 if (regs[i].addr == 0x6028 && regs[i].val == 0x4000) {
1007 ret = s5kjn1_write_reg(client, regs[i].addr,
1008 S5KJN1_REG_VALUE_16BIT, regs[i].val);
1009 if (ret)
1010 dev_err(&client->dev, "%s failed !\n", __func__);
1011 continue;
1012 } else if (regs[i].addr == 0x6028 && regs[i].val == 0x2400) {
1013 ret = s5kjn1_write_reg(client, 0x602C,
1014 S5KJN1_REG_VALUE_16BIT, regs[i].val);
1015 if (ret)
1016 dev_err(&client->dev, "%s failed !\n", __func__);
1017 continue;
1018 } else if (regs[i].addr == 0x602A) {
1019 ret = s5kjn1_write_reg(client, 0x602E,
1020 S5KJN1_REG_VALUE_16BIT, regs[i].val);
1021 if (ret)
1022 dev_err(&client->dev, "%s failed !\n", __func__);
1023 continue;
1024 }
1025 ret = s5kjn1_read_reg(client, regs[i].addr,
1026 S5KJN1_REG_VALUE_16BIT, &value);
1027 if (value != regs[i].val) {
1028 dev_info(&client->dev, "%s: 0x%04x is 0x%x instead of 0x%x\n",
1029 __func__, regs[i].addr, value, regs[i].val);
1030 }
1031 }
1032 return ret;
1033 }
1034 #endif
1035
s5kjn1_get_reso_dist(const struct s5kjn1_mode * mode,struct v4l2_mbus_framefmt * framefmt)1036 static int s5kjn1_get_reso_dist(const struct s5kjn1_mode *mode,
1037 struct v4l2_mbus_framefmt *framefmt)
1038 {
1039 return abs(mode->width - framefmt->width) +
1040 abs(mode->height - framefmt->height);
1041 }
1042
1043 static const struct s5kjn1_mode *
s5kjn1_find_best_fit(struct s5kjn1 * s5kjn1,struct v4l2_subdev_format * fmt)1044 s5kjn1_find_best_fit(struct s5kjn1 *s5kjn1, struct v4l2_subdev_format *fmt)
1045 {
1046 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1047 int dist;
1048 int cur_best_fit = 0;
1049 int cur_best_fit_dist = -1;
1050 unsigned int i;
1051
1052 for (i = 0; i < s5kjn1->cfg_num; i++) {
1053 dist = s5kjn1_get_reso_dist(&s5kjn1->support_modes[i], framefmt);
1054 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
1055 (s5kjn1->support_modes[i].bus_fmt == framefmt->code)) {
1056 cur_best_fit_dist = dist;
1057 cur_best_fit = i;
1058 }
1059 }
1060 dev_info(&s5kjn1->client->dev, "%s: cur_best_fit(%d)",
1061 __func__, cur_best_fit);
1062 return &s5kjn1->support_modes[cur_best_fit];
1063 }
1064
s5kjn1_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1065 static int s5kjn1_set_fmt(struct v4l2_subdev *sd,
1066 struct v4l2_subdev_pad_config *cfg,
1067 struct v4l2_subdev_format *fmt)
1068 {
1069 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1070 const struct s5kjn1_mode *mode;
1071 s64 h_blank, vblank_def;
1072 u64 pixel_rate = 0;
1073 u32 lane_num = s5kjn1->bus_cfg.bus.mipi_csi2.num_data_lanes;
1074
1075 mutex_lock(&s5kjn1->mutex);
1076
1077 mode = s5kjn1_find_best_fit(s5kjn1, fmt);
1078 fmt->format.code = mode->bus_fmt;
1079 fmt->format.width = mode->width;
1080 fmt->format.height = mode->height;
1081 fmt->format.field = V4L2_FIELD_NONE;
1082 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1083 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1084 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1085 #else
1086 mutex_unlock(&s5kjn1->mutex);
1087 return -ENOTTY;
1088 #endif
1089 } else {
1090 s5kjn1->cur_mode = mode;
1091 h_blank = mode->hts_def - mode->width;
1092 __v4l2_ctrl_modify_range(s5kjn1->hblank, h_blank,
1093 h_blank, 1, h_blank);
1094 vblank_def = mode->vts_def - mode->height;
1095 __v4l2_ctrl_modify_range(s5kjn1->vblank, vblank_def,
1096 S5KJN1_VTS_MAX - mode->height,
1097 1, vblank_def);
1098 __v4l2_ctrl_s_ctrl(s5kjn1->vblank, vblank_def);
1099 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * lane_num;
1100 __v4l2_ctrl_s_ctrl_int64(s5kjn1->pixel_rate,
1101 pixel_rate);
1102 __v4l2_ctrl_s_ctrl(s5kjn1->link_freq,
1103 mode->mipi_freq_idx);
1104
1105 if (mode->width == 8128)
1106 __v4l2_ctrl_modify_range(s5kjn1->anal_gain, S5KJN1_GAIN_MIN,
1107 S5KJN1_FULL_SIZE_GAIN_MAX,
1108 S5KJN1_GAIN_STEP, S5KJN1_GAIN_DEFAULT);
1109 else
1110 __v4l2_ctrl_modify_range(s5kjn1->anal_gain, S5KJN1_GAIN_MIN,
1111 S5KJN1_GAIN_MAX,
1112 S5KJN1_GAIN_STEP, S5KJN1_GAIN_DEFAULT);
1113
1114 }
1115 dev_info(&s5kjn1->client->dev, "%s: mode->mipi_freq_idx(%d)",
1116 __func__, mode->mipi_freq_idx);
1117
1118 mutex_unlock(&s5kjn1->mutex);
1119
1120 return 0;
1121 }
1122
s5kjn1_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1123 static int s5kjn1_get_fmt(struct v4l2_subdev *sd,
1124 struct v4l2_subdev_pad_config *cfg,
1125 struct v4l2_subdev_format *fmt)
1126 {
1127 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1128 const struct s5kjn1_mode *mode = s5kjn1->cur_mode;
1129
1130 mutex_lock(&s5kjn1->mutex);
1131 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1132 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1133 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1134 #else
1135 mutex_unlock(&s5kjn1->mutex);
1136 return -ENOTTY;
1137 #endif
1138 } else {
1139 fmt->format.width = mode->width;
1140 fmt->format.height = mode->height;
1141 fmt->format.code = mode->bus_fmt;
1142 fmt->format.field = V4L2_FIELD_NONE;
1143 }
1144 mutex_unlock(&s5kjn1->mutex);
1145
1146 return 0;
1147 }
1148
s5kjn1_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1149 static int s5kjn1_enum_mbus_code(struct v4l2_subdev *sd,
1150 struct v4l2_subdev_pad_config *cfg,
1151 struct v4l2_subdev_mbus_code_enum *code)
1152 {
1153 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1154
1155 if (code->index != 0)
1156 return -EINVAL;
1157 code->code = s5kjn1->cur_mode->bus_fmt;
1158
1159 return 0;
1160 }
1161
s5kjn1_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1162 static int s5kjn1_enum_frame_sizes(struct v4l2_subdev *sd,
1163 struct v4l2_subdev_pad_config *cfg,
1164 struct v4l2_subdev_frame_size_enum *fse)
1165 {
1166 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1167
1168 if (fse->index >= s5kjn1->cfg_num)
1169 return -EINVAL;
1170
1171 if (fse->code != s5kjn1->support_modes[fse->index].bus_fmt)
1172 return -EINVAL;
1173
1174 fse->min_width = s5kjn1->support_modes[fse->index].width;
1175 fse->max_width = s5kjn1->support_modes[fse->index].width;
1176 fse->max_height = s5kjn1->support_modes[fse->index].height;
1177 fse->min_height = s5kjn1->support_modes[fse->index].height;
1178
1179 return 0;
1180 }
1181
s5kjn1_enable_test_pattern(struct s5kjn1 * s5kjn1,u32 pattern)1182 static int s5kjn1_enable_test_pattern(struct s5kjn1 *s5kjn1, u32 pattern)
1183 {
1184 u32 val;
1185 int ret = 0;
1186
1187 if (pattern)
1188 val = (pattern - 1) | S5KJN1_TEST_PATTERN_ENABLE;
1189 else
1190 val = S5KJN1_TEST_PATTERN_DISABLE;
1191 ret = s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_TEST_PATTERN,
1192 S5KJN1_REG_VALUE_08BIT, val);
1193 return ret;
1194 }
1195
s5kjn1_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1196 static int s5kjn1_g_frame_interval(struct v4l2_subdev *sd,
1197 struct v4l2_subdev_frame_interval *fi)
1198 {
1199 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1200 const struct s5kjn1_mode *mode = s5kjn1->cur_mode;
1201
1202 fi->interval = mode->max_fps;
1203
1204 return 0;
1205 }
1206
s5kjn1_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1207 static int s5kjn1_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1208 struct v4l2_mbus_config *config)
1209 {
1210 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1211 u32 lane_num = s5kjn1->bus_cfg.bus.mipi_csi2.num_data_lanes;
1212 u32 val = 0;
1213
1214 val = 1 << (lane_num - 1) |
1215 V4L2_MBUS_CSI2_CHANNEL_0 |
1216 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1217
1218 config->type = s5kjn1->bus_cfg.bus_type;
1219 config->flags = val;
1220
1221 return 0;
1222 }
1223
s5kjn1_get_otp(struct otp_info * otp,struct rkmodule_inf * inf)1224 static void s5kjn1_get_otp(struct otp_info *otp,
1225 struct rkmodule_inf *inf)
1226 {
1227 u32 i, j;
1228 u32 w, h;
1229
1230 /* awb */
1231 if (otp->awb_data.flag) {
1232 inf->awb.flag = 1;
1233 inf->awb.r_value = otp->awb_data.r_ratio;
1234 inf->awb.b_value = otp->awb_data.b_ratio;
1235 inf->awb.gr_value = otp->awb_data.g_ratio;
1236 inf->awb.gb_value = 0x0;
1237
1238 inf->awb.golden_r_value = otp->awb_data.r_golden;
1239 inf->awb.golden_b_value = otp->awb_data.b_golden;
1240 inf->awb.golden_gr_value = otp->awb_data.g_golden;
1241 inf->awb.golden_gb_value = 0x0;
1242 }
1243
1244 /* lsc */
1245 if (otp->lsc_data.flag) {
1246 inf->lsc.flag = 1;
1247 inf->lsc.width = otp->basic_data.size.width;
1248 inf->lsc.height = otp->basic_data.size.height;
1249 inf->lsc.table_size = otp->lsc_data.table_size;
1250
1251 for (i = 0; i < 289; i++) {
1252 inf->lsc.lsc_r[i] = (otp->lsc_data.data[i * 2] << 8) |
1253 otp->lsc_data.data[i * 2 + 1];
1254 inf->lsc.lsc_gr[i] = (otp->lsc_data.data[i * 2 + 578] << 8) |
1255 otp->lsc_data.data[i * 2 + 579];
1256 inf->lsc.lsc_gb[i] = (otp->lsc_data.data[i * 2 + 1156] << 8) |
1257 otp->lsc_data.data[i * 2 + 1157];
1258 inf->lsc.lsc_b[i] = (otp->lsc_data.data[i * 2 + 1734] << 8) |
1259 otp->lsc_data.data[i * 2 + 1735];
1260 }
1261 }
1262
1263 /* pdaf */
1264 if (otp->pdaf_data.flag) {
1265 inf->pdaf.flag = 1;
1266 inf->pdaf.gainmap_width = otp->pdaf_data.gainmap_width;
1267 inf->pdaf.gainmap_height = otp->pdaf_data.gainmap_height;
1268 inf->pdaf.dcc_mode = otp->pdaf_data.dcc_mode;
1269 inf->pdaf.dcc_dir = otp->pdaf_data.dcc_dir;
1270 inf->pdaf.dccmap_width = otp->pdaf_data.dccmap_width;
1271 inf->pdaf.dccmap_height = otp->pdaf_data.dccmap_height;
1272 w = otp->pdaf_data.gainmap_width;
1273 h = otp->pdaf_data.gainmap_height;
1274 for (i = 0; i < h; i++) {
1275 for (j = 0; j < w; j++) {
1276 inf->pdaf.gainmap[i * w + j] =
1277 (otp->pdaf_data.gainmap[(i * w + j) * 2] << 8) |
1278 otp->pdaf_data.gainmap[(i * w + j) * 2 + 1];
1279 }
1280 }
1281 w = otp->pdaf_data.dccmap_width;
1282 h = otp->pdaf_data.dccmap_height;
1283 for (i = 0; i < h; i++) {
1284 for (j = 0; j < w; j++) {
1285 inf->pdaf.dccmap[i * w + j] =
1286 (otp->pdaf_data.dccmap[(i * w + j) * 2] << 8) |
1287 otp->pdaf_data.dccmap[(i * w + j) * 2 + 1];
1288 }
1289 }
1290 }
1291
1292 /* af */
1293 if (otp->af_data.flag) {
1294 inf->af.flag = 1;
1295 inf->af.dir_cnt = 1;
1296 inf->af.af_otp[0].vcm_start = otp->af_data.af_inf;
1297 inf->af.af_otp[0].vcm_end = otp->af_data.af_macro;
1298 inf->af.af_otp[0].vcm_dir = 0;
1299 }
1300
1301 }
1302
s5kjn1_get_module_inf(struct s5kjn1 * s5kjn1,struct rkmodule_inf * inf)1303 static void s5kjn1_get_module_inf(struct s5kjn1 *s5kjn1,
1304 struct rkmodule_inf *inf)
1305 {
1306 struct otp_info *otp = s5kjn1->otp;
1307
1308 memset(inf, 0, sizeof(*inf));
1309 strscpy(inf->base.sensor, S5KJN1_NAME, sizeof(inf->base.sensor));
1310 strscpy(inf->base.module, s5kjn1->module_name,
1311 sizeof(inf->base.module));
1312 strscpy(inf->base.lens, s5kjn1->len_name, sizeof(inf->base.lens));
1313 if (otp)
1314 s5kjn1_get_otp(otp, inf);
1315 }
1316
s5kjn1_get_channel_info(struct s5kjn1 * s5kjn1,struct rkmodule_channel_info * ch_info)1317 static int s5kjn1_get_channel_info(struct s5kjn1 *s5kjn1, struct rkmodule_channel_info *ch_info)
1318 {
1319 const struct s5kjn1_mode *mode = s5kjn1->cur_mode;
1320
1321 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1322 return -EINVAL;
1323
1324 if (ch_info->index == s5kjn1->spd_id && mode->spd) {
1325 ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_1;
1326 ch_info->width = mode->spd->width;
1327 ch_info->height = mode->spd->height;
1328 ch_info->bus_fmt = mode->spd->bus_fmt;
1329 ch_info->data_type = mode->spd->data_type;
1330 ch_info->data_bit = mode->spd->data_bit;
1331 } else {
1332 ch_info->vc = s5kjn1->cur_mode->vc[ch_info->index];
1333 ch_info->width = s5kjn1->cur_mode->width;
1334 ch_info->height = s5kjn1->cur_mode->height;
1335 ch_info->bus_fmt = s5kjn1->cur_mode->bus_fmt;
1336 }
1337 return 0;
1338 }
1339
s5kjn1_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1340 static long s5kjn1_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1341 {
1342 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1343 struct rkmodule_hdr_cfg *hdr_cfg;
1344 struct rkmodule_channel_info *ch_info;
1345 long ret = 0;
1346 u32 i, h, w;
1347 u32 stream = 0;
1348
1349 switch (cmd) {
1350 case RKMODULE_SET_HDR_CFG:
1351 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1352 w = s5kjn1->cur_mode->width;
1353 h = s5kjn1->cur_mode->height;
1354 for (i = 0; i < s5kjn1->cfg_num; i++) {
1355 if (w == s5kjn1->support_modes[i].width &&
1356 h == s5kjn1->support_modes[i].height &&
1357 s5kjn1->support_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1358 s5kjn1->cur_mode = &s5kjn1->support_modes[i];
1359 break;
1360 }
1361 }
1362 if (i == s5kjn1->cfg_num) {
1363 dev_err(&s5kjn1->client->dev,
1364 "not find hdr mode:%d %dx%d config\n",
1365 hdr_cfg->hdr_mode, w, h);
1366 ret = -EINVAL;
1367 } else {
1368 w = s5kjn1->cur_mode->hts_def - s5kjn1->cur_mode->width;
1369 h = s5kjn1->cur_mode->vts_def - s5kjn1->cur_mode->height;
1370 __v4l2_ctrl_modify_range(s5kjn1->hblank, w, w, 1, w);
1371 __v4l2_ctrl_modify_range(s5kjn1->vblank, h,
1372 S5KJN1_VTS_MAX - s5kjn1->cur_mode->height,
1373 1, h);
1374 dev_info(&s5kjn1->client->dev,
1375 "sensor mode: %d\n",
1376 s5kjn1->cur_mode->hdr_mode);
1377 }
1378 dev_info(&s5kjn1->client->dev, "%s: matched mode index(%d)",
1379 __func__, i);
1380 break;
1381 case RKMODULE_GET_MODULE_INFO:
1382 s5kjn1_get_module_inf(s5kjn1, (struct rkmodule_inf *)arg);
1383 break;
1384 case RKMODULE_GET_HDR_CFG:
1385 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1386 hdr_cfg->esp.mode = HDR_NORMAL_VC;
1387 hdr_cfg->hdr_mode = s5kjn1->cur_mode->hdr_mode;
1388 break;
1389 case RKMODULE_SET_QUICK_STREAM:
1390
1391 stream = *((u32 *)arg);
1392
1393 if (stream)
1394 ret = s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_CTRL_MODE,
1395 S5KJN1_REG_VALUE_08BIT, S5KJN1_MODE_STREAMING);
1396 else
1397 ret = s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_CTRL_MODE,
1398 S5KJN1_REG_VALUE_08BIT, S5KJN1_MODE_SW_STANDBY);
1399 break;
1400 case RKMODULE_GET_CHANNEL_INFO:
1401 ch_info = (struct rkmodule_channel_info *)arg;
1402 ret = s5kjn1_get_channel_info(s5kjn1, ch_info);
1403 break;
1404 default:
1405 ret = -ENOIOCTLCMD;
1406 break;
1407 }
1408
1409 return ret;
1410 }
1411
1412 #ifdef CONFIG_COMPAT
s5kjn1_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1413 static long s5kjn1_compat_ioctl32(struct v4l2_subdev *sd,
1414 unsigned int cmd, unsigned long arg)
1415 {
1416 void __user *up = compat_ptr(arg);
1417 struct rkmodule_inf *inf;
1418 struct rkmodule_awb_cfg *cfg;
1419 struct rkmodule_hdr_cfg *hdr;
1420 struct rkmodule_channel_info *ch_info;
1421 long ret;
1422 u32 stream = 0;
1423
1424 switch (cmd) {
1425 case RKMODULE_GET_MODULE_INFO:
1426 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1427 if (!inf) {
1428 ret = -ENOMEM;
1429 return ret;
1430 }
1431
1432 ret = s5kjn1_ioctl(sd, cmd, inf);
1433 if (!ret) {
1434 ret = copy_to_user(up, inf, sizeof(*inf));
1435 if (ret)
1436 ret = -EFAULT;
1437 }
1438 kfree(inf);
1439 break;
1440 case RKMODULE_AWB_CFG:
1441 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1442 if (!cfg) {
1443 ret = -ENOMEM;
1444 return ret;
1445 }
1446
1447 ret = copy_from_user(cfg, up, sizeof(*cfg));
1448 if (!ret)
1449 ret = s5kjn1_ioctl(sd, cmd, cfg);
1450 else
1451 ret = -EFAULT;
1452 kfree(cfg);
1453 break;
1454 case RKMODULE_GET_HDR_CFG:
1455 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1456 if (!hdr) {
1457 ret = -ENOMEM;
1458 return ret;
1459 }
1460
1461 ret = s5kjn1_ioctl(sd, cmd, hdr);
1462 if (!ret) {
1463 ret = copy_to_user(up, hdr, sizeof(*hdr));
1464 if (ret)
1465 ret = -EFAULT;
1466 }
1467 kfree(hdr);
1468 break;
1469 case RKMODULE_SET_HDR_CFG:
1470 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1471 if (!hdr) {
1472 ret = -ENOMEM;
1473 return ret;
1474 }
1475
1476 ret = copy_from_user(hdr, up, sizeof(*hdr));
1477 if (!ret)
1478 ret = s5kjn1_ioctl(sd, cmd, hdr);
1479 else
1480 ret = -EFAULT;
1481 kfree(hdr);
1482 break;
1483 case RKMODULE_SET_QUICK_STREAM:
1484 ret = copy_from_user(&stream, up, sizeof(u32));
1485 if (!ret)
1486 ret = s5kjn1_ioctl(sd, cmd, &stream);
1487 else
1488 ret = -EFAULT;
1489 break;
1490 case RKMODULE_GET_CHANNEL_INFO:
1491 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1492 if (!ch_info) {
1493 ret = -ENOMEM;
1494 return ret;
1495 }
1496 ret = copy_from_user(ch_info, up, sizeof(*ch_info));
1497 if (!ret) {
1498 ret = s5kjn1_ioctl(sd, cmd, ch_info);
1499 if (!ret) {
1500 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1501 if (ret)
1502 ret = -EFAULT;
1503 }
1504 } else {
1505 ret = -EFAULT;
1506 }
1507 kfree(ch_info);
1508 break;
1509 default:
1510 ret = -ENOIOCTLCMD;
1511 break;
1512 }
1513
1514 return ret;
1515 }
1516 #endif
1517
__s5kjn1_start_stream(struct s5kjn1 * s5kjn1)1518 static int __s5kjn1_start_stream(struct s5kjn1 *s5kjn1)
1519 {
1520 int ret;
1521
1522 if (!s5kjn1->is_thunderboot) {
1523 ret = s5kjn1_write_array(s5kjn1->client, s5kjn1->cur_mode->reg_list);
1524 if (ret)
1525 return ret;
1526 }
1527
1528 #ifdef CHECK_REG_VALUE
1529 /* verify default values to make sure everything has */
1530 /* been written correctly as expected */
1531 dev_info(&s5kjn1->client->dev, "%s:Check register value!\n", __func__);
1532 ret = s5kjn1_reg_verify(s5kjn1->client, s5kjn1->cur_mode->reg_list);
1533 if (ret)
1534 return ret;
1535 #endif
1536 /* In case these controls are set before streaming */
1537 ret = __v4l2_ctrl_handler_setup(&s5kjn1->ctrl_handler);
1538 if (ret)
1539 return ret;
1540
1541 return s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_CTRL_MODE,
1542 S5KJN1_REG_VALUE_08BIT, S5KJN1_MODE_STREAMING);
1543 }
1544
__s5kjn1_stop_stream(struct s5kjn1 * s5kjn1)1545 static int __s5kjn1_stop_stream(struct s5kjn1 *s5kjn1)
1546 {
1547 if (s5kjn1->is_thunderboot)
1548 s5kjn1->is_first_streamoff = true;
1549 return s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_CTRL_MODE,
1550 S5KJN1_REG_VALUE_08BIT, S5KJN1_MODE_SW_STANDBY);
1551 }
1552
s5kjn1_s_stream(struct v4l2_subdev * sd,int on)1553 static int s5kjn1_s_stream(struct v4l2_subdev *sd, int on)
1554 {
1555 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1556 struct i2c_client *client = s5kjn1->client;
1557 int ret = 0;
1558
1559 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1560 s5kjn1->cur_mode->width,
1561 s5kjn1->cur_mode->height,
1562 DIV_ROUND_CLOSEST(s5kjn1->cur_mode->max_fps.denominator,
1563 s5kjn1->cur_mode->max_fps.numerator));
1564
1565 mutex_lock(&s5kjn1->mutex);
1566 on = !!on;
1567 if (on == s5kjn1->streaming)
1568 goto unlock_and_return;
1569
1570 if (on) {
1571 if (s5kjn1->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1572 s5kjn1->is_thunderboot = false;
1573 __s5kjn1_power_on(s5kjn1);
1574 }
1575 ret = pm_runtime_get_sync(&client->dev);
1576 if (ret < 0) {
1577 pm_runtime_put_noidle(&client->dev);
1578 goto unlock_and_return;
1579 }
1580
1581 ret = __s5kjn1_start_stream(s5kjn1);
1582 if (ret) {
1583 v4l2_err(sd, "start stream failed while write regs\n");
1584 pm_runtime_put(&client->dev);
1585 goto unlock_and_return;
1586 }
1587 } else {
1588 __s5kjn1_stop_stream(s5kjn1);
1589 pm_runtime_put(&client->dev);
1590 }
1591
1592 s5kjn1->streaming = on;
1593
1594 unlock_and_return:
1595 mutex_unlock(&s5kjn1->mutex);
1596
1597 return ret;
1598 }
1599
s5kjn1_s_power(struct v4l2_subdev * sd,int on)1600 static int s5kjn1_s_power(struct v4l2_subdev *sd, int on)
1601 {
1602 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1603 struct i2c_client *client = s5kjn1->client;
1604 int ret = 0;
1605
1606 mutex_lock(&s5kjn1->mutex);
1607
1608 /* If the power state is not modified - no work to do. */
1609 if (s5kjn1->power_on == !!on)
1610 goto unlock_and_return;
1611
1612 if (on) {
1613 ret = pm_runtime_get_sync(&client->dev);
1614 if (ret < 0) {
1615 pm_runtime_put_noidle(&client->dev);
1616 goto unlock_and_return;
1617 }
1618
1619 if (!s5kjn1->is_thunderboot) {
1620 ret |= s5kjn1_write_reg(s5kjn1->client,
1621 S5KJN1_SOFTWARE_RESET_REG,
1622 S5KJN1_REG_VALUE_08BIT,
1623 0x01);
1624 usleep_range(100, 200);
1625 }
1626
1627 s5kjn1->power_on = true;
1628 } else {
1629 pm_runtime_put(&client->dev);
1630 s5kjn1->power_on = false;
1631 }
1632
1633 unlock_and_return:
1634 mutex_unlock(&s5kjn1->mutex);
1635
1636 return ret;
1637 }
1638
1639 /* Calculate the delay in us by clock rate and clock cycles */
s5kjn1_cal_delay(u32 cycles)1640 static inline u32 s5kjn1_cal_delay(u32 cycles)
1641 {
1642 return DIV_ROUND_UP(cycles, S5KJN1_XVCLK_FREQ / 1000 / 1000);
1643 }
1644
s5kjn1_enable_regulators(struct s5kjn1 * s5kjn1,struct regulator_bulk_data * consumers)1645 static int s5kjn1_enable_regulators(struct s5kjn1 *s5kjn1,
1646 struct regulator_bulk_data *consumers)
1647 {
1648 int i, j;
1649 int ret = 0;
1650 struct device *dev = &s5kjn1->client->dev;
1651 int num_consumers = S5KJN1_NUM_SUPPLIES;
1652
1653 for (i = 0; i < num_consumers; i++) {
1654
1655 ret = regulator_enable(consumers[i].consumer);
1656 if (ret < 0) {
1657 dev_err(dev, "Failed to enable regulator: %s\n",
1658 consumers[i].supply);
1659 goto err;
1660 }
1661 }
1662 return 0;
1663 err:
1664 for (j = 0; j < i; j++)
1665 regulator_disable(consumers[j].consumer);
1666
1667 return ret;
1668 }
1669
__s5kjn1_power_on(struct s5kjn1 * s5kjn1)1670 static int __s5kjn1_power_on(struct s5kjn1 *s5kjn1)
1671 {
1672 int ret;
1673 u32 delay_us;
1674 struct device *dev = &s5kjn1->client->dev;
1675
1676 if (s5kjn1->is_thunderboot)
1677 return 0;
1678
1679 if (!IS_ERR_OR_NULL(s5kjn1->pins_default)) {
1680 ret = pinctrl_select_state(s5kjn1->pinctrl,
1681 s5kjn1->pins_default);
1682 if (ret < 0)
1683 dev_err(dev, "could not set pins\n");
1684 }
1685 ret = clk_set_rate(s5kjn1->xvclk, S5KJN1_XVCLK_FREQ);
1686 if (ret < 0)
1687 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1688 if (clk_get_rate(s5kjn1->xvclk) != S5KJN1_XVCLK_FREQ)
1689 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1690 ret = clk_prepare_enable(s5kjn1->xvclk);
1691 if (ret < 0) {
1692 dev_err(dev, "Failed to enable xvclk\n");
1693 return ret;
1694 }
1695 if (!IS_ERR(s5kjn1->reset_gpio))
1696 gpiod_direction_output(s5kjn1->reset_gpio, 0);
1697
1698 ret = s5kjn1_enable_regulators(s5kjn1, s5kjn1->supplies);
1699 if (ret < 0) {
1700 dev_err(dev, "Failed to enable regulators\n");
1701 goto disable_clk;
1702 }
1703
1704 if (!IS_ERR(s5kjn1->reset_gpio))
1705 gpiod_direction_output(s5kjn1->reset_gpio, 1);
1706
1707 usleep_range(500, 1000);
1708 if (!IS_ERR(s5kjn1->pwdn_gpio))
1709 gpiod_direction_output(s5kjn1->pwdn_gpio, 1);
1710 /*
1711 * There is no need to wait for the delay of RC circuit
1712 * if the reset signal is directly controlled by GPIO.
1713 */
1714 if (!IS_ERR(s5kjn1->reset_gpio))
1715 usleep_range(8000, 10000);
1716 else
1717 usleep_range(12000, 16000);
1718
1719 /* 8192 cycles prior to first SCCB transaction */
1720 delay_us = s5kjn1_cal_delay(8192);
1721 usleep_range(delay_us, delay_us * 2);
1722
1723 return 0;
1724
1725 disable_clk:
1726 clk_disable_unprepare(s5kjn1->xvclk);
1727
1728 return ret;
1729 }
1730
__s5kjn1_power_off(struct s5kjn1 * s5kjn1)1731 static void __s5kjn1_power_off(struct s5kjn1 *s5kjn1)
1732 {
1733 int ret;
1734 struct device *dev = &s5kjn1->client->dev;
1735
1736 if (s5kjn1->is_thunderboot) {
1737 if (s5kjn1->is_first_streamoff) {
1738 s5kjn1->is_thunderboot = false;
1739 s5kjn1->is_first_streamoff = false;
1740 } else {
1741 return;
1742 }
1743 }
1744
1745 if (!IS_ERR(s5kjn1->pwdn_gpio))
1746 gpiod_direction_output(s5kjn1->pwdn_gpio, 0);
1747
1748 clk_disable_unprepare(s5kjn1->xvclk);
1749
1750 if (!IS_ERR(s5kjn1->reset_gpio))
1751 gpiod_direction_output(s5kjn1->reset_gpio, 0);
1752 if (!IS_ERR_OR_NULL(s5kjn1->pins_sleep)) {
1753 ret = pinctrl_select_state(s5kjn1->pinctrl,
1754 s5kjn1->pins_sleep);
1755 if (ret < 0)
1756 dev_dbg(dev, "could not set pins\n");
1757 }
1758
1759 if (s5kjn1->is_thunderboot_ng)
1760 s5kjn1->is_thunderboot_ng = false;
1761
1762 regulator_bulk_disable(S5KJN1_NUM_SUPPLIES, s5kjn1->supplies);
1763 }
1764
s5kjn1_runtime_resume(struct device * dev)1765 static int __maybe_unused s5kjn1_runtime_resume(struct device *dev)
1766 {
1767 struct i2c_client *client = to_i2c_client(dev);
1768 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1769 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1770
1771 return __s5kjn1_power_on(s5kjn1);
1772 }
1773
s5kjn1_runtime_suspend(struct device * dev)1774 static int __maybe_unused s5kjn1_runtime_suspend(struct device *dev)
1775 {
1776 struct i2c_client *client = to_i2c_client(dev);
1777 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1778 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1779
1780 __s5kjn1_power_off(s5kjn1);
1781
1782 return 0;
1783 }
1784
1785 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
s5kjn1_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1786 static int s5kjn1_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1787 {
1788 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1789 struct v4l2_mbus_framefmt *try_fmt =
1790 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1791 const struct s5kjn1_mode *def_mode = &s5kjn1->support_modes[0];
1792
1793 mutex_lock(&s5kjn1->mutex);
1794 /* Initialize try_fmt */
1795 try_fmt->width = def_mode->width;
1796 try_fmt->height = def_mode->height;
1797 try_fmt->code = def_mode->bus_fmt;
1798 try_fmt->field = V4L2_FIELD_NONE;
1799
1800 mutex_unlock(&s5kjn1->mutex);
1801 /* No crop or compose */
1802
1803 return 0;
1804 }
1805 #endif
1806
s5kjn1_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1807 static int s5kjn1_enum_frame_interval(struct v4l2_subdev *sd,
1808 struct v4l2_subdev_pad_config *cfg,
1809 struct v4l2_subdev_frame_interval_enum *fie)
1810 {
1811 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1812
1813 if (fie->index >= s5kjn1->cfg_num)
1814 return -EINVAL;
1815
1816 fie->code = s5kjn1->support_modes[fie->index].bus_fmt;
1817 fie->width = s5kjn1->support_modes[fie->index].width;
1818 fie->height = s5kjn1->support_modes[fie->index].height;
1819 fie->interval = s5kjn1->support_modes[fie->index].max_fps;
1820 fie->reserved[0] = s5kjn1->support_modes[fie->index].hdr_mode;
1821 return 0;
1822 }
1823
1824 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1825 #define DST_WIDTH 4064
1826 #define DST_HEIGHT 3072
s5kjn1_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1827 static int s5kjn1_get_selection(struct v4l2_subdev *sd,
1828 struct v4l2_subdev_pad_config *cfg,
1829 struct v4l2_subdev_selection *sel)
1830 {
1831 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
1832
1833
1834 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1835 if (s5kjn1->cur_mode->width == 4080) {
1836 sel->r.left = CROP_START(s5kjn1->cur_mode->width, DST_WIDTH);
1837 sel->r.width = DST_WIDTH;
1838 sel->r.top = CROP_START(s5kjn1->cur_mode->height, DST_HEIGHT);
1839 sel->r.height = DST_HEIGHT;
1840 } else {
1841 sel->r.left = CROP_START(s5kjn1->cur_mode->width, s5kjn1->cur_mode->width);
1842 sel->r.width = s5kjn1->cur_mode->width;
1843 sel->r.top = CROP_START(s5kjn1->cur_mode->height, s5kjn1->cur_mode->height);
1844 sel->r.height = s5kjn1->cur_mode->height;
1845 }
1846 return 0;
1847 }
1848 return -EINVAL;
1849 }
1850
1851 static const struct dev_pm_ops s5kjn1_pm_ops = {
1852 SET_RUNTIME_PM_OPS(s5kjn1_runtime_suspend,
1853 s5kjn1_runtime_resume, NULL)
1854 };
1855
1856 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1857 static const struct v4l2_subdev_internal_ops s5kjn1_internal_ops = {
1858 .open = s5kjn1_open,
1859 };
1860 #endif
1861
1862 static const struct v4l2_subdev_core_ops s5kjn1_core_ops = {
1863 .s_power = s5kjn1_s_power,
1864 .ioctl = s5kjn1_ioctl,
1865 #ifdef CONFIG_COMPAT
1866 .compat_ioctl32 = s5kjn1_compat_ioctl32,
1867 #endif
1868 };
1869
1870 static const struct v4l2_subdev_video_ops s5kjn1_video_ops = {
1871 .s_stream = s5kjn1_s_stream,
1872 .g_frame_interval = s5kjn1_g_frame_interval,
1873 };
1874
1875 static const struct v4l2_subdev_pad_ops s5kjn1_pad_ops = {
1876 .enum_mbus_code = s5kjn1_enum_mbus_code,
1877 .enum_frame_size = s5kjn1_enum_frame_sizes,
1878 .enum_frame_interval = s5kjn1_enum_frame_interval,
1879 .get_fmt = s5kjn1_get_fmt,
1880 .set_fmt = s5kjn1_set_fmt,
1881 .get_selection = s5kjn1_get_selection,
1882 .get_mbus_config = s5kjn1_g_mbus_config,
1883 };
1884
1885 static const struct v4l2_subdev_ops s5kjn1_subdev_ops = {
1886 .core = &s5kjn1_core_ops,
1887 .video = &s5kjn1_video_ops,
1888 .pad = &s5kjn1_pad_ops,
1889 };
1890
s5kjn1_set_ctrl(struct v4l2_ctrl * ctrl)1891 static int s5kjn1_set_ctrl(struct v4l2_ctrl *ctrl)
1892 {
1893 struct s5kjn1 *s5kjn1 = container_of(ctrl->handler,
1894 struct s5kjn1, ctrl_handler);
1895 struct i2c_client *client = s5kjn1->client;
1896 s64 max;
1897 int ret = 0;
1898
1899 /* Propagate change of current control to all related controls */
1900 switch (ctrl->id) {
1901 case V4L2_CID_VBLANK:
1902 /* Update max exposure while meeting expected vblanking */
1903 max = s5kjn1->cur_mode->height + ctrl->val - 4;
1904 __v4l2_ctrl_modify_range(s5kjn1->exposure,
1905 s5kjn1->exposure->minimum, max,
1906 s5kjn1->exposure->step,
1907 s5kjn1->exposure->default_value);
1908 break;
1909 }
1910
1911 if (!pm_runtime_get_if_in_use(&client->dev))
1912 return 0;
1913
1914 switch (ctrl->id) {
1915 case V4L2_CID_EXPOSURE:
1916 ret = s5kjn1_write_reg(s5kjn1->client,
1917 S5KJN1_REG_EXP_LONG_H,
1918 S5KJN1_REG_VALUE_16BIT,
1919 ctrl->val);
1920 dev_dbg(&client->dev, "set exposure 0x%x\n",
1921 ctrl->val);
1922 break;
1923 case V4L2_CID_ANALOGUE_GAIN:
1924 ret = s5kjn1_write_reg(s5kjn1->client,
1925 S5KJN1_REG_AGAIN_LONG_H,
1926 S5KJN1_REG_VALUE_16BIT,
1927 ctrl->val);
1928 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1929 ctrl->val);
1930 break;
1931 case V4L2_CID_VBLANK:
1932 ret = s5kjn1_write_reg(s5kjn1->client, S5KJN1_REG_VTS,
1933 S5KJN1_REG_VALUE_16BIT,
1934 ctrl->val + s5kjn1->cur_mode->height);
1935 dev_dbg(&client->dev, "set vblank 0x%x\n",
1936 ctrl->val);
1937 break;
1938 case V4L2_CID_TEST_PATTERN:
1939 ret = s5kjn1_enable_test_pattern(s5kjn1, ctrl->val);
1940 break;
1941 default:
1942 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1943 __func__, ctrl->id, ctrl->val);
1944 break;
1945 }
1946
1947 pm_runtime_put(&client->dev);
1948
1949 return ret;
1950 }
1951
1952 static const struct v4l2_ctrl_ops s5kjn1_ctrl_ops = {
1953 .s_ctrl = s5kjn1_set_ctrl,
1954 };
1955
s5kjn1_initialize_controls(struct s5kjn1 * s5kjn1)1956 static int s5kjn1_initialize_controls(struct s5kjn1 *s5kjn1)
1957 {
1958 const struct s5kjn1_mode *mode;
1959 struct v4l2_ctrl_handler *handler;
1960 s64 exposure_max, vblank_def;
1961 u32 h_blank;
1962 int ret;
1963 u64 dst_pixel_rate = 0;
1964 u32 lane_num = s5kjn1->bus_cfg.bus.mipi_csi2.num_data_lanes;
1965
1966 handler = &s5kjn1->ctrl_handler;
1967 mode = s5kjn1->cur_mode;
1968 ret = v4l2_ctrl_handler_init(handler, 9);
1969 if (ret)
1970 return ret;
1971 handler->lock = &s5kjn1->mutex;
1972
1973 s5kjn1->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1974 V4L2_CID_LINK_FREQ,
1975 1, 0, link_freq_items);
1976
1977 dst_pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * lane_num;
1978 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1979 s5kjn1->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1980 V4L2_CID_PIXEL_RATE,
1981 0, PIXEL_RATE_WITH_828M,
1982 1, dst_pixel_rate);
1983
1984 __v4l2_ctrl_s_ctrl(s5kjn1->link_freq,
1985 mode->mipi_freq_idx);
1986
1987 h_blank = mode->hts_def - mode->width;
1988 s5kjn1->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1989 h_blank, h_blank, 1, h_blank);
1990 if (s5kjn1->hblank)
1991 s5kjn1->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1992
1993 vblank_def = mode->vts_def - mode->height;
1994 s5kjn1->vblank = v4l2_ctrl_new_std(handler, &s5kjn1_ctrl_ops,
1995 V4L2_CID_VBLANK, vblank_def,
1996 S5KJN1_VTS_MAX - mode->height,
1997 1, vblank_def);
1998 if (mode->height == 6144)
1999 exposure_max = mode->vts_def - 44;
2000 else
2001 exposure_max = mode->vts_def - 22;
2002
2003 s5kjn1->exposure = v4l2_ctrl_new_std(handler, &s5kjn1_ctrl_ops,
2004 V4L2_CID_EXPOSURE, S5KJN1_EXPOSURE_MIN,
2005 exposure_max, S5KJN1_EXPOSURE_STEP,
2006 mode->exp_def);
2007
2008 s5kjn1->anal_gain = v4l2_ctrl_new_std(handler, &s5kjn1_ctrl_ops,
2009 V4L2_CID_ANALOGUE_GAIN, S5KJN1_GAIN_MIN,
2010 S5KJN1_GAIN_MAX, S5KJN1_GAIN_STEP,
2011 S5KJN1_GAIN_DEFAULT);
2012
2013 s5kjn1->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
2014 &s5kjn1_ctrl_ops, V4L2_CID_TEST_PATTERN,
2015 ARRAY_SIZE(s5kjn1_test_pattern_menu) - 1,
2016 0, 0, s5kjn1_test_pattern_menu);
2017
2018 if (handler->error) {
2019 ret = handler->error;
2020 dev_err(&s5kjn1->client->dev,
2021 "Failed to init controls(%d)\n", ret);
2022 goto err_free_handler;
2023 }
2024
2025 s5kjn1->subdev.ctrl_handler = handler;
2026
2027 return 0;
2028
2029 err_free_handler:
2030 v4l2_ctrl_handler_free(handler);
2031
2032 return ret;
2033 }
2034
s5kjn1_check_sensor_id(struct s5kjn1 * s5kjn1,struct i2c_client * client)2035 static int s5kjn1_check_sensor_id(struct s5kjn1 *s5kjn1,
2036 struct i2c_client *client)
2037 {
2038 struct device *dev = &s5kjn1->client->dev;
2039 u32 id = 0;
2040 int ret;
2041
2042 if (s5kjn1->is_thunderboot) {
2043 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
2044 return 0;
2045 }
2046
2047 ret = s5kjn1_read_reg(client, S5KJN1_REG_CHIP_ID,
2048 S5KJN1_REG_VALUE_16BIT, &id);
2049 if (id != CHIP_ID) {
2050 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2051 return -ENODEV;
2052 }
2053
2054 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
2055
2056 return 0;
2057 }
2058
s5kjn1_configure_regulators(struct s5kjn1 * s5kjn1)2059 static int s5kjn1_configure_regulators(struct s5kjn1 *s5kjn1)
2060 {
2061 unsigned int i;
2062
2063 for (i = 0; i < S5KJN1_NUM_SUPPLIES; i++)
2064 s5kjn1->supplies[i].supply = s5kjn1_supply_names[i];
2065
2066 return devm_regulator_bulk_get(&s5kjn1->client->dev,
2067 S5KJN1_NUM_SUPPLIES,
2068 s5kjn1->supplies);
2069 }
2070
s5kjn1_probe(struct i2c_client * client,const struct i2c_device_id * id)2071 static int s5kjn1_probe(struct i2c_client *client,
2072 const struct i2c_device_id *id)
2073 {
2074 struct device *dev = &client->dev;
2075 struct device_node *node = dev->of_node;
2076 struct s5kjn1 *s5kjn1;
2077 struct v4l2_subdev *sd;
2078 char facing[2];
2079 int ret;
2080 struct device_node *endpoint;
2081 struct device_node *eeprom_ctrl_node;
2082 struct i2c_client *eeprom_ctrl_client;
2083 struct v4l2_subdev *eeprom_ctrl;
2084 struct otp_info *otp_ptr;
2085
2086 dev_info(dev, "driver version: %02x.%02x.%02x",
2087 DRIVER_VERSION >> 16,
2088 (DRIVER_VERSION & 0xff00) >> 8,
2089 DRIVER_VERSION & 0x00ff);
2090
2091 s5kjn1 = devm_kzalloc(dev, sizeof(*s5kjn1), GFP_KERNEL);
2092 if (!s5kjn1)
2093 return -ENOMEM;
2094
2095 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2096 &s5kjn1->module_index);
2097 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2098 &s5kjn1->module_facing);
2099 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2100 &s5kjn1->module_name);
2101 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2102 &s5kjn1->len_name);
2103 if (ret) {
2104 dev_err(dev, "could not get module information!\n");
2105 return -EINVAL;
2106 }
2107
2108 s5kjn1->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
2109
2110 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2111 if (!endpoint) {
2112 dev_err(dev, "Failed to get endpoint\n");
2113 return -EINVAL;
2114 }
2115 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
2116 &s5kjn1->bus_cfg);
2117 if (ret) {
2118 dev_err(dev, "Failed to parse endpoint!\n");
2119 return ret;
2120 }
2121 if (s5kjn1->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) {
2122 s5kjn1->support_modes = supported_modes_dphy;
2123 s5kjn1->cfg_num = ARRAY_SIZE(supported_modes_dphy);
2124 } else {
2125 dev_err(dev, "not support!\n");
2126 }
2127
2128 s5kjn1->client = client;
2129 s5kjn1->cur_mode = &s5kjn1->support_modes[0];
2130
2131 s5kjn1->xvclk = devm_clk_get(dev, "xvclk");
2132 if (IS_ERR(s5kjn1->xvclk)) {
2133 dev_err(dev, "Failed to get xvclk\n");
2134 return -EINVAL;
2135 }
2136
2137 s5kjn1->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
2138 if (IS_ERR(s5kjn1->reset_gpio))
2139 dev_warn(dev, "Failed to get reset-gpios\n");
2140
2141 s5kjn1->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
2142 if (IS_ERR(s5kjn1->pwdn_gpio))
2143 dev_warn(dev, "Failed to get pwdn-gpios\n");
2144
2145 ret = of_property_read_u32(node,
2146 "rockchip,spd-id",
2147 &s5kjn1->spd_id);
2148 if (ret != 0) {
2149 s5kjn1->spd_id = PAD_MAX;
2150 dev_err(dev,
2151 "failed get spd_id, will not to use spd\n");
2152 }
2153
2154 s5kjn1->pinctrl = devm_pinctrl_get(dev);
2155 if (!IS_ERR(s5kjn1->pinctrl)) {
2156 s5kjn1->pins_default =
2157 pinctrl_lookup_state(s5kjn1->pinctrl,
2158 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2159 if (IS_ERR(s5kjn1->pins_default))
2160 dev_err(dev, "could not get default pinstate\n");
2161
2162 s5kjn1->pins_sleep =
2163 pinctrl_lookup_state(s5kjn1->pinctrl,
2164 OF_CAMERA_PINCTRL_STATE_SLEEP);
2165 if (IS_ERR(s5kjn1->pins_sleep))
2166 dev_err(dev, "could not get sleep pinstate\n");
2167 } else {
2168 dev_err(dev, "no pinctrl\n");
2169 }
2170
2171 ret = s5kjn1_configure_regulators(s5kjn1);
2172 if (ret) {
2173 dev_err(dev, "Failed to get power regulators\n");
2174 return ret;
2175 }
2176
2177 mutex_init(&s5kjn1->mutex);
2178
2179 sd = &s5kjn1->subdev;
2180 v4l2_i2c_subdev_init(sd, client, &s5kjn1_subdev_ops);
2181 ret = s5kjn1_initialize_controls(s5kjn1);
2182 if (ret)
2183 goto err_destroy_mutex;
2184 ret = __s5kjn1_power_on(s5kjn1);
2185 if (ret)
2186 goto err_free_handler;
2187
2188 ret = s5kjn1_check_sensor_id(s5kjn1, client);
2189 if (ret)
2190 goto err_power_off;
2191 eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
2192 if (eeprom_ctrl_node) {
2193 eeprom_ctrl_client =
2194 of_find_i2c_device_by_node(eeprom_ctrl_node);
2195 of_node_put(eeprom_ctrl_node);
2196 if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
2197 dev_err(dev, "can not get node\n");
2198 goto continue_probe;
2199 }
2200 eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
2201 if (IS_ERR_OR_NULL(eeprom_ctrl)) {
2202 dev_err(dev, "can not get eeprom i2c client\n");
2203 } else {
2204 otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
2205 if (!otp_ptr)
2206 return -ENOMEM;
2207 ret = v4l2_subdev_call(eeprom_ctrl,
2208 core, ioctl, 0, otp_ptr);
2209 if (!ret) {
2210 s5kjn1->otp = otp_ptr;
2211 } else {
2212 s5kjn1->otp = NULL;
2213 devm_kfree(dev, otp_ptr);
2214 }
2215 }
2216 }
2217 continue_probe:
2218
2219 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2220 sd->internal_ops = &s5kjn1_internal_ops;
2221 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2222 #endif
2223 #if defined(CONFIG_MEDIA_CONTROLLER)
2224 s5kjn1->pad.flags = MEDIA_PAD_FL_SOURCE;
2225 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2226 ret = media_entity_pads_init(&sd->entity, 1, &s5kjn1->pad);
2227 if (ret < 0)
2228 goto err_power_off;
2229 #endif
2230
2231 memset(facing, 0, sizeof(facing));
2232 if (strcmp(s5kjn1->module_facing, "back") == 0)
2233 facing[0] = 'b';
2234 else
2235 facing[0] = 'f';
2236
2237 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2238 s5kjn1->module_index, facing,
2239 S5KJN1_NAME, dev_name(sd->dev));
2240 ret = v4l2_async_register_subdev_sensor_common(sd);
2241 if (ret) {
2242 dev_err(dev, "v4l2 async register subdev failed\n");
2243 goto err_clean_entity;
2244 }
2245
2246 pm_runtime_set_active(dev);
2247 pm_runtime_enable(dev);
2248 pm_runtime_idle(dev);
2249 return 0;
2250
2251 err_clean_entity:
2252 #if defined(CONFIG_MEDIA_CONTROLLER)
2253 media_entity_cleanup(&sd->entity);
2254 #endif
2255 err_power_off:
2256 __s5kjn1_power_off(s5kjn1);
2257 err_free_handler:
2258 v4l2_ctrl_handler_free(&s5kjn1->ctrl_handler);
2259 err_destroy_mutex:
2260 mutex_destroy(&s5kjn1->mutex);
2261
2262 return ret;
2263 }
2264
s5kjn1_remove(struct i2c_client * client)2265 static int s5kjn1_remove(struct i2c_client *client)
2266 {
2267 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2268 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
2269
2270 v4l2_async_unregister_subdev(sd);
2271 #if defined(CONFIG_MEDIA_CONTROLLER)
2272 media_entity_cleanup(&sd->entity);
2273 #endif
2274 v4l2_ctrl_handler_free(&s5kjn1->ctrl_handler);
2275 mutex_destroy(&s5kjn1->mutex);
2276
2277 pm_runtime_disable(&client->dev);
2278 if (!pm_runtime_status_suspended(&client->dev))
2279 __s5kjn1_power_off(s5kjn1);
2280 pm_runtime_set_suspended(&client->dev);
2281
2282 return 0;
2283 }
2284
2285 #if IS_ENABLED(CONFIG_OF)
2286 static const struct of_device_id s5kjn1_of_match[] = {
2287 { .compatible = "samsung,s5kjn1" },
2288 {},
2289 };
2290 MODULE_DEVICE_TABLE(of, s5kjn1_of_match);
2291 #endif
2292
2293 static const struct i2c_device_id s5kjn1_match_id[] = {
2294 { "samsung,s5kjn1", 0 },
2295 { },
2296 };
2297
2298 static struct i2c_driver s5kjn1_i2c_driver = {
2299 .driver = {
2300 .name = S5KJN1_NAME,
2301 .pm = &s5kjn1_pm_ops,
2302 .of_match_table = of_match_ptr(s5kjn1_of_match),
2303 },
2304 .probe = &s5kjn1_probe,
2305 .remove = &s5kjn1_remove,
2306 .id_table = s5kjn1_match_id,
2307 };
2308
2309 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
2310 module_i2c_driver(s5kjn1_i2c_driver);
2311 #else
sensor_mod_init(void)2312 static int __init sensor_mod_init(void)
2313 {
2314 return i2c_add_driver(&s5kjn1_i2c_driver);
2315 }
2316
sensor_mod_exit(void)2317 static void __exit sensor_mod_exit(void)
2318 {
2319 i2c_del_driver(&s5kjn1_i2c_driver);
2320 }
2321
2322 device_initcall_sync(sensor_mod_init);
2323 module_exit(sensor_mod_exit);
2324 #endif
2325
2326 MODULE_DESCRIPTION("Samsung s5kjn1 sensor driver");
2327 MODULE_LICENSE("GPL");
2328