1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chips.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/math64.h>
10 #include <linux/module.h>
11
12 #include "rk628.h"
13 #include "rk628_cru.h"
14 #include "rk628_dsi.h"
15 #include "rk628_mipi_dphy.h"
16 #include "rk628_combtxphy.h"
17
18 enum {
19 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
20 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
21 VID_MODE_TYPE_BURST,
22 };
23
24 #define MIPI_DSI_MODE_VIDEO BIT(0)
25 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
26 #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
27 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
28 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
29 #define MIPI_DSI_MODE_EOT_PACKET BIT(9)
30 #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
31 #define MIPI_DSI_MODE_LPM BIT(11)
32
dsi_write(struct rk628 * rk628,int id,u32 reg,u32 val)33 static inline int dsi_write(struct rk628 *rk628, int id, u32 reg, u32 val)
34 {
35 unsigned int dsi_base;
36
37 dsi_base = id ? DSI1_BASE : DSI0_BASE;
38
39 return rk628_i2c_write(rk628, dsi_base + reg, val);
40 }
41
dsi_read(struct rk628 * rk628,int id,u32 reg,u32 * val)42 static inline int dsi_read(struct rk628 *rk628, int id, u32 reg, u32 *val)
43 {
44 unsigned int dsi_base;
45
46 dsi_base = id ? DSI1_BASE : DSI0_BASE;
47
48 return rk628_i2c_read(rk628, dsi_base + reg, val);
49 }
50
dsi_update_bits(struct rk628 * rk628,int id,u32 reg,u32 mask,u32 val)51 static inline int dsi_update_bits(struct rk628 *rk628, int id,
52 u32 reg, u32 mask, u32 val)
53 {
54 unsigned int dsi_base;
55
56 dsi_base = id ? DSI1_BASE : DSI0_BASE;
57
58 return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);
59 }
60
mipi_dphy_power_on_dsi(struct rk628_dsi * dsi)61 static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi)
62 {
63 int dev_id;
64 unsigned int dsi_base;
65 unsigned int val, mask;
66 int ret;
67 struct rk628 *rk628 = dsi->rk628;
68
69 dev_id = RK628_DEV_DSI0;
70 dsi_base = DSI0_BASE;
71
72 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
73 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
74 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, 0);
75 testif_testclr_assert(dsi->rk628);
76
77 /* Set all REQUEST inputs to zero */
78 rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
79 FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
80 FORCETXSTOPMODE(0) | FORCERXMODE(0));
81 udelay(1);
82
83 testif_testclr_deassert(dsi->rk628);
84
85 mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps);
86
87 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
88 PHY_ENABLECLK, PHY_ENABLECLK);
89 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
90 PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
91 dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
92 usleep_range(1500, 2000);
93
94 rk628_txphy_power_on(rk628);
95
96 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
97 dsi_base + DSI_PHY_STATUS,
98 val, val & PHY_LOCK, 0, 1000);
99 if (ret < 0)
100 dev_err(rk628->dev, "PHY is not locked\n");
101
102 usleep_range(100, 200);
103
104 mask = PHY_STOPSTATELANE;
105 ret = regmap_read_poll_timeout(rk628->regmap[dev_id],
106 dsi_base + DSI_PHY_STATUS,
107 val, (val & mask) == mask,
108 0, 1000);
109 if (ret < 0)
110 dev_err(rk628->dev, "lane module is not in stop state\n");
111
112 udelay(10);
113 }
114
rk628_dsi_pre_enable(struct rk628_dsi * dsi)115 static void rk628_dsi_pre_enable(struct rk628_dsi *dsi)
116 {
117 u32 val;
118 struct rk628 *rk628 = dsi->rk628;
119 u32 lane_mbps = dsi->lane_mbps;
120
121 dsi_write(rk628, 0, DSI_PWR_UP, RESET);
122 dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
123
124 val = DIV_ROUND_UP(lane_mbps >> 3, 20);
125 dsi_write(rk628, 0, DSI_CLKMGR_CFG,
126 TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
127
128 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
129 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
130 val &= ~EOTP_TX_EN;
131
132 dsi_write(rk628, 0, DSI_PCKHDL_CFG, val);
133
134 dsi_write(rk628, 0, DSI_TO_CNT_CFG,
135 HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
136 dsi_write(rk628, 0, DSI_BTA_TO_CNT, 0xd00);
137 dsi_write(rk628, 0, DSI_PHY_TMR_CFG,
138 PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
139 MAX_RD_TIME(10000));
140 dsi_write(rk628, 0, DSI_PHY_TMR_LPCLK_CFG,
141 PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
142 dsi_write(rk628, 0, DSI_PHY_IF_CFG,
143 PHY_STOP_WAIT_TIME(0x20) | N_LANES(4 - 1));
144
145 mipi_dphy_power_on_dsi(dsi);
146
147 dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
148 }
149
rk628_dsi_set_vid_mode(struct rk628_dsi * dsi)150 static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
151 {
152 unsigned int lanebyteclk = (dsi->lane_mbps * 1000L) >> 3;
153 u64 dpipclk;
154 u32 hline, hs, hbp, hline_time, hs_time, hbp_time;
155 u32 vactive, vs, vfp, vbp;
156 u32 val;
157 int pkt_size;
158 struct v4l2_bt_timings *bt = &dsi->timings.bt;
159 struct rk628 *rk628 = dsi->rk628;
160
161 dpipclk = bt->pixelclock;
162 do_div(dpipclk, 1000);
163 val = LP_HFP_EN | LP_HBP_EN | LP_VACT_EN | LP_VFP_EN | LP_VBP_EN |
164 LP_VSA_EN;
165
166 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
167 val &= ~LP_HFP_EN;
168
169 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
170 val &= ~LP_HBP_EN;
171
172 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
173 val |= VID_MODE_TYPE_BURST;
174 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
175 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
176 else
177 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
178
179 dsi_write(rk628, 0, DSI_VID_MODE_CFG, val);
180
181 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
182 dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
183 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
184
185
186 pkt_size = VID_PKT_SIZE(bt->width);
187
188 dsi_write(rk628, 0, DSI_VID_PKT_SIZE, pkt_size);
189
190 vactive = bt->height;
191 vs = bt->vsync;
192 vfp = bt->vfrontporch;
193 vbp = bt->vbackporch;
194 hs = bt->hsync;
195 hbp = bt->hbackporch;
196 hline = bt->width;
197
198 dev_info(dsi->rk628->dev, "h: %d %d %d %d, v:%d %d %d %d clock:%llu\n",
199 bt->width, bt->hfrontporch, bt->hsync, bt->hbackporch,
200 bt->height, bt->vfrontporch, bt->vsync, bt->vbackporch,
201 bt->pixelclock);
202
203 //hline_time = hline * lanebyteclk / dpipclk;
204 hline_time = DIV_ROUND_CLOSEST_ULL(hline * lanebyteclk, dpipclk);
205 dsi_write(rk628, 0, DSI_VID_HLINE_TIME,
206 VID_HLINE_TIME(hline_time));
207 //hs_time = hs * lanebyteclk / dpipclk;
208 hs_time = DIV_ROUND_CLOSEST_ULL(hs * lanebyteclk, dpipclk);
209 dsi_write(rk628, 0, DSI_VID_HSA_TIME, VID_HSA_TIME(hs_time));
210 //hbp_time = hbp * lanebyteclk / dpipclk;
211 hbp_time = DIV_ROUND_CLOSEST_ULL(hbp * lanebyteclk, dpipclk);
212 dsi_write(rk628, 0, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
213
214 dsi_write(rk628, 0, DSI_VID_VACTIVE_LINES, vactive);
215 dsi_write(rk628, 0, DSI_VID_VSA_LINES, vs);
216 dsi_write(rk628, 0, DSI_VID_VFP_LINES, vfp);
217 dsi_write(rk628, 0, DSI_VID_VBP_LINES, vbp);
218
219 dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
220 }
221
rk628_dsi_set_cmd_mode(struct rk628_dsi * dsi)222 static void rk628_dsi_set_cmd_mode(struct rk628_dsi *dsi)
223 {
224 struct rk628 *rk628 = dsi->rk628;
225
226 dsi_update_bits(rk628, 0, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
227 dsi_write(rk628, 0, DSI_EDPI_CMD_SIZE,
228 EDPI_ALLOWED_CMD_SIZE(dsi->timings.bt.width));
229 dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
230 }
231
rk628_dsi_enable(struct rk628_dsi * dsi)232 static void rk628_dsi_enable(struct rk628_dsi *dsi)
233 {
234 u32 val;
235 struct rk628 *rk628 = dsi->rk628;
236
237 dsi_write(rk628, 0, DSI_PWR_UP, RESET);
238
239 val = DPI_COLOR_CODING(5);
240
241 dsi_write(rk628, 0, DSI_DPI_COLOR_CODING, val);
242
243 val = 0;
244
245 /*
246 * if (mode->flags & DRM_MODE_FLAG_NVSYNC)
247 * val |= VSYNC_ACTIVE_LOW;
248 * if (mode->flags & DRM_MODE_FLAG_NHSYNC)
249 * val |= HSYNC_ACTIVE_LOW;
250 */
251
252 dsi_write(rk628, 0, DSI_DPI_CFG_POL, val);
253
254 dsi_write(rk628, 0, DSI_DPI_VCID, DPI_VID(0));
255 dsi_write(rk628, 0, DSI_DPI_LP_CMD_TIM,
256 OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
257 dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
258 PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL,
259 PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL);
260 if (dsi->vid_mode == VIDEO_MODE)
261 rk628_dsi_set_vid_mode(dsi);
262 else
263 rk628_dsi_set_cmd_mode(dsi);
264
265 dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
266 }
267
rk628_dsi_get_lane_rate(struct rk628_dsi * dsi)268 static u32 rk628_dsi_get_lane_rate(struct rk628_dsi *dsi)
269 {
270 u32 lane_rate;
271 u32 max_lane_rate = 1500;
272 u8 bpp, lanes;
273 u64 pixelclock = dsi->timings.bt.pixelclock;
274
275 bpp = 24;
276 lanes = 4;
277 pixelclock = div_u64(pixelclock, 1000 * 1000);
278 lane_rate = pixelclock * bpp;
279 lane_rate = div_u64(lane_rate, lanes);
280 lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
281
282 if (lane_rate > max_lane_rate)
283 lane_rate = max_lane_rate;
284
285 return lane_rate;
286 }
287
rk628_mipi_dsi_power_on(struct rk628_dsi * dsi)288 void rk628_mipi_dsi_power_on(struct rk628_dsi *dsi)
289 {
290 struct rk628 *rk628 = dsi->rk628;
291 u32 rate = rk628_dsi_get_lane_rate(dsi);
292 int bus_width;
293
294 rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
295 SW_OUTPUT_MODE(OUTPUT_MODE_DSI));
296 rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN, 0);
297
298 bus_width = rate << 8;
299 bus_width |= COMBTXPHY_MODULEA_EN;
300 rk628_txphy_set_bus_width(dsi->rk628, bus_width);
301 rk628_txphy_set_mode(dsi->rk628, PHY_MODE_VIDEO_MIPI);
302 dsi->lane_mbps = rk628_txphy_get_bus_width(dsi->rk628);
303 dev_dbg(dsi->rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__,
304 dsi->lane_mbps);
305
306 rk628_dsi_pre_enable(dsi);
307
308 rk628_dsi_enable(dsi);
309 }
310 EXPORT_SYMBOL(rk628_mipi_dsi_power_on);
311