1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * pisp_dmy driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/sysfs.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/v4l2-fwnode.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_graph.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_gpio.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/version.h>
30 #include <linux/rk-camera-module.h>
31 #include <linux/rk-preisp.h>
32
33 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x0)
34
35 #ifndef V4L2_CID_DIGITAL_GAIN
36 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
37 #endif
38
39 #define PISP_DMY_XVCLK_FREQ 24000000
40
41 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
42 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
43
44 #define OF_CAMERA_MODULE_REGULATORS "rockchip,regulator-names"
45 #define OF_CAMERA_MODULE_REGULATOR_VOLTAGES "rockchip,regulator-voltages"
46
47 #define PISP_DMY_NAME "pisp_dmy"
48
49 struct pisp_dmy_gpio {
50 int pltfrm_gpio;
51 const char *label;
52 enum of_gpio_flags active_low;
53 };
54
55 struct pisp_dmy_regulator {
56 struct regulator *regulator;
57 u32 min_uV;
58 u32 max_uV;
59 };
60
61 struct pisp_dmy_regulators {
62 u32 cnt;
63 struct pisp_dmy_regulator *regulator;
64 };
65
66 struct pisp_dmy {
67 struct i2c_client *client;
68 struct clk *xvclk;
69 struct gpio_desc *rst_gpio;
70 struct gpio_desc *rst2_gpio;
71 struct gpio_desc *pd_gpio;
72 struct gpio_desc *pd2_gpio;
73 struct gpio_desc *pwd_gpio;
74 struct gpio_desc *pwd2_gpio;
75
76 struct pinctrl *pinctrl;
77 struct pinctrl_state *pins_default;
78 struct pinctrl_state *pins_sleep;
79
80 struct v4l2_subdev subdev;
81 struct media_pad pad;
82 struct mutex mutex;
83 bool power_on;
84 struct pisp_dmy_regulators regulators;
85
86 u32 module_index;
87 const char *module_facing;
88 const char *module_name;
89 const char *len_name;
90 };
91
92 #define to_pisp_dmy(sd) container_of(sd, struct pisp_dmy, subdev)
93
__pisp_dmy_power_on(struct pisp_dmy * pisp_dmy)94 static int __pisp_dmy_power_on(struct pisp_dmy *pisp_dmy)
95 {
96 u32 i;
97 int ret;
98 struct pisp_dmy_regulator *regulator;
99 struct device *dev = &pisp_dmy->client->dev;
100
101 if (!IS_ERR_OR_NULL(pisp_dmy->pins_default)) {
102 ret = pinctrl_select_state(pisp_dmy->pinctrl,
103 pisp_dmy->pins_default);
104 if (ret < 0)
105 dev_err(dev, "could not set pins. ret=%d\n", ret);
106 }
107
108 ret = clk_prepare_enable(pisp_dmy->xvclk);
109 if (ret < 0) {
110 dev_err(dev, "Failed to enable xvclk\n");
111 return ret;
112 }
113
114 if (pisp_dmy->regulators.regulator) {
115 for (i = 0; i < pisp_dmy->regulators.cnt; i++) {
116 regulator = pisp_dmy->regulators.regulator + i;
117 if (IS_ERR(regulator->regulator))
118 continue;
119 regulator_set_voltage(
120 regulator->regulator,
121 regulator->min_uV,
122 regulator->max_uV);
123 if (regulator_enable(regulator->regulator)) {
124 dev_err(dev,
125 "regulator_enable failed!\n");
126 goto disable_clk;
127 }
128 }
129 }
130 usleep_range(3000, 5000);
131
132 if (!IS_ERR(pisp_dmy->pwd_gpio)) {
133 gpiod_direction_output(pisp_dmy->pwd_gpio, 1);
134 usleep_range(3000, 5000);
135 }
136
137 if (!IS_ERR(pisp_dmy->pwd2_gpio)) {
138 gpiod_direction_output(pisp_dmy->pwd2_gpio, 1);
139 usleep_range(3000, 5000);
140 }
141
142 if (!IS_ERR(pisp_dmy->pd_gpio)) {
143 gpiod_direction_output(pisp_dmy->pd_gpio, 1);
144 usleep_range(1500, 2000);
145 }
146
147 if (!IS_ERR(pisp_dmy->pd2_gpio)) {
148 gpiod_direction_output(pisp_dmy->pd2_gpio, 1);
149 usleep_range(1500, 2000);
150 }
151
152 if (!IS_ERR(pisp_dmy->rst_gpio)) {
153 gpiod_direction_output(pisp_dmy->rst_gpio, 0);
154 usleep_range(1500, 2000);
155 gpiod_direction_output(pisp_dmy->rst_gpio, 1);
156 }
157
158 if (!IS_ERR(pisp_dmy->rst2_gpio)) {
159 gpiod_direction_output(pisp_dmy->rst2_gpio, 0);
160 usleep_range(1500, 2000);
161 gpiod_direction_output(pisp_dmy->rst2_gpio, 1);
162 }
163
164 return 0;
165
166 disable_clk:
167 clk_disable_unprepare(pisp_dmy->xvclk);
168
169 return ret;
170 }
171
__pisp_dmy_power_off(struct pisp_dmy * pisp_dmy)172 static void __pisp_dmy_power_off(struct pisp_dmy *pisp_dmy)
173 {
174 u32 i;
175 int ret;
176 struct pisp_dmy_regulator *regulator;
177 struct device *dev = &pisp_dmy->client->dev;
178
179 if (!IS_ERR(pisp_dmy->pd_gpio))
180 gpiod_direction_output(pisp_dmy->pd_gpio, 0);
181
182 if (!IS_ERR(pisp_dmy->pd2_gpio))
183 gpiod_direction_output(pisp_dmy->pd2_gpio, 0);
184
185 clk_disable_unprepare(pisp_dmy->xvclk);
186
187 if (!IS_ERR(pisp_dmy->rst_gpio))
188 gpiod_direction_output(pisp_dmy->rst_gpio, 0);
189
190 if (!IS_ERR(pisp_dmy->rst2_gpio))
191 gpiod_direction_output(pisp_dmy->rst2_gpio, 0);
192
193 if (!IS_ERR(pisp_dmy->pwd_gpio))
194 gpiod_direction_output(pisp_dmy->pwd_gpio, 0);
195
196 if (!IS_ERR(pisp_dmy->pwd2_gpio))
197 gpiod_direction_output(pisp_dmy->pwd2_gpio, 0);
198
199 if (!IS_ERR_OR_NULL(pisp_dmy->pins_sleep)) {
200 ret = pinctrl_select_state(pisp_dmy->pinctrl,
201 pisp_dmy->pins_sleep);
202 if (ret < 0)
203 dev_err(dev, "could not set pins\n");
204 }
205
206 if (pisp_dmy->regulators.regulator) {
207 for (i = 0; i < pisp_dmy->regulators.cnt; i++) {
208 regulator = pisp_dmy->regulators.regulator + i;
209 if (IS_ERR(regulator->regulator))
210 continue;
211 regulator_disable(regulator->regulator);
212 }
213 }
214 }
215
pisp_dmy_power(struct v4l2_subdev * sd,int on)216 static int pisp_dmy_power(struct v4l2_subdev *sd, int on)
217 {
218 struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
219 int ret = 0;
220
221 mutex_lock(&pisp_dmy->mutex);
222
223 /* If the power state is not modified - no work to do. */
224 if (pisp_dmy->power_on == !!on)
225 goto exit;
226
227 if (on) {
228 ret = __pisp_dmy_power_on(pisp_dmy);
229 if (ret < 0)
230 goto exit;
231
232 pisp_dmy->power_on = true;
233 } else {
234 __pisp_dmy_power_off(pisp_dmy);
235 pisp_dmy->power_on = false;
236 }
237
238 exit:
239 mutex_unlock(&pisp_dmy->mutex);
240
241 return ret;
242 }
243
pisp_dmy_get_module_inf(struct pisp_dmy * pisp_dmy,struct rkmodule_inf * inf)244 static void pisp_dmy_get_module_inf(struct pisp_dmy *pisp_dmy,
245 struct rkmodule_inf *inf)
246 {
247 memset(inf, 0, sizeof(*inf));
248 strlcpy(inf->base.sensor, PISP_DMY_NAME, sizeof(inf->base.sensor));
249 strlcpy(inf->base.module, pisp_dmy->module_name,
250 sizeof(inf->base.module));
251 strlcpy(inf->base.lens, pisp_dmy->len_name, sizeof(inf->base.lens));
252 }
253
pisp_dmy_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)254 static long pisp_dmy_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
255 {
256 struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
257 long ret = 0;
258
259 switch (cmd) {
260 case RKMODULE_GET_MODULE_INFO:
261 pisp_dmy_get_module_inf(pisp_dmy, (struct rkmodule_inf *)arg);
262 break;
263 default:
264 ret = -ENOTTY;
265 break;
266 }
267
268 return ret;
269 }
270
271 #ifdef CONFIG_COMPAT
pisp_dmy_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)272 static long pisp_dmy_compat_ioctl32(struct v4l2_subdev *sd,
273 unsigned int cmd, unsigned long arg)
274 {
275 void __user *up = compat_ptr(arg);
276 struct rkmodule_inf *inf;
277 struct rkmodule_awb_cfg *cfg;
278 long ret;
279
280 switch (cmd) {
281 case RKMODULE_GET_MODULE_INFO:
282 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
283 if (!inf) {
284 ret = -ENOMEM;
285 return ret;
286 }
287
288 ret = pisp_dmy_ioctl(sd, cmd, inf);
289 if (!ret)
290 if (copy_to_user(up, inf, sizeof(*inf))) {
291 kfree(inf);
292 return -EFAULT;
293 }
294 kfree(inf);
295 break;
296 case RKMODULE_AWB_CFG:
297 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
298 if (!cfg) {
299 ret = -ENOMEM;
300 return ret;
301 }
302
303 if (copy_from_user(cfg, up, sizeof(*cfg))) {
304 kfree(cfg);
305 return -EFAULT;
306 }
307
308 ret = pisp_dmy_ioctl(sd, cmd, cfg);
309 kfree(cfg);
310 break;
311 default:
312 ret = -ENOIOCTLCMD;
313 break;
314 }
315
316 return ret;
317 }
318 #endif
319
pisp_dmy_runtime_resume(struct device * dev)320 static int pisp_dmy_runtime_resume(struct device *dev)
321 {
322 struct i2c_client *client = to_i2c_client(dev);
323 struct v4l2_subdev *sd = i2c_get_clientdata(client);
324 struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
325
326 return __pisp_dmy_power_on(pisp_dmy);
327 }
328
pisp_dmy_runtime_suspend(struct device * dev)329 static int pisp_dmy_runtime_suspend(struct device *dev)
330 {
331 struct i2c_client *client = to_i2c_client(dev);
332 struct v4l2_subdev *sd = i2c_get_clientdata(client);
333 struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
334
335 __pisp_dmy_power_off(pisp_dmy);
336
337 return 0;
338 }
339
340 static const struct dev_pm_ops pisp_dmy_pm_ops = {
341 SET_RUNTIME_PM_OPS(pisp_dmy_runtime_suspend,
342 pisp_dmy_runtime_resume, NULL)
343 };
344
345 static const struct v4l2_subdev_core_ops pisp_dmy_core_ops = {
346 .s_power = pisp_dmy_power,
347 .ioctl = pisp_dmy_ioctl,
348 #ifdef CONFIG_COMPAT
349 .compat_ioctl32 = pisp_dmy_compat_ioctl32,
350 #endif
351 };
352
353 static const struct v4l2_subdev_ops pisp_dmy_subdev_ops = {
354 .core = &pisp_dmy_core_ops,
355 };
356
pisp_dmy_analyze_dts(struct pisp_dmy * pisp_dmy)357 static int pisp_dmy_analyze_dts(struct pisp_dmy *pisp_dmy)
358 {
359 int ret;
360 int elem_size, elem_index;
361 const char *str = "";
362 struct property *prop;
363 struct pisp_dmy_regulator *regulator;
364 struct device *dev = &pisp_dmy->client->dev;
365 struct device_node *np = of_node_get(dev->of_node);
366
367 pisp_dmy->xvclk = devm_clk_get(dev, "xvclk");
368 if (IS_ERR(pisp_dmy->xvclk)) {
369 dev_err(dev, "Failed to get xvclk\n");
370 return -EINVAL;
371 }
372 ret = clk_set_rate(pisp_dmy->xvclk, PISP_DMY_XVCLK_FREQ);
373 if (ret < 0) {
374 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
375 return ret;
376 }
377 if (clk_get_rate(pisp_dmy->xvclk) != PISP_DMY_XVCLK_FREQ)
378 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
379
380 pisp_dmy->pinctrl = devm_pinctrl_get(dev);
381 if (!IS_ERR(pisp_dmy->pinctrl)) {
382 pisp_dmy->pins_default =
383 pinctrl_lookup_state(pisp_dmy->pinctrl,
384 OF_CAMERA_PINCTRL_STATE_DEFAULT);
385 if (IS_ERR(pisp_dmy->pins_default))
386 dev_err(dev, "could not get default pinstate\n");
387
388 pisp_dmy->pins_sleep =
389 pinctrl_lookup_state(pisp_dmy->pinctrl,
390 OF_CAMERA_PINCTRL_STATE_SLEEP);
391 if (IS_ERR(pisp_dmy->pins_sleep))
392 dev_err(dev, "could not get sleep pinstate\n");
393 } else {
394 dev_err(dev, "no pinctrl\n");
395 }
396
397 elem_size = of_property_count_elems_of_size(
398 np,
399 OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
400 sizeof(u32));
401 prop = of_find_property(
402 np,
403 OF_CAMERA_MODULE_REGULATORS,
404 NULL);
405 if (elem_size > 0 && !IS_ERR_OR_NULL(prop)) {
406 pisp_dmy->regulators.regulator =
407 devm_kzalloc(&pisp_dmy->client->dev,
408 elem_size * sizeof(struct pisp_dmy_regulator),
409 GFP_KERNEL);
410 if (!pisp_dmy->regulators.regulator) {
411 dev_err(dev, "could not malloc pisp_dmy_regulator\n");
412 return -ENOMEM;
413 }
414
415 pisp_dmy->regulators.cnt = elem_size;
416
417 str = NULL;
418 elem_index = 0;
419 regulator = pisp_dmy->regulators.regulator;
420 do {
421 str = of_prop_next_string(prop, str);
422 if (!str) {
423 dev_err(dev, "%s is not match %s in dts\n",
424 OF_CAMERA_MODULE_REGULATORS,
425 OF_CAMERA_MODULE_REGULATOR_VOLTAGES);
426 break;
427 }
428 regulator->regulator =
429 devm_regulator_get_optional(dev, str);
430 if (IS_ERR(regulator->regulator))
431 dev_err(dev, "devm_regulator_get %s failed\n",
432 str);
433 of_property_read_u32_index(
434 np,
435 OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
436 elem_index++,
437 ®ulator->min_uV);
438 regulator->max_uV = regulator->min_uV;
439 regulator++;
440 } while (--elem_size);
441 }
442
443 pisp_dmy->pd_gpio = devm_gpiod_get(dev, "pd", GPIOD_OUT_LOW);
444 if (IS_ERR(pisp_dmy->pd_gpio))
445 dev_warn(dev, "can not find pd-gpios, error %ld\n",
446 PTR_ERR(pisp_dmy->pd_gpio));
447
448 pisp_dmy->pd2_gpio = devm_gpiod_get(dev, "pd2", GPIOD_OUT_LOW);
449 if (IS_ERR(pisp_dmy->pd2_gpio))
450 dev_warn(dev, "can not find pd2-gpios, error %ld\n",
451 PTR_ERR(pisp_dmy->pd2_gpio));
452
453 pisp_dmy->rst_gpio = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
454 if (IS_ERR(pisp_dmy->rst_gpio))
455 dev_warn(dev, "can not find rst-gpios, error %ld\n",
456 PTR_ERR(pisp_dmy->rst_gpio));
457
458 pisp_dmy->rst2_gpio = devm_gpiod_get(dev, "rst2", GPIOD_OUT_LOW);
459 if (IS_ERR(pisp_dmy->rst2_gpio))
460 dev_warn(dev, "can not find rst2-gpios, error %ld\n",
461 PTR_ERR(pisp_dmy->rst2_gpio));
462
463 pisp_dmy->pwd_gpio = devm_gpiod_get(dev, "pwd", GPIOD_OUT_HIGH);
464 if (IS_ERR(pisp_dmy->pwd_gpio))
465 dev_warn(dev, "can not find pwd-gpios, error %ld\n",
466 PTR_ERR(pisp_dmy->pwd_gpio));
467
468 pisp_dmy->pwd2_gpio = devm_gpiod_get(dev, "pwd2", GPIOD_OUT_HIGH);
469 if (IS_ERR(pisp_dmy->pwd2_gpio))
470 dev_warn(dev, "can not find pwd2-gpios, error %ld\n",
471 PTR_ERR(pisp_dmy->pwd2_gpio));
472
473 return 0;
474 }
475
pisp_dmy_probe(struct i2c_client * client,const struct i2c_device_id * id)476 static int pisp_dmy_probe(struct i2c_client *client,
477 const struct i2c_device_id *id)
478 {
479 struct device *dev = &client->dev;
480 struct device_node *node = dev->of_node;
481 struct pisp_dmy *pisp_dmy;
482 struct v4l2_subdev *sd;
483 int ret;
484
485 dev_info(dev, "driver version: %02x.%02x.%02x",
486 DRIVER_VERSION >> 16,
487 (DRIVER_VERSION & 0xff00) >> 8,
488 DRIVER_VERSION & 0x00ff);
489
490 pisp_dmy = devm_kzalloc(dev, sizeof(*pisp_dmy), GFP_KERNEL);
491 if (!pisp_dmy)
492 return -ENOMEM;
493
494 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
495 &pisp_dmy->module_index);
496 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
497 &pisp_dmy->module_facing);
498 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
499 &pisp_dmy->module_name);
500 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
501 &pisp_dmy->len_name);
502 if (ret) {
503 dev_err(dev, "could not get module information!\n");
504 return -EINVAL;
505 }
506
507 pisp_dmy->client = client;
508
509 ret = pisp_dmy_analyze_dts(pisp_dmy);
510 if (ret) {
511 dev_err(dev, "Failed to analyze dts\n");
512 return ret;
513 }
514
515 mutex_init(&pisp_dmy->mutex);
516
517 sd = &pisp_dmy->subdev;
518 v4l2_i2c_subdev_init(sd, client, &pisp_dmy_subdev_ops);
519
520 __pisp_dmy_power_on(pisp_dmy);
521
522 pm_runtime_set_active(dev);
523 pm_runtime_enable(dev);
524 pm_runtime_idle(dev);
525
526 return 0;
527 }
528
pisp_dmy_remove(struct i2c_client * client)529 static int pisp_dmy_remove(struct i2c_client *client)
530 {
531 struct v4l2_subdev *sd = i2c_get_clientdata(client);
532 struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
533
534 mutex_destroy(&pisp_dmy->mutex);
535
536 pm_runtime_disable(&client->dev);
537 if (!pm_runtime_status_suspended(&client->dev))
538 __pisp_dmy_power_off(pisp_dmy);
539 pm_runtime_set_suspended(&client->dev);
540
541 return 0;
542 }
543
544 #if IS_ENABLED(CONFIG_OF)
545 static const struct of_device_id pisp_dmy_of_match[] = {
546 { .compatible = "pisp_dmy" },
547 {},
548 };
549 MODULE_DEVICE_TABLE(of, pisp_dmy_of_match);
550 #endif
551
552 static const struct i2c_device_id pisp_dmy_match_id[] = {
553 { "pisp_dmy", 0 },
554 { },
555 };
556
557 static struct i2c_driver pisp_dmy_i2c_driver = {
558 .driver = {
559 .name = PISP_DMY_NAME,
560 .pm = &pisp_dmy_pm_ops,
561 .of_match_table = of_match_ptr(pisp_dmy_of_match),
562 },
563 .probe = &pisp_dmy_probe,
564 .remove = &pisp_dmy_remove,
565 .id_table = pisp_dmy_match_id,
566 };
567
sensor_mod_init(void)568 static int __init sensor_mod_init(void)
569 {
570 return i2c_add_driver(&pisp_dmy_i2c_driver);
571 }
572
sensor_mod_exit(void)573 static void __exit sensor_mod_exit(void)
574 {
575 i2c_del_driver(&pisp_dmy_i2c_driver);
576 }
577
578 device_initcall_sync(sensor_mod_init);
579 module_exit(sensor_mod_exit);
580
581 MODULE_DESCRIPTION("preisp dummy sensor driver");
582 MODULE_LICENSE("GPL v2");
583