1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ov9750 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun * V0.0X01.0X02 fix mclk issue when probe multiple camera.
7*4882a593Smuzhiyun * V0.0X01.0X03 add enum_frame_interval function.
8*4882a593Smuzhiyun * V0.0X01.0X04 add quick stream on/off
9*4882a593Smuzhiyun * V0.0X01.0X05 add function g_mbus_config
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
20*4882a593Smuzhiyun #include <linux/sysfs.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
23*4882a593Smuzhiyun #include <media/media-entity.h>
24*4882a593Smuzhiyun #include <media/v4l2-async.h>
25*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
26*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
27*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
28*4882a593Smuzhiyun #include <linux/version.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x5)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
33*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define OV9750_LINK_FREQ_400MHZ 400000000
37*4882a593Smuzhiyun /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
38*4882a593Smuzhiyun #define OV9750_PIXEL_RATE (OV9750_LINK_FREQ_400MHZ * 2 * 2 / 10)
39*4882a593Smuzhiyun #define OV9750_XVCLK_FREQ 24000000
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define CHIP_ID 0x9750
42*4882a593Smuzhiyun #define OV9750_REG_CHIP_ID 0x300B
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define OV9750_REG_CTRL_MODE 0x0100
45*4882a593Smuzhiyun #define OV9750_MODE_SW_STANDBY 0x0
46*4882a593Smuzhiyun #define OV9750_MODE_STREAMING BIT(0)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define OV9750_REG_EXPOSURE 0x3500
49*4882a593Smuzhiyun #define OV9750_EXPOSURE_MIN 4
50*4882a593Smuzhiyun #define OV9750_EXPOSURE_STEP 1
51*4882a593Smuzhiyun #define OV9750_VTS_MAX 0x7fff
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define OV9750_REG_GAIN_H 0x3508
54*4882a593Smuzhiyun #define OV9750_REG_GAIN_L 0x3509
55*4882a593Smuzhiyun #define OV9750_GAIN_H_MASK 0x1f
56*4882a593Smuzhiyun #define OV9750_GAIN_L_MASK 0xff
57*4882a593Smuzhiyun #define OV9750_GAIN_MIN 0x0080
58*4882a593Smuzhiyun #define OV9750_GAIN_MAX 0x1000
59*4882a593Smuzhiyun #define OV9750_GAIN_STEP 1
60*4882a593Smuzhiyun #define OV9750_GAIN_DEFAULT 0x0080
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define OV9750_REG_TEST_PATTERN 0x5e00
63*4882a593Smuzhiyun #define OV9750_TEST_PATTERN_ENABLE 0x80
64*4882a593Smuzhiyun #define OV9750_TEST_PATTERN_DISABLE 0x0
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define OV9750_REG_VTS 0x380e
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define REG_NULL 0xFFFF
69*4882a593Smuzhiyun #define REG_DELAY 0xFFFE
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define OV9750_REG_VALUE_08BIT 1
72*4882a593Smuzhiyun #define OV9750_REG_VALUE_16BIT 2
73*4882a593Smuzhiyun #define OV9750_REG_VALUE_24BIT 3
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define OV9750_LANES 2
76*4882a593Smuzhiyun #define OV9750_BITS_PER_SAMPLE 10
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
79*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define OV9750_NAME "ov9750"
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const char * const ov9750_supply_names[] = {
84*4882a593Smuzhiyun "avdd", /* Analog power */
85*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
86*4882a593Smuzhiyun "dvdd", /* Digital core power */
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define OV9750_NUM_SUPPLIES ARRAY_SIZE(ov9750_supply_names)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct regval {
92*4882a593Smuzhiyun u16 addr;
93*4882a593Smuzhiyun u8 val;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct ov9750_mode {
97*4882a593Smuzhiyun u32 width;
98*4882a593Smuzhiyun u32 height;
99*4882a593Smuzhiyun struct v4l2_fract max_fps;
100*4882a593Smuzhiyun u32 hts_def;
101*4882a593Smuzhiyun u32 vts_def;
102*4882a593Smuzhiyun u32 exp_def;
103*4882a593Smuzhiyun const struct regval *reg_list;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun struct ov9750 {
107*4882a593Smuzhiyun struct i2c_client *client;
108*4882a593Smuzhiyun struct clk *xvclk;
109*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
110*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
111*4882a593Smuzhiyun struct regulator_bulk_data supplies[OV9750_NUM_SUPPLIES];
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun struct pinctrl *pinctrl;
114*4882a593Smuzhiyun struct pinctrl_state *pins_default;
115*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun struct v4l2_subdev subdev;
118*4882a593Smuzhiyun struct media_pad pad;
119*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
120*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
121*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
122*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
123*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
124*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
125*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
126*4882a593Smuzhiyun struct mutex mutex;
127*4882a593Smuzhiyun bool streaming;
128*4882a593Smuzhiyun bool power_on;
129*4882a593Smuzhiyun const struct ov9750_mode *cur_mode;
130*4882a593Smuzhiyun u32 module_index;
131*4882a593Smuzhiyun const char *module_facing;
132*4882a593Smuzhiyun const char *module_name;
133*4882a593Smuzhiyun const char *len_name;
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define to_ov9750(sd) container_of(sd, struct ov9750, subdev)
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * Xclk 24Mhz
140*4882a593Smuzhiyun */
141*4882a593Smuzhiyun static const struct regval ov9750_global_regs[] = {
142*4882a593Smuzhiyun {0x0103, 0x01},
143*4882a593Smuzhiyun {REG_DELAY, 0x10},
144*4882a593Smuzhiyun {0x0100, 0x00},
145*4882a593Smuzhiyun {REG_DELAY, 0x10},
146*4882a593Smuzhiyun {0x0300, 0x04},
147*4882a593Smuzhiyun {0x0302, 0x64},
148*4882a593Smuzhiyun {0x0303, 0x00},
149*4882a593Smuzhiyun {0x0304, 0x03},
150*4882a593Smuzhiyun {0x0305, 0x01},
151*4882a593Smuzhiyun {0x0306, 0x01},
152*4882a593Smuzhiyun {0x030a, 0x00},
153*4882a593Smuzhiyun {0x030b, 0x00},
154*4882a593Smuzhiyun {0x030d, 0x1e},
155*4882a593Smuzhiyun {0x030e, 0x01},
156*4882a593Smuzhiyun {0x030f, 0x04},
157*4882a593Smuzhiyun {0x0312, 0x01},
158*4882a593Smuzhiyun {0x031e, 0x04},
159*4882a593Smuzhiyun {0x3000, 0x00},
160*4882a593Smuzhiyun {0x3001, 0x00},
161*4882a593Smuzhiyun {0x3002, 0x21},
162*4882a593Smuzhiyun {0x3005, 0xf0},
163*4882a593Smuzhiyun {0x3011, 0x00},
164*4882a593Smuzhiyun {0x3016, 0x53},
165*4882a593Smuzhiyun {0x3018, 0x32},
166*4882a593Smuzhiyun {0x301a, 0xf0},
167*4882a593Smuzhiyun {0x301b, 0xf0},
168*4882a593Smuzhiyun {0x301c, 0xf0},
169*4882a593Smuzhiyun {0x301d, 0xf0},
170*4882a593Smuzhiyun {0x301e, 0xf0},
171*4882a593Smuzhiyun {0x3022, 0x01},
172*4882a593Smuzhiyun {0x3031, 0x0a},
173*4882a593Smuzhiyun {0x3032, 0x80},
174*4882a593Smuzhiyun {0x303c, 0xff},
175*4882a593Smuzhiyun {0x303e, 0xff},
176*4882a593Smuzhiyun {0x3040, 0xf0},
177*4882a593Smuzhiyun {0x3041, 0x00},
178*4882a593Smuzhiyun {0x3042, 0xf0},
179*4882a593Smuzhiyun {0x3104, 0x01},
180*4882a593Smuzhiyun {0x3106, 0x15},
181*4882a593Smuzhiyun {0x3107, 0x01},
182*4882a593Smuzhiyun {0x3500, 0x00},
183*4882a593Smuzhiyun {0x3501, 0x3d},
184*4882a593Smuzhiyun {0x3502, 0x00},
185*4882a593Smuzhiyun {0x3503, 0x08},
186*4882a593Smuzhiyun {0x3504, 0x03},
187*4882a593Smuzhiyun {0x3505, 0x83},
188*4882a593Smuzhiyun {0x3508, 0x02},
189*4882a593Smuzhiyun {0x3509, 0x80},
190*4882a593Smuzhiyun {0x3600, 0x65},
191*4882a593Smuzhiyun {0x3601, 0x60},
192*4882a593Smuzhiyun {0x3602, 0x22},
193*4882a593Smuzhiyun {0x3610, 0xe8},
194*4882a593Smuzhiyun {0x3611, 0x56},
195*4882a593Smuzhiyun {0x3612, 0x48},
196*4882a593Smuzhiyun {0x3613, 0x5a},
197*4882a593Smuzhiyun {0x3614, 0x91},
198*4882a593Smuzhiyun {0x3615, 0x79},
199*4882a593Smuzhiyun {0x3617, 0x57},
200*4882a593Smuzhiyun {0x3621, 0x90},
201*4882a593Smuzhiyun {0x3622, 0x00},
202*4882a593Smuzhiyun {0x3623, 0x00},
203*4882a593Smuzhiyun {0x3625, 0x07},
204*4882a593Smuzhiyun {0x3633, 0x10},
205*4882a593Smuzhiyun {0x3634, 0x10},
206*4882a593Smuzhiyun {0x3635, 0x14},
207*4882a593Smuzhiyun {0x3636, 0x13},
208*4882a593Smuzhiyun {0x3650, 0x00},
209*4882a593Smuzhiyun {0x3652, 0xff},
210*4882a593Smuzhiyun {0x3654, 0x00},
211*4882a593Smuzhiyun {0x3653, 0x34},
212*4882a593Smuzhiyun {0x3655, 0x20},
213*4882a593Smuzhiyun {0x3656, 0xff},
214*4882a593Smuzhiyun {0x3657, 0xc4},
215*4882a593Smuzhiyun {0x365a, 0xff},
216*4882a593Smuzhiyun {0x365b, 0xff},
217*4882a593Smuzhiyun {0x365e, 0xff},
218*4882a593Smuzhiyun {0x365f, 0x00},
219*4882a593Smuzhiyun {0x3668, 0x00},
220*4882a593Smuzhiyun {0x366a, 0x07},
221*4882a593Smuzhiyun {0x366d, 0x00},
222*4882a593Smuzhiyun {0x366e, 0x10},
223*4882a593Smuzhiyun {0x3702, 0x1d},
224*4882a593Smuzhiyun {0x3703, 0x10},
225*4882a593Smuzhiyun {0x3704, 0x14},
226*4882a593Smuzhiyun {0x3705, 0x00},
227*4882a593Smuzhiyun {0x3706, 0x27},
228*4882a593Smuzhiyun {0x3709, 0x24},
229*4882a593Smuzhiyun {0x370a, 0x00},
230*4882a593Smuzhiyun {0x370b, 0x7d},
231*4882a593Smuzhiyun {0x3714, 0x24},
232*4882a593Smuzhiyun {0x371a, 0x5e},
233*4882a593Smuzhiyun {0x3730, 0x82},
234*4882a593Smuzhiyun {0x3733, 0x10},
235*4882a593Smuzhiyun {0x373e, 0x18},
236*4882a593Smuzhiyun {0x3755, 0x00},
237*4882a593Smuzhiyun {0x3758, 0x00},
238*4882a593Smuzhiyun {0x375b, 0x13},
239*4882a593Smuzhiyun {0x3772, 0x23},
240*4882a593Smuzhiyun {0x3773, 0x05},
241*4882a593Smuzhiyun {0x3774, 0x16},
242*4882a593Smuzhiyun {0x3775, 0x12},
243*4882a593Smuzhiyun {0x3776, 0x08},
244*4882a593Smuzhiyun {0x37a8, 0x38},
245*4882a593Smuzhiyun {0x37b5, 0x36},
246*4882a593Smuzhiyun {0x37c2, 0x04},
247*4882a593Smuzhiyun {0x37c5, 0x00},
248*4882a593Smuzhiyun {0x37c7, 0x38},
249*4882a593Smuzhiyun {0x37c8, 0x00},
250*4882a593Smuzhiyun {0x37d1, 0x13},
251*4882a593Smuzhiyun {0x3800, 0x00},
252*4882a593Smuzhiyun {0x3801, 0x00},
253*4882a593Smuzhiyun {0x3802, 0x00},
254*4882a593Smuzhiyun {0x3803, 0x04},
255*4882a593Smuzhiyun {0x3804, 0x05},
256*4882a593Smuzhiyun {0x3805, 0x0f},
257*4882a593Smuzhiyun {0x3806, 0x03},
258*4882a593Smuzhiyun {0x3807, 0xcb},
259*4882a593Smuzhiyun {0x3808, 0x05},
260*4882a593Smuzhiyun {0x3809, 0x00},
261*4882a593Smuzhiyun {0x380a, 0x03},
262*4882a593Smuzhiyun {0x380b, 0xc0},
263*4882a593Smuzhiyun {0x380c, 0x03},
264*4882a593Smuzhiyun {0x380d, 0x2a},
265*4882a593Smuzhiyun {0x380e, 0x03},
266*4882a593Smuzhiyun {0x380f, 0xdc},
267*4882a593Smuzhiyun {0x3810, 0x00},
268*4882a593Smuzhiyun {0x3811, 0x08},
269*4882a593Smuzhiyun {0x3812, 0x00},
270*4882a593Smuzhiyun {0x3813, 0x04},
271*4882a593Smuzhiyun {0x3814, 0x01},
272*4882a593Smuzhiyun {0x3815, 0x01},
273*4882a593Smuzhiyun {0x3816, 0x00},
274*4882a593Smuzhiyun {0x3817, 0x00},
275*4882a593Smuzhiyun {0x3818, 0x00},
276*4882a593Smuzhiyun {0x3819, 0x00},
277*4882a593Smuzhiyun {0x3820, 0x80},
278*4882a593Smuzhiyun {0x3821, 0x40},
279*4882a593Smuzhiyun {0x3826, 0x00},
280*4882a593Smuzhiyun {0x3827, 0x08},
281*4882a593Smuzhiyun {0x382a, 0x01},
282*4882a593Smuzhiyun {0x382b, 0x01},
283*4882a593Smuzhiyun {0x3836, 0x02},
284*4882a593Smuzhiyun {0x3838, 0x10},
285*4882a593Smuzhiyun {0x3861, 0x00},
286*4882a593Smuzhiyun {0x3862, 0x00},
287*4882a593Smuzhiyun {0x3863, 0x02},
288*4882a593Smuzhiyun {0x3b00, 0x00},
289*4882a593Smuzhiyun {0x3c00, 0x89},
290*4882a593Smuzhiyun {0x3c01, 0xab},
291*4882a593Smuzhiyun {0x3c02, 0x01},
292*4882a593Smuzhiyun {0x3c03, 0x00},
293*4882a593Smuzhiyun {0x3c04, 0x00},
294*4882a593Smuzhiyun {0x3c05, 0x03},
295*4882a593Smuzhiyun {0x3c06, 0x00},
296*4882a593Smuzhiyun {0x3c07, 0x05},
297*4882a593Smuzhiyun {0x3c0c, 0x00},
298*4882a593Smuzhiyun {0x3c0d, 0x00},
299*4882a593Smuzhiyun {0x3c0e, 0x00},
300*4882a593Smuzhiyun {0x3c0f, 0x00},
301*4882a593Smuzhiyun {0x3c40, 0x00},
302*4882a593Smuzhiyun {0x3c41, 0xa3},
303*4882a593Smuzhiyun {0x3c43, 0x7d},
304*4882a593Smuzhiyun {0x3c56, 0x80},
305*4882a593Smuzhiyun {0x3c80, 0x08},
306*4882a593Smuzhiyun {0x3c82, 0x01},
307*4882a593Smuzhiyun {0x3c83, 0x61},
308*4882a593Smuzhiyun {0x3d85, 0x17},
309*4882a593Smuzhiyun {0x3f08, 0x08},
310*4882a593Smuzhiyun {0x3f0a, 0x00},
311*4882a593Smuzhiyun {0x3f0b, 0x30},
312*4882a593Smuzhiyun {0x4000, 0xcd},
313*4882a593Smuzhiyun {0x4003, 0x40},
314*4882a593Smuzhiyun {0x4009, 0x0d},
315*4882a593Smuzhiyun {0x4010, 0xf0},
316*4882a593Smuzhiyun {0x4011, 0x70},
317*4882a593Smuzhiyun {0x4017, 0x10},
318*4882a593Smuzhiyun {0x4040, 0x00},
319*4882a593Smuzhiyun {0x4041, 0x00},
320*4882a593Smuzhiyun {0x4303, 0x00},
321*4882a593Smuzhiyun {0x4307, 0x30},
322*4882a593Smuzhiyun {0x4500, 0x30},
323*4882a593Smuzhiyun {0x4502, 0x40},
324*4882a593Smuzhiyun {0x4503, 0x06},
325*4882a593Smuzhiyun {0x4508, 0xaa},
326*4882a593Smuzhiyun {0x450b, 0x00},
327*4882a593Smuzhiyun {0x450c, 0x00},
328*4882a593Smuzhiyun {0x4600, 0x00},
329*4882a593Smuzhiyun {0x4601, 0x80},
330*4882a593Smuzhiyun {0x4700, 0x04},
331*4882a593Smuzhiyun {0x4704, 0x00},
332*4882a593Smuzhiyun {0x4705, 0x04},
333*4882a593Smuzhiyun {0x4837, 0x14},
334*4882a593Smuzhiyun {0x484a, 0x3f},
335*4882a593Smuzhiyun {0x5000, 0x10},
336*4882a593Smuzhiyun {0x5001, 0x01},
337*4882a593Smuzhiyun {0x5002, 0x28},
338*4882a593Smuzhiyun {0x5004, 0x0c},
339*4882a593Smuzhiyun {0x5006, 0x0c},
340*4882a593Smuzhiyun {0x5007, 0xe0},
341*4882a593Smuzhiyun {0x5008, 0x01},
342*4882a593Smuzhiyun {0x5009, 0xb0},
343*4882a593Smuzhiyun {0x502a, 0x18},
344*4882a593Smuzhiyun {0x5901, 0x00},
345*4882a593Smuzhiyun {0x5a01, 0x00},
346*4882a593Smuzhiyun {0x5a03, 0x00},
347*4882a593Smuzhiyun {0x5a04, 0x0c},
348*4882a593Smuzhiyun {0x5a05, 0xe0},
349*4882a593Smuzhiyun {0x5a06, 0x09},
350*4882a593Smuzhiyun {0x5a07, 0xb0},
351*4882a593Smuzhiyun {0x5a08, 0x06},
352*4882a593Smuzhiyun {0x5e00, 0x00},
353*4882a593Smuzhiyun {0x5e10, 0xfc},
354*4882a593Smuzhiyun {0x300f, 0x00},
355*4882a593Smuzhiyun {0x3733, 0x10},
356*4882a593Smuzhiyun {0x3610, 0xe8},
357*4882a593Smuzhiyun {0x3611, 0x56},
358*4882a593Smuzhiyun {0x3635, 0x14},
359*4882a593Smuzhiyun {0x3636, 0x13},
360*4882a593Smuzhiyun {0x3620, 0x84},
361*4882a593Smuzhiyun {0x3614, 0x96},
362*4882a593Smuzhiyun {0x481f, 0x30},
363*4882a593Smuzhiyun {0x3788, 0x00},
364*4882a593Smuzhiyun {0x3789, 0x04},
365*4882a593Smuzhiyun {0x378a, 0x01},
366*4882a593Smuzhiyun {0x378b, 0x60},
367*4882a593Smuzhiyun {0x3799, 0x27},
368*4882a593Smuzhiyun {REG_NULL, 0x00},
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /*
372*4882a593Smuzhiyun * Xclk 24Mhz
373*4882a593Smuzhiyun * max_framerate 60fps
374*4882a593Smuzhiyun * mipi_datarate per lane 800Mbps
375*4882a593Smuzhiyun */
376*4882a593Smuzhiyun static const struct regval ov9750_1280x960_regs[] = {
377*4882a593Smuzhiyun {REG_NULL, 0x00},
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun static const struct ov9750_mode supported_modes[] = {
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun .width = 1280,
383*4882a593Smuzhiyun .height = 960,
384*4882a593Smuzhiyun .max_fps = {
385*4882a593Smuzhiyun .numerator = 10000,
386*4882a593Smuzhiyun .denominator = 600000,
387*4882a593Smuzhiyun },
388*4882a593Smuzhiyun .exp_def = 0x03D0,
389*4882a593Smuzhiyun .hts_def = 0x0654,//0x32A*2
390*4882a593Smuzhiyun .vts_def = 0x03DC,
391*4882a593Smuzhiyun .reg_list = ov9750_1280x960_regs,
392*4882a593Smuzhiyun },
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
396*4882a593Smuzhiyun OV9750_LINK_FREQ_400MHZ
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static const char * const ov9750_test_pattern_menu[] = {
400*4882a593Smuzhiyun "Disabled",
401*4882a593Smuzhiyun "Vertical Color Bar Type 1",
402*4882a593Smuzhiyun "Vertical Color Bar Type 2",
403*4882a593Smuzhiyun "Vertical Color Bar Type 3",
404*4882a593Smuzhiyun "Vertical Color Bar Type 4"
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* Write registers up to 4 at a time */
ov9750_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)408*4882a593Smuzhiyun static int ov9750_write_reg(struct i2c_client *client, u16 reg,
409*4882a593Smuzhiyun u32 len, u32 val)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun u32 buf_i, val_i;
412*4882a593Smuzhiyun u8 buf[6];
413*4882a593Smuzhiyun u8 *val_p;
414*4882a593Smuzhiyun __be32 val_be;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (len > 4)
417*4882a593Smuzhiyun return -EINVAL;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun buf[0] = reg >> 8;
420*4882a593Smuzhiyun buf[1] = reg & 0xff;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun val_be = cpu_to_be32(val);
423*4882a593Smuzhiyun val_p = (u8 *)&val_be;
424*4882a593Smuzhiyun buf_i = 2;
425*4882a593Smuzhiyun val_i = 4 - len;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun while (val_i < 4)
428*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
431*4882a593Smuzhiyun return -EIO;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
ov9750_write_array(struct i2c_client * client,const struct regval * regs)436*4882a593Smuzhiyun static int ov9750_write_array(struct i2c_client *client,
437*4882a593Smuzhiyun const struct regval *regs)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun u32 i;
440*4882a593Smuzhiyun int ret = 0;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
443*4882a593Smuzhiyun if (unlikely(regs[i].addr == REG_DELAY))
444*4882a593Smuzhiyun usleep_range(regs[i].val, regs[i].val * 2);
445*4882a593Smuzhiyun else
446*4882a593Smuzhiyun ret = ov9750_write_reg(client, regs[i].addr,
447*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, regs[i].val);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun return ret;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /* Read registers up to 4 at a time */
ov9750_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)453*4882a593Smuzhiyun static int ov9750_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
454*4882a593Smuzhiyun u32 *val)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun struct i2c_msg msgs[2];
457*4882a593Smuzhiyun u8 *data_be_p;
458*4882a593Smuzhiyun __be32 data_be = 0;
459*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
460*4882a593Smuzhiyun int ret;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (len > 4 || !len)
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
466*4882a593Smuzhiyun /* Write register address */
467*4882a593Smuzhiyun msgs[0].addr = client->addr;
468*4882a593Smuzhiyun msgs[0].flags = 0;
469*4882a593Smuzhiyun msgs[0].len = 2;
470*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /* Read data from register */
473*4882a593Smuzhiyun msgs[1].addr = client->addr;
474*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
475*4882a593Smuzhiyun msgs[1].len = len;
476*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
479*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
480*4882a593Smuzhiyun return -EIO;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
ov9750_get_reso_dist(const struct ov9750_mode * mode,struct v4l2_mbus_framefmt * framefmt)487*4882a593Smuzhiyun static int ov9750_get_reso_dist(const struct ov9750_mode *mode,
488*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
491*4882a593Smuzhiyun abs(mode->height - framefmt->height);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun static const struct ov9750_mode *
ov9750_find_best_fit(struct v4l2_subdev_format * fmt)495*4882a593Smuzhiyun ov9750_find_best_fit(struct v4l2_subdev_format *fmt)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
498*4882a593Smuzhiyun int dist;
499*4882a593Smuzhiyun int cur_best_fit = 0;
500*4882a593Smuzhiyun int cur_best_fit_dist = -1;
501*4882a593Smuzhiyun unsigned int i;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
504*4882a593Smuzhiyun dist = ov9750_get_reso_dist(&supported_modes[i], framefmt);
505*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
506*4882a593Smuzhiyun cur_best_fit_dist = dist;
507*4882a593Smuzhiyun cur_best_fit = i;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
ov9750_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)514*4882a593Smuzhiyun static int ov9750_set_fmt(struct v4l2_subdev *sd,
515*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
516*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
519*4882a593Smuzhiyun const struct ov9750_mode *mode;
520*4882a593Smuzhiyun s64 h_blank, vblank_def;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun mode = ov9750_find_best_fit(fmt);
525*4882a593Smuzhiyun fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
526*4882a593Smuzhiyun fmt->format.width = mode->width;
527*4882a593Smuzhiyun fmt->format.height = mode->height;
528*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
529*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
530*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
531*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
532*4882a593Smuzhiyun #else
533*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
534*4882a593Smuzhiyun return -ENOTTY;
535*4882a593Smuzhiyun #endif
536*4882a593Smuzhiyun } else {
537*4882a593Smuzhiyun ov9750->cur_mode = mode;
538*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
539*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov9750->hblank, h_blank,
540*4882a593Smuzhiyun h_blank, 1, h_blank);
541*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
542*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov9750->vblank, vblank_def,
543*4882a593Smuzhiyun OV9750_VTS_MAX - mode->height,
544*4882a593Smuzhiyun 1, vblank_def);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun return 0;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
ov9750_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)552*4882a593Smuzhiyun static int ov9750_get_fmt(struct v4l2_subdev *sd,
553*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
554*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
557*4882a593Smuzhiyun const struct ov9750_mode *mode = ov9750->cur_mode;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
560*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
561*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
562*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
563*4882a593Smuzhiyun #else
564*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
565*4882a593Smuzhiyun return -ENOTTY;
566*4882a593Smuzhiyun #endif
567*4882a593Smuzhiyun } else {
568*4882a593Smuzhiyun fmt->format.width = mode->width;
569*4882a593Smuzhiyun fmt->format.height = mode->height;
570*4882a593Smuzhiyun fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
571*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun return 0;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
ov9750_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)578*4882a593Smuzhiyun static int ov9750_enum_mbus_code(struct v4l2_subdev *sd,
579*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
580*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun if (code->index != 0)
583*4882a593Smuzhiyun return -EINVAL;
584*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
ov9750_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)589*4882a593Smuzhiyun static int ov9750_enum_frame_sizes(struct v4l2_subdev *sd,
590*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
591*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
594*4882a593Smuzhiyun return -EINVAL;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
597*4882a593Smuzhiyun return -EINVAL;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
600*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
601*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
602*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun return 0;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
ov9750_enable_test_pattern(struct ov9750 * ov9750,u32 pattern)607*4882a593Smuzhiyun static int ov9750_enable_test_pattern(struct ov9750 *ov9750, u32 pattern)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun u32 val;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun if (pattern)
612*4882a593Smuzhiyun val = ((pattern - 1) < 2) | OV9750_TEST_PATTERN_ENABLE;
613*4882a593Smuzhiyun else
614*4882a593Smuzhiyun val = OV9750_TEST_PATTERN_DISABLE;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return ov9750_write_reg(ov9750->client, OV9750_REG_TEST_PATTERN,
617*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, val);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
ov9750_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)620*4882a593Smuzhiyun static int ov9750_g_frame_interval(struct v4l2_subdev *sd,
621*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
624*4882a593Smuzhiyun const struct ov9750_mode *mode = ov9750->cur_mode;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun fi->interval = mode->max_fps;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun return 0;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
ov9750_get_module_inf(struct ov9750 * ov9750,struct rkmodule_inf * inf)631*4882a593Smuzhiyun static void ov9750_get_module_inf(struct ov9750 *ov9750,
632*4882a593Smuzhiyun struct rkmodule_inf *inf)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
635*4882a593Smuzhiyun strlcpy(inf->base.sensor, OV9750_NAME, sizeof(inf->base.sensor));
636*4882a593Smuzhiyun strlcpy(inf->base.module, ov9750->module_name,
637*4882a593Smuzhiyun sizeof(inf->base.module));
638*4882a593Smuzhiyun strlcpy(inf->base.lens, ov9750->len_name, sizeof(inf->base.lens));
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
ov9750_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)641*4882a593Smuzhiyun static long ov9750_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
644*4882a593Smuzhiyun long ret = 0;
645*4882a593Smuzhiyun u32 stream = 0;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun switch (cmd) {
648*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
649*4882a593Smuzhiyun ov9750_get_module_inf(ov9750, (struct rkmodule_inf *)arg);
650*4882a593Smuzhiyun break;
651*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun stream = *((u32 *)arg);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun if (stream)
656*4882a593Smuzhiyun ret = ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
657*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, OV9750_MODE_STREAMING);
658*4882a593Smuzhiyun else
659*4882a593Smuzhiyun ret = ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
660*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, OV9750_MODE_SW_STANDBY);
661*4882a593Smuzhiyun break;
662*4882a593Smuzhiyun default:
663*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
664*4882a593Smuzhiyun break;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun return ret;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
ov9750_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)671*4882a593Smuzhiyun static long ov9750_compat_ioctl32(struct v4l2_subdev *sd,
672*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
675*4882a593Smuzhiyun struct rkmodule_inf *inf;
676*4882a593Smuzhiyun long ret;
677*4882a593Smuzhiyun u32 stream = 0;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun switch (cmd) {
680*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
681*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
682*4882a593Smuzhiyun if (!inf) {
683*4882a593Smuzhiyun ret = -ENOMEM;
684*4882a593Smuzhiyun return ret;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun ret = ov9750_ioctl(sd, cmd, inf);
687*4882a593Smuzhiyun if (!ret)
688*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
689*4882a593Smuzhiyun kfree(inf);
690*4882a593Smuzhiyun break;
691*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
692*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
693*4882a593Smuzhiyun if (!ret)
694*4882a593Smuzhiyun ret = ov9750_ioctl(sd, cmd, &stream);
695*4882a593Smuzhiyun break;
696*4882a593Smuzhiyun default:
697*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
698*4882a593Smuzhiyun break;
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun return ret;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun #endif
704*4882a593Smuzhiyun
__ov9750_start_stream(struct ov9750 * ov9750)705*4882a593Smuzhiyun static int __ov9750_start_stream(struct ov9750 *ov9750)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun int ret;
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun ret = ov9750_write_array(ov9750->client, ov9750->cur_mode->reg_list);
710*4882a593Smuzhiyun if (ret)
711*4882a593Smuzhiyun return ret;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun /* In case these controls are set before streaming */
714*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
715*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&ov9750->ctrl_handler);
716*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
717*4882a593Smuzhiyun if (ret)
718*4882a593Smuzhiyun return ret;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun return ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
721*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, OV9750_MODE_STREAMING);
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
__ov9750_stop_stream(struct ov9750 * ov9750)724*4882a593Smuzhiyun static int __ov9750_stop_stream(struct ov9750 *ov9750)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun return ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
727*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT, OV9750_MODE_SW_STANDBY);
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun
ov9750_s_stream(struct v4l2_subdev * sd,int on)730*4882a593Smuzhiyun static int ov9750_s_stream(struct v4l2_subdev *sd, int on)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
733*4882a593Smuzhiyun struct i2c_client *client = ov9750->client;
734*4882a593Smuzhiyun int ret = 0;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
737*4882a593Smuzhiyun on = !!on;
738*4882a593Smuzhiyun if (on == ov9750->streaming)
739*4882a593Smuzhiyun goto unlock_and_return;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun if (on) {
742*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
743*4882a593Smuzhiyun if (ret < 0) {
744*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
745*4882a593Smuzhiyun goto unlock_and_return;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun ret = __ov9750_start_stream(ov9750);
749*4882a593Smuzhiyun if (ret) {
750*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
751*4882a593Smuzhiyun pm_runtime_put(&client->dev);
752*4882a593Smuzhiyun goto unlock_and_return;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun } else {
755*4882a593Smuzhiyun __ov9750_stop_stream(ov9750);
756*4882a593Smuzhiyun pm_runtime_put(&client->dev);
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun ov9750->streaming = on;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun unlock_and_return:
762*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun return ret;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
ov9750_s_power(struct v4l2_subdev * sd,int on)767*4882a593Smuzhiyun static int ov9750_s_power(struct v4l2_subdev *sd, int on)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
770*4882a593Smuzhiyun struct i2c_client *client = ov9750->client;
771*4882a593Smuzhiyun int ret = 0;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
776*4882a593Smuzhiyun if (ov9750->power_on == !!on)
777*4882a593Smuzhiyun goto unlock_and_return;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun if (on) {
780*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
781*4882a593Smuzhiyun if (ret < 0) {
782*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
783*4882a593Smuzhiyun goto unlock_and_return;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun ret = ov9750_write_array(ov9750->client, ov9750_global_regs);
786*4882a593Smuzhiyun if (ret) {
787*4882a593Smuzhiyun v4l2_err(sd, "could not set init registers\n");
788*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
789*4882a593Smuzhiyun goto unlock_and_return;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun ov9750->power_on = true;
792*4882a593Smuzhiyun } else {
793*4882a593Smuzhiyun pm_runtime_put(&client->dev);
794*4882a593Smuzhiyun ov9750->power_on = false;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun unlock_and_return:
798*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun return ret;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
ov9750_cal_delay(u32 cycles)804*4882a593Smuzhiyun static inline u32 ov9750_cal_delay(u32 cycles)
805*4882a593Smuzhiyun {
806*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, OV9750_XVCLK_FREQ / 1000 / 1000);
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun
__ov9750_power_on(struct ov9750 * ov9750)809*4882a593Smuzhiyun static int __ov9750_power_on(struct ov9750 *ov9750)
810*4882a593Smuzhiyun {
811*4882a593Smuzhiyun int ret;
812*4882a593Smuzhiyun u32 delay_us;
813*4882a593Smuzhiyun struct device *dev = &ov9750->client->dev;
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(ov9750->pins_default)) {
816*4882a593Smuzhiyun ret = pinctrl_select_state(ov9750->pinctrl,
817*4882a593Smuzhiyun ov9750->pins_default);
818*4882a593Smuzhiyun if (ret < 0)
819*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun ret = clk_set_rate(ov9750->xvclk, OV9750_XVCLK_FREQ);
823*4882a593Smuzhiyun if (ret < 0)
824*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
825*4882a593Smuzhiyun if (clk_get_rate(ov9750->xvclk) != OV9750_XVCLK_FREQ)
826*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
827*4882a593Smuzhiyun ret = clk_prepare_enable(ov9750->xvclk);
828*4882a593Smuzhiyun if (ret < 0) {
829*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
830*4882a593Smuzhiyun return ret;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (!IS_ERR(ov9750->reset_gpio))
834*4882a593Smuzhiyun gpiod_set_value_cansleep(ov9750->reset_gpio, 0);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun ret = regulator_bulk_enable(OV9750_NUM_SUPPLIES, ov9750->supplies);
837*4882a593Smuzhiyun if (ret < 0) {
838*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
839*4882a593Smuzhiyun goto disable_clk;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun if (!IS_ERR(ov9750->reset_gpio))
843*4882a593Smuzhiyun gpiod_set_value_cansleep(ov9750->reset_gpio, 1);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun usleep_range(500, 1000);
846*4882a593Smuzhiyun if (!IS_ERR(ov9750->pwdn_gpio))
847*4882a593Smuzhiyun gpiod_set_value_cansleep(ov9750->pwdn_gpio, 1);
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
850*4882a593Smuzhiyun delay_us = ov9750_cal_delay(8192);
851*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun return 0;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun disable_clk:
856*4882a593Smuzhiyun clk_disable_unprepare(ov9750->xvclk);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun return ret;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun
__ov9750_power_off(struct ov9750 * ov9750)861*4882a593Smuzhiyun static void __ov9750_power_off(struct ov9750 *ov9750)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun int ret;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun if (!IS_ERR(ov9750->pwdn_gpio))
866*4882a593Smuzhiyun gpiod_set_value_cansleep(ov9750->pwdn_gpio, 0);
867*4882a593Smuzhiyun clk_disable_unprepare(ov9750->xvclk);
868*4882a593Smuzhiyun if (!IS_ERR(ov9750->reset_gpio))
869*4882a593Smuzhiyun gpiod_set_value_cansleep(ov9750->reset_gpio, 0);
870*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(ov9750->pins_sleep)) {
871*4882a593Smuzhiyun ret = pinctrl_select_state(ov9750->pinctrl,
872*4882a593Smuzhiyun ov9750->pins_sleep);
873*4882a593Smuzhiyun if (ret < 0)
874*4882a593Smuzhiyun dev_dbg(&ov9750->client->dev, "could not set pins\n");
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun regulator_bulk_disable(OV9750_NUM_SUPPLIES, ov9750->supplies);
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun
ov9750_runtime_resume(struct device * dev)879*4882a593Smuzhiyun static int ov9750_runtime_resume(struct device *dev)
880*4882a593Smuzhiyun {
881*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
882*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
883*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun return __ov9750_power_on(ov9750);
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
ov9750_runtime_suspend(struct device * dev)888*4882a593Smuzhiyun static int ov9750_runtime_suspend(struct device *dev)
889*4882a593Smuzhiyun {
890*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
891*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
892*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun __ov9750_power_off(ov9750);
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun return 0;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov9750_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)900*4882a593Smuzhiyun static int ov9750_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
901*4882a593Smuzhiyun {
902*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
903*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
904*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
905*4882a593Smuzhiyun const struct ov9750_mode *def_mode = &supported_modes[0];
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun mutex_lock(&ov9750->mutex);
908*4882a593Smuzhiyun /* Initialize try_fmt */
909*4882a593Smuzhiyun try_fmt->width = def_mode->width;
910*4882a593Smuzhiyun try_fmt->height = def_mode->height;
911*4882a593Smuzhiyun try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
912*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun mutex_unlock(&ov9750->mutex);
915*4882a593Smuzhiyun /* No crop or compose */
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun return 0;
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun #endif
920*4882a593Smuzhiyun
ov9750_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)921*4882a593Smuzhiyun static int ov9750_enum_frame_interval(struct v4l2_subdev *sd,
922*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
923*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
924*4882a593Smuzhiyun {
925*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
926*4882a593Smuzhiyun return -EINVAL;
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
929*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
930*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
931*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
932*4882a593Smuzhiyun return 0;
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun
ov9750_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)935*4882a593Smuzhiyun static int ov9750_g_mbus_config(struct v4l2_subdev *sd,
936*4882a593Smuzhiyun struct v4l2_mbus_config *config)
937*4882a593Smuzhiyun {
938*4882a593Smuzhiyun u32 val = 0;
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun val = 1 << (OV9750_LANES - 1) |
941*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
942*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
943*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2;
944*4882a593Smuzhiyun config->flags = val;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun return 0;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun static const struct dev_pm_ops ov9750_pm_ops = {
950*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(ov9750_runtime_suspend,
951*4882a593Smuzhiyun ov9750_runtime_resume, NULL)
952*4882a593Smuzhiyun };
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
955*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops ov9750_internal_ops = {
956*4882a593Smuzhiyun .open = ov9750_open,
957*4882a593Smuzhiyun };
958*4882a593Smuzhiyun #endif
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops ov9750_core_ops = {
961*4882a593Smuzhiyun .s_power = ov9750_s_power,
962*4882a593Smuzhiyun .ioctl = ov9750_ioctl,
963*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
964*4882a593Smuzhiyun .compat_ioctl32 = ov9750_compat_ioctl32,
965*4882a593Smuzhiyun #endif
966*4882a593Smuzhiyun };
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov9750_video_ops = {
969*4882a593Smuzhiyun .s_stream = ov9750_s_stream,
970*4882a593Smuzhiyun .g_frame_interval = ov9750_g_frame_interval,
971*4882a593Smuzhiyun .g_mbus_config = ov9750_g_mbus_config,
972*4882a593Smuzhiyun };
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov9750_pad_ops = {
975*4882a593Smuzhiyun .enum_mbus_code = ov9750_enum_mbus_code,
976*4882a593Smuzhiyun .enum_frame_size = ov9750_enum_frame_sizes,
977*4882a593Smuzhiyun .enum_frame_interval = ov9750_enum_frame_interval,
978*4882a593Smuzhiyun .get_fmt = ov9750_get_fmt,
979*4882a593Smuzhiyun .set_fmt = ov9750_set_fmt,
980*4882a593Smuzhiyun };
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov9750_subdev_ops = {
983*4882a593Smuzhiyun .core = &ov9750_core_ops,
984*4882a593Smuzhiyun .video = &ov9750_video_ops,
985*4882a593Smuzhiyun .pad = &ov9750_pad_ops,
986*4882a593Smuzhiyun };
987*4882a593Smuzhiyun
ov9750_set_ctrl(struct v4l2_ctrl * ctrl)988*4882a593Smuzhiyun static int ov9750_set_ctrl(struct v4l2_ctrl *ctrl)
989*4882a593Smuzhiyun {
990*4882a593Smuzhiyun struct ov9750 *ov9750 = container_of(ctrl->handler,
991*4882a593Smuzhiyun struct ov9750, ctrl_handler);
992*4882a593Smuzhiyun struct i2c_client *client = ov9750->client;
993*4882a593Smuzhiyun s64 max;
994*4882a593Smuzhiyun int ret = 0;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
997*4882a593Smuzhiyun switch (ctrl->id) {
998*4882a593Smuzhiyun case V4L2_CID_VBLANK:
999*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1000*4882a593Smuzhiyun max = ov9750->cur_mode->height + ctrl->val - 4;
1001*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov9750->exposure,
1002*4882a593Smuzhiyun ov9750->exposure->minimum, max,
1003*4882a593Smuzhiyun ov9750->exposure->step,
1004*4882a593Smuzhiyun ov9750->exposure->default_value);
1005*4882a593Smuzhiyun break;
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1009*4882a593Smuzhiyun return 0;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun switch (ctrl->id) {
1012*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1013*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
1014*4882a593Smuzhiyun ret = ov9750_write_reg(ov9750->client, OV9750_REG_EXPOSURE,
1015*4882a593Smuzhiyun OV9750_REG_VALUE_24BIT, ctrl->val << 4);
1016*4882a593Smuzhiyun break;
1017*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1018*4882a593Smuzhiyun ret = ov9750_write_reg(ov9750->client, OV9750_REG_GAIN_H,
1019*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT,
1020*4882a593Smuzhiyun (ctrl->val >> 8) & OV9750_GAIN_H_MASK);
1021*4882a593Smuzhiyun ret |= ov9750_write_reg(ov9750->client, OV9750_REG_GAIN_L,
1022*4882a593Smuzhiyun OV9750_REG_VALUE_08BIT,
1023*4882a593Smuzhiyun ctrl->val & OV9750_GAIN_L_MASK);
1024*4882a593Smuzhiyun break;
1025*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1026*4882a593Smuzhiyun ret = ov9750_write_reg(ov9750->client, OV9750_REG_VTS,
1027*4882a593Smuzhiyun OV9750_REG_VALUE_16BIT,
1028*4882a593Smuzhiyun ctrl->val + ov9750->cur_mode->height);
1029*4882a593Smuzhiyun break;
1030*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
1031*4882a593Smuzhiyun ret = ov9750_enable_test_pattern(ov9750, ctrl->val);
1032*4882a593Smuzhiyun break;
1033*4882a593Smuzhiyun default:
1034*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1035*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
1036*4882a593Smuzhiyun break;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun return ret;
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov9750_ctrl_ops = {
1045*4882a593Smuzhiyun .s_ctrl = ov9750_set_ctrl,
1046*4882a593Smuzhiyun };
1047*4882a593Smuzhiyun
ov9750_initialize_controls(struct ov9750 * ov9750)1048*4882a593Smuzhiyun static int ov9750_initialize_controls(struct ov9750 *ov9750)
1049*4882a593Smuzhiyun {
1050*4882a593Smuzhiyun const struct ov9750_mode *mode;
1051*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1052*4882a593Smuzhiyun struct v4l2_ctrl *ctrl;
1053*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1054*4882a593Smuzhiyun u32 h_blank;
1055*4882a593Smuzhiyun int ret;
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun handler = &ov9750->ctrl_handler;
1058*4882a593Smuzhiyun mode = ov9750->cur_mode;
1059*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 8);
1060*4882a593Smuzhiyun if (ret)
1061*4882a593Smuzhiyun return ret;
1062*4882a593Smuzhiyun handler->lock = &ov9750->mutex;
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1065*4882a593Smuzhiyun 0, 0, link_freq_menu_items);
1066*4882a593Smuzhiyun if (ctrl)
1067*4882a593Smuzhiyun ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1070*4882a593Smuzhiyun 0, OV9750_PIXEL_RATE, 1, OV9750_PIXEL_RATE);
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1073*4882a593Smuzhiyun ov9750->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1074*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1075*4882a593Smuzhiyun if (ov9750->hblank)
1076*4882a593Smuzhiyun ov9750->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1079*4882a593Smuzhiyun ov9750->vblank = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
1080*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1081*4882a593Smuzhiyun OV9750_VTS_MAX - mode->height,
1082*4882a593Smuzhiyun 1, vblank_def);
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun exposure_max = mode->vts_def - 4;
1085*4882a593Smuzhiyun ov9750->exposure = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
1086*4882a593Smuzhiyun V4L2_CID_EXPOSURE, OV9750_EXPOSURE_MIN,
1087*4882a593Smuzhiyun exposure_max, OV9750_EXPOSURE_STEP,
1088*4882a593Smuzhiyun mode->exp_def);
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun ov9750->anal_gain = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
1091*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN, OV9750_GAIN_MIN,
1092*4882a593Smuzhiyun OV9750_GAIN_MAX, OV9750_GAIN_STEP,
1093*4882a593Smuzhiyun OV9750_GAIN_DEFAULT);
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun ov9750->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1096*4882a593Smuzhiyun &ov9750_ctrl_ops, V4L2_CID_TEST_PATTERN,
1097*4882a593Smuzhiyun ARRAY_SIZE(ov9750_test_pattern_menu) - 1,
1098*4882a593Smuzhiyun 0, 0, ov9750_test_pattern_menu);
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun if (handler->error) {
1101*4882a593Smuzhiyun ret = handler->error;
1102*4882a593Smuzhiyun dev_err(&ov9750->client->dev,
1103*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1104*4882a593Smuzhiyun goto err_free_handler;
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun ov9750->subdev.ctrl_handler = handler;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun return 0;
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun err_free_handler:
1112*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun return ret;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
ov9750_check_sensor_id(struct ov9750 * ov9750,struct i2c_client * client)1117*4882a593Smuzhiyun static int ov9750_check_sensor_id(struct ov9750 *ov9750,
1118*4882a593Smuzhiyun struct i2c_client *client)
1119*4882a593Smuzhiyun {
1120*4882a593Smuzhiyun struct device *dev = &ov9750->client->dev;
1121*4882a593Smuzhiyun u32 id = 0;
1122*4882a593Smuzhiyun int ret;
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun ret = ov9750_read_reg(client, OV9750_REG_CHIP_ID,
1125*4882a593Smuzhiyun OV9750_REG_VALUE_16BIT, &id);
1126*4882a593Smuzhiyun if (id != CHIP_ID) {
1127*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1128*4882a593Smuzhiyun return -ENODEV;
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun dev_info(dev, "Detected OV%04x sensor\n", id);
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun return 0;
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
ov9750_configure_regulators(struct ov9750 * ov9750)1136*4882a593Smuzhiyun static int ov9750_configure_regulators(struct ov9750 *ov9750)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun unsigned int i;
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun for (i = 0; i < OV9750_NUM_SUPPLIES; i++)
1141*4882a593Smuzhiyun ov9750->supplies[i].supply = ov9750_supply_names[i];
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun return devm_regulator_bulk_get(&ov9750->client->dev,
1144*4882a593Smuzhiyun OV9750_NUM_SUPPLIES,
1145*4882a593Smuzhiyun ov9750->supplies);
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun
ov9750_probe(struct i2c_client * client,const struct i2c_device_id * id)1148*4882a593Smuzhiyun static int ov9750_probe(struct i2c_client *client,
1149*4882a593Smuzhiyun const struct i2c_device_id *id)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun struct device *dev = &client->dev;
1152*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1153*4882a593Smuzhiyun struct ov9750 *ov9750;
1154*4882a593Smuzhiyun struct v4l2_subdev *sd;
1155*4882a593Smuzhiyun char facing[2];
1156*4882a593Smuzhiyun int ret;
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1159*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1160*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1161*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun ov9750 = devm_kzalloc(dev, sizeof(*ov9750), GFP_KERNEL);
1164*4882a593Smuzhiyun if (!ov9750)
1165*4882a593Smuzhiyun return -ENOMEM;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1168*4882a593Smuzhiyun &ov9750->module_index);
1169*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1170*4882a593Smuzhiyun &ov9750->module_facing);
1171*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1172*4882a593Smuzhiyun &ov9750->module_name);
1173*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1174*4882a593Smuzhiyun &ov9750->len_name);
1175*4882a593Smuzhiyun if (ret) {
1176*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1177*4882a593Smuzhiyun return -EINVAL;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun ov9750->client = client;
1181*4882a593Smuzhiyun ov9750->cur_mode = &supported_modes[0];
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun ov9750->xvclk = devm_clk_get(dev, "xvclk");
1184*4882a593Smuzhiyun if (IS_ERR(ov9750->xvclk)) {
1185*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1186*4882a593Smuzhiyun return -EINVAL;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun ov9750->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1190*4882a593Smuzhiyun if (IS_ERR(ov9750->reset_gpio))
1191*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun ov9750->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1194*4882a593Smuzhiyun if (IS_ERR(ov9750->pwdn_gpio))
1195*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun ov9750->pinctrl = devm_pinctrl_get(dev);
1198*4882a593Smuzhiyun if (!IS_ERR(ov9750->pinctrl)) {
1199*4882a593Smuzhiyun ov9750->pins_default =
1200*4882a593Smuzhiyun pinctrl_lookup_state(ov9750->pinctrl,
1201*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
1202*4882a593Smuzhiyun if (IS_ERR(ov9750->pins_default))
1203*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun ov9750->pins_sleep =
1206*4882a593Smuzhiyun pinctrl_lookup_state(ov9750->pinctrl,
1207*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
1208*4882a593Smuzhiyun if (IS_ERR(ov9750->pins_sleep))
1209*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1210*4882a593Smuzhiyun } else {
1211*4882a593Smuzhiyun dev_err(dev, "no pinctrl\n");
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun ret = ov9750_configure_regulators(ov9750);
1215*4882a593Smuzhiyun if (ret) {
1216*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1217*4882a593Smuzhiyun return ret;
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun mutex_init(&ov9750->mutex);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun sd = &ov9750->subdev;
1223*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &ov9750_subdev_ops);
1224*4882a593Smuzhiyun ret = ov9750_initialize_controls(ov9750);
1225*4882a593Smuzhiyun if (ret)
1226*4882a593Smuzhiyun goto err_destroy_mutex;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun ret = __ov9750_power_on(ov9750);
1229*4882a593Smuzhiyun if (ret)
1230*4882a593Smuzhiyun goto err_free_handler;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun ret = ov9750_check_sensor_id(ov9750, client);
1233*4882a593Smuzhiyun if (ret)
1234*4882a593Smuzhiyun goto err_power_off;
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1237*4882a593Smuzhiyun sd->internal_ops = &ov9750_internal_ops;
1238*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1239*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
1240*4882a593Smuzhiyun #endif
1241*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1242*4882a593Smuzhiyun ov9750->pad.flags = MEDIA_PAD_FL_SOURCE;
1243*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1244*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &ov9750->pad);
1245*4882a593Smuzhiyun if (ret < 0)
1246*4882a593Smuzhiyun goto err_power_off;
1247*4882a593Smuzhiyun #endif
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1250*4882a593Smuzhiyun if (strcmp(ov9750->module_facing, "back") == 0)
1251*4882a593Smuzhiyun facing[0] = 'b';
1252*4882a593Smuzhiyun else
1253*4882a593Smuzhiyun facing[0] = 'f';
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1256*4882a593Smuzhiyun ov9750->module_index, facing,
1257*4882a593Smuzhiyun OV9750_NAME, dev_name(sd->dev));
1258*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1259*4882a593Smuzhiyun if (ret) {
1260*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1261*4882a593Smuzhiyun goto err_clean_entity;
1262*4882a593Smuzhiyun }
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun pm_runtime_set_active(dev);
1265*4882a593Smuzhiyun pm_runtime_enable(dev);
1266*4882a593Smuzhiyun pm_runtime_idle(dev);
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun return 0;
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun err_clean_entity:
1271*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1272*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1273*4882a593Smuzhiyun #endif
1274*4882a593Smuzhiyun err_power_off:
1275*4882a593Smuzhiyun __ov9750_power_off(ov9750);
1276*4882a593Smuzhiyun err_free_handler:
1277*4882a593Smuzhiyun v4l2_ctrl_handler_free(&ov9750->ctrl_handler);
1278*4882a593Smuzhiyun err_destroy_mutex:
1279*4882a593Smuzhiyun mutex_destroy(&ov9750->mutex);
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun return ret;
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun
ov9750_remove(struct i2c_client * client)1284*4882a593Smuzhiyun static int ov9750_remove(struct i2c_client *client)
1285*4882a593Smuzhiyun {
1286*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1287*4882a593Smuzhiyun struct ov9750 *ov9750 = to_ov9750(sd);
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1290*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1291*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1292*4882a593Smuzhiyun #endif
1293*4882a593Smuzhiyun v4l2_ctrl_handler_free(&ov9750->ctrl_handler);
1294*4882a593Smuzhiyun mutex_destroy(&ov9750->mutex);
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1297*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1298*4882a593Smuzhiyun __ov9750_power_off(ov9750);
1299*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun return 0;
1302*4882a593Smuzhiyun }
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1305*4882a593Smuzhiyun static const struct of_device_id ov9750_of_match[] = {
1306*4882a593Smuzhiyun { .compatible = "ovti,ov9750" },
1307*4882a593Smuzhiyun {},
1308*4882a593Smuzhiyun };
1309*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ov9750_of_match);
1310*4882a593Smuzhiyun #endif
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun static const struct i2c_device_id ov9750_match_id[] = {
1313*4882a593Smuzhiyun { "ovti,ov9750", 0 },
1314*4882a593Smuzhiyun { },
1315*4882a593Smuzhiyun };
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun static struct i2c_driver ov9750_i2c_driver = {
1318*4882a593Smuzhiyun .driver = {
1319*4882a593Smuzhiyun .name = OV9750_NAME,
1320*4882a593Smuzhiyun .pm = &ov9750_pm_ops,
1321*4882a593Smuzhiyun .of_match_table = of_match_ptr(ov9750_of_match),
1322*4882a593Smuzhiyun },
1323*4882a593Smuzhiyun .probe = &ov9750_probe,
1324*4882a593Smuzhiyun .remove = &ov9750_remove,
1325*4882a593Smuzhiyun .id_table = ov9750_match_id,
1326*4882a593Smuzhiyun };
1327*4882a593Smuzhiyun
sensor_mod_init(void)1328*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1329*4882a593Smuzhiyun {
1330*4882a593Smuzhiyun return i2c_add_driver(&ov9750_i2c_driver);
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun
sensor_mod_exit(void)1333*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1334*4882a593Smuzhiyun {
1335*4882a593Smuzhiyun i2c_del_driver(&ov9750_i2c_driver);
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1339*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun MODULE_DESCRIPTION("OmniVision ov9750 sensor driver");
1342*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1343