1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ov7750 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X01 add poweron function.
8*4882a593Smuzhiyun * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9*4882a593Smuzhiyun * V0.0X01.0X03 add enum_frame_interval function.
10*4882a593Smuzhiyun * V0.0X01.0X04 add quick stream on/off
11*4882a593Smuzhiyun * V0.0X01.0X05 add function g_mbus_config
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/device.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/pm_runtime.h>
21*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
22*4882a593Smuzhiyun #include <linux/sysfs.h>
23*4882a593Smuzhiyun #include <linux/slab.h>
24*4882a593Smuzhiyun #include <linux/version.h>
25*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
26*4882a593Smuzhiyun #include <media/media-entity.h>
27*4882a593Smuzhiyun #include <media/v4l2-async.h>
28*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
29*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
30*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
35*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36*4882a593Smuzhiyun #endif
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* 45Mhz * 4 Binning */
39*4882a593Smuzhiyun #define OV7750_PIXEL_RATE (49 * 1000 * 1000)
40*4882a593Smuzhiyun #define OV7750_XVCLK_FREQ 24000000
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define CHIP_ID 0x7750
43*4882a593Smuzhiyun #define OV7750_REG_CHIP_ID 0x300a
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define OV7750_REG_CTRL_MODE 0x0100
46*4882a593Smuzhiyun #define OV7750_MODE_SW_STANDBY 0x0
47*4882a593Smuzhiyun #define OV7750_MODE_STREAMING BIT(0)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define OV7750_REG_EXPOSURE 0x3500
50*4882a593Smuzhiyun #define OV7750_EXPOSURE_MIN 4
51*4882a593Smuzhiyun #define OV7750_EXPOSURE_STEP 1
52*4882a593Smuzhiyun #define OV7750_VTS_MAX 0x7fff
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define OV7750_REG_GAIN_H 0x350a
55*4882a593Smuzhiyun #define OV7750_REG_GAIN_L 0x350b
56*4882a593Smuzhiyun #define OV7750_GAIN_H_MASK 0x07
57*4882a593Smuzhiyun #define OV7750_GAIN_H_SHIFT 8
58*4882a593Smuzhiyun #define OV7750_GAIN_L_MASK 0xff
59*4882a593Smuzhiyun #define OV7750_GAIN_MIN 0x10
60*4882a593Smuzhiyun #define OV7750_GAIN_MAX 0xf8
61*4882a593Smuzhiyun #define OV7750_GAIN_STEP 1
62*4882a593Smuzhiyun #define OV7750_GAIN_DEFAULT 0x10
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define OV7750_REG_TEST_PATTERN 0x5e00
65*4882a593Smuzhiyun #define OV7750_TEST_PATTERN_ENABLE 0x80
66*4882a593Smuzhiyun #define OV7750_TEST_PATTERN_DISABLE 0x0
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define OV7750_REG_VTS 0x380e
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define REG_NULL 0xFFFF
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define OV7750_REG_VALUE_08BIT 1
73*4882a593Smuzhiyun #define OV7750_REG_VALUE_16BIT 2
74*4882a593Smuzhiyun #define OV7750_REG_VALUE_24BIT 3
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define OV7750_BITS_PER_SAMPLE 10
77*4882a593Smuzhiyun #define OV7750_REG_MANUAL_CTL 0x3503
78*4882a593Smuzhiyun #define OV7750_CHIP_REVISION_REG 0x3029
79*4882a593Smuzhiyun #define OV7750_R1F 0x70
80*4882a593Smuzhiyun #define OV7750_EXP_MARGIN_LIMIT 10
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_DEFAULT "rockchip,camera_default"
83*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_SLEEP "rockchip,camera_sleep"
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define OV7750_NAME "ov7750"
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define OV7750_LANES 1
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct regval *ov7750_global_regs;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const char * const ov7750_supply_names[] = {
92*4882a593Smuzhiyun "avdd", /* Analog power */
93*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
94*4882a593Smuzhiyun "dvdd", /* Digital core power */
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define OV7750_NUM_SUPPLIES ARRAY_SIZE(ov7750_supply_names)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct regval {
100*4882a593Smuzhiyun u16 addr;
101*4882a593Smuzhiyun u8 val;
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun struct ov7750_mode {
105*4882a593Smuzhiyun u32 width;
106*4882a593Smuzhiyun u32 height;
107*4882a593Smuzhiyun struct v4l2_fract max_fps;
108*4882a593Smuzhiyun u32 hts_def;
109*4882a593Smuzhiyun u32 vts_def;
110*4882a593Smuzhiyun u32 exp_def;
111*4882a593Smuzhiyun const struct regval *reg_list;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct ov7750 {
115*4882a593Smuzhiyun struct i2c_client *client;
116*4882a593Smuzhiyun struct clk *xvclk;
117*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
118*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
119*4882a593Smuzhiyun struct regulator_bulk_data supplies[OV7750_NUM_SUPPLIES];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct pinctrl *pinctrl;
122*4882a593Smuzhiyun struct pinctrl_state *pins_default;
123*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun struct v4l2_subdev subdev;
126*4882a593Smuzhiyun struct media_pad pad;
127*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
128*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
129*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
130*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
131*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
132*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
133*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
134*4882a593Smuzhiyun struct mutex mutex;
135*4882a593Smuzhiyun bool streaming;
136*4882a593Smuzhiyun bool power_on;
137*4882a593Smuzhiyun const struct ov7750_mode *cur_mode;
138*4882a593Smuzhiyun u32 module_index;
139*4882a593Smuzhiyun const char *module_facing;
140*4882a593Smuzhiyun const char *module_name;
141*4882a593Smuzhiyun const char *len_name;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define to_ov7750(sd) container_of(sd, struct ov7750, subdev)
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * Rev: 1F
148*4882a593Smuzhiyun * Xclk 24Mhz
149*4882a593Smuzhiyun */
150*4882a593Smuzhiyun static const struct regval ov7750_global_regs_r1f[] = {
151*4882a593Smuzhiyun {0x0103, 0x01},
152*4882a593Smuzhiyun {0x0100, 0x00},
153*4882a593Smuzhiyun {0x3005, 0x00},
154*4882a593Smuzhiyun {0x3012, 0xc0},
155*4882a593Smuzhiyun {0x3013, 0xd2},
156*4882a593Smuzhiyun {0x3014, 0x04},
157*4882a593Smuzhiyun {0x3016, 0x10},
158*4882a593Smuzhiyun {0x3017, 0x00},
159*4882a593Smuzhiyun {0x3018, 0x00},
160*4882a593Smuzhiyun {0x301a, 0x00},
161*4882a593Smuzhiyun {0x301b, 0x00},
162*4882a593Smuzhiyun {0x301c, 0x00},
163*4882a593Smuzhiyun {0x3023, 0x05},
164*4882a593Smuzhiyun {0x3037, 0xf0},
165*4882a593Smuzhiyun {0x3098, 0x04},
166*4882a593Smuzhiyun {0x3099, 0x28},
167*4882a593Smuzhiyun {0x309a, 0x05},
168*4882a593Smuzhiyun {0x309b, 0x04},
169*4882a593Smuzhiyun {0x30b0, 0x0a},
170*4882a593Smuzhiyun {0x30b1, 0x01},
171*4882a593Smuzhiyun {0x30b3, 0x64},
172*4882a593Smuzhiyun {0x30b4, 0x03},
173*4882a593Smuzhiyun {0x30b5, 0x05},
174*4882a593Smuzhiyun {0x3106, 0xda},
175*4882a593Smuzhiyun {0x3500, 0x00},
176*4882a593Smuzhiyun {0x3501, 0x1f},
177*4882a593Smuzhiyun {0x3502, 0x80},
178*4882a593Smuzhiyun {0x3503, 0x07},
179*4882a593Smuzhiyun {0x3509, 0x10},
180*4882a593Smuzhiyun {0x350b, 0x10},
181*4882a593Smuzhiyun {0x3600, 0x1c},
182*4882a593Smuzhiyun {0x3602, 0x62},
183*4882a593Smuzhiyun {0x3620, 0xb7},
184*4882a593Smuzhiyun {0x3622, 0x04},
185*4882a593Smuzhiyun {0x3626, 0x21},
186*4882a593Smuzhiyun {0x3627, 0x30},
187*4882a593Smuzhiyun {0x3630, 0x44},
188*4882a593Smuzhiyun {0x3631, 0x35},
189*4882a593Smuzhiyun {0x3634, 0x60},
190*4882a593Smuzhiyun {0x3636, 0x00},
191*4882a593Smuzhiyun {0x3662, 0x01},
192*4882a593Smuzhiyun {0x3663, 0x70},
193*4882a593Smuzhiyun {0x3664, 0xf0},
194*4882a593Smuzhiyun {0x3666, 0x0a},
195*4882a593Smuzhiyun {0x3669, 0x1a},
196*4882a593Smuzhiyun {0x366a, 0x00},
197*4882a593Smuzhiyun {0x366b, 0x50},
198*4882a593Smuzhiyun {0x3673, 0x01},
199*4882a593Smuzhiyun {0x3674, 0xff},
200*4882a593Smuzhiyun {0x3675, 0x03},
201*4882a593Smuzhiyun {0x3705, 0xc1},
202*4882a593Smuzhiyun {0x3709, 0x40},
203*4882a593Smuzhiyun {0x373c, 0x08},
204*4882a593Smuzhiyun {0x3742, 0x00},
205*4882a593Smuzhiyun {0x3757, 0xb3},
206*4882a593Smuzhiyun {0x3788, 0x00},
207*4882a593Smuzhiyun {0x37a8, 0x01},
208*4882a593Smuzhiyun {0x37a9, 0xc0},
209*4882a593Smuzhiyun {0x3800, 0x00},
210*4882a593Smuzhiyun {0x3801, 0x04},
211*4882a593Smuzhiyun {0x3802, 0x00},
212*4882a593Smuzhiyun {0x3803, 0x04},
213*4882a593Smuzhiyun {0x3804, 0x02},
214*4882a593Smuzhiyun {0x3805, 0x8b},
215*4882a593Smuzhiyun {0x3806, 0x01},
216*4882a593Smuzhiyun {0x3807, 0xeb},
217*4882a593Smuzhiyun {0x3808, 0x02},
218*4882a593Smuzhiyun {0x3809, 0x80},
219*4882a593Smuzhiyun {0x380a, 0x01},
220*4882a593Smuzhiyun {0x380b, 0xe0},
221*4882a593Smuzhiyun /* line length_pclk */
222*4882a593Smuzhiyun {0x380c, 0x03}, //{0x380c, 0x03},
223*4882a593Smuzhiyun {0x380d, 0xa0}, //{0x380d, 0x10},
224*4882a593Smuzhiyun /* frame_length_line */
225*4882a593Smuzhiyun {0x380e, 0x07}, //{0x380e, 0x02},
226*4882a593Smuzhiyun {0x380f, 0xd0}, //{0x380f, 0x00},
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun {0x3810, 0x00},
229*4882a593Smuzhiyun {0x3811, 0x04},
230*4882a593Smuzhiyun {0x3812, 0x00},
231*4882a593Smuzhiyun {0x3813, 0x05},
232*4882a593Smuzhiyun {0x3814, 0x11},
233*4882a593Smuzhiyun {0x3815, 0x11},
234*4882a593Smuzhiyun {0x3820, 0x40},
235*4882a593Smuzhiyun {0x3821, 0x00},
236*4882a593Smuzhiyun {0x382f, 0x0e},
237*4882a593Smuzhiyun {0x3832, 0x00},
238*4882a593Smuzhiyun {0x3833, 0x05},
239*4882a593Smuzhiyun {0x3834, 0x00},
240*4882a593Smuzhiyun {0x3835, 0x0c},
241*4882a593Smuzhiyun {0x3837, 0x00},
242*4882a593Smuzhiyun {0x3b80, 0x00},
243*4882a593Smuzhiyun {0x3b81, 0xa5},
244*4882a593Smuzhiyun {0x3b82, 0x10},
245*4882a593Smuzhiyun {0x3b83, 0x00},
246*4882a593Smuzhiyun {0x3b84, 0x08},
247*4882a593Smuzhiyun {0x3b85, 0x00},
248*4882a593Smuzhiyun {0x3b86, 0x01},
249*4882a593Smuzhiyun {0x3b87, 0x00},
250*4882a593Smuzhiyun {0x3b88, 0x00},
251*4882a593Smuzhiyun {0x3b89, 0x00},
252*4882a593Smuzhiyun {0x3b8a, 0x00},
253*4882a593Smuzhiyun {0x3b8b, 0x05},
254*4882a593Smuzhiyun {0x3b8c, 0x00},
255*4882a593Smuzhiyun {0x3b8d, 0x00},
256*4882a593Smuzhiyun {0x3b8e, 0x00},
257*4882a593Smuzhiyun {0x3b8f, 0x1a},
258*4882a593Smuzhiyun {0x3b94, 0x05},
259*4882a593Smuzhiyun {0x3b95, 0xf2},
260*4882a593Smuzhiyun {0x3b96, 0x40},
261*4882a593Smuzhiyun {0x3c00, 0x89},
262*4882a593Smuzhiyun {0x3c01, 0x63},
263*4882a593Smuzhiyun {0x3c02, 0x01},
264*4882a593Smuzhiyun {0x3c03, 0x00},
265*4882a593Smuzhiyun {0x3c04, 0x00},
266*4882a593Smuzhiyun {0x3c05, 0x03},
267*4882a593Smuzhiyun {0x3c06, 0x00},
268*4882a593Smuzhiyun {0x3c07, 0x06},
269*4882a593Smuzhiyun {0x3c0c, 0x01},
270*4882a593Smuzhiyun {0x3c0d, 0xd0},
271*4882a593Smuzhiyun {0x3c0e, 0x02},
272*4882a593Smuzhiyun {0x3c0f, 0x04},
273*4882a593Smuzhiyun {0x4001, 0x42},
274*4882a593Smuzhiyun {0x4004, 0x04},
275*4882a593Smuzhiyun {0x4005, 0x00},
276*4882a593Smuzhiyun {0x404e, 0x01},
277*4882a593Smuzhiyun {0x4241, 0x00},
278*4882a593Smuzhiyun {0x4242, 0x00},
279*4882a593Smuzhiyun {0x4300, 0xff},
280*4882a593Smuzhiyun {0x4301, 0x00},
281*4882a593Smuzhiyun {0x4501, 0x48},
282*4882a593Smuzhiyun {0x4600, 0x00},
283*4882a593Smuzhiyun {0x4601, 0x4e},
284*4882a593Smuzhiyun {0x4801, 0x0f},
285*4882a593Smuzhiyun {0x4806, 0x0f},
286*4882a593Smuzhiyun {0x4819, 0xaa},
287*4882a593Smuzhiyun {0x4823, 0x3e},
288*4882a593Smuzhiyun {0x4837, 0x19},
289*4882a593Smuzhiyun {0x4a0d, 0x00},
290*4882a593Smuzhiyun {0x4a47, 0x7f},
291*4882a593Smuzhiyun {0x4a49, 0xf0},
292*4882a593Smuzhiyun {0x4a4b, 0x30},
293*4882a593Smuzhiyun {0x5000, 0x85},
294*4882a593Smuzhiyun {0x5001, 0x80},
295*4882a593Smuzhiyun {REG_NULL, 0x00}
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /*
299*4882a593Smuzhiyun * Rev: xx
300*4882a593Smuzhiyun * Xclk 24Mhz
301*4882a593Smuzhiyun */
302*4882a593Smuzhiyun static const struct regval ov7750_global_regs_rxx[] = {
303*4882a593Smuzhiyun {REG_NULL, 0x00}
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /*
307*4882a593Smuzhiyun * Xclk 24Mhz
308*4882a593Smuzhiyun * max_framerate 60fps
309*4882a593Smuzhiyun * mipi_datarate per lane 400Mbps
310*4882a593Smuzhiyun */
311*4882a593Smuzhiyun static const struct regval ov7750_640x480_regs[] = {
312*4882a593Smuzhiyun {0x3500, 0x00},
313*4882a593Smuzhiyun {0x3501, 0x1f},
314*4882a593Smuzhiyun {0x3502, 0x80},
315*4882a593Smuzhiyun {0x3503, 0x07},
316*4882a593Smuzhiyun {0x3509, 0x10},
317*4882a593Smuzhiyun {0x350b, 0x10},
318*4882a593Smuzhiyun {0x3600, 0x1c},
319*4882a593Smuzhiyun {0x3602, 0x62},
320*4882a593Smuzhiyun {0x3620, 0xb7},
321*4882a593Smuzhiyun {0x3622, 0x04},
322*4882a593Smuzhiyun {0x3626, 0x21},
323*4882a593Smuzhiyun {0x3627, 0x30},
324*4882a593Smuzhiyun {0x3630, 0x44},
325*4882a593Smuzhiyun {0x3631, 0x35},
326*4882a593Smuzhiyun {0x3634, 0x60},
327*4882a593Smuzhiyun {0x3636, 0x00},
328*4882a593Smuzhiyun {0x3662, 0x01},
329*4882a593Smuzhiyun {0x3663, 0x70},
330*4882a593Smuzhiyun {0x3664, 0xf0},
331*4882a593Smuzhiyun {0x3666, 0x0a},
332*4882a593Smuzhiyun {0x3669, 0x1a},
333*4882a593Smuzhiyun {0x366a, 0x00},
334*4882a593Smuzhiyun {0x366b, 0x50},
335*4882a593Smuzhiyun {0x3673, 0x01},
336*4882a593Smuzhiyun {0x3674, 0xff},
337*4882a593Smuzhiyun {0x3675, 0x03},
338*4882a593Smuzhiyun {0x3705, 0xc1},
339*4882a593Smuzhiyun {0x3709, 0x40},
340*4882a593Smuzhiyun {0x373c, 0x08},
341*4882a593Smuzhiyun {0x3742, 0x00},
342*4882a593Smuzhiyun {0x3757, 0xb3},
343*4882a593Smuzhiyun {0x3788, 0x00},
344*4882a593Smuzhiyun {0x37a8, 0x01},
345*4882a593Smuzhiyun {0x37a9, 0xc0},
346*4882a593Smuzhiyun /* vga */
347*4882a593Smuzhiyun {0x3800, 0x00},
348*4882a593Smuzhiyun {0x3801, 0x04},
349*4882a593Smuzhiyun {0x3802, 0x00},
350*4882a593Smuzhiyun {0x3803, 0x04},
351*4882a593Smuzhiyun {0x3804, 0x02},
352*4882a593Smuzhiyun {0x3805, 0x8b},
353*4882a593Smuzhiyun {0x3806, 0x01},
354*4882a593Smuzhiyun {0x3807, 0xeb},
355*4882a593Smuzhiyun /* vaga end */
356*4882a593Smuzhiyun {0x3808, 0x02},
357*4882a593Smuzhiyun {0x3809, 0x80},
358*4882a593Smuzhiyun {0x380a, 0x01},
359*4882a593Smuzhiyun {0x380b, 0xe0},
360*4882a593Smuzhiyun {0x380c, 0x03},
361*4882a593Smuzhiyun {0x380d, 0xa0},
362*4882a593Smuzhiyun {0x380e, 0x07},
363*4882a593Smuzhiyun {0x380f, 0xd0},
364*4882a593Smuzhiyun {0x3810, 0x00},
365*4882a593Smuzhiyun {0x3811, 0x04},
366*4882a593Smuzhiyun {0x3812, 0x00},
367*4882a593Smuzhiyun {0x3813, 0x05},
368*4882a593Smuzhiyun {0x3814, 0x11},
369*4882a593Smuzhiyun {0x3815, 0x11},
370*4882a593Smuzhiyun {0x3820, 0x40},
371*4882a593Smuzhiyun {0x3821, 0x00},
372*4882a593Smuzhiyun {0x382f, 0x0e},
373*4882a593Smuzhiyun {0x3832, 0x00},
374*4882a593Smuzhiyun {0x3833, 0x05},
375*4882a593Smuzhiyun {0x3834, 0x00},
376*4882a593Smuzhiyun {0x3835, 0x0c},
377*4882a593Smuzhiyun {0x3837, 0x00},
378*4882a593Smuzhiyun {REG_NULL, 0x00}
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun static const struct ov7750_mode supported_modes[] = {
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun .width = 640,
384*4882a593Smuzhiyun .height = 480,
385*4882a593Smuzhiyun .max_fps = {
386*4882a593Smuzhiyun .numerator = 10000,
387*4882a593Smuzhiyun .denominator = 600000,
388*4882a593Smuzhiyun },
389*4882a593Smuzhiyun .exp_def = 0x0200,
390*4882a593Smuzhiyun .hts_def = 0x03a0,
391*4882a593Smuzhiyun .vts_def = 0x07d0,
392*4882a593Smuzhiyun .reg_list = ov7750_640x480_regs,
393*4882a593Smuzhiyun },
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun #define OV7750_LINK_FREQ_400MHZ 400000000
397*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
398*4882a593Smuzhiyun OV7750_LINK_FREQ_400MHZ
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun static const char * const ov7750_test_pattern_menu[] = {
402*4882a593Smuzhiyun "Disabled",
403*4882a593Smuzhiyun "Vertical Color Bar Type 1",
404*4882a593Smuzhiyun "Vertical Color Bar Type 2",
405*4882a593Smuzhiyun "Vertical Color Bar Type 3",
406*4882a593Smuzhiyun "Vertical Color Bar Type 4"
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /* Write registers up to 4 at a time */
ov7750_write_reg(struct i2c_client * client,u16 reg,int len,u32 val)410*4882a593Smuzhiyun static int ov7750_write_reg(struct i2c_client *client, u16 reg,
411*4882a593Smuzhiyun int len, u32 val)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun u32 buf_i, val_i;
414*4882a593Smuzhiyun u8 buf[6];
415*4882a593Smuzhiyun u8 *val_p;
416*4882a593Smuzhiyun __be32 val_be;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (len > 4)
419*4882a593Smuzhiyun return -EINVAL;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun buf[0] = reg >> 8;
422*4882a593Smuzhiyun buf[1] = reg & 0xff;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun val_be = cpu_to_be32(val);
425*4882a593Smuzhiyun val_p = (u8 *)&val_be;
426*4882a593Smuzhiyun buf_i = 2;
427*4882a593Smuzhiyun val_i = 4 - len;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun while (val_i < 4)
430*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
433*4882a593Smuzhiyun return -EIO;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
ov7750_write_array(struct i2c_client * client,const struct regval * regs)438*4882a593Smuzhiyun static int ov7750_write_array(struct i2c_client *client,
439*4882a593Smuzhiyun const struct regval *regs)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun u32 i;
442*4882a593Smuzhiyun int ret = 0;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
445*4882a593Smuzhiyun ret = ov7750_write_reg(client, regs[i].addr,
446*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
447*4882a593Smuzhiyun regs[i].val);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun return ret;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /* Read registers up to 4 at a time */
ov7750_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)453*4882a593Smuzhiyun static int ov7750_read_reg(struct i2c_client *client, u16 reg,
454*4882a593Smuzhiyun unsigned int len, u32 *val)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun struct i2c_msg msgs[2];
457*4882a593Smuzhiyun u8 *data_be_p;
458*4882a593Smuzhiyun __be32 data_be = 0;
459*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
460*4882a593Smuzhiyun int ret;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (len > 4 || !len)
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
466*4882a593Smuzhiyun /* Write register address */
467*4882a593Smuzhiyun msgs[0].addr = client->addr;
468*4882a593Smuzhiyun msgs[0].flags = 0;
469*4882a593Smuzhiyun msgs[0].len = 2;
470*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /* Read data from register */
473*4882a593Smuzhiyun msgs[1].addr = client->addr;
474*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
475*4882a593Smuzhiyun msgs[1].len = len;
476*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
479*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
480*4882a593Smuzhiyun return -EIO;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
ov7750_get_reso_dist(const struct ov7750_mode * mode,struct v4l2_mbus_framefmt * framefmt)487*4882a593Smuzhiyun static int ov7750_get_reso_dist(const struct ov7750_mode *mode,
488*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
491*4882a593Smuzhiyun abs(mode->height - framefmt->height);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun static const struct ov7750_mode *
ov7750_find_best_fit(struct v4l2_subdev_format * fmt)495*4882a593Smuzhiyun ov7750_find_best_fit(struct v4l2_subdev_format *fmt)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
498*4882a593Smuzhiyun int dist;
499*4882a593Smuzhiyun int cur_best_fit = 0;
500*4882a593Smuzhiyun int cur_best_fit_dist = -1;
501*4882a593Smuzhiyun unsigned int i;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
504*4882a593Smuzhiyun dist = ov7750_get_reso_dist(&supported_modes[i], framefmt);
505*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
506*4882a593Smuzhiyun cur_best_fit_dist = dist;
507*4882a593Smuzhiyun cur_best_fit = i;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
ov7750_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)514*4882a593Smuzhiyun static int ov7750_set_fmt(struct v4l2_subdev *sd,
515*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
516*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
519*4882a593Smuzhiyun const struct ov7750_mode *mode;
520*4882a593Smuzhiyun s64 h_blank, vblank_def;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun mode = ov7750_find_best_fit(fmt);
525*4882a593Smuzhiyun fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
526*4882a593Smuzhiyun fmt->format.width = mode->width;
527*4882a593Smuzhiyun fmt->format.height = mode->height;
528*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
529*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
530*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
531*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
532*4882a593Smuzhiyun #else
533*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
534*4882a593Smuzhiyun return -ENOTTY;
535*4882a593Smuzhiyun #endif
536*4882a593Smuzhiyun } else {
537*4882a593Smuzhiyun ov7750->cur_mode = mode;
538*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
539*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov7750->hblank, h_blank,
540*4882a593Smuzhiyun h_blank, 1, h_blank);
541*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
542*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov7750->vblank, vblank_def,
543*4882a593Smuzhiyun OV7750_VTS_MAX - mode->height,
544*4882a593Smuzhiyun 1, vblank_def);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun return 0;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
ov7750_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)552*4882a593Smuzhiyun static int ov7750_get_fmt(struct v4l2_subdev *sd,
553*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
554*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
557*4882a593Smuzhiyun const struct ov7750_mode *mode = ov7750->cur_mode;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
560*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
561*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
562*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
563*4882a593Smuzhiyun #else
564*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
565*4882a593Smuzhiyun return -ENOTTY;
566*4882a593Smuzhiyun #endif
567*4882a593Smuzhiyun } else {
568*4882a593Smuzhiyun fmt->format.width = mode->width;
569*4882a593Smuzhiyun fmt->format.height = mode->height;
570*4882a593Smuzhiyun fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
571*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun return 0;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
ov7750_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)578*4882a593Smuzhiyun static int ov7750_enum_mbus_code(struct v4l2_subdev *sd,
579*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
580*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun if (code->index != 0)
583*4882a593Smuzhiyun return -EINVAL;
584*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
ov7750_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)589*4882a593Smuzhiyun static int ov7750_enum_frame_sizes(struct v4l2_subdev *sd,
590*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
591*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
594*4882a593Smuzhiyun return -EINVAL;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
597*4882a593Smuzhiyun return -EINVAL;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
600*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
601*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
602*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun return 0;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
ov7750_enable_test_pattern(struct ov7750 * ov7750,u32 pattern)607*4882a593Smuzhiyun static int ov7750_enable_test_pattern(struct ov7750 *ov7750, u32 pattern)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun u32 val;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun if (pattern)
612*4882a593Smuzhiyun val = (pattern - 1) | OV7750_TEST_PATTERN_ENABLE;
613*4882a593Smuzhiyun else
614*4882a593Smuzhiyun val = OV7750_TEST_PATTERN_DISABLE;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return ov7750_write_reg(ov7750->client,
617*4882a593Smuzhiyun OV7750_REG_TEST_PATTERN,
618*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
619*4882a593Smuzhiyun val);
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
ov7750_get_module_inf(struct ov7750 * ov7750,struct rkmodule_inf * inf)622*4882a593Smuzhiyun static void ov7750_get_module_inf(struct ov7750 *ov7750,
623*4882a593Smuzhiyun struct rkmodule_inf *inf)
624*4882a593Smuzhiyun {
625*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
626*4882a593Smuzhiyun strlcpy(inf->base.sensor, OV7750_NAME, sizeof(inf->base.sensor));
627*4882a593Smuzhiyun strlcpy(inf->base.module, ov7750->module_name,
628*4882a593Smuzhiyun sizeof(inf->base.module));
629*4882a593Smuzhiyun strlcpy(inf->base.lens, ov7750->len_name, sizeof(inf->base.lens));
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
ov7750_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)632*4882a593Smuzhiyun static long ov7750_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
635*4882a593Smuzhiyun long ret = 0;
636*4882a593Smuzhiyun u32 stream = 0;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun switch (cmd) {
639*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
640*4882a593Smuzhiyun ov7750_get_module_inf(ov7750, (struct rkmodule_inf *)arg);
641*4882a593Smuzhiyun break;
642*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun stream = *((u32 *)arg);
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun if (stream)
647*4882a593Smuzhiyun ret = ov7750_write_reg(ov7750->client,
648*4882a593Smuzhiyun OV7750_REG_CTRL_MODE,
649*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
650*4882a593Smuzhiyun OV7750_MODE_STREAMING);
651*4882a593Smuzhiyun else
652*4882a593Smuzhiyun ret = ov7750_write_reg(ov7750->client,
653*4882a593Smuzhiyun OV7750_REG_CTRL_MODE,
654*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
655*4882a593Smuzhiyun OV7750_MODE_SW_STANDBY);
656*4882a593Smuzhiyun break;
657*4882a593Smuzhiyun default:
658*4882a593Smuzhiyun ret = -ENOTTY;
659*4882a593Smuzhiyun break;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun return ret;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
ov7750_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)666*4882a593Smuzhiyun static long ov7750_compat_ioctl32(struct v4l2_subdev *sd,
667*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
670*4882a593Smuzhiyun struct rkmodule_inf *inf;
671*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
672*4882a593Smuzhiyun long ret;
673*4882a593Smuzhiyun u32 stream = 0;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun switch (cmd) {
676*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
677*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
678*4882a593Smuzhiyun if (!inf) {
679*4882a593Smuzhiyun ret = -ENOMEM;
680*4882a593Smuzhiyun return ret;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun ret = ov7750_ioctl(sd, cmd, inf);
684*4882a593Smuzhiyun if (!ret)
685*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
686*4882a593Smuzhiyun kfree(inf);
687*4882a593Smuzhiyun break;
688*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
689*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
690*4882a593Smuzhiyun if (!cfg) {
691*4882a593Smuzhiyun ret = -ENOMEM;
692*4882a593Smuzhiyun return ret;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
696*4882a593Smuzhiyun if (!ret)
697*4882a593Smuzhiyun ret = ov7750_ioctl(sd, cmd, cfg);
698*4882a593Smuzhiyun kfree(cfg);
699*4882a593Smuzhiyun break;
700*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
701*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
702*4882a593Smuzhiyun if (!ret)
703*4882a593Smuzhiyun ret = ov7750_ioctl(sd, cmd, &stream);
704*4882a593Smuzhiyun break;
705*4882a593Smuzhiyun default:
706*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
707*4882a593Smuzhiyun break;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun return ret;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun #endif
713*4882a593Smuzhiyun
__ov7750_start_stream(struct ov7750 * ov7750)714*4882a593Smuzhiyun static int __ov7750_start_stream(struct ov7750 *ov7750)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun int ret;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun ret = ov7750_write_array(ov7750->client, ov7750->cur_mode->reg_list);
719*4882a593Smuzhiyun if (ret)
720*4882a593Smuzhiyun return ret;
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun /* In case these controls are set before streaming */
723*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
724*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&ov7750->ctrl_handler);
725*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
726*4882a593Smuzhiyun if (ret)
727*4882a593Smuzhiyun return ret;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun return ov7750_write_reg(ov7750->client,
730*4882a593Smuzhiyun OV7750_REG_CTRL_MODE,
731*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
732*4882a593Smuzhiyun OV7750_MODE_STREAMING);
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
__ov7750_stop_stream(struct ov7750 * ov7750)735*4882a593Smuzhiyun static int __ov7750_stop_stream(struct ov7750 *ov7750)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun return ov7750_write_reg(ov7750->client,
738*4882a593Smuzhiyun OV7750_REG_CTRL_MODE,
739*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
740*4882a593Smuzhiyun OV7750_MODE_SW_STANDBY);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
ov7750_s_stream(struct v4l2_subdev * sd,int on)743*4882a593Smuzhiyun static int ov7750_s_stream(struct v4l2_subdev *sd, int on)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
746*4882a593Smuzhiyun struct i2c_client *client = ov7750->client;
747*4882a593Smuzhiyun int ret = 0;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
750*4882a593Smuzhiyun on = !!on;
751*4882a593Smuzhiyun if (on == ov7750->streaming)
752*4882a593Smuzhiyun goto unlock_and_return;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun if (on) {
755*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
756*4882a593Smuzhiyun if (ret < 0) {
757*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
758*4882a593Smuzhiyun goto unlock_and_return;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun ret = __ov7750_start_stream(ov7750);
762*4882a593Smuzhiyun if (ret) {
763*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
764*4882a593Smuzhiyun pm_runtime_put(&client->dev);
765*4882a593Smuzhiyun goto unlock_and_return;
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun } else {
768*4882a593Smuzhiyun __ov7750_stop_stream(ov7750);
769*4882a593Smuzhiyun pm_runtime_put(&client->dev);
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun ov7750->streaming = on;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun unlock_and_return:
775*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun return ret;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
ov7750_s_power(struct v4l2_subdev * sd,int on)780*4882a593Smuzhiyun static int ov7750_s_power(struct v4l2_subdev *sd, int on)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
783*4882a593Smuzhiyun struct i2c_client *client = ov7750->client;
784*4882a593Smuzhiyun int ret = 0;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
789*4882a593Smuzhiyun if (ov7750->power_on == !!on)
790*4882a593Smuzhiyun goto unlock_and_return;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun if (on) {
793*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
794*4882a593Smuzhiyun if (ret < 0) {
795*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
796*4882a593Smuzhiyun goto unlock_and_return;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun ret = ov7750_write_array(ov7750->client, ov7750_global_regs);
800*4882a593Smuzhiyun if (ret) {
801*4882a593Smuzhiyun v4l2_err(sd, "could not set init registers\n");
802*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
803*4882a593Smuzhiyun goto unlock_and_return;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun ov7750->power_on = true;
807*4882a593Smuzhiyun } else {
808*4882a593Smuzhiyun pm_runtime_put(&client->dev);
809*4882a593Smuzhiyun ov7750->power_on = false;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun unlock_and_return:
813*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun return ret;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
ov7750_cal_delay(u32 cycles)819*4882a593Smuzhiyun static inline u32 ov7750_cal_delay(u32 cycles)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, OV7750_XVCLK_FREQ / 1000 / 1000);
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun
__ov7750_power_on(struct ov7750 * ov7750)824*4882a593Smuzhiyun static int __ov7750_power_on(struct ov7750 *ov7750)
825*4882a593Smuzhiyun {
826*4882a593Smuzhiyun int ret;
827*4882a593Smuzhiyun u32 delay_us;
828*4882a593Smuzhiyun struct device *dev = &ov7750->client->dev;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(ov7750->pins_default)) {
831*4882a593Smuzhiyun ret = pinctrl_select_state(ov7750->pinctrl,
832*4882a593Smuzhiyun ov7750->pins_default);
833*4882a593Smuzhiyun if (ret < 0)
834*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun ret = clk_set_rate(ov7750->xvclk, OV7750_XVCLK_FREQ);
838*4882a593Smuzhiyun if (ret < 0)
839*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
840*4882a593Smuzhiyun if (clk_get_rate(ov7750->xvclk) != OV7750_XVCLK_FREQ)
841*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
842*4882a593Smuzhiyun ret = clk_prepare_enable(ov7750->xvclk);
843*4882a593Smuzhiyun if (ret < 0) {
844*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
845*4882a593Smuzhiyun return ret;
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun if (!IS_ERR(ov7750->reset_gpio))
849*4882a593Smuzhiyun gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun ret = regulator_bulk_enable(OV7750_NUM_SUPPLIES, ov7750->supplies);
852*4882a593Smuzhiyun if (ret < 0) {
853*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
854*4882a593Smuzhiyun goto disable_clk;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (!IS_ERR(ov7750->reset_gpio))
858*4882a593Smuzhiyun gpiod_set_value_cansleep(ov7750->reset_gpio, 1);
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun usleep_range(500, 1000);
861*4882a593Smuzhiyun if (!IS_ERR(ov7750->pwdn_gpio))
862*4882a593Smuzhiyun gpiod_set_value_cansleep(ov7750->pwdn_gpio, 1);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
865*4882a593Smuzhiyun delay_us = ov7750_cal_delay(8192);
866*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun return 0;
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun disable_clk:
871*4882a593Smuzhiyun clk_disable_unprepare(ov7750->xvclk);
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun return ret;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
__ov7750_power_off(struct ov7750 * ov7750)876*4882a593Smuzhiyun static void __ov7750_power_off(struct ov7750 *ov7750)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun int ret;
879*4882a593Smuzhiyun struct device *dev = &ov7750->client->dev;
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun if (!IS_ERR(ov7750->pwdn_gpio))
882*4882a593Smuzhiyun gpiod_set_value_cansleep(ov7750->pwdn_gpio, 0);
883*4882a593Smuzhiyun clk_disable_unprepare(ov7750->xvclk);
884*4882a593Smuzhiyun if (!IS_ERR(ov7750->reset_gpio))
885*4882a593Smuzhiyun gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
886*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(ov7750->pins_sleep)) {
887*4882a593Smuzhiyun ret = pinctrl_select_state(ov7750->pinctrl,
888*4882a593Smuzhiyun ov7750->pins_sleep);
889*4882a593Smuzhiyun if (ret < 0)
890*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun regulator_bulk_disable(OV7750_NUM_SUPPLIES, ov7750->supplies);
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
ov7750_runtime_resume(struct device * dev)895*4882a593Smuzhiyun static int ov7750_runtime_resume(struct device *dev)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
898*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
899*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun return __ov7750_power_on(ov7750);
902*4882a593Smuzhiyun }
903*4882a593Smuzhiyun
ov7750_runtime_suspend(struct device * dev)904*4882a593Smuzhiyun static int ov7750_runtime_suspend(struct device *dev)
905*4882a593Smuzhiyun {
906*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
907*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
908*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun __ov7750_power_off(ov7750);
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun return 0;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov7750_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)916*4882a593Smuzhiyun static int ov7750_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
917*4882a593Smuzhiyun {
918*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
919*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
920*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
921*4882a593Smuzhiyun const struct ov7750_mode *def_mode = &supported_modes[0];
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun mutex_lock(&ov7750->mutex);
924*4882a593Smuzhiyun /* Initialize try_fmt */
925*4882a593Smuzhiyun try_fmt->width = def_mode->width;
926*4882a593Smuzhiyun try_fmt->height = def_mode->height;
927*4882a593Smuzhiyun try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
928*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun mutex_unlock(&ov7750->mutex);
931*4882a593Smuzhiyun /* No crop or compose */
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun return 0;
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun #endif
936*4882a593Smuzhiyun
ov7750_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)937*4882a593Smuzhiyun static int ov7750_enum_frame_interval(struct v4l2_subdev *sd,
938*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
939*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
942*4882a593Smuzhiyun return -EINVAL;
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
945*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
946*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
947*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
948*4882a593Smuzhiyun return 0;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
ov7750_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)951*4882a593Smuzhiyun static int ov7750_g_mbus_config(struct v4l2_subdev *sd,
952*4882a593Smuzhiyun struct v4l2_mbus_config *config)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun u32 val = 0;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun val = 1 << (OV7750_LANES - 1) |
957*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
958*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
959*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2;
960*4882a593Smuzhiyun config->flags = val;
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun return 0;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun static const struct dev_pm_ops ov7750_pm_ops = {
966*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(ov7750_runtime_suspend,
967*4882a593Smuzhiyun ov7750_runtime_resume, NULL)
968*4882a593Smuzhiyun };
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
971*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops ov7750_internal_ops = {
972*4882a593Smuzhiyun .open = ov7750_open,
973*4882a593Smuzhiyun };
974*4882a593Smuzhiyun #endif
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops ov7750_core_ops = {
977*4882a593Smuzhiyun .s_power = ov7750_s_power,
978*4882a593Smuzhiyun .ioctl = ov7750_ioctl,
979*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
980*4882a593Smuzhiyun .compat_ioctl32 = ov7750_compat_ioctl32,
981*4882a593Smuzhiyun #endif
982*4882a593Smuzhiyun };
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov7750_video_ops = {
985*4882a593Smuzhiyun .s_stream = ov7750_s_stream,
986*4882a593Smuzhiyun .g_mbus_config = ov7750_g_mbus_config,
987*4882a593Smuzhiyun };
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov7750_pad_ops = {
990*4882a593Smuzhiyun .enum_mbus_code = ov7750_enum_mbus_code,
991*4882a593Smuzhiyun .enum_frame_size = ov7750_enum_frame_sizes,
992*4882a593Smuzhiyun .enum_frame_interval = ov7750_enum_frame_interval,
993*4882a593Smuzhiyun .get_fmt = ov7750_get_fmt,
994*4882a593Smuzhiyun .set_fmt = ov7750_set_fmt,
995*4882a593Smuzhiyun };
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov7750_subdev_ops = {
998*4882a593Smuzhiyun .core = &ov7750_core_ops,
999*4882a593Smuzhiyun .video = &ov7750_video_ops,
1000*4882a593Smuzhiyun .pad = &ov7750_pad_ops,
1001*4882a593Smuzhiyun };
1002*4882a593Smuzhiyun
ov7750_set_ctrl(struct v4l2_ctrl * ctrl)1003*4882a593Smuzhiyun static int ov7750_set_ctrl(struct v4l2_ctrl *ctrl)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun struct ov7750 *ov7750 = container_of(ctrl->handler,
1006*4882a593Smuzhiyun struct ov7750, ctrl_handler);
1007*4882a593Smuzhiyun struct i2c_client *client = ov7750->client;
1008*4882a593Smuzhiyun s64 max;
1009*4882a593Smuzhiyun int ret = 0;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
1012*4882a593Smuzhiyun switch (ctrl->id) {
1013*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1014*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1015*4882a593Smuzhiyun max = ov7750->cur_mode->height + ctrl->val -
1016*4882a593Smuzhiyun OV7750_EXP_MARGIN_LIMIT;
1017*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov7750->exposure,
1018*4882a593Smuzhiyun ov7750->exposure->minimum, max,
1019*4882a593Smuzhiyun ov7750->exposure->step,
1020*4882a593Smuzhiyun ov7750->exposure->default_value);
1021*4882a593Smuzhiyun break;
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1025*4882a593Smuzhiyun return 0;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun switch (ctrl->id) {
1028*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1029*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
1030*4882a593Smuzhiyun ret = ov7750_write_reg(ov7750->client,
1031*4882a593Smuzhiyun OV7750_REG_EXPOSURE,
1032*4882a593Smuzhiyun OV7750_REG_VALUE_24BIT,
1033*4882a593Smuzhiyun ctrl->val << 4);
1034*4882a593Smuzhiyun break;
1035*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1036*4882a593Smuzhiyun ret = ov7750_write_reg(ov7750->client,
1037*4882a593Smuzhiyun OV7750_REG_GAIN_H,
1038*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
1039*4882a593Smuzhiyun (ctrl->val >> OV7750_GAIN_H_SHIFT) &
1040*4882a593Smuzhiyun OV7750_GAIN_H_MASK);
1041*4882a593Smuzhiyun ret |= ov7750_write_reg(ov7750->client,
1042*4882a593Smuzhiyun OV7750_REG_GAIN_L,
1043*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT,
1044*4882a593Smuzhiyun ctrl->val & OV7750_GAIN_L_MASK);
1045*4882a593Smuzhiyun break;
1046*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1047*4882a593Smuzhiyun ret = ov7750_write_reg(ov7750->client,
1048*4882a593Smuzhiyun OV7750_REG_VTS,
1049*4882a593Smuzhiyun OV7750_REG_VALUE_16BIT,
1050*4882a593Smuzhiyun ctrl->val + ov7750->cur_mode->height);
1051*4882a593Smuzhiyun break;
1052*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
1053*4882a593Smuzhiyun ret = ov7750_enable_test_pattern(ov7750, ctrl->val);
1054*4882a593Smuzhiyun break;
1055*4882a593Smuzhiyun default:
1056*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1057*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
1058*4882a593Smuzhiyun break;
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun return ret;
1064*4882a593Smuzhiyun }
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov7750_ctrl_ops = {
1067*4882a593Smuzhiyun .s_ctrl = ov7750_set_ctrl,
1068*4882a593Smuzhiyun };
1069*4882a593Smuzhiyun
ov7750_initialize_controls(struct ov7750 * ov7750)1070*4882a593Smuzhiyun static int ov7750_initialize_controls(struct ov7750 *ov7750)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun const struct ov7750_mode *mode;
1073*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1074*4882a593Smuzhiyun struct v4l2_ctrl *ctrl;
1075*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1076*4882a593Smuzhiyun u32 h_blank;
1077*4882a593Smuzhiyun int ret;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun handler = &ov7750->ctrl_handler;
1080*4882a593Smuzhiyun mode = ov7750->cur_mode;
1081*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 8);
1082*4882a593Smuzhiyun if (ret)
1083*4882a593Smuzhiyun return ret;
1084*4882a593Smuzhiyun handler->lock = &ov7750->mutex;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1087*4882a593Smuzhiyun 0, 0, link_freq_menu_items);
1088*4882a593Smuzhiyun if (ctrl)
1089*4882a593Smuzhiyun ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1092*4882a593Smuzhiyun 0, OV7750_PIXEL_RATE, 1, OV7750_PIXEL_RATE);
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1095*4882a593Smuzhiyun ov7750->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1096*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1097*4882a593Smuzhiyun if (ov7750->hblank)
1098*4882a593Smuzhiyun ov7750->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1101*4882a593Smuzhiyun ov7750->vblank = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1102*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1103*4882a593Smuzhiyun OV7750_VTS_MAX - mode->height,
1104*4882a593Smuzhiyun 1, vblank_def);
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun exposure_max = mode->vts_def - OV7750_EXP_MARGIN_LIMIT;
1107*4882a593Smuzhiyun ov7750->exposure = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1108*4882a593Smuzhiyun V4L2_CID_EXPOSURE, OV7750_EXPOSURE_MIN,
1109*4882a593Smuzhiyun exposure_max, OV7750_EXPOSURE_STEP,
1110*4882a593Smuzhiyun mode->exp_def);
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun ov7750->anal_gain = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1113*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN, OV7750_GAIN_MIN,
1114*4882a593Smuzhiyun OV7750_GAIN_MAX, OV7750_GAIN_STEP,
1115*4882a593Smuzhiyun OV7750_GAIN_DEFAULT);
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun ov7750->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1118*4882a593Smuzhiyun &ov7750_ctrl_ops, V4L2_CID_TEST_PATTERN,
1119*4882a593Smuzhiyun ARRAY_SIZE(ov7750_test_pattern_menu) - 1,
1120*4882a593Smuzhiyun 0, 0, ov7750_test_pattern_menu);
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun if (handler->error) {
1123*4882a593Smuzhiyun ret = handler->error;
1124*4882a593Smuzhiyun dev_err(&ov7750->client->dev,
1125*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1126*4882a593Smuzhiyun goto err_free_handler;
1127*4882a593Smuzhiyun }
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun ov7750->subdev.ctrl_handler = handler;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun return 0;
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun err_free_handler:
1134*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun return ret;
1137*4882a593Smuzhiyun }
1138*4882a593Smuzhiyun
ov7750_check_sensor_id(struct ov7750 * ov7750,struct i2c_client * client)1139*4882a593Smuzhiyun static int ov7750_check_sensor_id(struct ov7750 *ov7750,
1140*4882a593Smuzhiyun struct i2c_client *client)
1141*4882a593Smuzhiyun {
1142*4882a593Smuzhiyun struct device *dev = &ov7750->client->dev;
1143*4882a593Smuzhiyun u32 id = 0;
1144*4882a593Smuzhiyun int ret;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun ret = ov7750_read_reg(client, OV7750_REG_CHIP_ID,
1147*4882a593Smuzhiyun OV7750_REG_VALUE_16BIT, &id);
1148*4882a593Smuzhiyun if (id != CHIP_ID) {
1149*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1150*4882a593Smuzhiyun return -ENODEV;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun ret = ov7750_read_reg(client, OV7750_CHIP_REVISION_REG,
1154*4882a593Smuzhiyun OV7750_REG_VALUE_08BIT, &id);
1155*4882a593Smuzhiyun if (ret) {
1156*4882a593Smuzhiyun dev_err(dev, "Read chip revision register error\n");
1157*4882a593Smuzhiyun return ret;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun id &= 0xf0;
1160*4882a593Smuzhiyun if (id == OV7750_R1F)
1161*4882a593Smuzhiyun ov7750_global_regs = ov7750_global_regs_r1f;
1162*4882a593Smuzhiyun else
1163*4882a593Smuzhiyun ov7750_global_regs = ov7750_global_regs_rxx;
1164*4882a593Smuzhiyun dev_info(dev, "Detected OV%04x sensor, REVISION 0x%x\n", CHIP_ID, id);
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun return 0;
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
ov7750_configure_regulators(struct ov7750 * ov7750)1169*4882a593Smuzhiyun static int ov7750_configure_regulators(struct ov7750 *ov7750)
1170*4882a593Smuzhiyun {
1171*4882a593Smuzhiyun unsigned int i;
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun for (i = 0; i < OV7750_NUM_SUPPLIES; i++)
1174*4882a593Smuzhiyun ov7750->supplies[i].supply = ov7750_supply_names[i];
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun return devm_regulator_bulk_get(&ov7750->client->dev,
1177*4882a593Smuzhiyun OV7750_NUM_SUPPLIES,
1178*4882a593Smuzhiyun ov7750->supplies);
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun
ov7750_probe(struct i2c_client * client,const struct i2c_device_id * id)1181*4882a593Smuzhiyun static int ov7750_probe(struct i2c_client *client,
1182*4882a593Smuzhiyun const struct i2c_device_id *id)
1183*4882a593Smuzhiyun {
1184*4882a593Smuzhiyun struct device *dev = &client->dev;
1185*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1186*4882a593Smuzhiyun struct ov7750 *ov7750;
1187*4882a593Smuzhiyun struct v4l2_subdev *sd;
1188*4882a593Smuzhiyun char facing[2];
1189*4882a593Smuzhiyun int ret;
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1192*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1193*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1194*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun ov7750 = devm_kzalloc(dev, sizeof(*ov7750), GFP_KERNEL);
1197*4882a593Smuzhiyun if (!ov7750)
1198*4882a593Smuzhiyun return -ENOMEM;
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1201*4882a593Smuzhiyun &ov7750->module_index);
1202*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1203*4882a593Smuzhiyun &ov7750->module_facing);
1204*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1205*4882a593Smuzhiyun &ov7750->module_name);
1206*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1207*4882a593Smuzhiyun &ov7750->len_name);
1208*4882a593Smuzhiyun if (ret) {
1209*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1210*4882a593Smuzhiyun return -EINVAL;
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun ov7750->client = client;
1214*4882a593Smuzhiyun ov7750->cur_mode = &supported_modes[0];
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun ov7750->xvclk = devm_clk_get(dev, "xvclk");
1217*4882a593Smuzhiyun if (IS_ERR(ov7750->xvclk)) {
1218*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1219*4882a593Smuzhiyun return -EINVAL;
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun ov7750->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1223*4882a593Smuzhiyun if (IS_ERR(ov7750->reset_gpio))
1224*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun ov7750->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1227*4882a593Smuzhiyun if (IS_ERR(ov7750->pwdn_gpio))
1228*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun ret = ov7750_configure_regulators(ov7750);
1231*4882a593Smuzhiyun if (ret) {
1232*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1233*4882a593Smuzhiyun return ret;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun ov7750->pinctrl = devm_pinctrl_get(dev);
1237*4882a593Smuzhiyun if (!IS_ERR(ov7750->pinctrl)) {
1238*4882a593Smuzhiyun ov7750->pins_default =
1239*4882a593Smuzhiyun pinctrl_lookup_state(ov7750->pinctrl,
1240*4882a593Smuzhiyun OF_CAMERA_PINCTRL_DEFAULT);
1241*4882a593Smuzhiyun if (IS_ERR(ov7750->pins_default))
1242*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun ov7750->pins_sleep =
1245*4882a593Smuzhiyun pinctrl_lookup_state(ov7750->pinctrl,
1246*4882a593Smuzhiyun OF_CAMERA_PINCTRL_SLEEP);
1247*4882a593Smuzhiyun if (IS_ERR(ov7750->pins_sleep))
1248*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1249*4882a593Smuzhiyun }
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun mutex_init(&ov7750->mutex);
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun sd = &ov7750->subdev;
1254*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &ov7750_subdev_ops);
1255*4882a593Smuzhiyun ret = ov7750_initialize_controls(ov7750);
1256*4882a593Smuzhiyun if (ret)
1257*4882a593Smuzhiyun goto err_destroy_mutex;
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun ret = __ov7750_power_on(ov7750);
1260*4882a593Smuzhiyun if (ret)
1261*4882a593Smuzhiyun goto err_free_handler;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun ret = ov7750_check_sensor_id(ov7750, client);
1264*4882a593Smuzhiyun if (ret)
1265*4882a593Smuzhiyun goto err_power_off;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1268*4882a593Smuzhiyun sd->internal_ops = &ov7750_internal_ops;
1269*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1270*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
1271*4882a593Smuzhiyun #endif
1272*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1273*4882a593Smuzhiyun ov7750->pad.flags = MEDIA_PAD_FL_SOURCE;
1274*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1275*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &ov7750->pad);
1276*4882a593Smuzhiyun if (ret < 0)
1277*4882a593Smuzhiyun goto err_power_off;
1278*4882a593Smuzhiyun #endif
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1281*4882a593Smuzhiyun if (strcmp(ov7750->module_facing, "back") == 0)
1282*4882a593Smuzhiyun facing[0] = 'b';
1283*4882a593Smuzhiyun else
1284*4882a593Smuzhiyun facing[0] = 'f';
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1287*4882a593Smuzhiyun ov7750->module_index, facing,
1288*4882a593Smuzhiyun OV7750_NAME, dev_name(sd->dev));
1289*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1290*4882a593Smuzhiyun if (ret) {
1291*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1292*4882a593Smuzhiyun goto err_clean_entity;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun pm_runtime_set_active(dev);
1296*4882a593Smuzhiyun pm_runtime_enable(dev);
1297*4882a593Smuzhiyun pm_runtime_idle(dev);
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun return 0;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun err_clean_entity:
1302*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1303*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1304*4882a593Smuzhiyun #endif
1305*4882a593Smuzhiyun err_power_off:
1306*4882a593Smuzhiyun __ov7750_power_off(ov7750);
1307*4882a593Smuzhiyun err_free_handler:
1308*4882a593Smuzhiyun v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
1309*4882a593Smuzhiyun err_destroy_mutex:
1310*4882a593Smuzhiyun mutex_destroy(&ov7750->mutex);
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun return ret;
1313*4882a593Smuzhiyun }
1314*4882a593Smuzhiyun
ov7750_remove(struct i2c_client * client)1315*4882a593Smuzhiyun static int ov7750_remove(struct i2c_client *client)
1316*4882a593Smuzhiyun {
1317*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1318*4882a593Smuzhiyun struct ov7750 *ov7750 = to_ov7750(sd);
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1321*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1322*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1323*4882a593Smuzhiyun #endif
1324*4882a593Smuzhiyun v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
1325*4882a593Smuzhiyun mutex_destroy(&ov7750->mutex);
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1328*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1329*4882a593Smuzhiyun __ov7750_power_off(ov7750);
1330*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun return 0;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1336*4882a593Smuzhiyun static const struct of_device_id ov7750_of_match[] = {
1337*4882a593Smuzhiyun { .compatible = "ovti,ov7750" },
1338*4882a593Smuzhiyun {},
1339*4882a593Smuzhiyun };
1340*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ov7750_of_match);
1341*4882a593Smuzhiyun #endif
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun static const struct i2c_device_id ov7750_match_id[] = {
1344*4882a593Smuzhiyun { "ovti,ov7750", 0 },
1345*4882a593Smuzhiyun { },
1346*4882a593Smuzhiyun };
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun static struct i2c_driver ov7750_i2c_driver = {
1349*4882a593Smuzhiyun .driver = {
1350*4882a593Smuzhiyun .name = OV7750_NAME,
1351*4882a593Smuzhiyun .pm = &ov7750_pm_ops,
1352*4882a593Smuzhiyun .of_match_table = of_match_ptr(ov7750_of_match),
1353*4882a593Smuzhiyun },
1354*4882a593Smuzhiyun .probe = &ov7750_probe,
1355*4882a593Smuzhiyun .remove = &ov7750_remove,
1356*4882a593Smuzhiyun .id_table = ov7750_match_id,
1357*4882a593Smuzhiyun };
1358*4882a593Smuzhiyun
sensor_mod_init(void)1359*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1360*4882a593Smuzhiyun {
1361*4882a593Smuzhiyun return i2c_add_driver(&ov7750_i2c_driver);
1362*4882a593Smuzhiyun }
1363*4882a593Smuzhiyun
sensor_mod_exit(void)1364*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1365*4882a593Smuzhiyun {
1366*4882a593Smuzhiyun i2c_del_driver(&ov7750_i2c_driver);
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1370*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun MODULE_DESCRIPTION("OmniVision ov7750 sensor driver");
1373*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1374*4882a593Smuzhiyun
1375