1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov7750 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 * V0.0X01.0X05 add function g_mbus_config
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 /* 45Mhz * 4 Binning */
39 #define OV7750_PIXEL_RATE (49 * 1000 * 1000)
40 #define OV7750_XVCLK_FREQ 24000000
41
42 #define CHIP_ID 0x7750
43 #define OV7750_REG_CHIP_ID 0x300a
44
45 #define OV7750_REG_CTRL_MODE 0x0100
46 #define OV7750_MODE_SW_STANDBY 0x0
47 #define OV7750_MODE_STREAMING BIT(0)
48
49 #define OV7750_REG_EXPOSURE 0x3500
50 #define OV7750_EXPOSURE_MIN 4
51 #define OV7750_EXPOSURE_STEP 1
52 #define OV7750_VTS_MAX 0x7fff
53
54 #define OV7750_REG_GAIN_H 0x350a
55 #define OV7750_REG_GAIN_L 0x350b
56 #define OV7750_GAIN_H_MASK 0x07
57 #define OV7750_GAIN_H_SHIFT 8
58 #define OV7750_GAIN_L_MASK 0xff
59 #define OV7750_GAIN_MIN 0x10
60 #define OV7750_GAIN_MAX 0xf8
61 #define OV7750_GAIN_STEP 1
62 #define OV7750_GAIN_DEFAULT 0x10
63
64 #define OV7750_REG_TEST_PATTERN 0x5e00
65 #define OV7750_TEST_PATTERN_ENABLE 0x80
66 #define OV7750_TEST_PATTERN_DISABLE 0x0
67
68 #define OV7750_REG_VTS 0x380e
69
70 #define REG_NULL 0xFFFF
71
72 #define OV7750_REG_VALUE_08BIT 1
73 #define OV7750_REG_VALUE_16BIT 2
74 #define OV7750_REG_VALUE_24BIT 3
75
76 #define OV7750_BITS_PER_SAMPLE 10
77 #define OV7750_REG_MANUAL_CTL 0x3503
78 #define OV7750_CHIP_REVISION_REG 0x3029
79 #define OV7750_R1F 0x70
80 #define OV7750_EXP_MARGIN_LIMIT 10
81
82 #define OF_CAMERA_PINCTRL_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_SLEEP "rockchip,camera_sleep"
84
85 #define OV7750_NAME "ov7750"
86
87 #define OV7750_LANES 1
88
89 static const struct regval *ov7750_global_regs;
90
91 static const char * const ov7750_supply_names[] = {
92 "avdd", /* Analog power */
93 "dovdd", /* Digital I/O power */
94 "dvdd", /* Digital core power */
95 };
96
97 #define OV7750_NUM_SUPPLIES ARRAY_SIZE(ov7750_supply_names)
98
99 struct regval {
100 u16 addr;
101 u8 val;
102 };
103
104 struct ov7750_mode {
105 u32 width;
106 u32 height;
107 struct v4l2_fract max_fps;
108 u32 hts_def;
109 u32 vts_def;
110 u32 exp_def;
111 const struct regval *reg_list;
112 };
113
114 struct ov7750 {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *reset_gpio;
118 struct gpio_desc *pwdn_gpio;
119 struct regulator_bulk_data supplies[OV7750_NUM_SUPPLIES];
120
121 struct pinctrl *pinctrl;
122 struct pinctrl_state *pins_default;
123 struct pinctrl_state *pins_sleep;
124
125 struct v4l2_subdev subdev;
126 struct media_pad pad;
127 struct v4l2_ctrl_handler ctrl_handler;
128 struct v4l2_ctrl *exposure;
129 struct v4l2_ctrl *anal_gain;
130 struct v4l2_ctrl *digi_gain;
131 struct v4l2_ctrl *hblank;
132 struct v4l2_ctrl *vblank;
133 struct v4l2_ctrl *test_pattern;
134 struct mutex mutex;
135 bool streaming;
136 bool power_on;
137 const struct ov7750_mode *cur_mode;
138 u32 module_index;
139 const char *module_facing;
140 const char *module_name;
141 const char *len_name;
142 };
143
144 #define to_ov7750(sd) container_of(sd, struct ov7750, subdev)
145
146 /*
147 * Rev: 1F
148 * Xclk 24Mhz
149 */
150 static const struct regval ov7750_global_regs_r1f[] = {
151 {0x0103, 0x01},
152 {0x0100, 0x00},
153 {0x3005, 0x00},
154 {0x3012, 0xc0},
155 {0x3013, 0xd2},
156 {0x3014, 0x04},
157 {0x3016, 0x10},
158 {0x3017, 0x00},
159 {0x3018, 0x00},
160 {0x301a, 0x00},
161 {0x301b, 0x00},
162 {0x301c, 0x00},
163 {0x3023, 0x05},
164 {0x3037, 0xf0},
165 {0x3098, 0x04},
166 {0x3099, 0x28},
167 {0x309a, 0x05},
168 {0x309b, 0x04},
169 {0x30b0, 0x0a},
170 {0x30b1, 0x01},
171 {0x30b3, 0x64},
172 {0x30b4, 0x03},
173 {0x30b5, 0x05},
174 {0x3106, 0xda},
175 {0x3500, 0x00},
176 {0x3501, 0x1f},
177 {0x3502, 0x80},
178 {0x3503, 0x07},
179 {0x3509, 0x10},
180 {0x350b, 0x10},
181 {0x3600, 0x1c},
182 {0x3602, 0x62},
183 {0x3620, 0xb7},
184 {0x3622, 0x04},
185 {0x3626, 0x21},
186 {0x3627, 0x30},
187 {0x3630, 0x44},
188 {0x3631, 0x35},
189 {0x3634, 0x60},
190 {0x3636, 0x00},
191 {0x3662, 0x01},
192 {0x3663, 0x70},
193 {0x3664, 0xf0},
194 {0x3666, 0x0a},
195 {0x3669, 0x1a},
196 {0x366a, 0x00},
197 {0x366b, 0x50},
198 {0x3673, 0x01},
199 {0x3674, 0xff},
200 {0x3675, 0x03},
201 {0x3705, 0xc1},
202 {0x3709, 0x40},
203 {0x373c, 0x08},
204 {0x3742, 0x00},
205 {0x3757, 0xb3},
206 {0x3788, 0x00},
207 {0x37a8, 0x01},
208 {0x37a9, 0xc0},
209 {0x3800, 0x00},
210 {0x3801, 0x04},
211 {0x3802, 0x00},
212 {0x3803, 0x04},
213 {0x3804, 0x02},
214 {0x3805, 0x8b},
215 {0x3806, 0x01},
216 {0x3807, 0xeb},
217 {0x3808, 0x02},
218 {0x3809, 0x80},
219 {0x380a, 0x01},
220 {0x380b, 0xe0},
221 /* line length_pclk */
222 {0x380c, 0x03}, //{0x380c, 0x03},
223 {0x380d, 0xa0}, //{0x380d, 0x10},
224 /* frame_length_line */
225 {0x380e, 0x07}, //{0x380e, 0x02},
226 {0x380f, 0xd0}, //{0x380f, 0x00},
227
228 {0x3810, 0x00},
229 {0x3811, 0x04},
230 {0x3812, 0x00},
231 {0x3813, 0x05},
232 {0x3814, 0x11},
233 {0x3815, 0x11},
234 {0x3820, 0x40},
235 {0x3821, 0x00},
236 {0x382f, 0x0e},
237 {0x3832, 0x00},
238 {0x3833, 0x05},
239 {0x3834, 0x00},
240 {0x3835, 0x0c},
241 {0x3837, 0x00},
242 {0x3b80, 0x00},
243 {0x3b81, 0xa5},
244 {0x3b82, 0x10},
245 {0x3b83, 0x00},
246 {0x3b84, 0x08},
247 {0x3b85, 0x00},
248 {0x3b86, 0x01},
249 {0x3b87, 0x00},
250 {0x3b88, 0x00},
251 {0x3b89, 0x00},
252 {0x3b8a, 0x00},
253 {0x3b8b, 0x05},
254 {0x3b8c, 0x00},
255 {0x3b8d, 0x00},
256 {0x3b8e, 0x00},
257 {0x3b8f, 0x1a},
258 {0x3b94, 0x05},
259 {0x3b95, 0xf2},
260 {0x3b96, 0x40},
261 {0x3c00, 0x89},
262 {0x3c01, 0x63},
263 {0x3c02, 0x01},
264 {0x3c03, 0x00},
265 {0x3c04, 0x00},
266 {0x3c05, 0x03},
267 {0x3c06, 0x00},
268 {0x3c07, 0x06},
269 {0x3c0c, 0x01},
270 {0x3c0d, 0xd0},
271 {0x3c0e, 0x02},
272 {0x3c0f, 0x04},
273 {0x4001, 0x42},
274 {0x4004, 0x04},
275 {0x4005, 0x00},
276 {0x404e, 0x01},
277 {0x4241, 0x00},
278 {0x4242, 0x00},
279 {0x4300, 0xff},
280 {0x4301, 0x00},
281 {0x4501, 0x48},
282 {0x4600, 0x00},
283 {0x4601, 0x4e},
284 {0x4801, 0x0f},
285 {0x4806, 0x0f},
286 {0x4819, 0xaa},
287 {0x4823, 0x3e},
288 {0x4837, 0x19},
289 {0x4a0d, 0x00},
290 {0x4a47, 0x7f},
291 {0x4a49, 0xf0},
292 {0x4a4b, 0x30},
293 {0x5000, 0x85},
294 {0x5001, 0x80},
295 {REG_NULL, 0x00}
296 };
297
298 /*
299 * Rev: xx
300 * Xclk 24Mhz
301 */
302 static const struct regval ov7750_global_regs_rxx[] = {
303 {REG_NULL, 0x00}
304 };
305
306 /*
307 * Xclk 24Mhz
308 * max_framerate 60fps
309 * mipi_datarate per lane 400Mbps
310 */
311 static const struct regval ov7750_640x480_regs[] = {
312 {0x3500, 0x00},
313 {0x3501, 0x1f},
314 {0x3502, 0x80},
315 {0x3503, 0x07},
316 {0x3509, 0x10},
317 {0x350b, 0x10},
318 {0x3600, 0x1c},
319 {0x3602, 0x62},
320 {0x3620, 0xb7},
321 {0x3622, 0x04},
322 {0x3626, 0x21},
323 {0x3627, 0x30},
324 {0x3630, 0x44},
325 {0x3631, 0x35},
326 {0x3634, 0x60},
327 {0x3636, 0x00},
328 {0x3662, 0x01},
329 {0x3663, 0x70},
330 {0x3664, 0xf0},
331 {0x3666, 0x0a},
332 {0x3669, 0x1a},
333 {0x366a, 0x00},
334 {0x366b, 0x50},
335 {0x3673, 0x01},
336 {0x3674, 0xff},
337 {0x3675, 0x03},
338 {0x3705, 0xc1},
339 {0x3709, 0x40},
340 {0x373c, 0x08},
341 {0x3742, 0x00},
342 {0x3757, 0xb3},
343 {0x3788, 0x00},
344 {0x37a8, 0x01},
345 {0x37a9, 0xc0},
346 /* vga */
347 {0x3800, 0x00},
348 {0x3801, 0x04},
349 {0x3802, 0x00},
350 {0x3803, 0x04},
351 {0x3804, 0x02},
352 {0x3805, 0x8b},
353 {0x3806, 0x01},
354 {0x3807, 0xeb},
355 /* vaga end */
356 {0x3808, 0x02},
357 {0x3809, 0x80},
358 {0x380a, 0x01},
359 {0x380b, 0xe0},
360 {0x380c, 0x03},
361 {0x380d, 0xa0},
362 {0x380e, 0x07},
363 {0x380f, 0xd0},
364 {0x3810, 0x00},
365 {0x3811, 0x04},
366 {0x3812, 0x00},
367 {0x3813, 0x05},
368 {0x3814, 0x11},
369 {0x3815, 0x11},
370 {0x3820, 0x40},
371 {0x3821, 0x00},
372 {0x382f, 0x0e},
373 {0x3832, 0x00},
374 {0x3833, 0x05},
375 {0x3834, 0x00},
376 {0x3835, 0x0c},
377 {0x3837, 0x00},
378 {REG_NULL, 0x00}
379 };
380
381 static const struct ov7750_mode supported_modes[] = {
382 {
383 .width = 640,
384 .height = 480,
385 .max_fps = {
386 .numerator = 10000,
387 .denominator = 600000,
388 },
389 .exp_def = 0x0200,
390 .hts_def = 0x03a0,
391 .vts_def = 0x07d0,
392 .reg_list = ov7750_640x480_regs,
393 },
394 };
395
396 #define OV7750_LINK_FREQ_400MHZ 400000000
397 static const s64 link_freq_menu_items[] = {
398 OV7750_LINK_FREQ_400MHZ
399 };
400
401 static const char * const ov7750_test_pattern_menu[] = {
402 "Disabled",
403 "Vertical Color Bar Type 1",
404 "Vertical Color Bar Type 2",
405 "Vertical Color Bar Type 3",
406 "Vertical Color Bar Type 4"
407 };
408
409 /* Write registers up to 4 at a time */
ov7750_write_reg(struct i2c_client * client,u16 reg,int len,u32 val)410 static int ov7750_write_reg(struct i2c_client *client, u16 reg,
411 int len, u32 val)
412 {
413 u32 buf_i, val_i;
414 u8 buf[6];
415 u8 *val_p;
416 __be32 val_be;
417
418 if (len > 4)
419 return -EINVAL;
420
421 buf[0] = reg >> 8;
422 buf[1] = reg & 0xff;
423
424 val_be = cpu_to_be32(val);
425 val_p = (u8 *)&val_be;
426 buf_i = 2;
427 val_i = 4 - len;
428
429 while (val_i < 4)
430 buf[buf_i++] = val_p[val_i++];
431
432 if (i2c_master_send(client, buf, len + 2) != len + 2)
433 return -EIO;
434
435 return 0;
436 }
437
ov7750_write_array(struct i2c_client * client,const struct regval * regs)438 static int ov7750_write_array(struct i2c_client *client,
439 const struct regval *regs)
440 {
441 u32 i;
442 int ret = 0;
443
444 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
445 ret = ov7750_write_reg(client, regs[i].addr,
446 OV7750_REG_VALUE_08BIT,
447 regs[i].val);
448
449 return ret;
450 }
451
452 /* Read registers up to 4 at a time */
ov7750_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)453 static int ov7750_read_reg(struct i2c_client *client, u16 reg,
454 unsigned int len, u32 *val)
455 {
456 struct i2c_msg msgs[2];
457 u8 *data_be_p;
458 __be32 data_be = 0;
459 __be16 reg_addr_be = cpu_to_be16(reg);
460 int ret;
461
462 if (len > 4 || !len)
463 return -EINVAL;
464
465 data_be_p = (u8 *)&data_be;
466 /* Write register address */
467 msgs[0].addr = client->addr;
468 msgs[0].flags = 0;
469 msgs[0].len = 2;
470 msgs[0].buf = (u8 *)®_addr_be;
471
472 /* Read data from register */
473 msgs[1].addr = client->addr;
474 msgs[1].flags = I2C_M_RD;
475 msgs[1].len = len;
476 msgs[1].buf = &data_be_p[4 - len];
477
478 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
479 if (ret != ARRAY_SIZE(msgs))
480 return -EIO;
481
482 *val = be32_to_cpu(data_be);
483
484 return 0;
485 }
486
ov7750_get_reso_dist(const struct ov7750_mode * mode,struct v4l2_mbus_framefmt * framefmt)487 static int ov7750_get_reso_dist(const struct ov7750_mode *mode,
488 struct v4l2_mbus_framefmt *framefmt)
489 {
490 return abs(mode->width - framefmt->width) +
491 abs(mode->height - framefmt->height);
492 }
493
494 static const struct ov7750_mode *
ov7750_find_best_fit(struct v4l2_subdev_format * fmt)495 ov7750_find_best_fit(struct v4l2_subdev_format *fmt)
496 {
497 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
498 int dist;
499 int cur_best_fit = 0;
500 int cur_best_fit_dist = -1;
501 unsigned int i;
502
503 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
504 dist = ov7750_get_reso_dist(&supported_modes[i], framefmt);
505 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
506 cur_best_fit_dist = dist;
507 cur_best_fit = i;
508 }
509 }
510
511 return &supported_modes[cur_best_fit];
512 }
513
ov7750_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)514 static int ov7750_set_fmt(struct v4l2_subdev *sd,
515 struct v4l2_subdev_pad_config *cfg,
516 struct v4l2_subdev_format *fmt)
517 {
518 struct ov7750 *ov7750 = to_ov7750(sd);
519 const struct ov7750_mode *mode;
520 s64 h_blank, vblank_def;
521
522 mutex_lock(&ov7750->mutex);
523
524 mode = ov7750_find_best_fit(fmt);
525 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
526 fmt->format.width = mode->width;
527 fmt->format.height = mode->height;
528 fmt->format.field = V4L2_FIELD_NONE;
529 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
530 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
531 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
532 #else
533 mutex_unlock(&ov7750->mutex);
534 return -ENOTTY;
535 #endif
536 } else {
537 ov7750->cur_mode = mode;
538 h_blank = mode->hts_def - mode->width;
539 __v4l2_ctrl_modify_range(ov7750->hblank, h_blank,
540 h_blank, 1, h_blank);
541 vblank_def = mode->vts_def - mode->height;
542 __v4l2_ctrl_modify_range(ov7750->vblank, vblank_def,
543 OV7750_VTS_MAX - mode->height,
544 1, vblank_def);
545 }
546
547 mutex_unlock(&ov7750->mutex);
548
549 return 0;
550 }
551
ov7750_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)552 static int ov7750_get_fmt(struct v4l2_subdev *sd,
553 struct v4l2_subdev_pad_config *cfg,
554 struct v4l2_subdev_format *fmt)
555 {
556 struct ov7750 *ov7750 = to_ov7750(sd);
557 const struct ov7750_mode *mode = ov7750->cur_mode;
558
559 mutex_lock(&ov7750->mutex);
560 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
561 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
562 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
563 #else
564 mutex_unlock(&ov7750->mutex);
565 return -ENOTTY;
566 #endif
567 } else {
568 fmt->format.width = mode->width;
569 fmt->format.height = mode->height;
570 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
571 fmt->format.field = V4L2_FIELD_NONE;
572 }
573 mutex_unlock(&ov7750->mutex);
574
575 return 0;
576 }
577
ov7750_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)578 static int ov7750_enum_mbus_code(struct v4l2_subdev *sd,
579 struct v4l2_subdev_pad_config *cfg,
580 struct v4l2_subdev_mbus_code_enum *code)
581 {
582 if (code->index != 0)
583 return -EINVAL;
584 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
585
586 return 0;
587 }
588
ov7750_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)589 static int ov7750_enum_frame_sizes(struct v4l2_subdev *sd,
590 struct v4l2_subdev_pad_config *cfg,
591 struct v4l2_subdev_frame_size_enum *fse)
592 {
593 if (fse->index >= ARRAY_SIZE(supported_modes))
594 return -EINVAL;
595
596 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
597 return -EINVAL;
598
599 fse->min_width = supported_modes[fse->index].width;
600 fse->max_width = supported_modes[fse->index].width;
601 fse->max_height = supported_modes[fse->index].height;
602 fse->min_height = supported_modes[fse->index].height;
603
604 return 0;
605 }
606
ov7750_enable_test_pattern(struct ov7750 * ov7750,u32 pattern)607 static int ov7750_enable_test_pattern(struct ov7750 *ov7750, u32 pattern)
608 {
609 u32 val;
610
611 if (pattern)
612 val = (pattern - 1) | OV7750_TEST_PATTERN_ENABLE;
613 else
614 val = OV7750_TEST_PATTERN_DISABLE;
615
616 return ov7750_write_reg(ov7750->client,
617 OV7750_REG_TEST_PATTERN,
618 OV7750_REG_VALUE_08BIT,
619 val);
620 }
621
ov7750_get_module_inf(struct ov7750 * ov7750,struct rkmodule_inf * inf)622 static void ov7750_get_module_inf(struct ov7750 *ov7750,
623 struct rkmodule_inf *inf)
624 {
625 memset(inf, 0, sizeof(*inf));
626 strlcpy(inf->base.sensor, OV7750_NAME, sizeof(inf->base.sensor));
627 strlcpy(inf->base.module, ov7750->module_name,
628 sizeof(inf->base.module));
629 strlcpy(inf->base.lens, ov7750->len_name, sizeof(inf->base.lens));
630 }
631
ov7750_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)632 static long ov7750_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
633 {
634 struct ov7750 *ov7750 = to_ov7750(sd);
635 long ret = 0;
636 u32 stream = 0;
637
638 switch (cmd) {
639 case RKMODULE_GET_MODULE_INFO:
640 ov7750_get_module_inf(ov7750, (struct rkmodule_inf *)arg);
641 break;
642 case RKMODULE_SET_QUICK_STREAM:
643
644 stream = *((u32 *)arg);
645
646 if (stream)
647 ret = ov7750_write_reg(ov7750->client,
648 OV7750_REG_CTRL_MODE,
649 OV7750_REG_VALUE_08BIT,
650 OV7750_MODE_STREAMING);
651 else
652 ret = ov7750_write_reg(ov7750->client,
653 OV7750_REG_CTRL_MODE,
654 OV7750_REG_VALUE_08BIT,
655 OV7750_MODE_SW_STANDBY);
656 break;
657 default:
658 ret = -ENOTTY;
659 break;
660 }
661
662 return ret;
663 }
664
665 #ifdef CONFIG_COMPAT
ov7750_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)666 static long ov7750_compat_ioctl32(struct v4l2_subdev *sd,
667 unsigned int cmd, unsigned long arg)
668 {
669 void __user *up = compat_ptr(arg);
670 struct rkmodule_inf *inf;
671 struct rkmodule_awb_cfg *cfg;
672 long ret;
673 u32 stream = 0;
674
675 switch (cmd) {
676 case RKMODULE_GET_MODULE_INFO:
677 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
678 if (!inf) {
679 ret = -ENOMEM;
680 return ret;
681 }
682
683 ret = ov7750_ioctl(sd, cmd, inf);
684 if (!ret)
685 ret = copy_to_user(up, inf, sizeof(*inf));
686 kfree(inf);
687 break;
688 case RKMODULE_AWB_CFG:
689 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
690 if (!cfg) {
691 ret = -ENOMEM;
692 return ret;
693 }
694
695 ret = copy_from_user(cfg, up, sizeof(*cfg));
696 if (!ret)
697 ret = ov7750_ioctl(sd, cmd, cfg);
698 kfree(cfg);
699 break;
700 case RKMODULE_SET_QUICK_STREAM:
701 ret = copy_from_user(&stream, up, sizeof(u32));
702 if (!ret)
703 ret = ov7750_ioctl(sd, cmd, &stream);
704 break;
705 default:
706 ret = -ENOIOCTLCMD;
707 break;
708 }
709
710 return ret;
711 }
712 #endif
713
__ov7750_start_stream(struct ov7750 * ov7750)714 static int __ov7750_start_stream(struct ov7750 *ov7750)
715 {
716 int ret;
717
718 ret = ov7750_write_array(ov7750->client, ov7750->cur_mode->reg_list);
719 if (ret)
720 return ret;
721
722 /* In case these controls are set before streaming */
723 mutex_unlock(&ov7750->mutex);
724 ret = v4l2_ctrl_handler_setup(&ov7750->ctrl_handler);
725 mutex_lock(&ov7750->mutex);
726 if (ret)
727 return ret;
728
729 return ov7750_write_reg(ov7750->client,
730 OV7750_REG_CTRL_MODE,
731 OV7750_REG_VALUE_08BIT,
732 OV7750_MODE_STREAMING);
733 }
734
__ov7750_stop_stream(struct ov7750 * ov7750)735 static int __ov7750_stop_stream(struct ov7750 *ov7750)
736 {
737 return ov7750_write_reg(ov7750->client,
738 OV7750_REG_CTRL_MODE,
739 OV7750_REG_VALUE_08BIT,
740 OV7750_MODE_SW_STANDBY);
741 }
742
ov7750_s_stream(struct v4l2_subdev * sd,int on)743 static int ov7750_s_stream(struct v4l2_subdev *sd, int on)
744 {
745 struct ov7750 *ov7750 = to_ov7750(sd);
746 struct i2c_client *client = ov7750->client;
747 int ret = 0;
748
749 mutex_lock(&ov7750->mutex);
750 on = !!on;
751 if (on == ov7750->streaming)
752 goto unlock_and_return;
753
754 if (on) {
755 ret = pm_runtime_get_sync(&client->dev);
756 if (ret < 0) {
757 pm_runtime_put_noidle(&client->dev);
758 goto unlock_and_return;
759 }
760
761 ret = __ov7750_start_stream(ov7750);
762 if (ret) {
763 v4l2_err(sd, "start stream failed while write regs\n");
764 pm_runtime_put(&client->dev);
765 goto unlock_and_return;
766 }
767 } else {
768 __ov7750_stop_stream(ov7750);
769 pm_runtime_put(&client->dev);
770 }
771
772 ov7750->streaming = on;
773
774 unlock_and_return:
775 mutex_unlock(&ov7750->mutex);
776
777 return ret;
778 }
779
ov7750_s_power(struct v4l2_subdev * sd,int on)780 static int ov7750_s_power(struct v4l2_subdev *sd, int on)
781 {
782 struct ov7750 *ov7750 = to_ov7750(sd);
783 struct i2c_client *client = ov7750->client;
784 int ret = 0;
785
786 mutex_lock(&ov7750->mutex);
787
788 /* If the power state is not modified - no work to do. */
789 if (ov7750->power_on == !!on)
790 goto unlock_and_return;
791
792 if (on) {
793 ret = pm_runtime_get_sync(&client->dev);
794 if (ret < 0) {
795 pm_runtime_put_noidle(&client->dev);
796 goto unlock_and_return;
797 }
798
799 ret = ov7750_write_array(ov7750->client, ov7750_global_regs);
800 if (ret) {
801 v4l2_err(sd, "could not set init registers\n");
802 pm_runtime_put_noidle(&client->dev);
803 goto unlock_and_return;
804 }
805
806 ov7750->power_on = true;
807 } else {
808 pm_runtime_put(&client->dev);
809 ov7750->power_on = false;
810 }
811
812 unlock_and_return:
813 mutex_unlock(&ov7750->mutex);
814
815 return ret;
816 }
817
818 /* Calculate the delay in us by clock rate and clock cycles */
ov7750_cal_delay(u32 cycles)819 static inline u32 ov7750_cal_delay(u32 cycles)
820 {
821 return DIV_ROUND_UP(cycles, OV7750_XVCLK_FREQ / 1000 / 1000);
822 }
823
__ov7750_power_on(struct ov7750 * ov7750)824 static int __ov7750_power_on(struct ov7750 *ov7750)
825 {
826 int ret;
827 u32 delay_us;
828 struct device *dev = &ov7750->client->dev;
829
830 if (!IS_ERR_OR_NULL(ov7750->pins_default)) {
831 ret = pinctrl_select_state(ov7750->pinctrl,
832 ov7750->pins_default);
833 if (ret < 0)
834 dev_err(dev, "could not set pins\n");
835 }
836
837 ret = clk_set_rate(ov7750->xvclk, OV7750_XVCLK_FREQ);
838 if (ret < 0)
839 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
840 if (clk_get_rate(ov7750->xvclk) != OV7750_XVCLK_FREQ)
841 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
842 ret = clk_prepare_enable(ov7750->xvclk);
843 if (ret < 0) {
844 dev_err(dev, "Failed to enable xvclk\n");
845 return ret;
846 }
847
848 if (!IS_ERR(ov7750->reset_gpio))
849 gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
850
851 ret = regulator_bulk_enable(OV7750_NUM_SUPPLIES, ov7750->supplies);
852 if (ret < 0) {
853 dev_err(dev, "Failed to enable regulators\n");
854 goto disable_clk;
855 }
856
857 if (!IS_ERR(ov7750->reset_gpio))
858 gpiod_set_value_cansleep(ov7750->reset_gpio, 1);
859
860 usleep_range(500, 1000);
861 if (!IS_ERR(ov7750->pwdn_gpio))
862 gpiod_set_value_cansleep(ov7750->pwdn_gpio, 1);
863
864 /* 8192 cycles prior to first SCCB transaction */
865 delay_us = ov7750_cal_delay(8192);
866 usleep_range(delay_us, delay_us * 2);
867
868 return 0;
869
870 disable_clk:
871 clk_disable_unprepare(ov7750->xvclk);
872
873 return ret;
874 }
875
__ov7750_power_off(struct ov7750 * ov7750)876 static void __ov7750_power_off(struct ov7750 *ov7750)
877 {
878 int ret;
879 struct device *dev = &ov7750->client->dev;
880
881 if (!IS_ERR(ov7750->pwdn_gpio))
882 gpiod_set_value_cansleep(ov7750->pwdn_gpio, 0);
883 clk_disable_unprepare(ov7750->xvclk);
884 if (!IS_ERR(ov7750->reset_gpio))
885 gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
886 if (!IS_ERR_OR_NULL(ov7750->pins_sleep)) {
887 ret = pinctrl_select_state(ov7750->pinctrl,
888 ov7750->pins_sleep);
889 if (ret < 0)
890 dev_err(dev, "could not set pins\n");
891 }
892 regulator_bulk_disable(OV7750_NUM_SUPPLIES, ov7750->supplies);
893 }
894
ov7750_runtime_resume(struct device * dev)895 static int ov7750_runtime_resume(struct device *dev)
896 {
897 struct i2c_client *client = to_i2c_client(dev);
898 struct v4l2_subdev *sd = i2c_get_clientdata(client);
899 struct ov7750 *ov7750 = to_ov7750(sd);
900
901 return __ov7750_power_on(ov7750);
902 }
903
ov7750_runtime_suspend(struct device * dev)904 static int ov7750_runtime_suspend(struct device *dev)
905 {
906 struct i2c_client *client = to_i2c_client(dev);
907 struct v4l2_subdev *sd = i2c_get_clientdata(client);
908 struct ov7750 *ov7750 = to_ov7750(sd);
909
910 __ov7750_power_off(ov7750);
911
912 return 0;
913 }
914
915 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov7750_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)916 static int ov7750_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
917 {
918 struct ov7750 *ov7750 = to_ov7750(sd);
919 struct v4l2_mbus_framefmt *try_fmt =
920 v4l2_subdev_get_try_format(sd, fh->pad, 0);
921 const struct ov7750_mode *def_mode = &supported_modes[0];
922
923 mutex_lock(&ov7750->mutex);
924 /* Initialize try_fmt */
925 try_fmt->width = def_mode->width;
926 try_fmt->height = def_mode->height;
927 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
928 try_fmt->field = V4L2_FIELD_NONE;
929
930 mutex_unlock(&ov7750->mutex);
931 /* No crop or compose */
932
933 return 0;
934 }
935 #endif
936
ov7750_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)937 static int ov7750_enum_frame_interval(struct v4l2_subdev *sd,
938 struct v4l2_subdev_pad_config *cfg,
939 struct v4l2_subdev_frame_interval_enum *fie)
940 {
941 if (fie->index >= ARRAY_SIZE(supported_modes))
942 return -EINVAL;
943
944 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
945 fie->width = supported_modes[fie->index].width;
946 fie->height = supported_modes[fie->index].height;
947 fie->interval = supported_modes[fie->index].max_fps;
948 return 0;
949 }
950
ov7750_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * config)951 static int ov7750_g_mbus_config(struct v4l2_subdev *sd,
952 struct v4l2_mbus_config *config)
953 {
954 u32 val = 0;
955
956 val = 1 << (OV7750_LANES - 1) |
957 V4L2_MBUS_CSI2_CHANNEL_0 |
958 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
959 config->type = V4L2_MBUS_CSI2;
960 config->flags = val;
961
962 return 0;
963 }
964
965 static const struct dev_pm_ops ov7750_pm_ops = {
966 SET_RUNTIME_PM_OPS(ov7750_runtime_suspend,
967 ov7750_runtime_resume, NULL)
968 };
969
970 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
971 static const struct v4l2_subdev_internal_ops ov7750_internal_ops = {
972 .open = ov7750_open,
973 };
974 #endif
975
976 static const struct v4l2_subdev_core_ops ov7750_core_ops = {
977 .s_power = ov7750_s_power,
978 .ioctl = ov7750_ioctl,
979 #ifdef CONFIG_COMPAT
980 .compat_ioctl32 = ov7750_compat_ioctl32,
981 #endif
982 };
983
984 static const struct v4l2_subdev_video_ops ov7750_video_ops = {
985 .s_stream = ov7750_s_stream,
986 .g_mbus_config = ov7750_g_mbus_config,
987 };
988
989 static const struct v4l2_subdev_pad_ops ov7750_pad_ops = {
990 .enum_mbus_code = ov7750_enum_mbus_code,
991 .enum_frame_size = ov7750_enum_frame_sizes,
992 .enum_frame_interval = ov7750_enum_frame_interval,
993 .get_fmt = ov7750_get_fmt,
994 .set_fmt = ov7750_set_fmt,
995 };
996
997 static const struct v4l2_subdev_ops ov7750_subdev_ops = {
998 .core = &ov7750_core_ops,
999 .video = &ov7750_video_ops,
1000 .pad = &ov7750_pad_ops,
1001 };
1002
ov7750_set_ctrl(struct v4l2_ctrl * ctrl)1003 static int ov7750_set_ctrl(struct v4l2_ctrl *ctrl)
1004 {
1005 struct ov7750 *ov7750 = container_of(ctrl->handler,
1006 struct ov7750, ctrl_handler);
1007 struct i2c_client *client = ov7750->client;
1008 s64 max;
1009 int ret = 0;
1010
1011 /* Propagate change of current control to all related controls */
1012 switch (ctrl->id) {
1013 case V4L2_CID_VBLANK:
1014 /* Update max exposure while meeting expected vblanking */
1015 max = ov7750->cur_mode->height + ctrl->val -
1016 OV7750_EXP_MARGIN_LIMIT;
1017 __v4l2_ctrl_modify_range(ov7750->exposure,
1018 ov7750->exposure->minimum, max,
1019 ov7750->exposure->step,
1020 ov7750->exposure->default_value);
1021 break;
1022 }
1023
1024 if (!pm_runtime_get_if_in_use(&client->dev))
1025 return 0;
1026
1027 switch (ctrl->id) {
1028 case V4L2_CID_EXPOSURE:
1029 /* 4 least significant bits of expsoure are fractional part */
1030 ret = ov7750_write_reg(ov7750->client,
1031 OV7750_REG_EXPOSURE,
1032 OV7750_REG_VALUE_24BIT,
1033 ctrl->val << 4);
1034 break;
1035 case V4L2_CID_ANALOGUE_GAIN:
1036 ret = ov7750_write_reg(ov7750->client,
1037 OV7750_REG_GAIN_H,
1038 OV7750_REG_VALUE_08BIT,
1039 (ctrl->val >> OV7750_GAIN_H_SHIFT) &
1040 OV7750_GAIN_H_MASK);
1041 ret |= ov7750_write_reg(ov7750->client,
1042 OV7750_REG_GAIN_L,
1043 OV7750_REG_VALUE_08BIT,
1044 ctrl->val & OV7750_GAIN_L_MASK);
1045 break;
1046 case V4L2_CID_VBLANK:
1047 ret = ov7750_write_reg(ov7750->client,
1048 OV7750_REG_VTS,
1049 OV7750_REG_VALUE_16BIT,
1050 ctrl->val + ov7750->cur_mode->height);
1051 break;
1052 case V4L2_CID_TEST_PATTERN:
1053 ret = ov7750_enable_test_pattern(ov7750, ctrl->val);
1054 break;
1055 default:
1056 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1057 __func__, ctrl->id, ctrl->val);
1058 break;
1059 }
1060
1061 pm_runtime_put(&client->dev);
1062
1063 return ret;
1064 }
1065
1066 static const struct v4l2_ctrl_ops ov7750_ctrl_ops = {
1067 .s_ctrl = ov7750_set_ctrl,
1068 };
1069
ov7750_initialize_controls(struct ov7750 * ov7750)1070 static int ov7750_initialize_controls(struct ov7750 *ov7750)
1071 {
1072 const struct ov7750_mode *mode;
1073 struct v4l2_ctrl_handler *handler;
1074 struct v4l2_ctrl *ctrl;
1075 s64 exposure_max, vblank_def;
1076 u32 h_blank;
1077 int ret;
1078
1079 handler = &ov7750->ctrl_handler;
1080 mode = ov7750->cur_mode;
1081 ret = v4l2_ctrl_handler_init(handler, 8);
1082 if (ret)
1083 return ret;
1084 handler->lock = &ov7750->mutex;
1085
1086 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1087 0, 0, link_freq_menu_items);
1088 if (ctrl)
1089 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1090
1091 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1092 0, OV7750_PIXEL_RATE, 1, OV7750_PIXEL_RATE);
1093
1094 h_blank = mode->hts_def - mode->width;
1095 ov7750->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1096 h_blank, h_blank, 1, h_blank);
1097 if (ov7750->hblank)
1098 ov7750->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1099
1100 vblank_def = mode->vts_def - mode->height;
1101 ov7750->vblank = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1102 V4L2_CID_VBLANK, vblank_def,
1103 OV7750_VTS_MAX - mode->height,
1104 1, vblank_def);
1105
1106 exposure_max = mode->vts_def - OV7750_EXP_MARGIN_LIMIT;
1107 ov7750->exposure = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1108 V4L2_CID_EXPOSURE, OV7750_EXPOSURE_MIN,
1109 exposure_max, OV7750_EXPOSURE_STEP,
1110 mode->exp_def);
1111
1112 ov7750->anal_gain = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
1113 V4L2_CID_ANALOGUE_GAIN, OV7750_GAIN_MIN,
1114 OV7750_GAIN_MAX, OV7750_GAIN_STEP,
1115 OV7750_GAIN_DEFAULT);
1116
1117 ov7750->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1118 &ov7750_ctrl_ops, V4L2_CID_TEST_PATTERN,
1119 ARRAY_SIZE(ov7750_test_pattern_menu) - 1,
1120 0, 0, ov7750_test_pattern_menu);
1121
1122 if (handler->error) {
1123 ret = handler->error;
1124 dev_err(&ov7750->client->dev,
1125 "Failed to init controls(%d)\n", ret);
1126 goto err_free_handler;
1127 }
1128
1129 ov7750->subdev.ctrl_handler = handler;
1130
1131 return 0;
1132
1133 err_free_handler:
1134 v4l2_ctrl_handler_free(handler);
1135
1136 return ret;
1137 }
1138
ov7750_check_sensor_id(struct ov7750 * ov7750,struct i2c_client * client)1139 static int ov7750_check_sensor_id(struct ov7750 *ov7750,
1140 struct i2c_client *client)
1141 {
1142 struct device *dev = &ov7750->client->dev;
1143 u32 id = 0;
1144 int ret;
1145
1146 ret = ov7750_read_reg(client, OV7750_REG_CHIP_ID,
1147 OV7750_REG_VALUE_16BIT, &id);
1148 if (id != CHIP_ID) {
1149 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1150 return -ENODEV;
1151 }
1152
1153 ret = ov7750_read_reg(client, OV7750_CHIP_REVISION_REG,
1154 OV7750_REG_VALUE_08BIT, &id);
1155 if (ret) {
1156 dev_err(dev, "Read chip revision register error\n");
1157 return ret;
1158 }
1159 id &= 0xf0;
1160 if (id == OV7750_R1F)
1161 ov7750_global_regs = ov7750_global_regs_r1f;
1162 else
1163 ov7750_global_regs = ov7750_global_regs_rxx;
1164 dev_info(dev, "Detected OV%04x sensor, REVISION 0x%x\n", CHIP_ID, id);
1165
1166 return 0;
1167 }
1168
ov7750_configure_regulators(struct ov7750 * ov7750)1169 static int ov7750_configure_regulators(struct ov7750 *ov7750)
1170 {
1171 unsigned int i;
1172
1173 for (i = 0; i < OV7750_NUM_SUPPLIES; i++)
1174 ov7750->supplies[i].supply = ov7750_supply_names[i];
1175
1176 return devm_regulator_bulk_get(&ov7750->client->dev,
1177 OV7750_NUM_SUPPLIES,
1178 ov7750->supplies);
1179 }
1180
ov7750_probe(struct i2c_client * client,const struct i2c_device_id * id)1181 static int ov7750_probe(struct i2c_client *client,
1182 const struct i2c_device_id *id)
1183 {
1184 struct device *dev = &client->dev;
1185 struct device_node *node = dev->of_node;
1186 struct ov7750 *ov7750;
1187 struct v4l2_subdev *sd;
1188 char facing[2];
1189 int ret;
1190
1191 dev_info(dev, "driver version: %02x.%02x.%02x",
1192 DRIVER_VERSION >> 16,
1193 (DRIVER_VERSION & 0xff00) >> 8,
1194 DRIVER_VERSION & 0x00ff);
1195
1196 ov7750 = devm_kzalloc(dev, sizeof(*ov7750), GFP_KERNEL);
1197 if (!ov7750)
1198 return -ENOMEM;
1199
1200 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1201 &ov7750->module_index);
1202 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1203 &ov7750->module_facing);
1204 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1205 &ov7750->module_name);
1206 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1207 &ov7750->len_name);
1208 if (ret) {
1209 dev_err(dev, "could not get module information!\n");
1210 return -EINVAL;
1211 }
1212
1213 ov7750->client = client;
1214 ov7750->cur_mode = &supported_modes[0];
1215
1216 ov7750->xvclk = devm_clk_get(dev, "xvclk");
1217 if (IS_ERR(ov7750->xvclk)) {
1218 dev_err(dev, "Failed to get xvclk\n");
1219 return -EINVAL;
1220 }
1221
1222 ov7750->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1223 if (IS_ERR(ov7750->reset_gpio))
1224 dev_warn(dev, "Failed to get reset-gpios\n");
1225
1226 ov7750->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1227 if (IS_ERR(ov7750->pwdn_gpio))
1228 dev_warn(dev, "Failed to get pwdn-gpios\n");
1229
1230 ret = ov7750_configure_regulators(ov7750);
1231 if (ret) {
1232 dev_err(dev, "Failed to get power regulators\n");
1233 return ret;
1234 }
1235
1236 ov7750->pinctrl = devm_pinctrl_get(dev);
1237 if (!IS_ERR(ov7750->pinctrl)) {
1238 ov7750->pins_default =
1239 pinctrl_lookup_state(ov7750->pinctrl,
1240 OF_CAMERA_PINCTRL_DEFAULT);
1241 if (IS_ERR(ov7750->pins_default))
1242 dev_err(dev, "could not get default pinstate\n");
1243
1244 ov7750->pins_sleep =
1245 pinctrl_lookup_state(ov7750->pinctrl,
1246 OF_CAMERA_PINCTRL_SLEEP);
1247 if (IS_ERR(ov7750->pins_sleep))
1248 dev_err(dev, "could not get sleep pinstate\n");
1249 }
1250
1251 mutex_init(&ov7750->mutex);
1252
1253 sd = &ov7750->subdev;
1254 v4l2_i2c_subdev_init(sd, client, &ov7750_subdev_ops);
1255 ret = ov7750_initialize_controls(ov7750);
1256 if (ret)
1257 goto err_destroy_mutex;
1258
1259 ret = __ov7750_power_on(ov7750);
1260 if (ret)
1261 goto err_free_handler;
1262
1263 ret = ov7750_check_sensor_id(ov7750, client);
1264 if (ret)
1265 goto err_power_off;
1266
1267 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1268 sd->internal_ops = &ov7750_internal_ops;
1269 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1270 V4L2_SUBDEV_FL_HAS_EVENTS;
1271 #endif
1272 #if defined(CONFIG_MEDIA_CONTROLLER)
1273 ov7750->pad.flags = MEDIA_PAD_FL_SOURCE;
1274 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1275 ret = media_entity_pads_init(&sd->entity, 1, &ov7750->pad);
1276 if (ret < 0)
1277 goto err_power_off;
1278 #endif
1279
1280 memset(facing, 0, sizeof(facing));
1281 if (strcmp(ov7750->module_facing, "back") == 0)
1282 facing[0] = 'b';
1283 else
1284 facing[0] = 'f';
1285
1286 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1287 ov7750->module_index, facing,
1288 OV7750_NAME, dev_name(sd->dev));
1289 ret = v4l2_async_register_subdev_sensor_common(sd);
1290 if (ret) {
1291 dev_err(dev, "v4l2 async register subdev failed\n");
1292 goto err_clean_entity;
1293 }
1294
1295 pm_runtime_set_active(dev);
1296 pm_runtime_enable(dev);
1297 pm_runtime_idle(dev);
1298
1299 return 0;
1300
1301 err_clean_entity:
1302 #if defined(CONFIG_MEDIA_CONTROLLER)
1303 media_entity_cleanup(&sd->entity);
1304 #endif
1305 err_power_off:
1306 __ov7750_power_off(ov7750);
1307 err_free_handler:
1308 v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
1309 err_destroy_mutex:
1310 mutex_destroy(&ov7750->mutex);
1311
1312 return ret;
1313 }
1314
ov7750_remove(struct i2c_client * client)1315 static int ov7750_remove(struct i2c_client *client)
1316 {
1317 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1318 struct ov7750 *ov7750 = to_ov7750(sd);
1319
1320 v4l2_async_unregister_subdev(sd);
1321 #if defined(CONFIG_MEDIA_CONTROLLER)
1322 media_entity_cleanup(&sd->entity);
1323 #endif
1324 v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
1325 mutex_destroy(&ov7750->mutex);
1326
1327 pm_runtime_disable(&client->dev);
1328 if (!pm_runtime_status_suspended(&client->dev))
1329 __ov7750_power_off(ov7750);
1330 pm_runtime_set_suspended(&client->dev);
1331
1332 return 0;
1333 }
1334
1335 #if IS_ENABLED(CONFIG_OF)
1336 static const struct of_device_id ov7750_of_match[] = {
1337 { .compatible = "ovti,ov7750" },
1338 {},
1339 };
1340 MODULE_DEVICE_TABLE(of, ov7750_of_match);
1341 #endif
1342
1343 static const struct i2c_device_id ov7750_match_id[] = {
1344 { "ovti,ov7750", 0 },
1345 { },
1346 };
1347
1348 static struct i2c_driver ov7750_i2c_driver = {
1349 .driver = {
1350 .name = OV7750_NAME,
1351 .pm = &ov7750_pm_ops,
1352 .of_match_table = of_match_ptr(ov7750_of_match),
1353 },
1354 .probe = &ov7750_probe,
1355 .remove = &ov7750_remove,
1356 .id_table = ov7750_match_id,
1357 };
1358
sensor_mod_init(void)1359 static int __init sensor_mod_init(void)
1360 {
1361 return i2c_add_driver(&ov7750_i2c_driver);
1362 }
1363
sensor_mod_exit(void)1364 static void __exit sensor_mod_exit(void)
1365 {
1366 i2c_del_driver(&ov7750_i2c_driver);
1367 }
1368
1369 device_initcall_sync(sensor_mod_init);
1370 module_exit(sensor_mod_exit);
1371
1372 MODULE_DESCRIPTION("OmniVision ov7750 sensor driver");
1373 MODULE_LICENSE("GPL v2");
1374
1375