xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/ov5695.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ov5695 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * V0.0X01.0X01 add poweron function.
8*4882a593Smuzhiyun  * V0.0X01.0X02 add enum_frame_interval function.
9*4882a593Smuzhiyun  * V0.0X01.0X03 add quick stream on/off
10*4882a593Smuzhiyun  * V0.0X01.0X04 add function g_mbus_config
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
21*4882a593Smuzhiyun #include <linux/sysfs.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/version.h>
24*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
25*4882a593Smuzhiyun #include <media/media-entity.h>
26*4882a593Smuzhiyun #include <media/v4l2-async.h>
27*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
28*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x04)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
33*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* 45Mhz * 4 Binning */
37*4882a593Smuzhiyun #define OV5695_PIXEL_RATE		(45 * 1000 * 1000 * 4)
38*4882a593Smuzhiyun #define OV5695_XVCLK_FREQ		24000000
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define CHIP_ID				0x005695
41*4882a593Smuzhiyun #define OV5695_REG_CHIP_ID		0x300a
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define OV5695_REG_CTRL_MODE		0x0100
44*4882a593Smuzhiyun #define OV5695_MODE_SW_STANDBY		0x0
45*4882a593Smuzhiyun #define OV5695_MODE_STREAMING		BIT(0)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define OV5695_REG_EXPOSURE		0x3500
48*4882a593Smuzhiyun #define	OV5695_EXPOSURE_MIN		4
49*4882a593Smuzhiyun #define	OV5695_EXPOSURE_STEP		1
50*4882a593Smuzhiyun #define OV5695_VTS_MAX			0x7fff
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define OV5695_REG_ANALOG_GAIN		0x3509
53*4882a593Smuzhiyun #define	ANALOG_GAIN_MIN			0x10
54*4882a593Smuzhiyun #define	ANALOG_GAIN_MAX			0xf8
55*4882a593Smuzhiyun #define	ANALOG_GAIN_STEP		1
56*4882a593Smuzhiyun #define	ANALOG_GAIN_DEFAULT		0xf8
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define OV5695_REG_DIGI_GAIN_H		0x350a
59*4882a593Smuzhiyun #define OV5695_REG_DIGI_GAIN_L		0x350b
60*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_L_MASK		0x3f
61*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_H_SHIFT	6
62*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_MIN		0
63*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_MAX		(0x4000 - 1)
64*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_STEP		1
65*4882a593Smuzhiyun #define OV5695_DIGI_GAIN_DEFAULT	1024
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define OV5695_REG_TEST_PATTERN		0x4503
68*4882a593Smuzhiyun #define	OV5695_TEST_PATTERN_ENABLE	0x80
69*4882a593Smuzhiyun #define	OV5695_TEST_PATTERN_DISABLE	0x0
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define OV5695_REG_VTS			0x380e
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define REG_NULL			0xFFFF
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define OV5695_REG_VALUE_08BIT		1
76*4882a593Smuzhiyun #define OV5695_REG_VALUE_16BIT		2
77*4882a593Smuzhiyun #define OV5695_REG_VALUE_24BIT		3
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define OV5695_LANES			2
80*4882a593Smuzhiyun #define OV5695_BITS_PER_SAMPLE		10
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define I2C_M_WR			0
83*4882a593Smuzhiyun #define I2C_MSG_MAX			300
84*4882a593Smuzhiyun #define I2C_DATA_MAX			(I2C_MSG_MAX * 3)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define OV5695_NAME			"ov5695"
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun static const char * const ov5695_supply_names[] = {
89*4882a593Smuzhiyun 	"avdd",		/* Analog power */
90*4882a593Smuzhiyun 	"dovdd",	/* Digital I/O power */
91*4882a593Smuzhiyun 	"dvdd",		/* Digital core power */
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define OV5695_NUM_SUPPLIES ARRAY_SIZE(ov5695_supply_names)
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun struct regval {
97*4882a593Smuzhiyun 	u16 addr;
98*4882a593Smuzhiyun 	u8 val;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct ov5695_mode {
102*4882a593Smuzhiyun 	u32 width;
103*4882a593Smuzhiyun 	u32 height;
104*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
105*4882a593Smuzhiyun 	u32 hts_def;
106*4882a593Smuzhiyun 	u32 vts_def;
107*4882a593Smuzhiyun 	u32 exp_def;
108*4882a593Smuzhiyun 	const struct regval *reg_list;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun struct ov5695 {
112*4882a593Smuzhiyun 	struct i2c_client	*client;
113*4882a593Smuzhiyun 	struct clk		*xvclk;
114*4882a593Smuzhiyun 	struct gpio_desc	*reset_gpio;
115*4882a593Smuzhiyun 	struct gpio_desc	*pwdn_gpio;
116*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[OV5695_NUM_SUPPLIES];
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	struct v4l2_subdev	subdev;
119*4882a593Smuzhiyun 	struct media_pad	pad;
120*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
121*4882a593Smuzhiyun 	struct v4l2_ctrl	*exposure;
122*4882a593Smuzhiyun 	struct v4l2_ctrl	*anal_gain;
123*4882a593Smuzhiyun 	struct v4l2_ctrl	*digi_gain;
124*4882a593Smuzhiyun 	struct v4l2_ctrl	*hblank;
125*4882a593Smuzhiyun 	struct v4l2_ctrl	*vblank;
126*4882a593Smuzhiyun 	struct v4l2_ctrl	*test_pattern;
127*4882a593Smuzhiyun 	struct mutex		mutex;
128*4882a593Smuzhiyun 	bool			streaming;
129*4882a593Smuzhiyun 	bool			power_on;
130*4882a593Smuzhiyun 	const struct ov5695_mode *cur_mode;
131*4882a593Smuzhiyun 	u32			module_index;
132*4882a593Smuzhiyun 	const char		*module_facing;
133*4882a593Smuzhiyun 	const char		*module_name;
134*4882a593Smuzhiyun 	const char		*len_name;
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #define to_ov5695(sd) container_of(sd, struct ov5695, subdev)
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun  * Xclk 24Mhz
141*4882a593Smuzhiyun  * Pclk 45Mhz
142*4882a593Smuzhiyun  * linelength 672(0x2a0)
143*4882a593Smuzhiyun  * framelength 2232(0x8b8)
144*4882a593Smuzhiyun  * grabwindow_width 1296
145*4882a593Smuzhiyun  * grabwindow_height 972
146*4882a593Smuzhiyun  * max_framerate 30fps
147*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
148*4882a593Smuzhiyun  */
149*4882a593Smuzhiyun static const struct regval ov5695_global_regs[] = {
150*4882a593Smuzhiyun 	{0x0103, 0x01},
151*4882a593Smuzhiyun 	{0x0100, 0x00},
152*4882a593Smuzhiyun 	{0x0300, 0x04},
153*4882a593Smuzhiyun 	{0x0301, 0x00},
154*4882a593Smuzhiyun 	{0x0302, 0x69},
155*4882a593Smuzhiyun 	{0x0303, 0x00},
156*4882a593Smuzhiyun 	{0x0304, 0x00},
157*4882a593Smuzhiyun 	{0x0305, 0x01},
158*4882a593Smuzhiyun 	{0x0307, 0x00},
159*4882a593Smuzhiyun 	{0x030b, 0x00},
160*4882a593Smuzhiyun 	{0x030c, 0x00},
161*4882a593Smuzhiyun 	{0x030d, 0x1e},
162*4882a593Smuzhiyun 	{0x030e, 0x04},
163*4882a593Smuzhiyun 	{0x030f, 0x03},
164*4882a593Smuzhiyun 	{0x0312, 0x01},
165*4882a593Smuzhiyun 	{0x3000, 0x00},
166*4882a593Smuzhiyun 	{0x3002, 0xa1},
167*4882a593Smuzhiyun 	{0x3008, 0x00},
168*4882a593Smuzhiyun 	{0x3010, 0x00},
169*4882a593Smuzhiyun 	{0x3022, 0x51},
170*4882a593Smuzhiyun 	{0x3106, 0x15},
171*4882a593Smuzhiyun 	{0x3107, 0x01},
172*4882a593Smuzhiyun 	{0x3108, 0x05},
173*4882a593Smuzhiyun 	{0x3500, 0x00},
174*4882a593Smuzhiyun 	{0x3501, 0x45},
175*4882a593Smuzhiyun 	{0x3502, 0x00},
176*4882a593Smuzhiyun 	{0x3503, 0x08},
177*4882a593Smuzhiyun 	{0x3504, 0x03},
178*4882a593Smuzhiyun 	{0x3505, 0x8c},
179*4882a593Smuzhiyun 	{0x3507, 0x03},
180*4882a593Smuzhiyun 	{0x3508, 0x00},
181*4882a593Smuzhiyun 	{0x3509, 0x10},
182*4882a593Smuzhiyun 	{0x350c, 0x00},
183*4882a593Smuzhiyun 	{0x350d, 0x80},
184*4882a593Smuzhiyun 	{0x3510, 0x00},
185*4882a593Smuzhiyun 	{0x3511, 0x02},
186*4882a593Smuzhiyun 	{0x3512, 0x00},
187*4882a593Smuzhiyun 	{0x3601, 0x55},
188*4882a593Smuzhiyun 	{0x3602, 0x58},
189*4882a593Smuzhiyun 	{0x3614, 0x30},
190*4882a593Smuzhiyun 	{0x3615, 0x77},
191*4882a593Smuzhiyun 	{0x3621, 0x08},
192*4882a593Smuzhiyun 	{0x3624, 0x40},
193*4882a593Smuzhiyun 	{0x3633, 0x0c},
194*4882a593Smuzhiyun 	{0x3634, 0x0c},
195*4882a593Smuzhiyun 	{0x3635, 0x0c},
196*4882a593Smuzhiyun 	{0x3636, 0x0c},
197*4882a593Smuzhiyun 	{0x3638, 0x00},
198*4882a593Smuzhiyun 	{0x3639, 0x00},
199*4882a593Smuzhiyun 	{0x363a, 0x00},
200*4882a593Smuzhiyun 	{0x363b, 0x00},
201*4882a593Smuzhiyun 	{0x363c, 0xff},
202*4882a593Smuzhiyun 	{0x363d, 0xfa},
203*4882a593Smuzhiyun 	{0x3650, 0x44},
204*4882a593Smuzhiyun 	{0x3651, 0x44},
205*4882a593Smuzhiyun 	{0x3652, 0x44},
206*4882a593Smuzhiyun 	{0x3653, 0x44},
207*4882a593Smuzhiyun 	{0x3654, 0x44},
208*4882a593Smuzhiyun 	{0x3655, 0x44},
209*4882a593Smuzhiyun 	{0x3656, 0x44},
210*4882a593Smuzhiyun 	{0x3657, 0x44},
211*4882a593Smuzhiyun 	{0x3660, 0x00},
212*4882a593Smuzhiyun 	{0x3661, 0x00},
213*4882a593Smuzhiyun 	{0x3662, 0x00},
214*4882a593Smuzhiyun 	{0x366a, 0x00},
215*4882a593Smuzhiyun 	{0x366e, 0x0c},
216*4882a593Smuzhiyun 	{0x3673, 0x04},
217*4882a593Smuzhiyun 	{0x3700, 0x14},
218*4882a593Smuzhiyun 	{0x3703, 0x0c},
219*4882a593Smuzhiyun 	{0x3715, 0x01},
220*4882a593Smuzhiyun 	{0x3733, 0x10},
221*4882a593Smuzhiyun 	{0x3734, 0x40},
222*4882a593Smuzhiyun 	{0x373f, 0xa0},
223*4882a593Smuzhiyun 	{0x3765, 0x20},
224*4882a593Smuzhiyun 	{0x37a1, 0x1d},
225*4882a593Smuzhiyun 	{0x37a8, 0x26},
226*4882a593Smuzhiyun 	{0x37ab, 0x14},
227*4882a593Smuzhiyun 	{0x37c2, 0x04},
228*4882a593Smuzhiyun 	{0x37cb, 0x09},
229*4882a593Smuzhiyun 	{0x37cc, 0x13},
230*4882a593Smuzhiyun 	{0x37cd, 0x1f},
231*4882a593Smuzhiyun 	{0x37ce, 0x1f},
232*4882a593Smuzhiyun 	{0x3800, 0x00},
233*4882a593Smuzhiyun 	{0x3801, 0x00},
234*4882a593Smuzhiyun 	{0x3802, 0x00},
235*4882a593Smuzhiyun 	{0x3803, 0x00},
236*4882a593Smuzhiyun 	{0x3804, 0x0a},
237*4882a593Smuzhiyun 	{0x3805, 0x3f},
238*4882a593Smuzhiyun 	{0x3806, 0x07},
239*4882a593Smuzhiyun 	{0x3807, 0xaf},
240*4882a593Smuzhiyun 	{0x3808, 0x05},
241*4882a593Smuzhiyun 	{0x3809, 0x10},
242*4882a593Smuzhiyun 	{0x380a, 0x03},
243*4882a593Smuzhiyun 	{0x380b, 0xcc},
244*4882a593Smuzhiyun 	{0x380c, 0x02},
245*4882a593Smuzhiyun 	{0x380d, 0xa0},
246*4882a593Smuzhiyun 	{0x380e, 0x08},
247*4882a593Smuzhiyun 	{0x380f, 0xb8},
248*4882a593Smuzhiyun 	{0x3810, 0x00},
249*4882a593Smuzhiyun 	{0x3811, 0x06},
250*4882a593Smuzhiyun 	{0x3812, 0x00},
251*4882a593Smuzhiyun 	{0x3813, 0x06},
252*4882a593Smuzhiyun 	{0x3814, 0x03},
253*4882a593Smuzhiyun 	{0x3815, 0x01},
254*4882a593Smuzhiyun 	{0x3816, 0x03},
255*4882a593Smuzhiyun 	{0x3817, 0x01},
256*4882a593Smuzhiyun 	{0x3818, 0x00},
257*4882a593Smuzhiyun 	{0x3819, 0x00},
258*4882a593Smuzhiyun 	{0x381a, 0x00},
259*4882a593Smuzhiyun 	{0x381b, 0x01},
260*4882a593Smuzhiyun 	{0x3820, 0x8b},
261*4882a593Smuzhiyun 	{0x3821, 0x01},
262*4882a593Smuzhiyun 	{0x3c80, 0x08},
263*4882a593Smuzhiyun 	{0x3c82, 0x00},
264*4882a593Smuzhiyun 	{0x3c83, 0x00},
265*4882a593Smuzhiyun 	{0x3c88, 0x00},
266*4882a593Smuzhiyun 	{0x3d85, 0x14},
267*4882a593Smuzhiyun 	{0x3f02, 0x08},
268*4882a593Smuzhiyun 	{0x3f03, 0x10},
269*4882a593Smuzhiyun 	{0x4008, 0x02},
270*4882a593Smuzhiyun 	{0x4009, 0x09},
271*4882a593Smuzhiyun 	{0x404e, 0x20},
272*4882a593Smuzhiyun 	{0x4501, 0x00},
273*4882a593Smuzhiyun 	{0x4502, 0x10},
274*4882a593Smuzhiyun 	{0x4800, 0x00},
275*4882a593Smuzhiyun 	{0x481f, 0x2a},
276*4882a593Smuzhiyun 	{0x4837, 0x13},
277*4882a593Smuzhiyun 	{0x5000, 0x17},
278*4882a593Smuzhiyun 	{0x5780, 0x3e},
279*4882a593Smuzhiyun 	{0x5781, 0x0f},
280*4882a593Smuzhiyun 	{0x5782, 0x44},
281*4882a593Smuzhiyun 	{0x5783, 0x02},
282*4882a593Smuzhiyun 	{0x5784, 0x01},
283*4882a593Smuzhiyun 	{0x5785, 0x01},
284*4882a593Smuzhiyun 	{0x5786, 0x00},
285*4882a593Smuzhiyun 	{0x5787, 0x04},
286*4882a593Smuzhiyun 	{0x5788, 0x02},
287*4882a593Smuzhiyun 	{0x5789, 0x0f},
288*4882a593Smuzhiyun 	{0x578a, 0xfd},
289*4882a593Smuzhiyun 	{0x578b, 0xf5},
290*4882a593Smuzhiyun 	{0x578c, 0xf5},
291*4882a593Smuzhiyun 	{0x578d, 0x03},
292*4882a593Smuzhiyun 	{0x578e, 0x08},
293*4882a593Smuzhiyun 	{0x578f, 0x0c},
294*4882a593Smuzhiyun 	{0x5790, 0x08},
295*4882a593Smuzhiyun 	{0x5791, 0x06},
296*4882a593Smuzhiyun 	{0x5792, 0x00},
297*4882a593Smuzhiyun 	{0x5793, 0x52},
298*4882a593Smuzhiyun 	{0x5794, 0xa3},
299*4882a593Smuzhiyun 	{0x5b00, 0x00},
300*4882a593Smuzhiyun 	{0x5b01, 0x1c},
301*4882a593Smuzhiyun 	{0x5b02, 0x00},
302*4882a593Smuzhiyun 	{0x5b03, 0x7f},
303*4882a593Smuzhiyun 	{0x5b05, 0x6c},
304*4882a593Smuzhiyun 	{0x5e10, 0xfc},
305*4882a593Smuzhiyun 	{0x4010, 0xf1},
306*4882a593Smuzhiyun 	{0x3503, 0x08},
307*4882a593Smuzhiyun 	{0x3505, 0x8c},
308*4882a593Smuzhiyun 	{0x3507, 0x03},
309*4882a593Smuzhiyun 	{0x3508, 0x00},
310*4882a593Smuzhiyun 	{0x3509, 0xf8},
311*4882a593Smuzhiyun 	{REG_NULL, 0x00},
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun /*
315*4882a593Smuzhiyun  * Xclk 24Mhz
316*4882a593Smuzhiyun  * Pclk 45Mhz
317*4882a593Smuzhiyun  * linelength 740(0x2e4)
318*4882a593Smuzhiyun  * framelength 2024(0x7e8)
319*4882a593Smuzhiyun  * grabwindow_width 2592
320*4882a593Smuzhiyun  * grabwindow_height 1944
321*4882a593Smuzhiyun  * max_framerate 30fps
322*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
323*4882a593Smuzhiyun  */
324*4882a593Smuzhiyun static const struct regval ov5695_2592x1944_regs[] = {
325*4882a593Smuzhiyun 	{0x3501, 0x7e},
326*4882a593Smuzhiyun 	{0x366e, 0x18},
327*4882a593Smuzhiyun 	{0x3800, 0x00},
328*4882a593Smuzhiyun 	{0x3801, 0x00},
329*4882a593Smuzhiyun 	{0x3802, 0x00},
330*4882a593Smuzhiyun 	{0x3803, 0x04},
331*4882a593Smuzhiyun 	{0x3804, 0x0a},
332*4882a593Smuzhiyun 	{0x3805, 0x3f},
333*4882a593Smuzhiyun 	{0x3806, 0x07},
334*4882a593Smuzhiyun 	{0x3807, 0xab},
335*4882a593Smuzhiyun 	{0x3808, 0x0a},
336*4882a593Smuzhiyun 	{0x3809, 0x20},
337*4882a593Smuzhiyun 	{0x380a, 0x07},
338*4882a593Smuzhiyun 	{0x380b, 0x98},
339*4882a593Smuzhiyun 	{0x380c, 0x02},
340*4882a593Smuzhiyun 	{0x380d, 0xe4},
341*4882a593Smuzhiyun 	{0x380e, 0x07},
342*4882a593Smuzhiyun 	{0x380f, 0xe8},
343*4882a593Smuzhiyun 	{0x3811, 0x06},
344*4882a593Smuzhiyun 	{0x3813, 0x08},
345*4882a593Smuzhiyun 	{0x3814, 0x01},
346*4882a593Smuzhiyun 	{0x3816, 0x01},
347*4882a593Smuzhiyun 	{0x3817, 0x01},
348*4882a593Smuzhiyun 	{0x3820, 0x88},
349*4882a593Smuzhiyun 	{0x3821, 0x00},
350*4882a593Smuzhiyun 	{0x4501, 0x00},
351*4882a593Smuzhiyun 	{0x4008, 0x04},
352*4882a593Smuzhiyun 	{0x4009, 0x13},
353*4882a593Smuzhiyun 	{REG_NULL, 0x00},
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun /*
357*4882a593Smuzhiyun  * Xclk 24Mhz
358*4882a593Smuzhiyun  * Pclk 45Mhz
359*4882a593Smuzhiyun  * linelength 672(0x2a0)
360*4882a593Smuzhiyun  * framelength 2232(0x8b8)
361*4882a593Smuzhiyun  * grabwindow_width 1920
362*4882a593Smuzhiyun  * grabwindow_height 1080
363*4882a593Smuzhiyun  * max_framerate 30fps
364*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
365*4882a593Smuzhiyun  */
366*4882a593Smuzhiyun static const struct regval ov5695_1920x1080_regs[] = {
367*4882a593Smuzhiyun 	{0x3501, 0x45},
368*4882a593Smuzhiyun 	{0x366e, 0x18},
369*4882a593Smuzhiyun 	{0x3800, 0x01},
370*4882a593Smuzhiyun 	{0x3801, 0x50},
371*4882a593Smuzhiyun 	{0x3802, 0x01},
372*4882a593Smuzhiyun 	{0x3803, 0xb8},
373*4882a593Smuzhiyun 	{0x3804, 0x08},
374*4882a593Smuzhiyun 	{0x3805, 0xef},
375*4882a593Smuzhiyun 	{0x3806, 0x05},
376*4882a593Smuzhiyun 	{0x3807, 0xf7},
377*4882a593Smuzhiyun 	{0x3808, 0x07},
378*4882a593Smuzhiyun 	{0x3809, 0x80},
379*4882a593Smuzhiyun 	{0x380a, 0x04},
380*4882a593Smuzhiyun 	{0x380b, 0x38},
381*4882a593Smuzhiyun 	{0x380c, 0x02},
382*4882a593Smuzhiyun 	{0x380d, 0xa0},
383*4882a593Smuzhiyun 	{0x380e, 0x08},
384*4882a593Smuzhiyun 	{0x380f, 0xb8},
385*4882a593Smuzhiyun 	{0x3811, 0x06},
386*4882a593Smuzhiyun 	{0x3813, 0x04},
387*4882a593Smuzhiyun 	{0x3814, 0x01},
388*4882a593Smuzhiyun 	{0x3816, 0x01},
389*4882a593Smuzhiyun 	{0x3817, 0x01},
390*4882a593Smuzhiyun 	{0x3820, 0x88},
391*4882a593Smuzhiyun 	{0x3821, 0x00},
392*4882a593Smuzhiyun 	{0x4501, 0x00},
393*4882a593Smuzhiyun 	{0x4008, 0x04},
394*4882a593Smuzhiyun 	{0x4009, 0x13},
395*4882a593Smuzhiyun 	{REG_NULL, 0x00}
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun /*
399*4882a593Smuzhiyun  * Xclk 24Mhz
400*4882a593Smuzhiyun  * Pclk 45Mhz
401*4882a593Smuzhiyun  * linelength 740(0x02e4)
402*4882a593Smuzhiyun  * framelength 1012(0x03f4)
403*4882a593Smuzhiyun  * grabwindow_width 1296
404*4882a593Smuzhiyun  * grabwindow_height 972
405*4882a593Smuzhiyun  * max_framerate 60fps
406*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
407*4882a593Smuzhiyun  */
408*4882a593Smuzhiyun static const struct regval ov5695_1296x972_regs[] = {
409*4882a593Smuzhiyun 	{0x3501, 0x3e},
410*4882a593Smuzhiyun 	{0x3611, 0x58},
411*4882a593Smuzhiyun 	{0x3706, 0x24},
412*4882a593Smuzhiyun 	{0x3714, 0x27},
413*4882a593Smuzhiyun 	{0x3716, 0x00},
414*4882a593Smuzhiyun 	{0x3717, 0x02},
415*4882a593Smuzhiyun 	{0x37c3, 0xf0},
416*4882a593Smuzhiyun 	{0x380d, 0xe4},
417*4882a593Smuzhiyun 	{0x380e, 0x03},
418*4882a593Smuzhiyun 	{0x380f, 0xf4},
419*4882a593Smuzhiyun 	{0x3811, 0x00},
420*4882a593Smuzhiyun 	{0x5000, 0x13},
421*4882a593Smuzhiyun 	{REG_NULL, 0x00}
422*4882a593Smuzhiyun };
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun /*
425*4882a593Smuzhiyun  * Xclk 24Mhz
426*4882a593Smuzhiyun  * Pclk 45Mhz
427*4882a593Smuzhiyun  * linelength 672(0x2a0)
428*4882a593Smuzhiyun  * framelength 2232(0x8b8)
429*4882a593Smuzhiyun  * grabwindow_width 1280
430*4882a593Smuzhiyun  * grabwindow_height 720
431*4882a593Smuzhiyun  * max_framerate 30fps
432*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
433*4882a593Smuzhiyun  */
434*4882a593Smuzhiyun static const struct regval ov5695_1280x720_regs[] = {
435*4882a593Smuzhiyun 	{0x3501, 0x45},
436*4882a593Smuzhiyun 	{0x366e, 0x0c},
437*4882a593Smuzhiyun 	{0x3800, 0x00},
438*4882a593Smuzhiyun 	{0x3801, 0x00},
439*4882a593Smuzhiyun 	{0x3802, 0x01},
440*4882a593Smuzhiyun 	{0x3803, 0x00},
441*4882a593Smuzhiyun 	{0x3804, 0x0a},
442*4882a593Smuzhiyun 	{0x3805, 0x3f},
443*4882a593Smuzhiyun 	{0x3806, 0x06},
444*4882a593Smuzhiyun 	{0x3807, 0xaf},
445*4882a593Smuzhiyun 	{0x3808, 0x05},
446*4882a593Smuzhiyun 	{0x3809, 0x00},
447*4882a593Smuzhiyun 	{0x380a, 0x02},
448*4882a593Smuzhiyun 	{0x380b, 0xd0},
449*4882a593Smuzhiyun 	{0x380c, 0x02},
450*4882a593Smuzhiyun 	{0x380d, 0xa0},
451*4882a593Smuzhiyun 	{0x380e, 0x08},
452*4882a593Smuzhiyun 	{0x380f, 0xb8},
453*4882a593Smuzhiyun 	{0x3811, 0x06},
454*4882a593Smuzhiyun 	{0x3813, 0x02},
455*4882a593Smuzhiyun 	{0x3814, 0x03},
456*4882a593Smuzhiyun 	{0x3816, 0x03},
457*4882a593Smuzhiyun 	{0x3817, 0x01},
458*4882a593Smuzhiyun 	{0x3820, 0x8b},
459*4882a593Smuzhiyun 	{0x3821, 0x01},
460*4882a593Smuzhiyun 	{0x4501, 0x00},
461*4882a593Smuzhiyun 	{0x4008, 0x02},
462*4882a593Smuzhiyun 	{0x4009, 0x09},
463*4882a593Smuzhiyun 	{REG_NULL, 0x00}
464*4882a593Smuzhiyun };
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun /*
467*4882a593Smuzhiyun  * Xclk 24Mhz
468*4882a593Smuzhiyun  * Pclk 45Mhz
469*4882a593Smuzhiyun  * linelength 672(0x2a0)
470*4882a593Smuzhiyun  * framelength 558(0x22e)
471*4882a593Smuzhiyun  * grabwindow_width 640
472*4882a593Smuzhiyun  * grabwindow_height 480
473*4882a593Smuzhiyun  * max_framerate 120fps
474*4882a593Smuzhiyun  * mipi_datarate per lane 840Mbps
475*4882a593Smuzhiyun  */
476*4882a593Smuzhiyun static const struct regval ov5695_640x480_regs[] = {
477*4882a593Smuzhiyun 	{0x3501, 0x22},
478*4882a593Smuzhiyun 	{0x366e, 0x0c},
479*4882a593Smuzhiyun 	{0x3800, 0x00},
480*4882a593Smuzhiyun 	{0x3801, 0x00},
481*4882a593Smuzhiyun 	{0x3802, 0x00},
482*4882a593Smuzhiyun 	{0x3803, 0x08},
483*4882a593Smuzhiyun 	{0x3804, 0x0a},
484*4882a593Smuzhiyun 	{0x3805, 0x3f},
485*4882a593Smuzhiyun 	{0x3806, 0x07},
486*4882a593Smuzhiyun 	{0x3807, 0xa7},
487*4882a593Smuzhiyun 	{0x3808, 0x02},
488*4882a593Smuzhiyun 	{0x3809, 0x80},
489*4882a593Smuzhiyun 	{0x380a, 0x01},
490*4882a593Smuzhiyun 	{0x380b, 0xe0},
491*4882a593Smuzhiyun 	{0x380c, 0x02},
492*4882a593Smuzhiyun 	{0x380d, 0xa0},
493*4882a593Smuzhiyun 	{0x380e, 0x02},
494*4882a593Smuzhiyun 	{0x380f, 0x2e},
495*4882a593Smuzhiyun 	{0x3811, 0x06},
496*4882a593Smuzhiyun 	{0x3813, 0x04},
497*4882a593Smuzhiyun 	{0x3814, 0x07},
498*4882a593Smuzhiyun 	{0x3816, 0x05},
499*4882a593Smuzhiyun 	{0x3817, 0x03},
500*4882a593Smuzhiyun 	{0x3820, 0x8d},
501*4882a593Smuzhiyun 	{0x3821, 0x01},
502*4882a593Smuzhiyun 	{0x4501, 0x00},
503*4882a593Smuzhiyun 	{0x4008, 0x02},
504*4882a593Smuzhiyun 	{0x4009, 0x09},
505*4882a593Smuzhiyun 	{REG_NULL, 0x00}
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun static const struct ov5695_mode supported_modes[] = {
509*4882a593Smuzhiyun 	{
510*4882a593Smuzhiyun 		.width = 2592,
511*4882a593Smuzhiyun 		.height = 1944,
512*4882a593Smuzhiyun 		.max_fps = {
513*4882a593Smuzhiyun 			.numerator = 10000,
514*4882a593Smuzhiyun 			.denominator = 300000,
515*4882a593Smuzhiyun 		},
516*4882a593Smuzhiyun 		.exp_def = 0x0450,
517*4882a593Smuzhiyun 		.hts_def = 0x02e4 * 4,
518*4882a593Smuzhiyun 		.vts_def = 0x07e8,
519*4882a593Smuzhiyun 		.reg_list = ov5695_2592x1944_regs,
520*4882a593Smuzhiyun 	},
521*4882a593Smuzhiyun 	{
522*4882a593Smuzhiyun 		.width = 1920,
523*4882a593Smuzhiyun 		.height = 1080,
524*4882a593Smuzhiyun 		.max_fps = {
525*4882a593Smuzhiyun 			.numerator = 10000,
526*4882a593Smuzhiyun 			.denominator = 300000,
527*4882a593Smuzhiyun 		},
528*4882a593Smuzhiyun 		.exp_def = 0x0450,
529*4882a593Smuzhiyun 		.hts_def = 0x02a0 * 4,
530*4882a593Smuzhiyun 		.vts_def = 0x08b8,
531*4882a593Smuzhiyun 		.reg_list = ov5695_1920x1080_regs,
532*4882a593Smuzhiyun 	},
533*4882a593Smuzhiyun 	{
534*4882a593Smuzhiyun 		.width = 1296,
535*4882a593Smuzhiyun 		.height = 972,
536*4882a593Smuzhiyun 		.max_fps = {
537*4882a593Smuzhiyun 			.numerator = 10000,
538*4882a593Smuzhiyun 			.denominator = 600000,
539*4882a593Smuzhiyun 		},
540*4882a593Smuzhiyun 		.exp_def = 0x03e0,
541*4882a593Smuzhiyun 		.hts_def = 0x02e4 * 4,
542*4882a593Smuzhiyun 		.vts_def = 0x03f4,
543*4882a593Smuzhiyun 		.reg_list = ov5695_1296x972_regs,
544*4882a593Smuzhiyun 	},
545*4882a593Smuzhiyun 	{
546*4882a593Smuzhiyun 		.width = 1280,
547*4882a593Smuzhiyun 		.height = 720,
548*4882a593Smuzhiyun 		.max_fps = {
549*4882a593Smuzhiyun 			.numerator = 10000,
550*4882a593Smuzhiyun 			.denominator = 300000,
551*4882a593Smuzhiyun 		},
552*4882a593Smuzhiyun 		.exp_def = 0x0450,
553*4882a593Smuzhiyun 		.hts_def = 0x02a0 * 4,
554*4882a593Smuzhiyun 		.vts_def = 0x08b8,
555*4882a593Smuzhiyun 		.reg_list = ov5695_1280x720_regs,
556*4882a593Smuzhiyun 	},
557*4882a593Smuzhiyun 	{
558*4882a593Smuzhiyun 		.width = 640,
559*4882a593Smuzhiyun 		.height = 480,
560*4882a593Smuzhiyun 		.max_fps = {
561*4882a593Smuzhiyun 			.numerator = 10000,
562*4882a593Smuzhiyun 			.denominator = 1200000,
563*4882a593Smuzhiyun 		},
564*4882a593Smuzhiyun 		.exp_def = 0x0200,
565*4882a593Smuzhiyun 		.hts_def = 0x02a0 * 4,
566*4882a593Smuzhiyun 		.vts_def = 0x022e,
567*4882a593Smuzhiyun 		.reg_list = ov5695_640x480_regs,
568*4882a593Smuzhiyun 	},
569*4882a593Smuzhiyun };
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun #define OV5695_LINK_FREQ_420MHZ		420000000
572*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
573*4882a593Smuzhiyun 	OV5695_LINK_FREQ_420MHZ
574*4882a593Smuzhiyun };
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun static const char * const ov5695_test_pattern_menu[] = {
577*4882a593Smuzhiyun 	"Disabled",
578*4882a593Smuzhiyun 	"Vertical Color Bar Type 1",
579*4882a593Smuzhiyun 	"Vertical Color Bar Type 2",
580*4882a593Smuzhiyun 	"Vertical Color Bar Type 3",
581*4882a593Smuzhiyun 	"Vertical Color Bar Type 4"
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun /* Write registers up to 4 at a time */
ov5695_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)585*4882a593Smuzhiyun static int ov5695_write_reg(struct i2c_client *client, u16 reg,
586*4882a593Smuzhiyun 			    u32 len, u32 val)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun 	u32 buf_i, val_i;
589*4882a593Smuzhiyun 	u8 buf[6];
590*4882a593Smuzhiyun 	u8 *val_p;
591*4882a593Smuzhiyun 	__be32 val_be;
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	if (len > 4)
594*4882a593Smuzhiyun 		return -EINVAL;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	buf[0] = reg >> 8;
597*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	val_be = cpu_to_be32(val);
600*4882a593Smuzhiyun 	val_p = (u8 *)&val_be;
601*4882a593Smuzhiyun 	buf_i = 2;
602*4882a593Smuzhiyun 	val_i = 4 - len;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	while (val_i < 4)
605*4882a593Smuzhiyun 		buf[buf_i++] = val_p[val_i++];
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2)
608*4882a593Smuzhiyun 		return -EIO;
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	return 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun 
ov5695_write_array(struct i2c_client * client,const struct regval * regs)613*4882a593Smuzhiyun static int ov5695_write_array(struct i2c_client *client,
614*4882a593Smuzhiyun 			      const struct regval *regs)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun 	u8 *data;
617*4882a593Smuzhiyun 	u32 i, j = 0, k = 0;
618*4882a593Smuzhiyun 	int ret = 0;
619*4882a593Smuzhiyun 	struct i2c_msg *msg;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	msg = kmalloc((sizeof(struct i2c_msg) * I2C_MSG_MAX),
622*4882a593Smuzhiyun 		GFP_KERNEL);
623*4882a593Smuzhiyun 	if (!msg)
624*4882a593Smuzhiyun 		return -ENOMEM;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	data = kmalloc((sizeof(unsigned char) * I2C_DATA_MAX),
627*4882a593Smuzhiyun 		GFP_KERNEL);
628*4882a593Smuzhiyun 	if (!data) {
629*4882a593Smuzhiyun 		kfree(msg);
630*4882a593Smuzhiyun 		return -ENOMEM;
631*4882a593Smuzhiyun 	}
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	for (i = 0; regs[i].addr != REG_NULL; i++) {
634*4882a593Smuzhiyun 		(msg + j)->addr = client->addr;
635*4882a593Smuzhiyun 		(msg + j)->flags = I2C_M_WR;
636*4882a593Smuzhiyun 		(msg + j)->buf = (data + k);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 		data[k + 0] = (u8)(regs[i].addr >> 8);
639*4882a593Smuzhiyun 		data[k + 1] = (u8)(regs[i].addr & 0xFF);
640*4882a593Smuzhiyun 		data[k + 2] = (u8)(regs[i].val & 0xFF);
641*4882a593Smuzhiyun 		k = k + 3;
642*4882a593Smuzhiyun 		(msg + j)->len = 3;
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 		if (j++ == (I2C_MSG_MAX - 1)) {
645*4882a593Smuzhiyun 			ret = i2c_transfer(client->adapter, msg, j);
646*4882a593Smuzhiyun 			if (ret < 0) {
647*4882a593Smuzhiyun 				kfree(msg);
648*4882a593Smuzhiyun 				kfree(data);
649*4882a593Smuzhiyun 				return ret;
650*4882a593Smuzhiyun 			}
651*4882a593Smuzhiyun 			j = 0;
652*4882a593Smuzhiyun 			k = 0;
653*4882a593Smuzhiyun 		}
654*4882a593Smuzhiyun 	}
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	if (j != 0) {
657*4882a593Smuzhiyun 		ret = i2c_transfer(client->adapter, msg, j);
658*4882a593Smuzhiyun 		if (ret < 0) {
659*4882a593Smuzhiyun 			kfree(msg);
660*4882a593Smuzhiyun 			kfree(data);
661*4882a593Smuzhiyun 			return ret;
662*4882a593Smuzhiyun 		}
663*4882a593Smuzhiyun 	}
664*4882a593Smuzhiyun 	kfree(msg);
665*4882a593Smuzhiyun 	kfree(data);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	return 0;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun /* Read registers up to 4 at a time */
ov5695_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)671*4882a593Smuzhiyun static int ov5695_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
672*4882a593Smuzhiyun 			   u32 *val)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
675*4882a593Smuzhiyun 	u8 *data_be_p;
676*4882a593Smuzhiyun 	__be32 data_be = 0;
677*4882a593Smuzhiyun 	__be16 reg_addr_be = cpu_to_be16(reg);
678*4882a593Smuzhiyun 	int ret;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	if (len > 4 || !len)
681*4882a593Smuzhiyun 		return -EINVAL;
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	data_be_p = (u8 *)&data_be;
684*4882a593Smuzhiyun 	/* Write register address */
685*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
686*4882a593Smuzhiyun 	msgs[0].flags = 0;
687*4882a593Smuzhiyun 	msgs[0].len = 2;
688*4882a593Smuzhiyun 	msgs[0].buf = (u8 *)&reg_addr_be;
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	/* Read data from register */
691*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
692*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
693*4882a593Smuzhiyun 	msgs[1].len = len;
694*4882a593Smuzhiyun 	msgs[1].buf = &data_be_p[4 - len];
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
697*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
698*4882a593Smuzhiyun 		return -EIO;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	*val = be32_to_cpu(data_be);
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	return 0;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun 
ov5695_get_reso_dist(const struct ov5695_mode * mode,struct v4l2_mbus_framefmt * framefmt)705*4882a593Smuzhiyun static int ov5695_get_reso_dist(const struct ov5695_mode *mode,
706*4882a593Smuzhiyun 				struct v4l2_mbus_framefmt *framefmt)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun 	return abs(mode->width - framefmt->width) +
709*4882a593Smuzhiyun 	       abs(mode->height - framefmt->height);
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun static const struct ov5695_mode *
ov5695_find_best_fit(struct v4l2_subdev_format * fmt)713*4882a593Smuzhiyun ov5695_find_best_fit(struct v4l2_subdev_format *fmt)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
716*4882a593Smuzhiyun 	int dist;
717*4882a593Smuzhiyun 	int cur_best_fit = 0;
718*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
719*4882a593Smuzhiyun 	int i;
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
722*4882a593Smuzhiyun 		dist = ov5695_get_reso_dist(&supported_modes[i], framefmt);
723*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
724*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
725*4882a593Smuzhiyun 			cur_best_fit = i;
726*4882a593Smuzhiyun 		}
727*4882a593Smuzhiyun 	}
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	return &supported_modes[cur_best_fit];
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun 
ov5695_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)732*4882a593Smuzhiyun static int ov5695_set_fmt(struct v4l2_subdev *sd,
733*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
734*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
737*4882a593Smuzhiyun 	const struct ov5695_mode *mode;
738*4882a593Smuzhiyun 	s64 h_blank, vblank_def;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	mode = ov5695_find_best_fit(fmt);
743*4882a593Smuzhiyun 	fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
744*4882a593Smuzhiyun 	fmt->format.width = mode->width;
745*4882a593Smuzhiyun 	fmt->format.height = mode->height;
746*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
747*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
748*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
749*4882a593Smuzhiyun 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
750*4882a593Smuzhiyun #else
751*4882a593Smuzhiyun 		mutex_unlock(&ov5695->mutex);
752*4882a593Smuzhiyun 		return -ENOTTY;
753*4882a593Smuzhiyun #endif
754*4882a593Smuzhiyun 	} else {
755*4882a593Smuzhiyun 		ov5695->cur_mode = mode;
756*4882a593Smuzhiyun 		h_blank = mode->hts_def - mode->width;
757*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5695->hblank, h_blank,
758*4882a593Smuzhiyun 					 h_blank, 1, h_blank);
759*4882a593Smuzhiyun 		vblank_def = mode->vts_def - mode->height;
760*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5695->vblank, vblank_def,
761*4882a593Smuzhiyun 					 OV5695_VTS_MAX - mode->height,
762*4882a593Smuzhiyun 					 1, vblank_def);
763*4882a593Smuzhiyun 	}
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	return 0;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun 
ov5695_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)770*4882a593Smuzhiyun static int ov5695_get_fmt(struct v4l2_subdev *sd,
771*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
772*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
775*4882a593Smuzhiyun 	const struct ov5695_mode *mode = ov5695->cur_mode;
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
778*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
779*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
780*4882a593Smuzhiyun 		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
781*4882a593Smuzhiyun #else
782*4882a593Smuzhiyun 		mutex_unlock(&ov5695->mutex);
783*4882a593Smuzhiyun 		return -ENOTTY;
784*4882a593Smuzhiyun #endif
785*4882a593Smuzhiyun 	} else {
786*4882a593Smuzhiyun 		fmt->format.width = mode->width;
787*4882a593Smuzhiyun 		fmt->format.height = mode->height;
788*4882a593Smuzhiyun 		fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
789*4882a593Smuzhiyun 		fmt->format.field = V4L2_FIELD_NONE;
790*4882a593Smuzhiyun 	}
791*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	return 0;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun 
ov5695_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)796*4882a593Smuzhiyun static int ov5695_enum_mbus_code(struct v4l2_subdev *sd,
797*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
798*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
799*4882a593Smuzhiyun {
800*4882a593Smuzhiyun 	if (code->index != 0)
801*4882a593Smuzhiyun 		return -EINVAL;
802*4882a593Smuzhiyun 	code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	return 0;
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun 
ov5695_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)807*4882a593Smuzhiyun static int ov5695_enum_frame_sizes(struct v4l2_subdev *sd,
808*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
809*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
810*4882a593Smuzhiyun {
811*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
812*4882a593Smuzhiyun 		return -EINVAL;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
815*4882a593Smuzhiyun 		return -EINVAL;
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	fse->min_width  = supported_modes[fse->index].width;
818*4882a593Smuzhiyun 	fse->max_width  = supported_modes[fse->index].width;
819*4882a593Smuzhiyun 	fse->max_height = supported_modes[fse->index].height;
820*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	return 0;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun 
ov5695_enable_test_pattern(struct ov5695 * ov5695,u32 pattern)825*4882a593Smuzhiyun static int ov5695_enable_test_pattern(struct ov5695 *ov5695, u32 pattern)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun 	u32 val;
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	if (pattern)
830*4882a593Smuzhiyun 		val = (pattern - 1) | OV5695_TEST_PATTERN_ENABLE;
831*4882a593Smuzhiyun 	else
832*4882a593Smuzhiyun 		val = OV5695_TEST_PATTERN_DISABLE;
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 	return ov5695_write_reg(ov5695->client, OV5695_REG_TEST_PATTERN,
835*4882a593Smuzhiyun 				OV5695_REG_VALUE_08BIT, val);
836*4882a593Smuzhiyun }
837*4882a593Smuzhiyun 
ov5695_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)838*4882a593Smuzhiyun static int ov5695_g_frame_interval(struct v4l2_subdev *sd,
839*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
842*4882a593Smuzhiyun 	const struct ov5695_mode *mode = ov5695->cur_mode;
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	return 0;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun 
ov5695_get_module_inf(struct ov5695 * ov5695,struct rkmodule_inf * inf)849*4882a593Smuzhiyun static void ov5695_get_module_inf(struct ov5695 *ov5695,
850*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
853*4882a593Smuzhiyun 	strscpy(inf->base.sensor, OV5695_NAME, sizeof(inf->base.sensor));
854*4882a593Smuzhiyun 	strscpy(inf->base.module, ov5695->module_name,
855*4882a593Smuzhiyun 		sizeof(inf->base.module));
856*4882a593Smuzhiyun 	strscpy(inf->base.lens, ov5695->len_name, sizeof(inf->base.lens));
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun 
ov5695_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)859*4882a593Smuzhiyun static long ov5695_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
862*4882a593Smuzhiyun 	long ret = 0;
863*4882a593Smuzhiyun 	u32 stream = 0;
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	switch (cmd) {
866*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
867*4882a593Smuzhiyun 		ov5695_get_module_inf(ov5695, (struct rkmodule_inf *)arg);
868*4882a593Smuzhiyun 		break;
869*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 		stream = *((u32 *)arg);
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 		if (stream)
874*4882a593Smuzhiyun 			ret = ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
875*4882a593Smuzhiyun 				OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
876*4882a593Smuzhiyun 		else
877*4882a593Smuzhiyun 			ret = ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
878*4882a593Smuzhiyun 				OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
879*4882a593Smuzhiyun 		break;
880*4882a593Smuzhiyun 	default:
881*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
882*4882a593Smuzhiyun 		break;
883*4882a593Smuzhiyun 	}
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun 	return ret;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
ov5695_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)889*4882a593Smuzhiyun static long ov5695_compat_ioctl32(struct v4l2_subdev *sd,
890*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
891*4882a593Smuzhiyun {
892*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
893*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
894*4882a593Smuzhiyun 	struct rkmodule_awb_cfg *cfg;
895*4882a593Smuzhiyun 	long ret;
896*4882a593Smuzhiyun 	u32 stream = 0;
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 	switch (cmd) {
899*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
900*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
901*4882a593Smuzhiyun 		if (!inf) {
902*4882a593Smuzhiyun 			ret = -ENOMEM;
903*4882a593Smuzhiyun 			return ret;
904*4882a593Smuzhiyun 		}
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 		ret = ov5695_ioctl(sd, cmd, inf);
907*4882a593Smuzhiyun 		if (!ret) {
908*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
909*4882a593Smuzhiyun 			if (ret)
910*4882a593Smuzhiyun 				ret = -EFAULT;
911*4882a593Smuzhiyun 		}
912*4882a593Smuzhiyun 		kfree(inf);
913*4882a593Smuzhiyun 		break;
914*4882a593Smuzhiyun 	case RKMODULE_AWB_CFG:
915*4882a593Smuzhiyun 		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
916*4882a593Smuzhiyun 		if (!cfg) {
917*4882a593Smuzhiyun 			ret = -ENOMEM;
918*4882a593Smuzhiyun 			return ret;
919*4882a593Smuzhiyun 		}
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 		ret = copy_from_user(cfg, up, sizeof(*cfg));
922*4882a593Smuzhiyun 		if (!ret)
923*4882a593Smuzhiyun 			ret = ov5695_ioctl(sd, cmd, cfg);
924*4882a593Smuzhiyun 		else
925*4882a593Smuzhiyun 			ret = -EFAULT;
926*4882a593Smuzhiyun 		kfree(cfg);
927*4882a593Smuzhiyun 		break;
928*4882a593Smuzhiyun 	case RKMODULE_SET_QUICK_STREAM:
929*4882a593Smuzhiyun 		ret = copy_from_user(&stream, up, sizeof(u32));
930*4882a593Smuzhiyun 		if (!ret)
931*4882a593Smuzhiyun 			ret = ov5695_ioctl(sd, cmd, &stream);
932*4882a593Smuzhiyun 		else
933*4882a593Smuzhiyun 			ret = -EFAULT;
934*4882a593Smuzhiyun 		break;
935*4882a593Smuzhiyun 	default:
936*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
937*4882a593Smuzhiyun 		break;
938*4882a593Smuzhiyun 	}
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	return ret;
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun #endif
943*4882a593Smuzhiyun 
__ov5695_start_stream(struct ov5695 * ov5695)944*4882a593Smuzhiyun static int __ov5695_start_stream(struct ov5695 *ov5695)
945*4882a593Smuzhiyun {
946*4882a593Smuzhiyun 	int ret;
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	ret = ov5695_write_array(ov5695->client, ov5695->cur_mode->reg_list);
949*4882a593Smuzhiyun 	if (ret)
950*4882a593Smuzhiyun 		return ret;
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	/* In case these controls are set before streaming */
953*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
954*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&ov5695->ctrl_handler);
955*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
956*4882a593Smuzhiyun 	if (ret)
957*4882a593Smuzhiyun 		return ret;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
960*4882a593Smuzhiyun 				OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun 
__ov5695_stop_stream(struct ov5695 * ov5695)963*4882a593Smuzhiyun static int __ov5695_stop_stream(struct ov5695 *ov5695)
964*4882a593Smuzhiyun {
965*4882a593Smuzhiyun 	return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
966*4882a593Smuzhiyun 				OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun 
ov5695_s_stream(struct v4l2_subdev * sd,int on)969*4882a593Smuzhiyun static int ov5695_s_stream(struct v4l2_subdev *sd, int on)
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
972*4882a593Smuzhiyun 	struct i2c_client *client = ov5695->client;
973*4882a593Smuzhiyun 	int ret = 0;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
976*4882a593Smuzhiyun 	on = !!on;
977*4882a593Smuzhiyun 	if (on == ov5695->streaming)
978*4882a593Smuzhiyun 		goto unlock_and_return;
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	if (on) {
981*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
982*4882a593Smuzhiyun 		if (ret < 0) {
983*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
984*4882a593Smuzhiyun 			goto unlock_and_return;
985*4882a593Smuzhiyun 		}
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 		ret = __ov5695_start_stream(ov5695);
988*4882a593Smuzhiyun 		if (ret) {
989*4882a593Smuzhiyun 			v4l2_err(sd, "start stream failed while write regs\n");
990*4882a593Smuzhiyun 			pm_runtime_put(&client->dev);
991*4882a593Smuzhiyun 			goto unlock_and_return;
992*4882a593Smuzhiyun 		}
993*4882a593Smuzhiyun 	} else {
994*4882a593Smuzhiyun 		__ov5695_stop_stream(ov5695);
995*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
996*4882a593Smuzhiyun 	}
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	ov5695->streaming = on;
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun unlock_and_return:
1001*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	return ret;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun 
ov5695_s_power(struct v4l2_subdev * sd,int on)1006*4882a593Smuzhiyun static int ov5695_s_power(struct v4l2_subdev *sd, int on)
1007*4882a593Smuzhiyun {
1008*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
1009*4882a593Smuzhiyun 	struct i2c_client *client = ov5695->client;
1010*4882a593Smuzhiyun 	int ret = 0;
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	/* If the power state is not modified - no work to do. */
1015*4882a593Smuzhiyun 	if (ov5695->power_on == !!on)
1016*4882a593Smuzhiyun 		goto unlock_and_return;
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	if (on) {
1019*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
1020*4882a593Smuzhiyun 		if (ret < 0) {
1021*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
1022*4882a593Smuzhiyun 			goto unlock_and_return;
1023*4882a593Smuzhiyun 		}
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun 		ret = ov5695_write_array(ov5695->client, ov5695_global_regs);
1026*4882a593Smuzhiyun 		if (ret) {
1027*4882a593Smuzhiyun 			v4l2_err(sd, "could not set init registers\n");
1028*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
1029*4882a593Smuzhiyun 			goto unlock_and_return;
1030*4882a593Smuzhiyun 		}
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 		ov5695->power_on = true;
1033*4882a593Smuzhiyun 	} else {
1034*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
1035*4882a593Smuzhiyun 		ov5695->power_on = false;
1036*4882a593Smuzhiyun 	}
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun unlock_and_return:
1039*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	return ret;
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
ov5695_cal_delay(u32 cycles)1045*4882a593Smuzhiyun static inline u32 ov5695_cal_delay(u32 cycles)
1046*4882a593Smuzhiyun {
1047*4882a593Smuzhiyun 	return DIV_ROUND_UP(cycles, OV5695_XVCLK_FREQ / 1000 / 1000);
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun 
__ov5695_power_on(struct ov5695 * ov5695)1050*4882a593Smuzhiyun static int __ov5695_power_on(struct ov5695 *ov5695)
1051*4882a593Smuzhiyun {
1052*4882a593Smuzhiyun 	int ret;
1053*4882a593Smuzhiyun 	u32 delay_us;
1054*4882a593Smuzhiyun 	struct device *dev = &ov5695->client->dev;
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun 	ret = clk_set_rate(ov5695->xvclk, OV5695_XVCLK_FREQ);
1057*4882a593Smuzhiyun 	if (ret < 0) {
1058*4882a593Smuzhiyun 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1059*4882a593Smuzhiyun 		return ret;
1060*4882a593Smuzhiyun 	}
1061*4882a593Smuzhiyun 	if (clk_get_rate(ov5695->xvclk) != OV5695_XVCLK_FREQ)
1062*4882a593Smuzhiyun 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1063*4882a593Smuzhiyun 	ret = clk_prepare_enable(ov5695->xvclk);
1064*4882a593Smuzhiyun 	if (ret < 0) {
1065*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable xvclk\n");
1066*4882a593Smuzhiyun 		return ret;
1067*4882a593Smuzhiyun 	}
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	if (!IS_ERR(ov5695->reset_gpio))
1070*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	ret = regulator_bulk_enable(OV5695_NUM_SUPPLIES, ov5695->supplies);
1073*4882a593Smuzhiyun 	if (ret < 0) {
1074*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable regulators\n");
1075*4882a593Smuzhiyun 		goto disable_clk;
1076*4882a593Smuzhiyun 	}
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	if (!IS_ERR(ov5695->reset_gpio))
1079*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ov5695->reset_gpio, 0);
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	if (!IS_ERR(ov5695->pwdn_gpio))
1082*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ov5695->pwdn_gpio, 1);
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	/* 8192 cycles prior to first SCCB transaction */
1085*4882a593Smuzhiyun 	delay_us = ov5695_cal_delay(8192);
1086*4882a593Smuzhiyun 	usleep_range(delay_us, delay_us * 2);
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	return 0;
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun disable_clk:
1091*4882a593Smuzhiyun 	clk_disable_unprepare(ov5695->xvclk);
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 	return ret;
1094*4882a593Smuzhiyun }
1095*4882a593Smuzhiyun 
__ov5695_power_off(struct ov5695 * ov5695)1096*4882a593Smuzhiyun static void __ov5695_power_off(struct ov5695 *ov5695)
1097*4882a593Smuzhiyun {
1098*4882a593Smuzhiyun 	if (!IS_ERR(ov5695->pwdn_gpio))
1099*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ov5695->pwdn_gpio, 0);
1100*4882a593Smuzhiyun 	clk_disable_unprepare(ov5695->xvclk);
1101*4882a593Smuzhiyun 	if (!IS_ERR(ov5695->reset_gpio))
1102*4882a593Smuzhiyun 		gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
1103*4882a593Smuzhiyun 	regulator_bulk_disable(OV5695_NUM_SUPPLIES, ov5695->supplies);
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun 
ov5695_runtime_resume(struct device * dev)1106*4882a593Smuzhiyun static int __maybe_unused ov5695_runtime_resume(struct device *dev)
1107*4882a593Smuzhiyun {
1108*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1109*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1110*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	return __ov5695_power_on(ov5695);
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun 
ov5695_runtime_suspend(struct device * dev)1115*4882a593Smuzhiyun static int __maybe_unused ov5695_runtime_suspend(struct device *dev)
1116*4882a593Smuzhiyun {
1117*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1118*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1119*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	__ov5695_power_off(ov5695);
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 	return 0;
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov5695_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1127*4882a593Smuzhiyun static int ov5695_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1128*4882a593Smuzhiyun {
1129*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
1130*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1131*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1132*4882a593Smuzhiyun 	const struct ov5695_mode *def_mode = &supported_modes[0];
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	mutex_lock(&ov5695->mutex);
1135*4882a593Smuzhiyun 	/* Initialize try_fmt */
1136*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1137*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1138*4882a593Smuzhiyun 	try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1139*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	mutex_unlock(&ov5695->mutex);
1142*4882a593Smuzhiyun 	/* No crop or compose */
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	return 0;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun #endif
1147*4882a593Smuzhiyun 
ov5695_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1148*4882a593Smuzhiyun static int ov5695_enum_frame_interval(struct v4l2_subdev *sd,
1149*4882a593Smuzhiyun 				      struct v4l2_subdev_pad_config *cfg,
1150*4882a593Smuzhiyun 				      struct v4l2_subdev_frame_interval_enum *fie)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun 	if (fie->index >= ARRAY_SIZE(supported_modes))
1153*4882a593Smuzhiyun 		return -EINVAL;
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1156*4882a593Smuzhiyun 	fie->width = supported_modes[fie->index].width;
1157*4882a593Smuzhiyun 	fie->height = supported_modes[fie->index].height;
1158*4882a593Smuzhiyun 	fie->interval = supported_modes[fie->index].max_fps;
1159*4882a593Smuzhiyun 	return 0;
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun 
ov5695_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1162*4882a593Smuzhiyun static int ov5695_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1163*4882a593Smuzhiyun 				struct v4l2_mbus_config *config)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun 	u32 val = 0;
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun 	val = 1 << (OV5695_LANES - 1) |
1168*4882a593Smuzhiyun 	      V4L2_MBUS_CSI2_CHANNEL_0 |
1169*4882a593Smuzhiyun 	      V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1170*4882a593Smuzhiyun 	config->type = V4L2_MBUS_CSI2_DPHY;
1171*4882a593Smuzhiyun 	config->flags = val;
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 	return 0;
1174*4882a593Smuzhiyun }
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun static const struct dev_pm_ops ov5695_pm_ops = {
1177*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(ov5695_runtime_suspend,
1178*4882a593Smuzhiyun 			   ov5695_runtime_resume, NULL)
1179*4882a593Smuzhiyun };
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1182*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops ov5695_internal_ops = {
1183*4882a593Smuzhiyun 	.open = ov5695_open,
1184*4882a593Smuzhiyun };
1185*4882a593Smuzhiyun #endif
1186*4882a593Smuzhiyun 
1187*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops ov5695_core_ops = {
1188*4882a593Smuzhiyun 	.s_power = ov5695_s_power,
1189*4882a593Smuzhiyun 	.ioctl = ov5695_ioctl,
1190*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1191*4882a593Smuzhiyun 	.compat_ioctl32 = ov5695_compat_ioctl32,
1192*4882a593Smuzhiyun #endif
1193*4882a593Smuzhiyun };
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov5695_video_ops = {
1196*4882a593Smuzhiyun 	.s_stream = ov5695_s_stream,
1197*4882a593Smuzhiyun 	.g_frame_interval = ov5695_g_frame_interval,
1198*4882a593Smuzhiyun };
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov5695_pad_ops = {
1201*4882a593Smuzhiyun 	.enum_mbus_code = ov5695_enum_mbus_code,
1202*4882a593Smuzhiyun 	.enum_frame_size = ov5695_enum_frame_sizes,
1203*4882a593Smuzhiyun 	.enum_frame_interval = ov5695_enum_frame_interval,
1204*4882a593Smuzhiyun 	.get_fmt = ov5695_get_fmt,
1205*4882a593Smuzhiyun 	.set_fmt = ov5695_set_fmt,
1206*4882a593Smuzhiyun 	.get_mbus_config = ov5695_g_mbus_config,
1207*4882a593Smuzhiyun };
1208*4882a593Smuzhiyun 
1209*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov5695_subdev_ops = {
1210*4882a593Smuzhiyun 	.core	= &ov5695_core_ops,
1211*4882a593Smuzhiyun 	.video	= &ov5695_video_ops,
1212*4882a593Smuzhiyun 	.pad	= &ov5695_pad_ops,
1213*4882a593Smuzhiyun };
1214*4882a593Smuzhiyun 
ov5695_set_ctrl(struct v4l2_ctrl * ctrl)1215*4882a593Smuzhiyun static int ov5695_set_ctrl(struct v4l2_ctrl *ctrl)
1216*4882a593Smuzhiyun {
1217*4882a593Smuzhiyun 	struct ov5695 *ov5695 = container_of(ctrl->handler,
1218*4882a593Smuzhiyun 					     struct ov5695, ctrl_handler);
1219*4882a593Smuzhiyun 	struct i2c_client *client = ov5695->client;
1220*4882a593Smuzhiyun 	s64 max;
1221*4882a593Smuzhiyun 	int ret = 0;
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun 	/* Propagate change of current control to all related controls */
1224*4882a593Smuzhiyun 	switch (ctrl->id) {
1225*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1226*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
1227*4882a593Smuzhiyun 		max = ov5695->cur_mode->height + ctrl->val - 4;
1228*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5695->exposure,
1229*4882a593Smuzhiyun 					 ov5695->exposure->minimum, max,
1230*4882a593Smuzhiyun 					 ov5695->exposure->step,
1231*4882a593Smuzhiyun 					 ov5695->exposure->default_value);
1232*4882a593Smuzhiyun 		break;
1233*4882a593Smuzhiyun 	}
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
1236*4882a593Smuzhiyun 		return 0;
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun 	switch (ctrl->id) {
1239*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
1240*4882a593Smuzhiyun 		/* 4 least significant bits of expsoure are fractional part */
1241*4882a593Smuzhiyun 		ret = ov5695_write_reg(ov5695->client, OV5695_REG_EXPOSURE,
1242*4882a593Smuzhiyun 				       OV5695_REG_VALUE_24BIT, ctrl->val << 4);
1243*4882a593Smuzhiyun 		break;
1244*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
1245*4882a593Smuzhiyun 		ret = ov5695_write_reg(ov5695->client, OV5695_REG_ANALOG_GAIN,
1246*4882a593Smuzhiyun 				       OV5695_REG_VALUE_08BIT, ctrl->val);
1247*4882a593Smuzhiyun 		break;
1248*4882a593Smuzhiyun 	case V4L2_CID_DIGITAL_GAIN:
1249*4882a593Smuzhiyun 		ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_L,
1250*4882a593Smuzhiyun 				       OV5695_REG_VALUE_08BIT,
1251*4882a593Smuzhiyun 				       ctrl->val & OV5695_DIGI_GAIN_L_MASK);
1252*4882a593Smuzhiyun 		ret |= ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_H,
1253*4882a593Smuzhiyun 				       OV5695_REG_VALUE_08BIT,
1254*4882a593Smuzhiyun 				       ctrl->val >> OV5695_DIGI_GAIN_H_SHIFT);
1255*4882a593Smuzhiyun 		break;
1256*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
1257*4882a593Smuzhiyun 		ret = ov5695_write_reg(ov5695->client, OV5695_REG_VTS,
1258*4882a593Smuzhiyun 				       OV5695_REG_VALUE_16BIT,
1259*4882a593Smuzhiyun 				       ctrl->val + ov5695->cur_mode->height);
1260*4882a593Smuzhiyun 		break;
1261*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
1262*4882a593Smuzhiyun 		ret = ov5695_enable_test_pattern(ov5695, ctrl->val);
1263*4882a593Smuzhiyun 		break;
1264*4882a593Smuzhiyun 	default:
1265*4882a593Smuzhiyun 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1266*4882a593Smuzhiyun 			 __func__, ctrl->id, ctrl->val);
1267*4882a593Smuzhiyun 		break;
1268*4882a593Smuzhiyun 	}
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
1271*4882a593Smuzhiyun 
1272*4882a593Smuzhiyun 	return ret;
1273*4882a593Smuzhiyun }
1274*4882a593Smuzhiyun 
1275*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov5695_ctrl_ops = {
1276*4882a593Smuzhiyun 	.s_ctrl = ov5695_set_ctrl,
1277*4882a593Smuzhiyun };
1278*4882a593Smuzhiyun 
ov5695_initialize_controls(struct ov5695 * ov5695)1279*4882a593Smuzhiyun static int ov5695_initialize_controls(struct ov5695 *ov5695)
1280*4882a593Smuzhiyun {
1281*4882a593Smuzhiyun 	const struct ov5695_mode *mode;
1282*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler;
1283*4882a593Smuzhiyun 	struct v4l2_ctrl *ctrl;
1284*4882a593Smuzhiyun 	s64 exposure_max, vblank_def;
1285*4882a593Smuzhiyun 	u32 h_blank;
1286*4882a593Smuzhiyun 	int ret;
1287*4882a593Smuzhiyun 
1288*4882a593Smuzhiyun 	handler = &ov5695->ctrl_handler;
1289*4882a593Smuzhiyun 	mode = ov5695->cur_mode;
1290*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(handler, 8);
1291*4882a593Smuzhiyun 	if (ret)
1292*4882a593Smuzhiyun 		return ret;
1293*4882a593Smuzhiyun 	handler->lock = &ov5695->mutex;
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1296*4882a593Smuzhiyun 				      0, 0, link_freq_menu_items);
1297*4882a593Smuzhiyun 	if (ctrl)
1298*4882a593Smuzhiyun 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1299*4882a593Smuzhiyun 
1300*4882a593Smuzhiyun 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1301*4882a593Smuzhiyun 			  0, OV5695_PIXEL_RATE, 1, OV5695_PIXEL_RATE);
1302*4882a593Smuzhiyun 
1303*4882a593Smuzhiyun 	h_blank = mode->hts_def - mode->width;
1304*4882a593Smuzhiyun 	ov5695->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1305*4882a593Smuzhiyun 				h_blank, h_blank, 1, h_blank);
1306*4882a593Smuzhiyun 	if (ov5695->hblank)
1307*4882a593Smuzhiyun 		ov5695->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	vblank_def = mode->vts_def - mode->height;
1310*4882a593Smuzhiyun 	ov5695->vblank = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1311*4882a593Smuzhiyun 				V4L2_CID_VBLANK, vblank_def,
1312*4882a593Smuzhiyun 				OV5695_VTS_MAX - mode->height,
1313*4882a593Smuzhiyun 				1, vblank_def);
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	exposure_max = mode->vts_def - 4;
1316*4882a593Smuzhiyun 	ov5695->exposure = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1317*4882a593Smuzhiyun 				V4L2_CID_EXPOSURE, OV5695_EXPOSURE_MIN,
1318*4882a593Smuzhiyun 				exposure_max, OV5695_EXPOSURE_STEP,
1319*4882a593Smuzhiyun 				mode->exp_def);
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	ov5695->anal_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1322*4882a593Smuzhiyun 				V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1323*4882a593Smuzhiyun 				ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1324*4882a593Smuzhiyun 				ANALOG_GAIN_DEFAULT);
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun 	/* Digital gain */
1327*4882a593Smuzhiyun 	ov5695->digi_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1328*4882a593Smuzhiyun 				V4L2_CID_DIGITAL_GAIN, OV5695_DIGI_GAIN_MIN,
1329*4882a593Smuzhiyun 				OV5695_DIGI_GAIN_MAX, OV5695_DIGI_GAIN_STEP,
1330*4882a593Smuzhiyun 				OV5695_DIGI_GAIN_DEFAULT);
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun 	ov5695->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1333*4882a593Smuzhiyun 				&ov5695_ctrl_ops, V4L2_CID_TEST_PATTERN,
1334*4882a593Smuzhiyun 				ARRAY_SIZE(ov5695_test_pattern_menu) - 1,
1335*4882a593Smuzhiyun 				0, 0, ov5695_test_pattern_menu);
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	if (handler->error) {
1338*4882a593Smuzhiyun 		ret = handler->error;
1339*4882a593Smuzhiyun 		dev_err(&ov5695->client->dev,
1340*4882a593Smuzhiyun 			"Failed to init controls(%d)\n", ret);
1341*4882a593Smuzhiyun 		goto err_free_handler;
1342*4882a593Smuzhiyun 	}
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	ov5695->subdev.ctrl_handler = handler;
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 	return 0;
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun err_free_handler:
1349*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(handler);
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 	return ret;
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun 
ov5695_check_sensor_id(struct ov5695 * ov5695,struct i2c_client * client)1354*4882a593Smuzhiyun static int ov5695_check_sensor_id(struct ov5695 *ov5695,
1355*4882a593Smuzhiyun 				  struct i2c_client *client)
1356*4882a593Smuzhiyun {
1357*4882a593Smuzhiyun 	struct device *dev = &ov5695->client->dev;
1358*4882a593Smuzhiyun 	u32 id = 0;
1359*4882a593Smuzhiyun 	int ret;
1360*4882a593Smuzhiyun 
1361*4882a593Smuzhiyun 	ret = ov5695_read_reg(client, OV5695_REG_CHIP_ID,
1362*4882a593Smuzhiyun 			      OV5695_REG_VALUE_24BIT, &id);
1363*4882a593Smuzhiyun 	if (id != CHIP_ID) {
1364*4882a593Smuzhiyun 		dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1365*4882a593Smuzhiyun 		return -ENODEV;
1366*4882a593Smuzhiyun 	}
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	return 0;
1371*4882a593Smuzhiyun }
1372*4882a593Smuzhiyun 
ov5695_configure_regulators(struct ov5695 * ov5695)1373*4882a593Smuzhiyun static int ov5695_configure_regulators(struct ov5695 *ov5695)
1374*4882a593Smuzhiyun {
1375*4882a593Smuzhiyun 	int i;
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	for (i = 0; i < OV5695_NUM_SUPPLIES; i++)
1378*4882a593Smuzhiyun 		ov5695->supplies[i].supply = ov5695_supply_names[i];
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&ov5695->client->dev,
1381*4882a593Smuzhiyun 				       OV5695_NUM_SUPPLIES,
1382*4882a593Smuzhiyun 				       ov5695->supplies);
1383*4882a593Smuzhiyun }
1384*4882a593Smuzhiyun 
ov5695_probe(struct i2c_client * client,const struct i2c_device_id * id)1385*4882a593Smuzhiyun static int ov5695_probe(struct i2c_client *client,
1386*4882a593Smuzhiyun 			const struct i2c_device_id *id)
1387*4882a593Smuzhiyun {
1388*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1389*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1390*4882a593Smuzhiyun 	struct ov5695 *ov5695;
1391*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1392*4882a593Smuzhiyun 	char facing[2];
1393*4882a593Smuzhiyun 	int ret;
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1396*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
1397*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
1398*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	ov5695 = devm_kzalloc(dev, sizeof(*ov5695), GFP_KERNEL);
1401*4882a593Smuzhiyun 	if (!ov5695)
1402*4882a593Smuzhiyun 		return -ENOMEM;
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1405*4882a593Smuzhiyun 				   &ov5695->module_index);
1406*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1407*4882a593Smuzhiyun 				       &ov5695->module_facing);
1408*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1409*4882a593Smuzhiyun 				       &ov5695->module_name);
1410*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1411*4882a593Smuzhiyun 				       &ov5695->len_name);
1412*4882a593Smuzhiyun 	if (ret) {
1413*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1414*4882a593Smuzhiyun 		return -EINVAL;
1415*4882a593Smuzhiyun 	}
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun 	ov5695->client = client;
1418*4882a593Smuzhiyun 	ov5695->cur_mode = &supported_modes[0];
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 	ov5695->xvclk = devm_clk_get(dev, "xvclk");
1421*4882a593Smuzhiyun 	if (IS_ERR(ov5695->xvclk)) {
1422*4882a593Smuzhiyun 		dev_err(dev, "Failed to get xvclk\n");
1423*4882a593Smuzhiyun 		return -EINVAL;
1424*4882a593Smuzhiyun 	}
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun 	ov5695->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1427*4882a593Smuzhiyun 	if (IS_ERR(ov5695->reset_gpio)) {
1428*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get reset-gpios\n");
1429*4882a593Smuzhiyun 	}
1430*4882a593Smuzhiyun 
1431*4882a593Smuzhiyun 	ov5695->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1432*4882a593Smuzhiyun 	if (IS_ERR(ov5695->pwdn_gpio))
1433*4882a593Smuzhiyun 		dev_warn(dev, "Failed to get pwdn-gpios\n");
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun 	ret = ov5695_configure_regulators(ov5695);
1436*4882a593Smuzhiyun 	if (ret) {
1437*4882a593Smuzhiyun 		dev_err(dev, "Failed to get power regulators\n");
1438*4882a593Smuzhiyun 		return ret;
1439*4882a593Smuzhiyun 	}
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	mutex_init(&ov5695->mutex);
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	sd = &ov5695->subdev;
1444*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &ov5695_subdev_ops);
1445*4882a593Smuzhiyun 	ret = ov5695_initialize_controls(ov5695);
1446*4882a593Smuzhiyun 	if (ret)
1447*4882a593Smuzhiyun 		goto err_destroy_mutex;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	ret = __ov5695_power_on(ov5695);
1450*4882a593Smuzhiyun 	if (ret)
1451*4882a593Smuzhiyun 		goto err_free_handler;
1452*4882a593Smuzhiyun 
1453*4882a593Smuzhiyun 	ret = ov5695_check_sensor_id(ov5695, client);
1454*4882a593Smuzhiyun 	if (ret)
1455*4882a593Smuzhiyun 		goto err_power_off;
1456*4882a593Smuzhiyun 
1457*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1458*4882a593Smuzhiyun 	sd->internal_ops = &ov5695_internal_ops;
1459*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1460*4882a593Smuzhiyun 		     V4L2_SUBDEV_FL_HAS_EVENTS;
1461*4882a593Smuzhiyun #endif
1462*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1463*4882a593Smuzhiyun 	ov5695->pad.flags = MEDIA_PAD_FL_SOURCE;
1464*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1465*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &ov5695->pad);
1466*4882a593Smuzhiyun 	if (ret < 0)
1467*4882a593Smuzhiyun 		goto err_power_off;
1468*4882a593Smuzhiyun #endif
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1471*4882a593Smuzhiyun 	if (strcmp(ov5695->module_facing, "back") == 0)
1472*4882a593Smuzhiyun 		facing[0] = 'b';
1473*4882a593Smuzhiyun 	else
1474*4882a593Smuzhiyun 		facing[0] = 'f';
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1477*4882a593Smuzhiyun 		 ov5695->module_index, facing,
1478*4882a593Smuzhiyun 		 OV5695_NAME, dev_name(sd->dev));
1479*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(sd);
1480*4882a593Smuzhiyun 	if (ret) {
1481*4882a593Smuzhiyun 		dev_err(dev, "v4l2 async register subdev failed\n");
1482*4882a593Smuzhiyun 		goto err_clean_entity;
1483*4882a593Smuzhiyun 	}
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
1486*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1487*4882a593Smuzhiyun 	pm_runtime_idle(dev);
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun 	return 0;
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun err_clean_entity:
1492*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1493*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1494*4882a593Smuzhiyun #endif
1495*4882a593Smuzhiyun err_power_off:
1496*4882a593Smuzhiyun 	__ov5695_power_off(ov5695);
1497*4882a593Smuzhiyun err_free_handler:
1498*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1499*4882a593Smuzhiyun err_destroy_mutex:
1500*4882a593Smuzhiyun 	mutex_destroy(&ov5695->mutex);
1501*4882a593Smuzhiyun 
1502*4882a593Smuzhiyun 	return ret;
1503*4882a593Smuzhiyun }
1504*4882a593Smuzhiyun 
ov5695_remove(struct i2c_client * client)1505*4882a593Smuzhiyun static int ov5695_remove(struct i2c_client *client)
1506*4882a593Smuzhiyun {
1507*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1508*4882a593Smuzhiyun 	struct ov5695 *ov5695 = to_ov5695(sd);
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1511*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1512*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1513*4882a593Smuzhiyun #endif
1514*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1515*4882a593Smuzhiyun 	mutex_destroy(&ov5695->mutex);
1516*4882a593Smuzhiyun 
1517*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1518*4882a593Smuzhiyun 	if (!pm_runtime_status_suspended(&client->dev))
1519*4882a593Smuzhiyun 		__ov5695_power_off(ov5695);
1520*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	return 0;
1523*4882a593Smuzhiyun }
1524*4882a593Smuzhiyun 
1525*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1526*4882a593Smuzhiyun static const struct of_device_id ov5695_of_match[] = {
1527*4882a593Smuzhiyun 	{ .compatible = "ovti,ov5695" },
1528*4882a593Smuzhiyun 	{},
1529*4882a593Smuzhiyun };
1530*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ov5695_of_match);
1531*4882a593Smuzhiyun #endif
1532*4882a593Smuzhiyun 
1533*4882a593Smuzhiyun static const struct i2c_device_id ov5695_match_id[] = {
1534*4882a593Smuzhiyun 	{ "ovti,ov5695", 0 },
1535*4882a593Smuzhiyun 	{ },
1536*4882a593Smuzhiyun };
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun static struct i2c_driver ov5695_i2c_driver = {
1539*4882a593Smuzhiyun 	.driver = {
1540*4882a593Smuzhiyun 		.name = OV5695_NAME,
1541*4882a593Smuzhiyun 		.pm = &ov5695_pm_ops,
1542*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(ov5695_of_match),
1543*4882a593Smuzhiyun 	},
1544*4882a593Smuzhiyun 	.probe		= &ov5695_probe,
1545*4882a593Smuzhiyun 	.remove		= &ov5695_remove,
1546*4882a593Smuzhiyun 	.id_table	= ov5695_match_id,
1547*4882a593Smuzhiyun };
1548*4882a593Smuzhiyun 
sensor_mod_init(void)1549*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun 	return i2c_add_driver(&ov5695_i2c_driver);
1552*4882a593Smuzhiyun }
1553*4882a593Smuzhiyun 
sensor_mod_exit(void)1554*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun 	i2c_del_driver(&ov5695_i2c_driver);
1557*4882a593Smuzhiyun }
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1560*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun MODULE_DESCRIPTION("OmniVision ov5695 sensor driver");
1563*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1564