1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov4689 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 add hdr config
12 * V0.0X01.0X06 support enum sensor fmt
13 * V0.0X01.0X07 add quick stream on/off
14 * V0.0X01.0X08 fixed hdr 2 exposure issue
15 */
16 //#define DEBUG
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sysfs.h>
26 #include <linux/slab.h>
27 #include <linux/version.h>
28 #include <linux/rk-camera-module.h>
29 #include <linux/rk-preisp.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-async.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-subdev.h>
34 #include <linux/pinctrl/consumer.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08)
37
38 #ifndef V4L2_CID_DIGITAL_GAIN
39 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40 #endif
41
42 #define OV4689_LANES 4
43 #define OV4689_BITS_PER_SAMPLE 10
44 #define OV4689_LINK_FREQ_500MHZ 500000000LL
45 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
46 #define OV4689_PIXEL_RATE (OV4689_LINK_FREQ_500MHZ * 2 * \
47 OV4689_LANES / OV4689_BITS_PER_SAMPLE)
48 #define OV4689_XVCLK_FREQ 24000000
49
50 #define CHIP_ID 0x004688
51 #define OV4689_REG_CHIP_ID 0x300a
52
53 #define OV4689_REG_CTRL_MODE 0x0100
54 #define OV4689_MODE_SW_STANDBY 0x0
55 #define OV4689_MODE_STREAMING BIT(0)
56
57 #define OV4689_REG_EXPOSURE 0x3500
58 #define OV4689_EXPOSURE_MIN 4
59 #define OV4689_EXPOSURE_STEP 1
60 #define OV4689_VTS_MAX 0x7fff
61
62 #define OV4689_REG_GAIN_H 0x3508
63 #define OV4689_REG_GAIN_L 0x3509
64 #define OV4689_GAIN_H_MASK 0x07
65 #define OV4689_GAIN_H_SHIFT 8
66 #define OV4689_GAIN_L_MASK 0xff
67 #define OV4689_GAIN_MIN 0x80
68 #define OV4689_GAIN_MAX 0x7f8
69 #define OV4689_GAIN_STEP 1
70 #define OV4689_GAIN_DEFAULT 0x80
71
72 #define OV4689_REG_L_GAIN 0x3508
73 #define OV4689_REG_M_GAIN 0x350e
74 #define OV4689_REG_S_GAIN 0x3514
75 #define OV4689_REG_L_EXP 0x3500
76 #define OV4689_REG_M_EXP 0x350a
77 #define OV4689_REG_S_EXP 0x3510
78
79 #define OV4689_GROUP_UPDATE_ADDRESS 0x3208
80 #define OV4689_GROUP_UPDATE_START_DATA 0x00
81 #define OV4689_GROUP_UPDATE_END_DATA 0x10
82 #define OV4689_GROUP_UPDATE_LAUNCH 0xA0
83
84 #define OV4689_REG_TEST_PATTERN 0x5040
85 #define OV4689_TEST_PATTERN_ENABLE 0x80
86 #define OV4689_TEST_PATTERN_DISABLE 0x0
87
88 #define OV4689_REG_VTS 0x380e
89
90 #define REG_NULL 0xFFFF
91
92 #define OV4689_REG_VALUE_08BIT 1
93 #define OV4689_REG_VALUE_16BIT 2
94 #define OV4689_REG_VALUE_24BIT 3
95
96 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
97 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
98 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
99 #define OV4689_NAME "ov4689"
100
101 static const char * const ov4689_supply_names[] = {
102 "avdd", /* Analog power */
103 "dovdd", /* Digital I/O power */
104 "dvdd", /* Digital core power */
105 };
106
107 #define OV4689_NUM_SUPPLIES ARRAY_SIZE(ov4689_supply_names)
108
109 struct regval {
110 u16 addr;
111 u8 val;
112 };
113
114 struct ov4689_mode {
115 u32 width;
116 u32 height;
117 struct v4l2_fract max_fps;
118 u32 hts_def;
119 u32 vts_def;
120 u32 exp_def;
121 const struct regval *reg_list;
122 u32 hdr_mode;
123 u32 vc[PAD_MAX];
124 };
125
126 struct ov4689 {
127 struct i2c_client *client;
128 struct clk *xvclk;
129 struct gpio_desc *reset_gpio;
130 struct gpio_desc *pwdn_gpio;
131 struct regulator_bulk_data supplies[OV4689_NUM_SUPPLIES];
132
133 struct pinctrl *pinctrl;
134 struct pinctrl_state *pins_default;
135 struct pinctrl_state *pins_sleep;
136
137 struct v4l2_subdev subdev;
138 struct media_pad pad;
139 struct v4l2_ctrl_handler ctrl_handler;
140 struct v4l2_ctrl *exposure;
141 struct v4l2_ctrl *anal_gain;
142 struct v4l2_ctrl *digi_gain;
143 struct v4l2_ctrl *hblank;
144 struct v4l2_ctrl *vblank;
145 struct v4l2_ctrl *test_pattern;
146 struct mutex mutex;
147 bool streaming;
148 bool power_on;
149 const struct ov4689_mode *cur_mode;
150 u32 module_index;
151 const char *module_facing;
152 const char *module_name;
153 const char *len_name;
154 bool has_init_exp;
155 struct preisp_hdrae_exp_s init_hdrae_exp;
156 u32 cur_vts;
157 };
158
159 #define to_ov4689(sd) container_of(sd, struct ov4689, subdev)
160
161 /*
162 * Xclk 24Mhz
163 */
164 static const struct regval ov4689_global_regs[] = {
165 {REG_NULL, 0x00},
166 };
167
168 /*
169 * Xclk 24Mhz
170 * max_framerate 90fps
171 * mipi_datarate per lane 1008Mbps, 4lane
172 */
173 static const struct regval ov4689_2688x1520_regs[] = {
174 {0x0103, 0x01},
175 {0x3638, 0x00},
176 {0x0300, 0x00},
177 {0x0302, 0x2a},
178 {0x0303, 0x00},
179 {0x0304, 0x03},
180 {0x030b, 0x00},
181 {0x030d, 0x1e},
182 {0x030e, 0x04},
183 {0x030f, 0x01},
184 {0x0312, 0x01},
185 {0x031e, 0x00},
186 {0x3000, 0x20},
187 {0x3002, 0x00},
188 {0x3018, 0x72},
189 {0x3020, 0x93},
190 {0x3021, 0x03},
191 {0x3022, 0x01},
192 {0x3031, 0x0a},
193 {0x303f, 0x0c},
194 {0x3305, 0xf1},
195 {0x3307, 0x04},
196 {0x3309, 0x29},
197 {0x3500, 0x00},
198 {0x3501, 0x60},
199 {0x3502, 0x00},
200 {0x3503, 0x04},
201 {0x3504, 0x00},
202 {0x3505, 0x00},
203 {0x3506, 0x00},
204 {0x3507, 0x00},
205 {0x3508, 0x00},
206 {0x3509, 0x80},
207 {0x350a, 0x00},
208 {0x350b, 0x00},
209 {0x350c, 0x00},
210 {0x350d, 0x00},
211 {0x350e, 0x00},
212 {0x350f, 0x80},
213 {0x3510, 0x00},
214 {0x3511, 0x00},
215 {0x3512, 0x00},
216 {0x3513, 0x00},
217 {0x3514, 0x00},
218 {0x3515, 0x80},
219 {0x3516, 0x00},
220 {0x3517, 0x00},
221 {0x3518, 0x00},
222 {0x3519, 0x00},
223 {0x351a, 0x00},
224 {0x351b, 0x80},
225 {0x351c, 0x00},
226 {0x351d, 0x00},
227 {0x351e, 0x00},
228 {0x351f, 0x00},
229 {0x3520, 0x00},
230 {0x3521, 0x80},
231 {0x3522, 0x08},
232 {0x3524, 0x08},
233 {0x3526, 0x08},
234 {0x3528, 0x08},
235 {0x352a, 0x08},
236 {0x3602, 0x00},
237 {0x3603, 0x40},
238 {0x3604, 0x02},
239 {0x3605, 0x00},
240 {0x3606, 0x00},
241 {0x3607, 0x00},
242 {0x3609, 0x12},
243 {0x360a, 0x40},
244 {0x360c, 0x08},
245 {0x360f, 0xe5},
246 {0x3608, 0x8f},
247 {0x3611, 0x00},
248 {0x3613, 0xf7},
249 {0x3616, 0x58},
250 {0x3619, 0x99},
251 {0x361b, 0x60},
252 {0x361c, 0x7a},
253 {0x361e, 0x79},
254 {0x361f, 0x02},
255 {0x3632, 0x00},
256 {0x3633, 0x10},
257 {0x3634, 0x10},
258 {0x3635, 0x10},
259 {0x3636, 0x15},
260 {0x3646, 0x86},
261 {0x364a, 0x0b},
262 {0x3700, 0x17},
263 {0x3701, 0x22},
264 {0x3703, 0x10},
265 {0x370a, 0x37},
266 {0x3705, 0x00},
267 {0x3706, 0x63},
268 {0x3709, 0x3c},
269 {0x370b, 0x01},
270 {0x370c, 0x30},
271 {0x3710, 0x24},
272 {0x3711, 0x0c},
273 {0x3716, 0x00},
274 {0x3720, 0x28},
275 {0x3729, 0x7b},
276 {0x372a, 0x84},
277 {0x372b, 0xbd},
278 {0x372c, 0xbc},
279 {0x372e, 0x52},
280 {0x373c, 0x0e},
281 {0x373e, 0x33},
282 {0x3743, 0x10},
283 {0x3744, 0x88},
284 {0x3745, 0xc0},
285 {0x374a, 0x43},
286 {0x374c, 0x00},
287 {0x374e, 0x23},
288 {0x3751, 0x7b},
289 {0x3752, 0x84},
290 {0x3753, 0xbd},
291 {0x3754, 0xbc},
292 {0x3756, 0x52},
293 {0x375c, 0x00},
294 {0x3760, 0x00},
295 {0x3761, 0x00},
296 {0x3762, 0x00},
297 {0x3763, 0x00},
298 {0x3764, 0x00},
299 {0x3767, 0x04},
300 {0x3768, 0x04},
301 {0x3769, 0x08},
302 {0x376a, 0x08},
303 {0x376b, 0x20},
304 {0x376c, 0x00},
305 {0x376d, 0x00},
306 {0x376e, 0x00},
307 {0x3773, 0x00},
308 {0x3774, 0x51},
309 {0x3776, 0xbd},
310 {0x3777, 0xbd},
311 {0x3781, 0x18},
312 {0x3783, 0x25},
313 {0x3798, 0x1b},
314 {0x3800, 0x00},
315 {0x3801, 0x08},
316 {0x3802, 0x00},
317 {0x3803, 0x04},
318 {0x3804, 0x0a},
319 {0x3805, 0x97},
320 {0x3806, 0x05},
321 {0x3807, 0xfb},
322 {0x3808, 0x0a},
323 {0x3809, 0x80},
324 {0x380a, 0x05},
325 {0x380b, 0xf0},
326 {0x380c, 0x03},
327 {0x380d, 0x60},
328 {0x380e, 0x06},
329 {0x380f, 0x12},
330 {0x3810, 0x00},
331 {0x3811, 0x08},
332 {0x3812, 0x00},
333 {0x3813, 0x04},
334 {0x3814, 0x01},
335 {0x3815, 0x01},
336 {0x3819, 0x01},
337 {0x3820, 0x00},
338 {0x3821, 0x06},
339 {0x3829, 0x00},
340 {0x382a, 0x01},
341 {0x382b, 0x01},
342 {0x382d, 0x7f},
343 {0x3830, 0x04},
344 {0x3836, 0x01},
345 {0x3837, 0x00},
346 {0x3841, 0x02},
347 {0x3846, 0x08},
348 {0x3847, 0x07},
349 {0x3d85, 0x36},
350 {0x3d8c, 0x71},
351 {0x3d8d, 0xcb},
352 {0x3f0a, 0x00},
353 {0x4000, 0xf1},
354 {0x4001, 0x40},
355 {0x4002, 0x04},
356 {0x4003, 0x14},
357 {0x400e, 0x00},
358 {0x4011, 0x00},
359 {0x401a, 0x00},
360 {0x401b, 0x00},
361 {0x401c, 0x00},
362 {0x401d, 0x00},
363 {0x401f, 0x00},
364 {0x4020, 0x00},
365 {0x4021, 0x10},
366 {0x4022, 0x07},
367 {0x4023, 0xcf},
368 {0x4024, 0x09},
369 {0x4025, 0x60},
370 {0x4026, 0x09},
371 {0x4027, 0x6f},
372 {0x4028, 0x00},
373 {0x4029, 0x02},
374 {0x402a, 0x06},
375 {0x402b, 0x04},
376 {0x402c, 0x02},
377 {0x402d, 0x02},
378 {0x402e, 0x0e},
379 {0x402f, 0x04},
380 {0x4302, 0xff},
381 {0x4303, 0xff},
382 {0x4304, 0x00},
383 {0x4305, 0x00},
384 {0x4306, 0x00},
385 {0x4308, 0x02},
386 {0x4500, 0x6c},
387 {0x4501, 0xc4},
388 {0x4502, 0x40},
389 {0x4503, 0x01},
390 {0x4601, 0xa7},
391 {0x4800, 0x04},
392 {0x4813, 0x08},
393 {0x481f, 0x40},
394 {0x4829, 0x78},
395 {0x4837, 0x10},
396 {0x4b00, 0x2a},
397 {0x4b0d, 0x00},
398 {0x4d00, 0x04},
399 {0x4d01, 0x42},
400 {0x4d02, 0xd1},
401 {0x4d03, 0x93},
402 {0x4d04, 0xf5},
403 {0x4d05, 0xc1},
404 {0x5000, 0xf3},
405 {0x5001, 0x11},
406 {0x5004, 0x00},
407 {0x500a, 0x00},
408 {0x500b, 0x00},
409 {0x5032, 0x00},
410 {0x5040, 0x00},
411 {0x5050, 0x0c},
412 {0x5500, 0x00},
413 {0x5501, 0x10},
414 {0x5502, 0x01},
415 {0x5503, 0x0f},
416 {0x8000, 0x00},
417 {0x8001, 0x00},
418 {0x8002, 0x00},
419 {0x8003, 0x00},
420 {0x8004, 0x00},
421 {0x8005, 0x00},
422 {0x8006, 0x00},
423 {0x8007, 0x00},
424 {0x8008, 0x00},
425 {0x3638, 0x00},
426 {REG_NULL, 0x00},
427 };
428
429 static const struct regval ov4689_linear_regs[] = {
430 {0x380c, 0x0a},
431 {0x380d, 0x18},
432 {0x3841, 0x02},
433 {0x4800, 0x04},
434 {0x376e, 0x00},
435 {REG_NULL, 0x00},
436 };
437
438 static const struct regval ov4689_hdr_x2_regs[] = {
439 {0x380c, 0x05},
440 {0x380d, 0x10},
441
442 {0x3841, 0x03},
443 {0x3846, 0x08},
444 {0x3847, 0x07},
445 {0x4800, 0x0c},
446 {0x376e, 0x01},
447 {0x350b, 0x08},
448 {0x3511, 0x01},
449 {0x3517, 0x00},
450 {0x351d, 0x00},
451
452 {0x3841, 0x03},//HDR_2
453 {0x3847, 0x06},//HDR_2_ALL
454 {REG_NULL, 0x00},
455 };
456
457 static const struct regval ov4689_hdr_x3_regs[] = {
458 {0x380c, 0x0a},
459 {0x380d, 0x20},
460
461 {0x3841, 0x03},
462 {0x3846, 0x08},
463 {0x3847, 0x07},
464 {0x4800, 0x0c},
465 {0x376e, 0x01},
466 {0x350b, 0x08},
467 {0x3511, 0x01},
468 {0x3517, 0x00},
469 {0x351d, 0x00},
470
471 {0x3841, 0x13},//HDR_3
472 {0x3847, 0x07},//HDR_3_ALL
473 {REG_NULL, 0x00},
474 };
475
476 static const struct ov4689_mode supported_modes[] = {
477 {
478 .width = 2688,
479 .height = 1520,
480 .max_fps = {
481 .numerator = 10000,
482 .denominator = 300000,
483 },
484 .exp_def = 0x0600,
485 .hts_def = 0x0a18,
486 .vts_def = 0x0612,
487 .reg_list = ov4689_linear_regs,
488 .hdr_mode = NO_HDR,
489 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
490 }, {
491 .width = 2688,
492 .height = 1520,
493 .max_fps = {
494 .numerator = 10000,
495 .denominator = 300000,
496 },
497 .exp_def = 0x0600,
498 .hts_def = 0x0510,
499 .vts_def = 0x0612,
500 .reg_list = ov4689_hdr_x2_regs,
501 .hdr_mode = HDR_X2,
502 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
503 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
504 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
505 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
506 }, {
507 .width = 2688,
508 .height = 1520,
509 .max_fps = {
510 .numerator = 10000,
511 .denominator = 100000,
512 },
513 .exp_def = 0x0600,
514 .hts_def = 0x0a20,
515 .vts_def = 0x0612,
516 .reg_list = ov4689_hdr_x3_regs,
517 .hdr_mode = HDR_X3,
518 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
519 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
520 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr1
521 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
522 },
523 };
524
525 static const s64 link_freq_menu_items[] = {
526 OV4689_LINK_FREQ_500MHZ
527 };
528
529 static const char * const ov4689_test_pattern_menu[] = {
530 "Disabled",
531 "Vertical Color Bar Type 1",
532 "Vertical Color Bar Type 2",
533 "Vertical Color Bar Type 3",
534 "Vertical Color Bar Type 4"
535 };
536
537 /* Write registers up to 4 at a time */
ov4689_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)538 static int ov4689_write_reg(struct i2c_client *client, u16 reg,
539 u32 len, u32 val)
540 {
541 u32 buf_i, val_i;
542 u8 buf[6];
543 u8 *val_p;
544 __be32 val_be;
545
546 if (len > 4)
547 return -EINVAL;
548
549 buf[0] = reg >> 8;
550 buf[1] = reg & 0xff;
551
552 val_be = cpu_to_be32(val);
553 val_p = (u8 *)&val_be;
554 buf_i = 2;
555 val_i = 4 - len;
556
557 while (val_i < 4)
558 buf[buf_i++] = val_p[val_i++];
559
560 if (i2c_master_send(client, buf, len + 2) != len + 2)
561 return -EIO;
562
563 return 0;
564 }
565
ov4689_write_array(struct i2c_client * client,const struct regval * regs)566 static int ov4689_write_array(struct i2c_client *client,
567 const struct regval *regs)
568 {
569 u32 i;
570 int ret = 0;
571
572 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
573 ret = ov4689_write_reg(client, regs[i].addr,
574 OV4689_REG_VALUE_08BIT, regs[i].val);
575
576 return ret;
577 }
578
579 /* Read registers up to 4 at a time */
ov4689_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)580 static int ov4689_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
581 u32 *val)
582 {
583 struct i2c_msg msgs[2];
584 u8 *data_be_p;
585 __be32 data_be = 0;
586 __be16 reg_addr_be = cpu_to_be16(reg);
587 int ret;
588
589 if (len > 4 || !len)
590 return -EINVAL;
591
592 data_be_p = (u8 *)&data_be;
593 /* Write register address */
594 msgs[0].addr = client->addr;
595 msgs[0].flags = 0;
596 msgs[0].len = 2;
597 msgs[0].buf = (u8 *)®_addr_be;
598
599 /* Read data from register */
600 msgs[1].addr = client->addr;
601 msgs[1].flags = I2C_M_RD;
602 msgs[1].len = len;
603 msgs[1].buf = &data_be_p[4 - len];
604
605 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
606 if (ret != ARRAY_SIZE(msgs))
607 return -EIO;
608
609 *val = be32_to_cpu(data_be);
610
611 return 0;
612 }
613
ov4689_get_reso_dist(const struct ov4689_mode * mode,struct v4l2_mbus_framefmt * framefmt)614 static int ov4689_get_reso_dist(const struct ov4689_mode *mode,
615 struct v4l2_mbus_framefmt *framefmt)
616 {
617 return abs(mode->width - framefmt->width) +
618 abs(mode->height - framefmt->height);
619 }
620
621 static const struct ov4689_mode *
ov4689_find_best_fit(struct v4l2_subdev_format * fmt)622 ov4689_find_best_fit(struct v4l2_subdev_format *fmt)
623 {
624 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
625 int dist;
626 int cur_best_fit = 0;
627 int cur_best_fit_dist = -1;
628 unsigned int i;
629
630 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
631 dist = ov4689_get_reso_dist(&supported_modes[i], framefmt);
632 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
633 cur_best_fit_dist = dist;
634 cur_best_fit = i;
635 }
636 }
637
638 return &supported_modes[cur_best_fit];
639 }
640
ov4689_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)641 static int ov4689_set_fmt(struct v4l2_subdev *sd,
642 struct v4l2_subdev_pad_config *cfg,
643 struct v4l2_subdev_format *fmt)
644 {
645 struct ov4689 *ov4689 = to_ov4689(sd);
646 const struct ov4689_mode *mode;
647 s64 h_blank, vblank_def;
648
649 mutex_lock(&ov4689->mutex);
650
651 mode = ov4689_find_best_fit(fmt);
652 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
653 fmt->format.width = mode->width;
654 fmt->format.height = mode->height;
655 fmt->format.field = V4L2_FIELD_NONE;
656 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
657 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
658 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
659 #else
660 mutex_unlock(&ov4689->mutex);
661 return -ENOTTY;
662 #endif
663 } else {
664 ov4689->cur_mode = mode;
665 h_blank = mode->hts_def - mode->width;
666 __v4l2_ctrl_modify_range(ov4689->hblank, h_blank,
667 h_blank, 1, h_blank);
668 vblank_def = mode->vts_def - mode->height;
669 __v4l2_ctrl_modify_range(ov4689->vblank, vblank_def,
670 OV4689_VTS_MAX - mode->height,
671 1, vblank_def);
672 }
673
674 mutex_unlock(&ov4689->mutex);
675
676 return 0;
677 }
678
ov4689_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)679 static int ov4689_get_fmt(struct v4l2_subdev *sd,
680 struct v4l2_subdev_pad_config *cfg,
681 struct v4l2_subdev_format *fmt)
682 {
683 struct ov4689 *ov4689 = to_ov4689(sd);
684 const struct ov4689_mode *mode = ov4689->cur_mode;
685
686 mutex_lock(&ov4689->mutex);
687 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
688 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
689 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
690 #else
691 mutex_unlock(&ov4689->mutex);
692 return -ENOTTY;
693 #endif
694 } else {
695 fmt->format.width = mode->width;
696 fmt->format.height = mode->height;
697 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
698 fmt->format.field = V4L2_FIELD_NONE;
699 /* format info: width/height/data type/virctual channel */
700 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
701 fmt->reserved[0] = mode->vc[fmt->pad];
702 else
703 fmt->reserved[0] = mode->vc[PAD0];
704 }
705 mutex_unlock(&ov4689->mutex);
706
707 return 0;
708 }
709
ov4689_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)710 static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
711 struct v4l2_subdev_pad_config *cfg,
712 struct v4l2_subdev_mbus_code_enum *code)
713 {
714 if (code->index != 0)
715 return -EINVAL;
716 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
717
718 return 0;
719 }
720
ov4689_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)721 static int ov4689_enum_frame_sizes(struct v4l2_subdev *sd,
722 struct v4l2_subdev_pad_config *cfg,
723 struct v4l2_subdev_frame_size_enum *fse)
724 {
725 if (fse->index >= ARRAY_SIZE(supported_modes))
726 return -EINVAL;
727
728 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
729 return -EINVAL;
730
731 fse->min_width = supported_modes[fse->index].width;
732 fse->max_width = supported_modes[fse->index].width;
733 fse->max_height = supported_modes[fse->index].height;
734 fse->min_height = supported_modes[fse->index].height;
735
736 return 0;
737 }
738
ov4689_enable_test_pattern(struct ov4689 * ov4689,u32 pattern)739 static int ov4689_enable_test_pattern(struct ov4689 *ov4689, u32 pattern)
740 {
741 u32 val;
742
743 if (pattern)
744 val = (pattern - 1) | OV4689_TEST_PATTERN_ENABLE;
745 else
746 val = OV4689_TEST_PATTERN_DISABLE;
747
748 return ov4689_write_reg(ov4689->client, OV4689_REG_TEST_PATTERN,
749 OV4689_REG_VALUE_08BIT, val);
750 }
751
ov4689_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)752 static int ov4689_g_frame_interval(struct v4l2_subdev *sd,
753 struct v4l2_subdev_frame_interval *fi)
754 {
755 struct ov4689 *ov4689 = to_ov4689(sd);
756 const struct ov4689_mode *mode = ov4689->cur_mode;
757
758 fi->interval = mode->max_fps;
759
760 return 0;
761 }
762
ov4689_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)763 static int ov4689_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
764 struct v4l2_mbus_config *config)
765 {
766 struct ov4689 *ov4689 = to_ov4689(sd);
767 const struct ov4689_mode *mode = ov4689->cur_mode;
768 u32 val = 1 << (OV4689_LANES - 1) |
769 V4L2_MBUS_CSI2_CHANNEL_0 |
770 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
771
772 if (mode->hdr_mode != NO_HDR)
773 val |= V4L2_MBUS_CSI2_CHANNEL_1;
774 if (mode->hdr_mode == HDR_X3)
775 val |= V4L2_MBUS_CSI2_CHANNEL_2;
776
777 config->type = V4L2_MBUS_CSI2_DPHY;
778 config->flags = val;
779
780 return 0;
781 }
782
ov4689_get_module_inf(struct ov4689 * ov4689,struct rkmodule_inf * inf)783 static void ov4689_get_module_inf(struct ov4689 *ov4689,
784 struct rkmodule_inf *inf)
785 {
786 memset(inf, 0, sizeof(*inf));
787 strlcpy(inf->base.sensor, OV4689_NAME, sizeof(inf->base.sensor));
788 strlcpy(inf->base.module, ov4689->module_name,
789 sizeof(inf->base.module));
790 strlcpy(inf->base.lens, ov4689->len_name, sizeof(inf->base.lens));
791 }
792
ov4689_set_hdrae(struct ov4689 * ov4689,struct preisp_hdrae_exp_s * ae)793 static int ov4689_set_hdrae(struct ov4689 *ov4689,
794 struct preisp_hdrae_exp_s *ae)
795 {
796 int ret = 0;
797 u32 l_exp = ae->long_exp_reg;
798 u32 m_exp = ae->middle_exp_reg;
799 u32 s_exp = ae->short_exp_reg;
800 u32 l_gain = ae->long_gain_reg;
801 u32 m_gain = ae->middle_gain_reg;
802 u32 s_gain = ae->short_gain_reg;
803
804 if (!ov4689->has_init_exp && !ov4689->streaming) {
805 ov4689->init_hdrae_exp = *ae;
806 ov4689->has_init_exp = true;
807 dev_dbg(&ov4689->client->dev, "ov4689 don't stream, record exp for hdr!\n");
808 return ret;
809 }
810 dev_dbg(&ov4689->client->dev,
811 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
812 l_exp, m_exp, s_exp, l_gain, m_gain, s_gain);
813
814 if (l_exp < 3)
815 l_exp = 3;
816 if (m_exp < 3)
817 m_exp = 3;
818 if (s_exp < 3)
819 s_exp = 3;
820
821 if (ov4689->cur_mode->hdr_mode == HDR_X2) {
822 l_gain = m_gain;
823 l_exp = m_exp;
824 m_gain = s_gain;
825 m_exp = s_exp;
826 if (l_exp <= m_exp ||
827 l_exp + m_exp >= ov4689->cur_vts - 4) {
828 dev_err(&ov4689->client->dev,
829 "exp parameter error, l_exp %d, s_exp %d, cur_vts %d\n",
830 l_exp, m_exp, ov4689->cur_vts);
831 return -EINVAL;
832 }
833 } else {
834 if (l_exp <= m_exp ||
835 m_exp <= s_exp ||
836 l_exp + m_exp + s_exp >= ov4689->cur_vts - 4) {
837 dev_err(&ov4689->client->dev,
838 "exp parameter error, l_exp %d, m_exp %d, s_exp %d, cur_vts %d\n",
839 l_exp, m_exp, s_exp, ov4689->cur_vts);
840 return -EINVAL;
841 }
842 }
843
844 ret = ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
845 OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_START_DATA);
846
847 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_L_GAIN,
848 OV4689_REG_VALUE_16BIT, l_gain);
849 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_L_EXP,
850 OV4689_REG_VALUE_24BIT, l_exp << 4);
851 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_M_GAIN,
852 OV4689_REG_VALUE_16BIT, m_gain);
853 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_M_EXP,
854 OV4689_REG_VALUE_24BIT, m_exp << 4);
855 if (ov4689->cur_mode->hdr_mode == HDR_X3) {
856 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_S_GAIN,
857 OV4689_REG_VALUE_16BIT, s_gain);
858 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_S_EXP,
859 OV4689_REG_VALUE_24BIT, s_exp << 4);
860 }
861 ret |= ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
862 OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_END_DATA);
863 ret |= ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
864 OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_LAUNCH);
865 return ret;
866 }
867
ov4689_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)868 static long ov4689_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
869 {
870 struct ov4689 *ov4689 = to_ov4689(sd);
871 struct rkmodule_hdr_cfg *hdr;
872 u32 i, h, w;
873 long ret = 0;
874 u32 stream = 0;
875
876 switch (cmd) {
877 case RKMODULE_GET_MODULE_INFO:
878 ov4689_get_module_inf(ov4689, (struct rkmodule_inf *)arg);
879 break;
880 case RKMODULE_GET_HDR_CFG:
881 hdr = (struct rkmodule_hdr_cfg *)arg;
882 hdr->esp.mode = HDR_NORMAL_VC;
883 hdr->hdr_mode = ov4689->cur_mode->hdr_mode;
884 break;
885 case RKMODULE_SET_HDR_CFG:
886 hdr = (struct rkmodule_hdr_cfg *)arg;
887 w = ov4689->cur_mode->width;
888 h = ov4689->cur_mode->height;
889 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
890 if (w == supported_modes[i].width &&
891 h == supported_modes[i].height &&
892 supported_modes[i].hdr_mode == hdr->hdr_mode) {
893 ov4689->cur_mode = &supported_modes[i];
894 break;
895 }
896 }
897 if (i == ARRAY_SIZE(supported_modes)) {
898 dev_err(&ov4689->client->dev,
899 "not find hdr mode:%d %dx%d config\n",
900 hdr->hdr_mode, w, h);
901 ret = -EINVAL;
902 } else {
903 dev_dbg(&ov4689->client->dev,
904 "set hdr mode:%d\n",
905 ov4689->cur_mode->hdr_mode);
906 w = ov4689->cur_mode->hts_def - ov4689->cur_mode->width;
907 h = ov4689->cur_mode->vts_def - ov4689->cur_mode->height;
908 __v4l2_ctrl_modify_range(ov4689->hblank, w, w, 1, w);
909 __v4l2_ctrl_modify_range(ov4689->vblank, h,
910 OV4689_VTS_MAX - ov4689->cur_mode->height, 1, h);
911 }
912 break;
913 case PREISP_CMD_SET_HDRAE_EXP:
914 return ov4689_set_hdrae(ov4689, arg);
915 case RKMODULE_SET_QUICK_STREAM:
916
917 stream = *((u32 *)arg);
918
919 if (stream)
920 ret = ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
921 OV4689_REG_VALUE_08BIT, OV4689_MODE_STREAMING);
922 else
923 ret = ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
924 OV4689_REG_VALUE_08BIT, OV4689_MODE_SW_STANDBY);
925 break;
926 default:
927 ret = -ENOIOCTLCMD;
928 break;
929 }
930
931 return ret;
932 }
933
934 #ifdef CONFIG_COMPAT
ov4689_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)935 static long ov4689_compat_ioctl32(struct v4l2_subdev *sd,
936 unsigned int cmd, unsigned long arg)
937 {
938 void __user *up = compat_ptr(arg);
939 struct rkmodule_inf *inf;
940 struct rkmodule_awb_cfg *cfg;
941 struct rkmodule_hdr_cfg *hdr;
942 struct preisp_hdrae_exp_s *hdrae;
943 long ret;
944 u32 stream = 0;
945
946 switch (cmd) {
947 case RKMODULE_GET_MODULE_INFO:
948 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
949 if (!inf) {
950 ret = -ENOMEM;
951 return ret;
952 }
953
954 ret = ov4689_ioctl(sd, cmd, inf);
955 if (!ret)
956 ret = copy_to_user(up, inf, sizeof(*inf));
957 kfree(inf);
958 break;
959 case RKMODULE_AWB_CFG:
960 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
961 if (!cfg) {
962 ret = -ENOMEM;
963 return ret;
964 }
965
966 ret = copy_from_user(cfg, up, sizeof(*cfg));
967 if (!ret)
968 ret = ov4689_ioctl(sd, cmd, cfg);
969 kfree(cfg);
970 break;
971 case RKMODULE_GET_HDR_CFG:
972 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
973 if (!hdr) {
974 ret = -ENOMEM;
975 return ret;
976 }
977
978 ret = ov4689_ioctl(sd, cmd, hdr);
979 if (!ret)
980 ret = copy_to_user(up, hdr, sizeof(*hdr));
981 kfree(hdr);
982 break;
983 case RKMODULE_SET_HDR_CFG:
984 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
985 if (!hdr) {
986 ret = -ENOMEM;
987 return ret;
988 }
989
990 ret = copy_from_user(hdr, up, sizeof(*hdr));
991 if (!ret)
992 ret = ov4689_ioctl(sd, cmd, hdr);
993 kfree(hdr);
994 break;
995 case PREISP_CMD_SET_HDRAE_EXP:
996 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
997 if (!hdrae) {
998 ret = -ENOMEM;
999 return ret;
1000 }
1001
1002 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1003 if (!ret)
1004 ret = ov4689_ioctl(sd, cmd, hdrae);
1005 kfree(hdrae);
1006 break;
1007 case RKMODULE_SET_QUICK_STREAM:
1008 ret = copy_from_user(&stream, up, sizeof(u32));
1009 if (!ret)
1010 ret = ov4689_ioctl(sd, cmd, &stream);
1011 break;
1012 default:
1013 ret = -ENOIOCTLCMD;
1014 break;
1015 }
1016
1017 return ret;
1018 }
1019 #endif
1020
__ov4689_start_stream(struct ov4689 * ov4689)1021 static int __ov4689_start_stream(struct ov4689 *ov4689)
1022 {
1023 int ret;
1024
1025 ret = ov4689_write_array(ov4689->client, ov4689_2688x1520_regs);
1026 ret |= ov4689_write_array(ov4689->client, ov4689->cur_mode->reg_list);
1027 if (ret)
1028 return ret;
1029
1030 /* In case these controls are set before streaming */
1031 ret = __v4l2_ctrl_handler_setup(&ov4689->ctrl_handler);
1032 if (ret)
1033 return ret;
1034 if (ov4689->has_init_exp && ov4689->cur_mode->hdr_mode != NO_HDR) {
1035 ret = ov4689_ioctl(&ov4689->subdev,
1036 PREISP_CMD_SET_HDRAE_EXP,
1037 &ov4689->init_hdrae_exp);
1038 if (ret) {
1039 dev_err(&ov4689->client->dev,
1040 "init exp fail in hdr mode\n");
1041 return ret;
1042 }
1043 }
1044
1045 return ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
1046 OV4689_REG_VALUE_08BIT, OV4689_MODE_STREAMING);
1047 }
1048
__ov4689_stop_stream(struct ov4689 * ov4689)1049 static int __ov4689_stop_stream(struct ov4689 *ov4689)
1050 {
1051 ov4689->has_init_exp = false;
1052 return ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
1053 OV4689_REG_VALUE_08BIT, OV4689_MODE_SW_STANDBY);
1054 }
1055
ov4689_s_stream(struct v4l2_subdev * sd,int on)1056 static int ov4689_s_stream(struct v4l2_subdev *sd, int on)
1057 {
1058 struct ov4689 *ov4689 = to_ov4689(sd);
1059 struct i2c_client *client = ov4689->client;
1060 int ret = 0;
1061
1062 mutex_lock(&ov4689->mutex);
1063 on = !!on;
1064 if (on == ov4689->streaming)
1065 goto unlock_and_return;
1066
1067 if (on) {
1068 ret = pm_runtime_get_sync(&client->dev);
1069 if (ret < 0) {
1070 pm_runtime_put_noidle(&client->dev);
1071 goto unlock_and_return;
1072 }
1073
1074 ret = __ov4689_start_stream(ov4689);
1075 if (ret) {
1076 v4l2_err(sd, "start stream failed while write regs\n");
1077 pm_runtime_put(&client->dev);
1078 goto unlock_and_return;
1079 }
1080 } else {
1081 __ov4689_stop_stream(ov4689);
1082 pm_runtime_put(&client->dev);
1083 }
1084
1085 ov4689->streaming = on;
1086
1087 unlock_and_return:
1088 mutex_unlock(&ov4689->mutex);
1089
1090 return ret;
1091 }
1092
ov4689_s_power(struct v4l2_subdev * sd,int on)1093 static int ov4689_s_power(struct v4l2_subdev *sd, int on)
1094 {
1095 struct ov4689 *ov4689 = to_ov4689(sd);
1096 struct i2c_client *client = ov4689->client;
1097 int ret = 0;
1098
1099 mutex_lock(&ov4689->mutex);
1100
1101 /* If the power state is not modified - no work to do. */
1102 if (ov4689->power_on == !!on)
1103 goto unlock_and_return;
1104
1105 if (on) {
1106 ret = pm_runtime_get_sync(&client->dev);
1107 if (ret < 0) {
1108 pm_runtime_put_noidle(&client->dev);
1109 goto unlock_and_return;
1110 }
1111
1112 ret = ov4689_write_array(ov4689->client, ov4689_global_regs);
1113 if (ret) {
1114 v4l2_err(sd, "could not set init registers\n");
1115 pm_runtime_put_noidle(&client->dev);
1116 goto unlock_and_return;
1117 }
1118
1119 ov4689->power_on = true;
1120 } else {
1121 pm_runtime_put(&client->dev);
1122 ov4689->power_on = false;
1123 }
1124
1125 unlock_and_return:
1126 mutex_unlock(&ov4689->mutex);
1127
1128 return ret;
1129 }
1130
1131 /* Calculate the delay in us by clock rate and clock cycles */
ov4689_cal_delay(u32 cycles)1132 static inline u32 ov4689_cal_delay(u32 cycles)
1133 {
1134 return DIV_ROUND_UP(cycles, OV4689_XVCLK_FREQ / 1000 / 1000);
1135 }
1136
__ov4689_power_on(struct ov4689 * ov4689)1137 static int __ov4689_power_on(struct ov4689 *ov4689)
1138 {
1139 int ret;
1140 u32 delay_us;
1141 struct device *dev = &ov4689->client->dev;
1142
1143 if (!IS_ERR_OR_NULL(ov4689->pins_default)) {
1144 ret = pinctrl_select_state(ov4689->pinctrl,
1145 ov4689->pins_default);
1146 if (ret < 0)
1147 dev_err(dev, "could not set pins\n");
1148 }
1149 ret = clk_set_rate(ov4689->xvclk, OV4689_XVCLK_FREQ);
1150 if (ret < 0)
1151 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1152 if (clk_get_rate(ov4689->xvclk) != OV4689_XVCLK_FREQ)
1153 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1154 ret = clk_prepare_enable(ov4689->xvclk);
1155 if (ret < 0) {
1156 dev_err(dev, "Failed to enable xvclk\n");
1157 return ret;
1158 }
1159 if (!IS_ERR(ov4689->reset_gpio))
1160 gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
1161
1162 ret = regulator_bulk_enable(OV4689_NUM_SUPPLIES, ov4689->supplies);
1163 if (ret < 0) {
1164 dev_err(dev, "Failed to enable regulators\n");
1165 goto disable_clk;
1166 }
1167
1168 if (!IS_ERR(ov4689->reset_gpio))
1169 gpiod_set_value_cansleep(ov4689->reset_gpio, 0);
1170
1171 usleep_range(500, 1000);
1172 if (!IS_ERR(ov4689->pwdn_gpio))
1173 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 1);
1174
1175 /* 8192 cycles prior to first SCCB transaction */
1176 delay_us = ov4689_cal_delay(8192);
1177 usleep_range(delay_us, delay_us * 2);
1178
1179 return 0;
1180
1181 disable_clk:
1182 clk_disable_unprepare(ov4689->xvclk);
1183
1184 return ret;
1185 }
1186
__ov4689_power_off(struct ov4689 * ov4689)1187 static void __ov4689_power_off(struct ov4689 *ov4689)
1188 {
1189 int ret;
1190 struct device *dev = &ov4689->client->dev;
1191
1192 if (!IS_ERR(ov4689->pwdn_gpio))
1193 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0);
1194 clk_disable_unprepare(ov4689->xvclk);
1195 if (!IS_ERR(ov4689->reset_gpio))
1196 gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
1197 if (!IS_ERR_OR_NULL(ov4689->pins_sleep)) {
1198 ret = pinctrl_select_state(ov4689->pinctrl,
1199 ov4689->pins_sleep);
1200 if (ret < 0)
1201 dev_dbg(dev, "could not set pins\n");
1202 }
1203 regulator_bulk_disable(OV4689_NUM_SUPPLIES, ov4689->supplies);
1204 }
1205
ov4689_runtime_resume(struct device * dev)1206 static int ov4689_runtime_resume(struct device *dev)
1207 {
1208 struct i2c_client *client = to_i2c_client(dev);
1209 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1210 struct ov4689 *ov4689 = to_ov4689(sd);
1211
1212 return __ov4689_power_on(ov4689);
1213 }
1214
ov4689_runtime_suspend(struct device * dev)1215 static int ov4689_runtime_suspend(struct device *dev)
1216 {
1217 struct i2c_client *client = to_i2c_client(dev);
1218 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1219 struct ov4689 *ov4689 = to_ov4689(sd);
1220
1221 __ov4689_power_off(ov4689);
1222
1223 return 0;
1224 }
1225
1226 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov4689_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1227 static int ov4689_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1228 {
1229 struct ov4689 *ov4689 = to_ov4689(sd);
1230 struct v4l2_mbus_framefmt *try_fmt =
1231 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1232 const struct ov4689_mode *def_mode = &supported_modes[0];
1233
1234 mutex_lock(&ov4689->mutex);
1235 /* Initialize try_fmt */
1236 try_fmt->width = def_mode->width;
1237 try_fmt->height = def_mode->height;
1238 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1239 try_fmt->field = V4L2_FIELD_NONE;
1240
1241 mutex_unlock(&ov4689->mutex);
1242 /* No crop or compose */
1243
1244 return 0;
1245 }
1246 #endif
1247
ov4689_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1248 static int ov4689_enum_frame_interval(struct v4l2_subdev *sd,
1249 struct v4l2_subdev_pad_config *cfg,
1250 struct v4l2_subdev_frame_interval_enum *fie)
1251 {
1252 if (fie->index >= ARRAY_SIZE(supported_modes))
1253 return -EINVAL;
1254
1255 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1256 fie->width = supported_modes[fie->index].width;
1257 fie->height = supported_modes[fie->index].height;
1258 fie->interval = supported_modes[fie->index].max_fps;
1259 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1260 return 0;
1261 }
1262
1263 static const struct dev_pm_ops ov4689_pm_ops = {
1264 SET_RUNTIME_PM_OPS(ov4689_runtime_suspend,
1265 ov4689_runtime_resume, NULL)
1266 };
1267
1268 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1269 static const struct v4l2_subdev_internal_ops ov4689_internal_ops = {
1270 .open = ov4689_open,
1271 };
1272 #endif
1273
1274 static const struct v4l2_subdev_core_ops ov4689_core_ops = {
1275 .s_power = ov4689_s_power,
1276 .ioctl = ov4689_ioctl,
1277 #ifdef CONFIG_COMPAT
1278 .compat_ioctl32 = ov4689_compat_ioctl32,
1279 #endif
1280 };
1281
1282 static const struct v4l2_subdev_video_ops ov4689_video_ops = {
1283 .s_stream = ov4689_s_stream,
1284 .g_frame_interval = ov4689_g_frame_interval,
1285 };
1286
1287 static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
1288 .enum_mbus_code = ov4689_enum_mbus_code,
1289 .enum_frame_size = ov4689_enum_frame_sizes,
1290 .enum_frame_interval = ov4689_enum_frame_interval,
1291 .get_fmt = ov4689_get_fmt,
1292 .set_fmt = ov4689_set_fmt,
1293 .get_mbus_config = ov4689_g_mbus_config,
1294 };
1295
1296 static const struct v4l2_subdev_ops ov4689_subdev_ops = {
1297 .core = &ov4689_core_ops,
1298 .video = &ov4689_video_ops,
1299 .pad = &ov4689_pad_ops,
1300 };
1301
ov4689_set_ctrl(struct v4l2_ctrl * ctrl)1302 static int ov4689_set_ctrl(struct v4l2_ctrl *ctrl)
1303 {
1304 struct ov4689 *ov4689 = container_of(ctrl->handler,
1305 struct ov4689, ctrl_handler);
1306 struct i2c_client *client = ov4689->client;
1307 s64 max;
1308 int ret = 0;
1309
1310 /* Propagate change of current control to all related controls */
1311 switch (ctrl->id) {
1312 case V4L2_CID_VBLANK:
1313 /* Update max exposure while meeting expected vblanking */
1314 max = ov4689->cur_mode->height + ctrl->val - 4;
1315 __v4l2_ctrl_modify_range(ov4689->exposure,
1316 ov4689->exposure->minimum, max,
1317 ov4689->exposure->step,
1318 ov4689->exposure->default_value);
1319 break;
1320 }
1321
1322 if (!pm_runtime_get_if_in_use(&client->dev))
1323 return 0;
1324
1325 switch (ctrl->id) {
1326 case V4L2_CID_EXPOSURE:
1327 /* 4 least significant bits of expsoure are fractional part */
1328 ret = ov4689_write_reg(ov4689->client, OV4689_REG_EXPOSURE,
1329 OV4689_REG_VALUE_24BIT, ctrl->val << 4);
1330 dev_dbg(&client->dev, "%s set exposure %d\n",
1331 __func__, ctrl->val);
1332 break;
1333 case V4L2_CID_ANALOGUE_GAIN:
1334 ret = ov4689_write_reg(ov4689->client, OV4689_REG_GAIN_H,
1335 OV4689_REG_VALUE_08BIT,
1336 (ctrl->val >> OV4689_GAIN_H_SHIFT) & OV4689_GAIN_H_MASK);
1337 ret |= ov4689_write_reg(ov4689->client, OV4689_REG_GAIN_L,
1338 OV4689_REG_VALUE_08BIT,
1339 ctrl->val & OV4689_GAIN_L_MASK);
1340 dev_dbg(&client->dev, "%s set gain %d\n",
1341 __func__, ctrl->val);
1342 break;
1343 case V4L2_CID_VBLANK:
1344 ret = ov4689_write_reg(ov4689->client, OV4689_REG_VTS,
1345 OV4689_REG_VALUE_16BIT,
1346 ctrl->val + ov4689->cur_mode->height);
1347 ov4689->cur_vts = ctrl->val + ov4689->cur_mode->height;
1348 dev_dbg(&client->dev, "%s set vts %d\n",
1349 __func__, ov4689->cur_vts);
1350 break;
1351 case V4L2_CID_TEST_PATTERN:
1352 ret = ov4689_enable_test_pattern(ov4689, ctrl->val);
1353 break;
1354 default:
1355 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1356 __func__, ctrl->id, ctrl->val);
1357 break;
1358 }
1359
1360 pm_runtime_put(&client->dev);
1361
1362 return ret;
1363 }
1364
1365 static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
1366 .s_ctrl = ov4689_set_ctrl,
1367 };
1368
ov4689_initialize_controls(struct ov4689 * ov4689)1369 static int ov4689_initialize_controls(struct ov4689 *ov4689)
1370 {
1371 const struct ov4689_mode *mode;
1372 struct v4l2_ctrl_handler *handler;
1373 struct v4l2_ctrl *ctrl;
1374 s64 exposure_max, vblank_def;
1375 u32 h_blank;
1376 int ret;
1377
1378 handler = &ov4689->ctrl_handler;
1379 mode = ov4689->cur_mode;
1380 ret = v4l2_ctrl_handler_init(handler, 8);
1381 if (ret)
1382 return ret;
1383 handler->lock = &ov4689->mutex;
1384
1385 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1386 0, 0, link_freq_menu_items);
1387 if (ctrl)
1388 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1389
1390 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1391 0, OV4689_PIXEL_RATE, 1, OV4689_PIXEL_RATE);
1392
1393 h_blank = mode->hts_def - mode->width;
1394 ov4689->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1395 h_blank, h_blank, 1, h_blank);
1396 if (ov4689->hblank)
1397 ov4689->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1398
1399 vblank_def = mode->vts_def - mode->height;
1400 ov4689->vblank = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
1401 V4L2_CID_VBLANK, vblank_def,
1402 OV4689_VTS_MAX - mode->height,
1403 1, vblank_def);
1404 ov4689->cur_vts = mode->vts_def;
1405
1406 exposure_max = mode->vts_def - 4;
1407 ov4689->exposure = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
1408 V4L2_CID_EXPOSURE, OV4689_EXPOSURE_MIN,
1409 exposure_max, OV4689_EXPOSURE_STEP,
1410 mode->exp_def);
1411
1412 ov4689->anal_gain = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
1413 V4L2_CID_ANALOGUE_GAIN, OV4689_GAIN_MIN,
1414 OV4689_GAIN_MAX, OV4689_GAIN_STEP,
1415 OV4689_GAIN_DEFAULT);
1416
1417 ov4689->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1418 &ov4689_ctrl_ops, V4L2_CID_TEST_PATTERN,
1419 ARRAY_SIZE(ov4689_test_pattern_menu) - 1,
1420 0, 0, ov4689_test_pattern_menu);
1421
1422 if (handler->error) {
1423 ret = handler->error;
1424 dev_err(&ov4689->client->dev,
1425 "Failed to init controls(%d)\n", ret);
1426 goto err_free_handler;
1427 }
1428
1429 ov4689->subdev.ctrl_handler = handler;
1430 ov4689->has_init_exp = false;
1431
1432 return 0;
1433
1434 err_free_handler:
1435 v4l2_ctrl_handler_free(handler);
1436
1437 return ret;
1438 }
1439
ov4689_check_sensor_id(struct ov4689 * ov4689,struct i2c_client * client)1440 static int ov4689_check_sensor_id(struct ov4689 *ov4689,
1441 struct i2c_client *client)
1442 {
1443 struct device *dev = &ov4689->client->dev;
1444 u32 id = 0;
1445 int ret;
1446
1447 ret = ov4689_read_reg(client, OV4689_REG_CHIP_ID,
1448 OV4689_REG_VALUE_16BIT, &id);
1449 if (id != CHIP_ID) {
1450 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1451 return -ENODEV;
1452 }
1453
1454 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1455
1456 return 0;
1457 }
1458
ov4689_configure_regulators(struct ov4689 * ov4689)1459 static int ov4689_configure_regulators(struct ov4689 *ov4689)
1460 {
1461 unsigned int i;
1462
1463 for (i = 0; i < OV4689_NUM_SUPPLIES; i++)
1464 ov4689->supplies[i].supply = ov4689_supply_names[i];
1465
1466 return devm_regulator_bulk_get(&ov4689->client->dev,
1467 OV4689_NUM_SUPPLIES,
1468 ov4689->supplies);
1469 }
1470
ov4689_probe(struct i2c_client * client,const struct i2c_device_id * id)1471 static int ov4689_probe(struct i2c_client *client,
1472 const struct i2c_device_id *id)
1473 {
1474 struct device *dev = &client->dev;
1475 struct device_node *node = dev->of_node;
1476 struct ov4689 *ov4689;
1477 struct v4l2_subdev *sd;
1478 char facing[2];
1479 int ret;
1480 u32 i, hdr_mode = 0;
1481
1482 dev_info(dev, "driver version: %02x.%02x.%02x",
1483 DRIVER_VERSION >> 16,
1484 (DRIVER_VERSION & 0xff00) >> 8,
1485 DRIVER_VERSION & 0x00ff);
1486
1487 ov4689 = devm_kzalloc(dev, sizeof(*ov4689), GFP_KERNEL);
1488 if (!ov4689)
1489 return -ENOMEM;
1490
1491 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1492 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1493 &ov4689->module_index);
1494 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1495 &ov4689->module_facing);
1496 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1497 &ov4689->module_name);
1498 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1499 &ov4689->len_name);
1500 if (ret) {
1501 dev_err(dev, "could not get module information!\n");
1502 return -EINVAL;
1503 }
1504
1505 ov4689->client = client;
1506 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1507 if (hdr_mode == supported_modes[i].hdr_mode) {
1508 ov4689->cur_mode = &supported_modes[i];
1509 break;
1510 }
1511 }
1512 if (i == ARRAY_SIZE(supported_modes))
1513 ov4689->cur_mode = &supported_modes[0];
1514
1515 ov4689->xvclk = devm_clk_get(dev, "xvclk");
1516 if (IS_ERR(ov4689->xvclk)) {
1517 dev_err(dev, "Failed to get xvclk\n");
1518 return -EINVAL;
1519 }
1520
1521 ov4689->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1522 if (IS_ERR(ov4689->reset_gpio))
1523 dev_warn(dev, "Failed to get reset-gpios\n");
1524
1525 ov4689->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1526 if (IS_ERR(ov4689->pwdn_gpio))
1527 dev_warn(dev, "Failed to get pwdn-gpios\n");
1528
1529 ov4689->pinctrl = devm_pinctrl_get(dev);
1530 if (!IS_ERR(ov4689->pinctrl)) {
1531 ov4689->pins_default =
1532 pinctrl_lookup_state(ov4689->pinctrl,
1533 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1534 if (IS_ERR(ov4689->pins_default))
1535 dev_err(dev, "could not get default pinstate\n");
1536
1537 ov4689->pins_sleep =
1538 pinctrl_lookup_state(ov4689->pinctrl,
1539 OF_CAMERA_PINCTRL_STATE_SLEEP);
1540 if (IS_ERR(ov4689->pins_sleep))
1541 dev_err(dev, "could not get sleep pinstate\n");
1542 } else {
1543 dev_err(dev, "no pinctrl\n");
1544 }
1545
1546 ret = ov4689_configure_regulators(ov4689);
1547 if (ret) {
1548 dev_err(dev, "Failed to get power regulators\n");
1549 return ret;
1550 }
1551
1552 mutex_init(&ov4689->mutex);
1553
1554 sd = &ov4689->subdev;
1555 v4l2_i2c_subdev_init(sd, client, &ov4689_subdev_ops);
1556 ret = ov4689_initialize_controls(ov4689);
1557 if (ret)
1558 goto err_destroy_mutex;
1559
1560 ret = __ov4689_power_on(ov4689);
1561 if (ret)
1562 goto err_free_handler;
1563
1564 ret = ov4689_check_sensor_id(ov4689, client);
1565 if (ret)
1566 goto err_power_off;
1567
1568 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1569 sd->internal_ops = &ov4689_internal_ops;
1570 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1571 V4L2_SUBDEV_FL_HAS_EVENTS;
1572 #endif
1573 #if defined(CONFIG_MEDIA_CONTROLLER)
1574 ov4689->pad.flags = MEDIA_PAD_FL_SOURCE;
1575 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1576 ret = media_entity_pads_init(&sd->entity, 1, &ov4689->pad);
1577 if (ret < 0)
1578 goto err_power_off;
1579 #endif
1580
1581 memset(facing, 0, sizeof(facing));
1582 if (strcmp(ov4689->module_facing, "back") == 0)
1583 facing[0] = 'b';
1584 else
1585 facing[0] = 'f';
1586
1587 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1588 ov4689->module_index, facing,
1589 OV4689_NAME, dev_name(sd->dev));
1590 ret = v4l2_async_register_subdev_sensor_common(sd);
1591 if (ret) {
1592 dev_err(dev, "v4l2 async register subdev failed\n");
1593 goto err_clean_entity;
1594 }
1595
1596 pm_runtime_set_active(dev);
1597 pm_runtime_enable(dev);
1598 pm_runtime_idle(dev);
1599
1600 return 0;
1601
1602 err_clean_entity:
1603 #if defined(CONFIG_MEDIA_CONTROLLER)
1604 media_entity_cleanup(&sd->entity);
1605 #endif
1606 err_power_off:
1607 __ov4689_power_off(ov4689);
1608 err_free_handler:
1609 v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
1610 err_destroy_mutex:
1611 mutex_destroy(&ov4689->mutex);
1612
1613 return ret;
1614 }
1615
ov4689_remove(struct i2c_client * client)1616 static int ov4689_remove(struct i2c_client *client)
1617 {
1618 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1619 struct ov4689 *ov4689 = to_ov4689(sd);
1620
1621 v4l2_async_unregister_subdev(sd);
1622 #if defined(CONFIG_MEDIA_CONTROLLER)
1623 media_entity_cleanup(&sd->entity);
1624 #endif
1625 v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
1626 mutex_destroy(&ov4689->mutex);
1627
1628 pm_runtime_disable(&client->dev);
1629 if (!pm_runtime_status_suspended(&client->dev))
1630 __ov4689_power_off(ov4689);
1631 pm_runtime_set_suspended(&client->dev);
1632
1633 return 0;
1634 }
1635
1636 #if IS_ENABLED(CONFIG_OF)
1637 static const struct of_device_id ov4689_of_match[] = {
1638 { .compatible = "ovti,ov4689" },
1639 {},
1640 };
1641 MODULE_DEVICE_TABLE(of, ov4689_of_match);
1642 #endif
1643
1644 static const struct i2c_device_id ov4689_match_id[] = {
1645 { "ovti,ov4689", 0 },
1646 { },
1647 };
1648
1649 static struct i2c_driver ov4689_i2c_driver = {
1650 .driver = {
1651 .name = OV4689_NAME,
1652 .pm = &ov4689_pm_ops,
1653 .of_match_table = of_match_ptr(ov4689_of_match),
1654 },
1655 .probe = &ov4689_probe,
1656 .remove = &ov4689_remove,
1657 .id_table = ov4689_match_id,
1658 };
1659
sensor_mod_init(void)1660 static int __init sensor_mod_init(void)
1661 {
1662 return i2c_add_driver(&ov4689_i2c_driver);
1663 }
1664
sensor_mod_exit(void)1665 static void __exit sensor_mod_exit(void)
1666 {
1667 i2c_del_driver(&ov4689_i2c_driver);
1668 }
1669
1670 device_initcall_sync(sensor_mod_init);
1671 module_exit(sensor_mod_exit);
1672
1673 MODULE_DESCRIPTION("OmniVision ov4689 sensor driver");
1674 MODULE_LICENSE("GPL v2");
1675