1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov4688 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 fix gain range.
10 * V0.0X01.0X04 add enum_frame_interval function.
11 * V0.0X01.0X05 add hdr config
12 * V0.0X01.0X06 support enum sensor fmt
13 * V0.0X01.0X07 support mirror and flip
14 * V0.0X01.0X08 add quick stream on/off
15 */
16
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sysfs.h>
26 #include <linux/slab.h>
27 #include <linux/version.h>
28 #include <linux/rk-camera-module.h>
29 #include <linux/rk-preisp.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-async.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-subdev.h>
34 #include <linux/pinctrl/consumer.h>
35
36 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08)
37
38 #ifndef V4L2_CID_DIGITAL_GAIN
39 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
40 #endif
41
42 #define OV4688_LANES 4
43 #define OV4688_BITS_PER_SAMPLE 10
44 #define OV4688_LINK_FREQ_300MHZ 300000000LL
45 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
46 #define OV4688_PIXEL_RATE (OV4688_LINK_FREQ_300MHZ * 2 * \
47 OV4688_LANES / OV4688_BITS_PER_SAMPLE)
48 #define OV4688_XVCLK_FREQ 24000000
49
50 #define CHIP_ID 0x4688
51 #define OV4688_REG_CHIP_ID 0x300a
52
53 #define OV4688_REG_CTRL_MODE 0x0100
54 #define OV4688_MODE_SW_STANDBY 0x0
55 #define OV4688_MODE_STREAMING BIT(0)
56
57 #define OV4688_REG_EXPOSURE_L 0x3500
58 #define OV4688_EXPOSURE_MIN 4
59 #define OV4688_EXPOSURE_STEP 1
60 #define OV4688_VTS_MAX 0x7fff
61
62 #define OV4688_REG_GAIN_H 0x3508
63 #define OV4688_REG_GAIN_L 0x3509
64 #define OV4688_REG_DGAIN_H 0x352A
65 #define OV4688_REG_DGAIN_L 0x352B
66 #define OV4688_GAIN_H_MASK 0x07
67 #define OV4688_GAIN_H_SHIFT 8
68 #define OV4688_GAIN_L_MASK 0xff
69 #define OV4688_GAIN_MIN 0x80
70 #define OV4688_GAIN_MAX 0x87f8
71 #define OV4688_GAIN_STEP 1
72 #define OV4688_GAIN_DEFAULT 0x80
73
74
75 #define OV4688_REG_TEST_PATTERN 0x5040
76 #define OV4688_TEST_PATTERN_ENABLE 0x80
77 #define OV4688_TEST_PATTERN_DISABLE 0x0
78
79 #define OV4688_REG_VTS 0x380e
80
81 #define REG_NULL 0xFFFF
82 #define REG_DELAY 0xFFFE
83
84 #define OV4688_FLIP_REG 0x3820
85 #define OV4688_MIRROR_REG 0x3821
86 #define OV4688_ARRAY_BIT_MASK BIT(1)
87 #define OV4688_DIGITAL_BIT_MASK BIT(2)
88
89 #define OV4688_REG_VALUE_08BIT 1
90 #define OV4688_REG_VALUE_16BIT 2
91 #define OV4688_REG_VALUE_24BIT 3
92
93 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
94 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
95 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
96 #define OV4688_NAME "ov4688"
97
98 static const char * const ov4688_supply_names[] = {
99 "avdd", /* Analog power */
100 "dovdd", /* Digital I/O power */
101 "dvdd", /* Digital core power */
102 };
103
104 #define OV4688_NUM_SUPPLIES ARRAY_SIZE(ov4688_supply_names)
105
106 struct regval {
107 u16 addr;
108 u8 val;
109 };
110
111 struct ov4688_mode {
112 u32 bus_fmt;
113 u32 width;
114 u32 height;
115 struct v4l2_fract max_fps;
116 u32 hts_def;
117 u32 vts_def;
118 u32 exp_def;
119 const struct regval *reg_list;
120 u32 hdr_mode;
121 u32 vc[PAD_MAX];
122 };
123
124 struct ov4688 {
125 struct i2c_client *client;
126 struct clk *xvclk;
127 struct gpio_desc *reset_gpio;
128 struct gpio_desc *pwdn_gpio;
129 struct regulator_bulk_data supplies[OV4688_NUM_SUPPLIES];
130
131 struct pinctrl *pinctrl;
132 struct pinctrl_state *pins_default;
133 struct pinctrl_state *pins_sleep;
134
135 struct v4l2_subdev subdev;
136 struct media_pad pad;
137 struct v4l2_ctrl_handler ctrl_handler;
138 struct v4l2_ctrl *exposure;
139 struct v4l2_ctrl *anal_gain;
140 struct v4l2_ctrl *digi_gain;
141 struct v4l2_ctrl *hblank;
142 struct v4l2_ctrl *vblank;
143 struct v4l2_ctrl *h_flip;
144 struct v4l2_ctrl *v_flip;
145 struct v4l2_ctrl *test_pattern;
146 struct mutex mutex;
147 bool streaming;
148 bool power_on;
149 const struct ov4688_mode *cur_mode;
150 u32 module_index;
151 const char *module_facing;
152 const char *module_name;
153 const char *len_name;
154 u8 flip;
155 };
156
157 #define to_ov4688(sd) container_of(sd, struct ov4688, subdev)
158
159 /*
160 * Xclk 24Mhz
161 */
162 static const struct regval ov4688_global_regs[] = {
163 {REG_NULL, 0x00},
164 };
165
166 /*
167 * Xclk 24Mhz
168 * max_framerate 90fps
169 * mipi_datarate per lane 1008Mbps, 4lane
170 */
171 static const struct regval ov4688_linear_2688x1520_30fps_regs[] = {
172 {0x0103, 0x01},
173 {0x3638, 0x00},
174 {0x0300, 0x02},
175 {0x0302, 0x32},
176 {0x0303, 0x00},
177 {0x0304, 0x03},
178 {0x030b, 0x00},
179 {0x030d, 0x1e},
180 {0x030e, 0x04},
181 {0x030f, 0x01},
182 {0x0312, 0x01},
183 {0x031e, 0x00},
184 {0x3000, 0x20},
185 {0x3002, 0x00},
186 {0x3018, 0x72},
187 {0x3020, 0x93},
188 {0x3021, 0x03},
189 {0x3022, 0x01},
190 {0x3031, 0x0a},
191 {0x3305, 0xf1},
192 {0x3307, 0x04},
193 {0x3309, 0x29},
194 {0x3500, 0x01},
195 {0x3501, 0x22},
196 {0x3502, 0xe0},
197 {0x3503, 0x04},
198 {0x3504, 0x00},
199 {0x3505, 0x00},
200 {0x3506, 0x00},
201 {0x3507, 0x00},
202 {0x3508, 0x00},
203 {0x3509, 0x80},
204 {0x350a, 0x00},
205 {0x350b, 0x00},
206 {0x350c, 0x00},
207 {0x350d, 0x00},
208 {0x350e, 0x00},
209 {0x350f, 0x80},
210 {0x3510, 0x00},
211 {0x3511, 0x00},
212 {0x3512, 0x00},
213 {0x3513, 0x00},
214 {0x3514, 0x00},
215 {0x3515, 0x80},
216 {0x3516, 0x00},
217 {0x3517, 0x00},
218 {0x3518, 0x00},
219 {0x3519, 0x00},
220 {0x351a, 0x00},
221 {0x351b, 0x80},
222 {0x351c, 0x00},
223 {0x351d, 0x00},
224 {0x351e, 0x00},
225 {0x351f, 0x00},
226 {0x3520, 0x00},
227 {0x3521, 0x80},
228 {0x3522, 0x08},
229 {0x3524, 0x08},
230 {0x3526, 0x08},
231 {0x3528, 0x08},
232 {0x352a, 0x08},
233 {0x3602, 0x00},
234 {0x3604, 0x02},
235 {0x3605, 0x00},
236 {0x3606, 0x00},
237 {0x3607, 0x00},
238 {0x3609, 0x12},
239 {0x360a, 0x40},
240 {0x360c, 0x08},
241 {0x360f, 0xe5},
242 {0x3608, 0x8f},
243 {0x3611, 0x00},
244 {0x3613, 0xf7},
245 {0x3616, 0x58},
246 {0x3619, 0x99},
247 {0x361b, 0x60},
248 {0x361c, 0x7a},
249 {0x361e, 0x79},
250 {0x361f, 0x02},
251 {0x3632, 0x00},
252 {0x3633, 0x10},
253 {0x3634, 0x10},
254 {0x3635, 0x10},
255 {0x3636, 0x15},
256 {0x3646, 0x86},
257 {0x364a, 0x0b},
258 {0x3700, 0x17},
259 {0x3701, 0x22},
260 {0x3703, 0x10},
261 {0x370a, 0x37},
262 {0x3705, 0x00},
263 {0x3706, 0x63},
264 {0x3709, 0x3c},
265 {0x370b, 0x01},
266 {0x370c, 0x30},
267 {0x3710, 0x24},
268 {0x3711, 0x0c},
269 {0x3716, 0x00},
270 {0x3720, 0x28},
271 {0x3729, 0x7b},
272 {0x372a, 0x84},
273 {0x372b, 0xbd},
274 {0x372c, 0xbc},
275 {0x372e, 0x52},
276 {0x373c, 0x0e},
277 {0x373e, 0x33},
278 {0x3743, 0x10},
279 {0x3744, 0x88},
280 {0x374a, 0x43},
281 {0x374c, 0x00},
282 {0x374e, 0x23},
283 {0x3751, 0x7b},
284 {0x3752, 0x84},
285 {0x3753, 0xbd},
286 {0x3754, 0xbc},
287 {0x3756, 0x52},
288 {0x375c, 0x00},
289 {0x3760, 0x00},
290 {0x3761, 0x00},
291 {0x3762, 0x00},
292 {0x3763, 0x00},
293 {0x3764, 0x00},
294 {0x3767, 0x04},
295 {0x3768, 0x04},
296 {0x3769, 0x08},
297 {0x376a, 0x08},
298 {0x376b, 0x20},
299 {0x376c, 0x00},
300 {0x376d, 0x00},
301 {0x376e, 0x00},
302 {0x3773, 0x00},
303 {0x3774, 0x51},
304 {0x3776, 0xbd},
305 {0x3777, 0xbd},
306 {0x3781, 0x18},
307 {0x3783, 0x25},
308 {0x3800, 0x00},
309 {0x3801, 0x08},
310 {0x3802, 0x00},
311 {0x3803, 0x04},
312 {0x3804, 0x0a},
313 {0x3805, 0x97},
314 {0x3806, 0x05},
315 {0x3807, 0xfb},
316 {0x3808, 0x0a},
317 {0x3809, 0x80},
318 {0x380a, 0x05},
319 {0x380b, 0xf0},
320 {0x380c, 0x0a},
321 {0x380d, 0x18},
322 {0x380e, 0x06},
323 {0x380f, 0x12},
324 {0x3810, 0x00},
325 {0x3811, 0x08},
326 {0x3812, 0x00},
327 {0x3813, 0x04},
328 {0x3814, 0x01},
329 {0x3815, 0x01},
330 {0x3819, 0x01},
331 {0x3820, 0x00},
332 {0x3821, 0x06},
333 {0x3829, 0x00},
334 {0x382a, 0x01},
335 {0x382b, 0x01},
336 {0x382d, 0x7f},
337 {0x3830, 0x04},
338 {0x3836, 0x01},
339 {0x3841, 0x02},
340 {0x3846, 0x08},
341 {0x3847, 0x07},
342 {0x3d85, 0x36},
343 {0x3d8c, 0x71},
344 {0x3d8d, 0xcb},
345 {0x3f0a, 0x00},
346 {0x4000, 0x71},
347 {0x4001, 0x40},
348 {0x4002, 0x04},
349 {0x4003, 0x14},
350 {0x400e, 0x00},
351 {0x4011, 0x00},
352 {0x401a, 0x00},
353 {0x401b, 0x00},
354 {0x401c, 0x00},
355 {0x401d, 0x00},
356 {0x401f, 0x00},
357 {0x4020, 0x00},
358 {0x4021, 0x10},
359 {0x4022, 0x07},
360 {0x4023, 0xcf},
361 {0x4024, 0x09},
362 {0x4025, 0x60},
363 {0x4026, 0x09},
364 {0x4027, 0x6f},
365 {0x4028, 0x00},
366 {0x4029, 0x02},
367 {0x402a, 0x06},
368 {0x402b, 0x04},
369 {0x402c, 0x02},
370 {0x402d, 0x02},
371 {0x402e, 0x0e},
372 {0x402f, 0x04},
373 {0x4302, 0xff},
374 {0x4303, 0xff},
375 {0x4304, 0x00},
376 {0x4305, 0x00},
377 {0x4306, 0x00},
378 {0x4308, 0x02},
379 {0x4500, 0x6c},
380 {0x4501, 0xc4},
381 {0x4502, 0x40},
382 {0x4503, 0x02},
383 {0x4601, 0xA7},
384 {0x4800, 0x04},
385 {0x4813, 0x08},
386 {0x481f, 0x40},
387 {0x4829, 0x78},
388 {0x4837, 0x10},
389 {0x4b00, 0x2a},
390 {0x4b0d, 0x00},
391 {0x4d00, 0x04},
392 {0x4d01, 0x42},
393 {0x4d02, 0xd1},
394 {0x4d03, 0x93},
395 {0x4d04, 0xf5},
396 {0x4d05, 0xc1},
397 {0x5000, 0xf3},
398 {0x5001, 0x11},
399 {0x5004, 0x00},
400 {0x500a, 0x00},
401 {0x500b, 0x00},
402 {0x5032, 0x00},
403 {0x5040, 0x00},
404 {0x5050, 0x0c},
405 {0x5500, 0x00},
406 {0x5501, 0x10},
407 {0x5502, 0x01},
408 {0x5503, 0x0f},
409 {0x8000, 0x00},
410 {0x8001, 0x00},
411 {0x8002, 0x00},
412 {0x8003, 0x00},
413 {0x8004, 0x00},
414 {0x8005, 0x00},
415 {0x8006, 0x00},
416 {0x8007, 0x00},
417 {0x8008, 0x00},
418 {0x3638, 0x00},
419 {0x3105, 0x31},
420 {0x301a, 0xf9},
421 {0x3508, 0x07},
422 {0x484b, 0x05},
423 {0x4805, 0x03},
424 {0x3601, 0x01},
425 {0x3745, 0xc0},
426 {0x3798, 0x1b},
427 {REG_NULL, 0x00},
428 };
429
430 static const struct regval ov4688_linear_1920x1080_60fps_regs[] = {
431 {0x0103, 0x01},
432 {0x3638, 0x00},
433 {0x0300, 0x02},
434 {0x0302, 0x32},
435 {0x0303, 0x00},
436 {0x0304, 0x03},
437 {0x030b, 0x00},
438 {0x030d, 0x1e},
439 {0x030e, 0x04},
440 {0x030f, 0x01},
441 {0x0312, 0x01},
442 {0x031e, 0x00},
443 {0x3000, 0x20},
444 {0x3002, 0x00},
445 {0x3018, 0x72},
446 {0x3020, 0x93},
447 {0x3021, 0x03},
448 {0x3022, 0x01},
449 {0x3031, 0x0a},
450 {0x3305, 0xf1},
451 {0x3307, 0x04},
452 {0x3309, 0x29},
453 {0x3500, 0x00},
454 {0x3501, 0x48},
455 {0x3502, 0x00},
456 {0x3503, 0x04},
457 {0x3504, 0x00},
458 {0x3505, 0x00},
459 {0x3506, 0x00},
460 {0x3507, 0x00},
461 {0x3508, 0x00},
462 {0x3509, 0x80},
463 {0x350a, 0x00},
464 {0x350b, 0x00},
465 {0x350c, 0x00},
466 {0x350d, 0x00},
467 {0x350e, 0x00},
468 {0x350f, 0x80},
469 {0x3510, 0x00},
470 {0x3511, 0x00},
471 {0x3512, 0x00},
472 {0x3513, 0x00},
473 {0x3514, 0x00},
474 {0x3515, 0x80},
475 {0x3516, 0x00},
476 {0x3517, 0x00},
477 {0x3518, 0x00},
478 {0x3519, 0x00},
479 {0x351a, 0x00},
480 {0x351b, 0x80},
481 {0x351c, 0x00},
482 {0x351d, 0x00},
483 {0x351e, 0x00},
484 {0x351f, 0x00},
485 {0x3520, 0x00},
486 {0x3521, 0x80},
487 {0x3522, 0x08},
488 {0x3524, 0x08},
489 {0x3526, 0x08},
490 {0x3528, 0x08},
491 {0x352a, 0x08},
492 {0x3602, 0x00},
493 {0x3604, 0x02},
494 {0x3605, 0x00},
495 {0x3606, 0x00},
496 {0x3607, 0x00},
497 {0x3609, 0x12},
498 {0x360a, 0x40},
499 {0x360c, 0x08},
500 {0x360f, 0xe5},
501 {0x3608, 0x8f},
502 {0x3611, 0x00},
503 {0x3613, 0xf7},
504 {0x3616, 0x58},
505 {0x3619, 0x99},
506 {0x361b, 0x60},
507 {0x361c, 0x7a},
508 {0x361e, 0x79},
509 {0x361f, 0x02},
510 {0x3632, 0x00},
511 {0x3633, 0x10},
512 {0x3634, 0x10},
513 {0x3635, 0x10},
514 {0x3636, 0x15},
515 {0x3646, 0x86},
516 {0x364a, 0x0b},
517 {0x3700, 0x17},
518 {0x3701, 0x22},
519 {0x3703, 0x10},
520 {0x370a, 0x37},
521 {0x3705, 0x00},
522 {0x3706, 0x63},
523 {0x3709, 0x3c},
524 {0x370b, 0x01},
525 {0x370c, 0x30},
526 {0x3710, 0x24},
527 {0x3711, 0x0c},
528 {0x3716, 0x00},
529 {0x3720, 0x28},
530 {0x3729, 0x7b},
531 {0x372a, 0x84},
532 {0x372b, 0xbd},
533 {0x372c, 0xbc},
534 {0x372e, 0x52},
535 {0x373c, 0x0e},
536 {0x373e, 0x33},
537 {0x3743, 0x10},
538 {0x3744, 0x88},
539 {0x374a, 0x43},
540 {0x374c, 0x00},
541 {0x374e, 0x23},
542 {0x3751, 0x7b},
543 {0x3752, 0x84},
544 {0x3753, 0xbd},
545 {0x3754, 0xbc},
546 {0x3756, 0x52},
547 {0x375c, 0x00},
548 {0x3760, 0x00},
549 {0x3761, 0x00},
550 {0x3762, 0x00},
551 {0x3763, 0x00},
552 {0x3764, 0x00},
553 {0x3767, 0x04},
554 {0x3768, 0x04},
555 {0x3769, 0x08},
556 {0x376a, 0x08},
557 {0x376b, 0x20},
558 {0x376c, 0x00},
559 {0x376d, 0x00},
560 {0x376e, 0x00},
561 {0x3773, 0x00},
562 {0x3774, 0x51},
563 {0x3776, 0xbd},
564 {0x3777, 0xbd},
565 {0x3781, 0x18},
566 {0x3783, 0x25},
567 {0x3800, 0x01},
568 {0x3801, 0x88},
569 {0x3802, 0x00},
570 {0x3803, 0xe0},
571 {0x3804, 0x09},
572 {0x3805, 0x17},
573 {0x3806, 0x05},
574 {0x3807, 0x1f},
575 {0x3808, 0x07},
576 {0x3809, 0x80},
577 {0x380a, 0x04},
578 {0x380b, 0x38},
579 {0x380c, 0x06},
580 {0x380d, 0xb8},
581 {0x380e, 0x04},
582 {0x380f, 0x8a},
583 {0x3810, 0x00},
584 {0x3811, 0x08},
585 {0x3812, 0x00},
586 {0x3813, 0x04},
587 {0x3814, 0x01},
588 {0x3815, 0x01},
589 {0x3819, 0x01},
590 {0x3820, 0x00},
591 {0x3821, 0x06},
592 {0x3829, 0x00},
593 {0x382a, 0x01},
594 {0x382b, 0x01},
595 {0x382d, 0x7f},
596 {0x3830, 0x04},
597 {0x3836, 0x01},
598 {0x3841, 0x02},
599 {0x3846, 0x08},
600 {0x3847, 0x07},
601 {0x3d85, 0x36},
602 {0x3d8c, 0x71},
603 {0x3d8d, 0xcb},
604 {0x3f0a, 0x00},
605 {0x4000, 0x71},
606 {0x4001, 0x40},
607 {0x4002, 0x04},
608 {0x4003, 0x14},
609 {0x400e, 0x00},
610 {0x4011, 0x00},
611 {0x401a, 0x00},
612 {0x401b, 0x00},
613 {0x401c, 0x00},
614 {0x401d, 0x00},
615 {0x401f, 0x00},
616 {0x4020, 0x00},
617 {0x4021, 0x10},
618 {0x4022, 0x06},
619 {0x4023, 0x13},
620 {0x4024, 0x07},
621 {0x4025, 0x40},
622 {0x4026, 0x07},
623 {0x4027, 0x50},
624 {0x4028, 0x00},
625 {0x4029, 0x02},
626 {0x402a, 0x06},
627 {0x402b, 0x04},
628 {0x402c, 0x02},
629 {0x402d, 0x02},
630 {0x402e, 0x0e},
631 {0x402f, 0x04},
632 {0x4302, 0xff},
633 {0x4303, 0xff},
634 {0x4304, 0x00},
635 {0x4305, 0x00},
636 {0x4306, 0x00},
637 {0x4308, 0x02},
638 {0x4500, 0x6c},
639 {0x4501, 0xc4},
640 {0x4502, 0x40},
641 {0x4503, 0x02},
642 {0x4601, 0x77},
643 {0x4800, 0x04},
644 {0x4813, 0x08},
645 {0x481f, 0x40},
646 {0x4829, 0x78},
647 {0x4837, 0x10},
648 {0x4b00, 0x2a},
649 {0x4b0d, 0x00},
650 {0x4d00, 0x04},
651 {0x4d01, 0x42},
652 {0x4d02, 0xd1},
653 {0x4d03, 0x93},
654 {0x4d04, 0xf5},
655 {0x4d05, 0xc1},
656 {0x5000, 0xf3},
657 {0x5001, 0x11},
658 {0x5004, 0x00},
659 {0x500a, 0x00},
660 {0x500b, 0x00},
661 {0x5032, 0x00},
662 {0x5040, 0x00},
663 {0x5050, 0x0c},
664 {0x5500, 0x00},
665 {0x5501, 0x10},
666 {0x5502, 0x01},
667 {0x5503, 0x0f},
668 {0x8000, 0x00},
669 {0x8001, 0x00},
670 {0x8002, 0x00},
671 {0x8003, 0x00},
672 {0x8004, 0x00},
673 {0x8005, 0x00},
674 {0x8006, 0x00},
675 {0x8007, 0x00},
676 {0x8008, 0x00},
677 {0x3638, 0x00},
678 {0x3105, 0x31},
679 {0x301a, 0xf9},
680 {0x3508, 0x07},
681 {0x484b, 0x05},
682 {0x4805, 0x03},
683 {0x3601, 0x01},
684 {0x3745, 0xc0},
685 {0x3798, 0x1b},
686 {REG_NULL, 0x00},
687 };
688
689 static const struct regval ov4688_linear_global_regs[] = {
690 {0x3105, 0x11},
691 {0x301a, 0xf1},
692 {0x4805, 0x00},
693 {0x301a, 0xf0},
694 {0x3208, 0x00},
695 {0x302a, 0x00},
696 {0x302a, 0x00},
697 {0x302a, 0x00},
698 {0x302a, 0x00},
699 {0x302a, 0x00},
700 {0x3601, 0x00},
701 {0x3638, 0x00},
702 {0x3208, 0x10},
703 {0x3208, 0xa0},
704 {REG_NULL, 0x00},
705 };
706
707 static const struct ov4688_mode supported_modes[] = {
708 {
709 .width = 2688,
710 .height = 1520,
711 .max_fps = {
712 .numerator = 10000,
713 .denominator = 300000,
714 },
715 .exp_def = 0x0600,
716 .hts_def = 0x0a18,
717 .vts_def = 0x0612,
718 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
719 .reg_list = ov4688_linear_2688x1520_30fps_regs,
720 .hdr_mode = NO_HDR,
721 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
722 }, {
723 .width = 1920,
724 .height = 1080,
725 .max_fps = {
726 .numerator = 10000,
727 .denominator = 600000,
728 },
729 .exp_def = 0x0200,
730 .hts_def = 0x06B8 * 2,
731 .vts_def = 0x048a,
732 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
733 .reg_list = ov4688_linear_1920x1080_60fps_regs,
734 .hdr_mode = NO_HDR,
735 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
736 },
737 };
738
739 static const s64 link_freq_menu_items[] = {
740 OV4688_LINK_FREQ_300MHZ
741 };
742
743 static const char * const ov4688_test_pattern_menu[] = {
744 "Disabled",
745 "Vertical Color Bar Type 1",
746 "Vertical Color Bar Type 2",
747 "Vertical Color Bar Type 3",
748 "Vertical Color Bar Type 4"
749 };
750
751 /* Write registers up to 4 at a time */
ov4688_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)752 static int ov4688_write_reg(struct i2c_client *client, u16 reg,
753 u32 len, u32 val)
754 {
755 u32 buf_i, val_i;
756 u8 buf[6];
757 u8 *val_p;
758 __be32 val_be;
759
760 if (len > 4)
761 return -EINVAL;
762
763 buf[0] = reg >> 8;
764 buf[1] = reg & 0xff;
765
766 val_be = cpu_to_be32(val);
767 val_p = (u8 *)&val_be;
768 buf_i = 2;
769 val_i = 4 - len;
770
771 while (val_i < 4)
772 buf[buf_i++] = val_p[val_i++];
773
774 if (i2c_master_send(client, buf, len + 2) != len + 2)
775 return -EIO;
776
777 return 0;
778 }
779
ov4688_write_array(struct i2c_client * client,const struct regval * regs)780 static int ov4688_write_array(struct i2c_client *client,
781 const struct regval *regs)
782 {
783 u32 i;
784 int ret = 0;
785
786 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
787 if (regs[i].addr == REG_DELAY) {
788 usleep_range(regs[i].val * 1000, regs[i].val * 1000 * 2);
789 continue;
790 }
791 ret = ov4688_write_reg(client, regs[i].addr,
792 OV4688_REG_VALUE_08BIT, regs[i].val);
793 }
794
795 return ret;
796 }
797
798 /* Read registers up to 4 at a time */
ov4688_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)799 static int ov4688_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
800 u32 *val)
801 {
802 struct i2c_msg msgs[2];
803 u8 *data_be_p;
804 __be32 data_be = 0;
805 __be16 reg_addr_be = cpu_to_be16(reg);
806 int ret;
807
808 if (len > 4 || !len)
809 return -EINVAL;
810
811 data_be_p = (u8 *)&data_be;
812 /* Write register address */
813 msgs[0].addr = client->addr;
814 msgs[0].flags = 0;
815 msgs[0].len = 2;
816 msgs[0].buf = (u8 *)®_addr_be;
817
818 /* Read data from register */
819 msgs[1].addr = client->addr;
820 msgs[1].flags = I2C_M_RD;
821 msgs[1].len = len;
822 msgs[1].buf = &data_be_p[4 - len];
823
824 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
825 if (ret != ARRAY_SIZE(msgs))
826 return -EIO;
827
828 *val = be32_to_cpu(data_be);
829
830 return 0;
831 }
832
ov4688_get_reso_dist(const struct ov4688_mode * mode,struct v4l2_mbus_framefmt * framefmt)833 static int ov4688_get_reso_dist(const struct ov4688_mode *mode,
834 struct v4l2_mbus_framefmt *framefmt)
835 {
836 return abs(mode->width - framefmt->width) +
837 abs(mode->height - framefmt->height);
838 }
839
840 static const struct ov4688_mode *
ov4688_find_best_fit(struct v4l2_subdev_format * fmt)841 ov4688_find_best_fit(struct v4l2_subdev_format *fmt)
842 {
843 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
844 int dist;
845 int cur_best_fit = 0;
846 int cur_best_fit_dist = -1;
847 unsigned int i;
848
849 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
850 dist = ov4688_get_reso_dist(&supported_modes[i], framefmt);
851 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
852 cur_best_fit_dist = dist;
853 cur_best_fit = i;
854 }
855 }
856
857 return &supported_modes[cur_best_fit];
858 }
859
ov4688_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)860 static int ov4688_set_fmt(struct v4l2_subdev *sd,
861 struct v4l2_subdev_pad_config *cfg,
862 struct v4l2_subdev_format *fmt)
863 {
864 struct ov4688 *ov4688 = to_ov4688(sd);
865 const struct ov4688_mode *mode;
866 s64 h_blank, vblank_def;
867
868 mutex_lock(&ov4688->mutex);
869
870 mode = ov4688_find_best_fit(fmt);
871 fmt->format.code = mode->bus_fmt;
872 fmt->format.width = mode->width;
873 fmt->format.height = mode->height;
874 fmt->format.field = V4L2_FIELD_NONE;
875 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
876 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
877 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
878 #else
879 mutex_unlock(&ov4688->mutex);
880 return -ENOTTY;
881 #endif
882 } else {
883 ov4688->cur_mode = mode;
884 h_blank = mode->hts_def - mode->width;
885 __v4l2_ctrl_modify_range(ov4688->hblank, h_blank,
886 h_blank, 1, h_blank);
887 vblank_def = mode->vts_def - mode->height;
888 __v4l2_ctrl_modify_range(ov4688->vblank, vblank_def,
889 OV4688_VTS_MAX - mode->height,
890 1, vblank_def);
891 }
892
893 mutex_unlock(&ov4688->mutex);
894
895 return 0;
896 }
897
ov4688_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)898 static int ov4688_get_fmt(struct v4l2_subdev *sd,
899 struct v4l2_subdev_pad_config *cfg,
900 struct v4l2_subdev_format *fmt)
901 {
902 struct ov4688 *ov4688 = to_ov4688(sd);
903 const struct ov4688_mode *mode = ov4688->cur_mode;
904
905 mutex_lock(&ov4688->mutex);
906 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
907 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
908 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
909 #else
910 mutex_unlock(&ov4688->mutex);
911 return -ENOTTY;
912 #endif
913 } else {
914 fmt->format.width = mode->width;
915 fmt->format.height = mode->height;
916 fmt->format.code = mode->bus_fmt;
917 fmt->format.field = V4L2_FIELD_NONE;
918 /* format info: width/height/data type/virctual channel */
919 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
920 fmt->reserved[0] = mode->vc[fmt->pad];
921 else
922 fmt->reserved[0] = mode->vc[PAD0];
923 }
924 mutex_unlock(&ov4688->mutex);
925
926 return 0;
927 }
928
ov4688_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)929 static int ov4688_enum_mbus_code(struct v4l2_subdev *sd,
930 struct v4l2_subdev_pad_config *cfg,
931 struct v4l2_subdev_mbus_code_enum *code)
932 {
933 struct ov4688 *ov4688 = to_ov4688(sd);
934
935 if (code->index != 0)
936 return -EINVAL;
937 code->code = ov4688->cur_mode->bus_fmt;
938
939 return 0;
940 }
941
ov4688_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)942 static int ov4688_enum_frame_sizes(struct v4l2_subdev *sd,
943 struct v4l2_subdev_pad_config *cfg,
944 struct v4l2_subdev_frame_size_enum *fse)
945 {
946 if (fse->index >= ARRAY_SIZE(supported_modes))
947 return -EINVAL;
948
949 if (fse->code != supported_modes[0].bus_fmt)
950 return -EINVAL;
951
952 fse->min_width = supported_modes[fse->index].width;
953 fse->max_width = supported_modes[fse->index].width;
954 fse->max_height = supported_modes[fse->index].height;
955 fse->min_height = supported_modes[fse->index].height;
956
957 return 0;
958 }
959
ov4688_enable_test_pattern(struct ov4688 * ov4688,u32 pattern)960 static int ov4688_enable_test_pattern(struct ov4688 *ov4688, u32 pattern)
961 {
962 u32 val;
963
964 if (pattern)
965 val = (pattern - 1) | OV4688_TEST_PATTERN_ENABLE;
966 else
967 val = OV4688_TEST_PATTERN_DISABLE;
968
969 return ov4688_write_reg(ov4688->client, OV4688_REG_TEST_PATTERN,
970 OV4688_REG_VALUE_08BIT, val);
971 }
972
ov4688_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)973 static int ov4688_g_frame_interval(struct v4l2_subdev *sd,
974 struct v4l2_subdev_frame_interval *fi)
975 {
976 struct ov4688 *ov4688 = to_ov4688(sd);
977 const struct ov4688_mode *mode = ov4688->cur_mode;
978
979 fi->interval = mode->max_fps;
980
981 return 0;
982 }
983
ov4688_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)984 static int ov4688_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
985 struct v4l2_mbus_config *config)
986 {
987 struct ov4688 *ov4688 = to_ov4688(sd);
988 const struct ov4688_mode *mode = ov4688->cur_mode;
989 u32 val = 1 << (OV4688_LANES - 1) |
990 V4L2_MBUS_CSI2_CHANNEL_0 |
991 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
992
993 if (mode->hdr_mode != NO_HDR)
994 val |= V4L2_MBUS_CSI2_CHANNEL_1;
995 if (mode->hdr_mode == HDR_X3)
996 val |= V4L2_MBUS_CSI2_CHANNEL_2;
997
998 config->type = V4L2_MBUS_CSI2_DPHY;
999 config->flags = val;
1000
1001 return 0;
1002 }
1003
ov4688_get_module_inf(struct ov4688 * ov4688,struct rkmodule_inf * inf)1004 static void ov4688_get_module_inf(struct ov4688 *ov4688,
1005 struct rkmodule_inf *inf)
1006 {
1007 memset(inf, 0, sizeof(*inf));
1008 strlcpy(inf->base.sensor, OV4688_NAME, sizeof(inf->base.sensor));
1009 strlcpy(inf->base.module, ov4688->module_name,
1010 sizeof(inf->base.module));
1011 strlcpy(inf->base.lens, ov4688->len_name, sizeof(inf->base.lens));
1012 }
1013
ov4688_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1014 static long ov4688_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1015 {
1016 struct ov4688 *ov4688 = to_ov4688(sd);
1017 struct rkmodule_hdr_cfg *hdr;
1018 u32 i, h, w;
1019 long ret = 0;
1020 u32 stream = 0;
1021
1022 switch (cmd) {
1023 case RKMODULE_GET_MODULE_INFO:
1024 ov4688_get_module_inf(ov4688, (struct rkmodule_inf *)arg);
1025 break;
1026 case RKMODULE_GET_HDR_CFG:
1027 hdr = (struct rkmodule_hdr_cfg *)arg;
1028 hdr->esp.mode = HDR_NORMAL_VC;
1029 hdr->hdr_mode = ov4688->cur_mode->hdr_mode;
1030 break;
1031 case RKMODULE_SET_HDR_CFG:
1032 hdr = (struct rkmodule_hdr_cfg *)arg;
1033 w = ov4688->cur_mode->width;
1034 h = ov4688->cur_mode->height;
1035 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1036 if (w == supported_modes[i].width &&
1037 h == supported_modes[i].height &&
1038 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1039 ov4688->cur_mode = &supported_modes[i];
1040 break;
1041 }
1042 }
1043 if (i == ARRAY_SIZE(supported_modes)) {
1044 dev_err(&ov4688->client->dev,
1045 "not find hdr mode:%d %dx%d config\n",
1046 hdr->hdr_mode, w, h);
1047 ret = -EINVAL;
1048 } else {
1049 w = ov4688->cur_mode->hts_def - ov4688->cur_mode->width;
1050 h = ov4688->cur_mode->vts_def - ov4688->cur_mode->height;
1051 __v4l2_ctrl_modify_range(ov4688->hblank, w, w, 1, w);
1052 __v4l2_ctrl_modify_range(ov4688->vblank, h,
1053 OV4688_VTS_MAX - ov4688->cur_mode->height, 1, h);
1054 }
1055 break;
1056 case RKMODULE_SET_QUICK_STREAM:
1057 stream = *((u32 *)arg);
1058 if (stream)
1059 ret = ov4688_write_reg(ov4688->client, OV4688_REG_CTRL_MODE,
1060 OV4688_REG_VALUE_08BIT, OV4688_MODE_STREAMING);
1061 else
1062 ret = ov4688_write_reg(ov4688->client, OV4688_REG_CTRL_MODE,
1063 OV4688_REG_VALUE_08BIT, OV4688_MODE_SW_STANDBY);
1064 break;
1065 case PREISP_CMD_SET_HDRAE_EXP:
1066 break;
1067 default:
1068 ret = -ENOIOCTLCMD;
1069 break;
1070 }
1071
1072 return ret;
1073 }
1074
1075 #ifdef CONFIG_COMPAT
ov4688_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1076 static long ov4688_compat_ioctl32(struct v4l2_subdev *sd,
1077 unsigned int cmd, unsigned long arg)
1078 {
1079 void __user *up = compat_ptr(arg);
1080 struct rkmodule_inf *inf;
1081 struct rkmodule_awb_cfg *cfg;
1082 struct rkmodule_hdr_cfg *hdr;
1083 struct preisp_hdrae_exp_s *hdrae;
1084 long ret;
1085 u32 stream = 0;
1086
1087 switch (cmd) {
1088 case RKMODULE_GET_MODULE_INFO:
1089 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1090 if (!inf) {
1091 ret = -ENOMEM;
1092 return ret;
1093 }
1094
1095 ret = ov4688_ioctl(sd, cmd, inf);
1096 if (!ret) {
1097 ret = copy_to_user(up, inf, sizeof(*inf));
1098 if (ret)
1099 ret = -EFAULT;
1100 }
1101 kfree(inf);
1102 break;
1103 case RKMODULE_AWB_CFG:
1104 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1105 if (!cfg) {
1106 ret = -ENOMEM;
1107 return ret;
1108 }
1109
1110 ret = copy_from_user(cfg, up, sizeof(*cfg));
1111 if (ret) {
1112 kfree(cfg);
1113 return -EFAULT;
1114 }
1115 ret = ov4688_ioctl(sd, cmd, cfg);
1116 kfree(cfg);
1117 break;
1118 case RKMODULE_GET_HDR_CFG:
1119 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1120 if (!hdr) {
1121 ret = -ENOMEM;
1122 return ret;
1123 }
1124
1125 ret = ov4688_ioctl(sd, cmd, hdr);
1126 if (!ret) {
1127 ret = copy_to_user(up, hdr, sizeof(*hdr));
1128 if (ret)
1129 ret = -EFAULT;
1130 }
1131 kfree(hdr);
1132 break;
1133 case RKMODULE_SET_HDR_CFG:
1134 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1135 if (!hdr) {
1136 ret = -ENOMEM;
1137 return ret;
1138 }
1139
1140 ret = copy_from_user(hdr, up, sizeof(*hdr));
1141 if (ret) {
1142 kfree(hdr);
1143 return -EFAULT;
1144 }
1145 ret = ov4688_ioctl(sd, cmd, hdr);
1146 kfree(hdr);
1147 break;
1148 case RKMODULE_SET_QUICK_STREAM:
1149 ret = copy_from_user(&stream, up, sizeof(u32));
1150 if (ret)
1151 return -EFAULT;
1152 ret = ov4688_ioctl(sd, cmd, &stream);
1153 break;
1154 case PREISP_CMD_SET_HDRAE_EXP:
1155 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1156 if (!hdrae) {
1157 ret = -ENOMEM;
1158 return ret;
1159 }
1160
1161 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1162 if (ret) {
1163 kfree(hdrae);
1164 return -EFAULT;
1165 }
1166 ret = ov4688_ioctl(sd, cmd, hdrae);
1167 kfree(hdrae);
1168 break;
1169 default:
1170 ret = -ENOIOCTLCMD;
1171 break;
1172 }
1173
1174 return ret;
1175 }
1176 #endif
1177
__ov4688_start_stream(struct ov4688 * ov4688)1178 static int __ov4688_start_stream(struct ov4688 *ov4688)
1179 {
1180 int ret;
1181
1182 ret = ov4688_write_array(ov4688->client, ov4688->cur_mode->reg_list);
1183 if (ret)
1184 return ret;
1185
1186 /* In case these controls are set before streaming */
1187 mutex_unlock(&ov4688->mutex);
1188 ret = v4l2_ctrl_handler_setup(&ov4688->ctrl_handler);
1189 mutex_lock(&ov4688->mutex);
1190 if (ret)
1191 return ret;
1192
1193 ret |= ov4688_write_reg(ov4688->client, OV4688_REG_CTRL_MODE,
1194 OV4688_REG_VALUE_08BIT, OV4688_MODE_STREAMING);
1195 usleep_range(1000 * 10, 1000 * 11);
1196 ret |= ov4688_write_array(ov4688->client, ov4688_linear_global_regs);
1197
1198 return ret;
1199 }
1200
__ov4688_stop_stream(struct ov4688 * ov4688)1201 static int __ov4688_stop_stream(struct ov4688 *ov4688)
1202 {
1203 return ov4688_write_reg(ov4688->client, OV4688_REG_CTRL_MODE,
1204 OV4688_REG_VALUE_08BIT, OV4688_MODE_SW_STANDBY);
1205 }
1206
ov4688_s_stream(struct v4l2_subdev * sd,int on)1207 static int ov4688_s_stream(struct v4l2_subdev *sd, int on)
1208 {
1209 struct ov4688 *ov4688 = to_ov4688(sd);
1210 struct i2c_client *client = ov4688->client;
1211 int ret = 0;
1212
1213 mutex_lock(&ov4688->mutex);
1214 on = !!on;
1215 if (on == ov4688->streaming)
1216 goto unlock_and_return;
1217
1218 if (on) {
1219 ret = pm_runtime_get_sync(&client->dev);
1220 if (ret < 0) {
1221 pm_runtime_put_noidle(&client->dev);
1222 goto unlock_and_return;
1223 }
1224
1225 ret = __ov4688_start_stream(ov4688);
1226 if (ret) {
1227 v4l2_err(sd, "start stream failed while write regs\n");
1228 pm_runtime_put(&client->dev);
1229 goto unlock_and_return;
1230 }
1231 } else {
1232 __ov4688_stop_stream(ov4688);
1233 pm_runtime_put(&client->dev);
1234 }
1235
1236 ov4688->streaming = on;
1237
1238 unlock_and_return:
1239 mutex_unlock(&ov4688->mutex);
1240
1241 return ret;
1242 }
1243
ov4688_s_power(struct v4l2_subdev * sd,int on)1244 static int ov4688_s_power(struct v4l2_subdev *sd, int on)
1245 {
1246 struct ov4688 *ov4688 = to_ov4688(sd);
1247 struct i2c_client *client = ov4688->client;
1248 int ret = 0;
1249
1250 mutex_lock(&ov4688->mutex);
1251
1252 /* If the power state is not modified - no work to do. */
1253 if (ov4688->power_on == !!on)
1254 goto unlock_and_return;
1255
1256 if (on) {
1257 ret = pm_runtime_get_sync(&client->dev);
1258 if (ret < 0) {
1259 pm_runtime_put_noidle(&client->dev);
1260 goto unlock_and_return;
1261 }
1262
1263 ret = ov4688_write_array(ov4688->client, ov4688_global_regs);
1264 if (ret) {
1265 v4l2_err(sd, "could not set init registers\n");
1266 pm_runtime_put_noidle(&client->dev);
1267 goto unlock_and_return;
1268 }
1269
1270 ov4688->power_on = true;
1271 } else {
1272 pm_runtime_put(&client->dev);
1273 ov4688->power_on = false;
1274 }
1275
1276 unlock_and_return:
1277 mutex_unlock(&ov4688->mutex);
1278
1279 return ret;
1280 }
1281
1282 /* Calculate the delay in us by clock rate and clock cycles */
ov4688_cal_delay(u32 cycles)1283 static inline u32 ov4688_cal_delay(u32 cycles)
1284 {
1285 return DIV_ROUND_UP(cycles, OV4688_XVCLK_FREQ / 1000 / 1000);
1286 }
1287
__ov4688_power_on(struct ov4688 * ov4688)1288 static int __ov4688_power_on(struct ov4688 *ov4688)
1289 {
1290 int ret;
1291 u32 delay_us;
1292 struct device *dev = &ov4688->client->dev;
1293
1294 if (!IS_ERR_OR_NULL(ov4688->pins_default)) {
1295 ret = pinctrl_select_state(ov4688->pinctrl,
1296 ov4688->pins_default);
1297 if (ret < 0)
1298 dev_err(dev, "could not set pins\n");
1299 }
1300 ret = clk_set_rate(ov4688->xvclk, OV4688_XVCLK_FREQ);
1301 if (ret < 0)
1302 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1303 if (clk_get_rate(ov4688->xvclk) != OV4688_XVCLK_FREQ)
1304 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1305 ret = clk_prepare_enable(ov4688->xvclk);
1306 if (ret < 0) {
1307 dev_err(dev, "Failed to enable xvclk\n");
1308 return ret;
1309 }
1310 if (!IS_ERR(ov4688->reset_gpio))
1311 gpiod_set_value_cansleep(ov4688->reset_gpio, 1);
1312
1313 ret = regulator_bulk_enable(OV4688_NUM_SUPPLIES, ov4688->supplies);
1314 if (ret < 0) {
1315 dev_err(dev, "Failed to enable regulators\n");
1316 goto disable_clk;
1317 }
1318
1319 usleep_range(500, 1000);
1320 if (!IS_ERR(ov4688->reset_gpio))
1321 gpiod_set_value_cansleep(ov4688->reset_gpio, 0);
1322
1323 usleep_range(500, 1000);
1324 if (!IS_ERR(ov4688->pwdn_gpio))
1325 gpiod_set_value_cansleep(ov4688->pwdn_gpio, 1);
1326
1327 usleep_range(1000 * 10, 1000 * 11);
1328 /* 8192 cycles prior to first SCCB transaction */
1329 delay_us = ov4688_cal_delay(8192);
1330 usleep_range(delay_us, delay_us * 2);
1331
1332 return 0;
1333
1334 disable_clk:
1335 clk_disable_unprepare(ov4688->xvclk);
1336
1337 return ret;
1338 }
1339
__ov4688_power_off(struct ov4688 * ov4688)1340 static void __ov4688_power_off(struct ov4688 *ov4688)
1341 {
1342 int ret;
1343 struct device *dev = &ov4688->client->dev;
1344
1345 if (!IS_ERR(ov4688->pwdn_gpio))
1346 gpiod_set_value_cansleep(ov4688->pwdn_gpio, 0);
1347 clk_disable_unprepare(ov4688->xvclk);
1348 if (!IS_ERR(ov4688->reset_gpio))
1349 gpiod_set_value_cansleep(ov4688->reset_gpio, 0);
1350 if (!IS_ERR_OR_NULL(ov4688->pins_sleep)) {
1351 ret = pinctrl_select_state(ov4688->pinctrl,
1352 ov4688->pins_sleep);
1353 if (ret < 0)
1354 dev_dbg(dev, "could not set pins\n");
1355 }
1356 regulator_bulk_disable(OV4688_NUM_SUPPLIES, ov4688->supplies);
1357 }
1358
ov4688_runtime_resume(struct device * dev)1359 static int ov4688_runtime_resume(struct device *dev)
1360 {
1361 struct i2c_client *client = to_i2c_client(dev);
1362 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1363 struct ov4688 *ov4688 = to_ov4688(sd);
1364
1365 return __ov4688_power_on(ov4688);
1366 }
1367
ov4688_runtime_suspend(struct device * dev)1368 static int ov4688_runtime_suspend(struct device *dev)
1369 {
1370 struct i2c_client *client = to_i2c_client(dev);
1371 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1372 struct ov4688 *ov4688 = to_ov4688(sd);
1373
1374 __ov4688_power_off(ov4688);
1375
1376 return 0;
1377 }
1378
1379 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov4688_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1380 static int ov4688_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1381 {
1382 struct ov4688 *ov4688 = to_ov4688(sd);
1383 struct v4l2_mbus_framefmt *try_fmt =
1384 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1385 const struct ov4688_mode *def_mode = &supported_modes[0];
1386
1387 mutex_lock(&ov4688->mutex);
1388 /* Initialize try_fmt */
1389 try_fmt->width = def_mode->width;
1390 try_fmt->height = def_mode->height;
1391 try_fmt->code = def_mode->bus_fmt;
1392 try_fmt->field = V4L2_FIELD_NONE;
1393
1394 mutex_unlock(&ov4688->mutex);
1395 /* No crop or compose */
1396
1397 return 0;
1398 }
1399 #endif
1400
ov4688_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1401 static int ov4688_enum_frame_interval(struct v4l2_subdev *sd,
1402 struct v4l2_subdev_pad_config *cfg,
1403 struct v4l2_subdev_frame_interval_enum *fie)
1404 {
1405 if (fie->index >= ARRAY_SIZE(supported_modes))
1406 return -EINVAL;
1407
1408 fie->code = supported_modes[fie->index].bus_fmt;
1409 fie->width = supported_modes[fie->index].width;
1410 fie->height = supported_modes[fie->index].height;
1411 fie->interval = supported_modes[fie->index].max_fps;
1412 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1413 return 0;
1414 }
1415
1416 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1417
1418 /*
1419 * The resolution of the driver configuration needs to be exactly
1420 * the same as the current output resolution of the sensor,
1421 * the input width of the isp needs to be 16 aligned,
1422 * the input height of the isp needs to be 8 aligned.
1423 * Can be cropped to standard resolution by this function,
1424 * otherwise it will crop out strange resolution according
1425 * to the alignment rules.
1426 */
1427
ov4688_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1428 static int ov4688_get_selection(struct v4l2_subdev *sd,
1429 struct v4l2_subdev_pad_config *cfg,
1430 struct v4l2_subdev_selection *sel)
1431 {
1432 struct ov4688 *ov4688 = to_ov4688(sd);
1433
1434 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1435 if (ov4688->cur_mode->width == 2688) {
1436 sel->r.left = CROP_START(ov4688->cur_mode->width, 2560);
1437 sel->r.width = 2560;
1438 sel->r.top = CROP_START(ov4688->cur_mode->height, 1440);
1439 sel->r.height = 1440;
1440 } else {
1441 sel->r.left = CROP_START(ov4688->cur_mode->width, 1920);
1442 sel->r.width = 1920;
1443 sel->r.top = CROP_START(ov4688->cur_mode->height, 1080);
1444 sel->r.height = 1080;
1445 }
1446 return 0;
1447 }
1448 return -EINVAL;
1449 }
1450
1451 static const struct dev_pm_ops ov4688_pm_ops = {
1452 SET_RUNTIME_PM_OPS(ov4688_runtime_suspend,
1453 ov4688_runtime_resume, NULL)
1454 };
1455
1456 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1457 static const struct v4l2_subdev_internal_ops ov4688_internal_ops = {
1458 .open = ov4688_open,
1459 };
1460 #endif
1461
1462 static const struct v4l2_subdev_core_ops ov4688_core_ops = {
1463 .s_power = ov4688_s_power,
1464 .ioctl = ov4688_ioctl,
1465 #ifdef CONFIG_COMPAT
1466 .compat_ioctl32 = ov4688_compat_ioctl32,
1467 #endif
1468 };
1469
1470 static const struct v4l2_subdev_video_ops ov4688_video_ops = {
1471 .s_stream = ov4688_s_stream,
1472 .g_frame_interval = ov4688_g_frame_interval,
1473 };
1474
1475 static const struct v4l2_subdev_pad_ops ov4688_pad_ops = {
1476 .enum_mbus_code = ov4688_enum_mbus_code,
1477 .enum_frame_size = ov4688_enum_frame_sizes,
1478 .enum_frame_interval = ov4688_enum_frame_interval,
1479 .get_fmt = ov4688_get_fmt,
1480 .set_fmt = ov4688_set_fmt,
1481 .get_selection = ov4688_get_selection,
1482 .get_mbus_config = ov4688_g_mbus_config,
1483 };
1484
1485 static const struct v4l2_subdev_ops ov4688_subdev_ops = {
1486 .core = &ov4688_core_ops,
1487 .video = &ov4688_video_ops,
1488 .pad = &ov4688_pad_ops,
1489 };
1490
ov4688_set_ctrl(struct v4l2_ctrl * ctrl)1491 static int ov4688_set_ctrl(struct v4l2_ctrl *ctrl)
1492 {
1493 struct ov4688 *ov4688 = container_of(ctrl->handler,
1494 struct ov4688, ctrl_handler);
1495 struct i2c_client *client = ov4688->client;
1496 s64 max;
1497 int ret = 0;
1498 u32 val = 0;
1499 u32 again = 0;
1500 u32 dgain = 0;
1501
1502 /* Propagate change of current control to all related controls */
1503 switch (ctrl->id) {
1504 case V4L2_CID_VBLANK:
1505 /* Update max exposure while meeting expected vblanking */
1506 max = ov4688->cur_mode->height + ctrl->val - 4;
1507 __v4l2_ctrl_modify_range(ov4688->exposure,
1508 ov4688->exposure->minimum, max,
1509 ov4688->exposure->step,
1510 ov4688->exposure->default_value);
1511 break;
1512 }
1513
1514 if (!pm_runtime_get_if_in_use(&client->dev))
1515 return 0;
1516
1517 switch (ctrl->id) {
1518 case V4L2_CID_EXPOSURE:
1519 /* 4 least significant bits of expsoure are fractional part */
1520 ret = ov4688_write_reg(ov4688->client, OV4688_REG_EXPOSURE_L,
1521 OV4688_REG_VALUE_24BIT, ctrl->val << 4);
1522 break;
1523 case V4L2_CID_ANALOGUE_GAIN:
1524 if (ctrl->val > 2040) {
1525 again = 2040;
1526 dgain = ctrl->val - 2040;
1527 if (dgain == 0x8000)
1528 dgain = 0x7fff;
1529 } else {
1530 again = ctrl->val;
1531 dgain = 2048;
1532 }
1533 ret = ov4688_write_reg(ov4688->client, OV4688_REG_GAIN_H,
1534 OV4688_REG_VALUE_08BIT,
1535 (again >> OV4688_GAIN_H_SHIFT) & OV4688_GAIN_H_MASK);
1536 ret |= ov4688_write_reg(ov4688->client, OV4688_REG_GAIN_L,
1537 OV4688_REG_VALUE_08BIT,
1538 again & OV4688_GAIN_L_MASK);
1539 ret |= ov4688_write_reg(ov4688->client, OV4688_REG_DGAIN_H,
1540 OV4688_REG_VALUE_08BIT,
1541 (dgain >> 8) & 0x7f);
1542 ret |= ov4688_write_reg(ov4688->client, OV4688_REG_DGAIN_L,
1543 OV4688_REG_VALUE_08BIT,
1544 dgain & 0xff);
1545 break;
1546 case V4L2_CID_VBLANK:
1547 ret = ov4688_write_reg(ov4688->client, OV4688_REG_VTS,
1548 OV4688_REG_VALUE_16BIT,
1549 ctrl->val + ov4688->cur_mode->height);
1550 break;
1551 case V4L2_CID_HFLIP:
1552 ret = ov4688_read_reg(ov4688->client, OV4688_MIRROR_REG,
1553 OV4688_REG_VALUE_08BIT, &val);
1554 if (!ctrl->val) {
1555 val |= OV4688_DIGITAL_BIT_MASK;
1556 val |= OV4688_ARRAY_BIT_MASK;
1557 } else {
1558 val &= ~OV4688_DIGITAL_BIT_MASK;
1559 val &= ~OV4688_ARRAY_BIT_MASK;
1560 }
1561 ret |= ov4688_write_reg(ov4688->client, OV4688_MIRROR_REG,
1562 OV4688_REG_VALUE_08BIT, val);
1563 if (ret == 0)
1564 ov4688->flip = val;
1565 break;
1566 case V4L2_CID_VFLIP:
1567 ret = ov4688_read_reg(ov4688->client, OV4688_FLIP_REG,
1568 OV4688_REG_VALUE_08BIT, &val);
1569 if (ctrl->val) {
1570 val |= OV4688_DIGITAL_BIT_MASK;
1571 val |= OV4688_ARRAY_BIT_MASK;
1572 } else {
1573 val &= ~OV4688_DIGITAL_BIT_MASK;
1574 val &= ~OV4688_ARRAY_BIT_MASK;
1575 }
1576 ret |= ov4688_write_reg(ov4688->client, OV4688_FLIP_REG,
1577 OV4688_REG_VALUE_08BIT, val);
1578 if (ret == 0)
1579 ov4688->flip = val;
1580 break;
1581 case V4L2_CID_TEST_PATTERN:
1582 ret = ov4688_enable_test_pattern(ov4688, ctrl->val);
1583 break;
1584 default:
1585 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1586 __func__, ctrl->id, ctrl->val);
1587 break;
1588 }
1589
1590 pm_runtime_put(&client->dev);
1591
1592 return ret;
1593 }
1594
1595 static const struct v4l2_ctrl_ops ov4688_ctrl_ops = {
1596 .s_ctrl = ov4688_set_ctrl,
1597 };
1598
ov4688_initialize_controls(struct ov4688 * ov4688)1599 static int ov4688_initialize_controls(struct ov4688 *ov4688)
1600 {
1601 const struct ov4688_mode *mode;
1602 struct v4l2_ctrl_handler *handler;
1603 struct v4l2_ctrl *ctrl;
1604 s64 exposure_max, vblank_def;
1605 u32 h_blank;
1606 int ret;
1607
1608 handler = &ov4688->ctrl_handler;
1609 mode = ov4688->cur_mode;
1610 ret = v4l2_ctrl_handler_init(handler, 9);
1611 if (ret)
1612 return ret;
1613 handler->lock = &ov4688->mutex;
1614
1615 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1616 0, 0, link_freq_menu_items);
1617 if (ctrl)
1618 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1619
1620 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1621 0, OV4688_PIXEL_RATE, 1, OV4688_PIXEL_RATE);
1622
1623 h_blank = mode->hts_def - mode->width;
1624 ov4688->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1625 h_blank, h_blank, 1, h_blank);
1626 if (ov4688->hblank)
1627 ov4688->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1628
1629 vblank_def = mode->vts_def - mode->height;
1630 ov4688->vblank = v4l2_ctrl_new_std(handler, &ov4688_ctrl_ops,
1631 V4L2_CID_VBLANK, vblank_def,
1632 OV4688_VTS_MAX - mode->height,
1633 1, vblank_def);
1634
1635 exposure_max = mode->vts_def - 4;
1636 ov4688->exposure = v4l2_ctrl_new_std(handler, &ov4688_ctrl_ops,
1637 V4L2_CID_EXPOSURE, OV4688_EXPOSURE_MIN,
1638 exposure_max, OV4688_EXPOSURE_STEP,
1639 mode->exp_def);
1640
1641 ov4688->anal_gain = v4l2_ctrl_new_std(handler, &ov4688_ctrl_ops,
1642 V4L2_CID_ANALOGUE_GAIN, OV4688_GAIN_MIN,
1643 OV4688_GAIN_MAX, OV4688_GAIN_STEP,
1644 OV4688_GAIN_DEFAULT);
1645
1646 ov4688->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1647 &ov4688_ctrl_ops, V4L2_CID_TEST_PATTERN,
1648 ARRAY_SIZE(ov4688_test_pattern_menu) - 1,
1649 0, 0, ov4688_test_pattern_menu);
1650
1651 ov4688->h_flip = v4l2_ctrl_new_std(handler, &ov4688_ctrl_ops,
1652 V4L2_CID_HFLIP, 0, 1, 1, 0);
1653
1654 ov4688->v_flip = v4l2_ctrl_new_std(handler, &ov4688_ctrl_ops,
1655 V4L2_CID_VFLIP, 0, 1, 1, 0);
1656 ov4688->flip = 0;
1657
1658 if (handler->error) {
1659 ret = handler->error;
1660 dev_err(&ov4688->client->dev,
1661 "Failed to init controls(%d)\n", ret);
1662 goto err_free_handler;
1663 }
1664
1665 ov4688->subdev.ctrl_handler = handler;
1666
1667 return 0;
1668
1669 err_free_handler:
1670 v4l2_ctrl_handler_free(handler);
1671
1672 return ret;
1673 }
1674
ov4688_check_sensor_id(struct ov4688 * ov4688,struct i2c_client * client)1675 static int ov4688_check_sensor_id(struct ov4688 *ov4688,
1676 struct i2c_client *client)
1677 {
1678 struct device *dev = &ov4688->client->dev;
1679 u32 id = 0;
1680 int ret;
1681
1682 ret = ov4688_read_reg(client, OV4688_REG_CHIP_ID,
1683 OV4688_REG_VALUE_16BIT, &id);
1684 if (id != CHIP_ID) {
1685 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1686 return -ENODEV;
1687 }
1688
1689 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1690
1691 return 0;
1692 }
1693
ov4688_configure_regulators(struct ov4688 * ov4688)1694 static int ov4688_configure_regulators(struct ov4688 *ov4688)
1695 {
1696 unsigned int i;
1697
1698 for (i = 0; i < OV4688_NUM_SUPPLIES; i++)
1699 ov4688->supplies[i].supply = ov4688_supply_names[i];
1700
1701 return devm_regulator_bulk_get(&ov4688->client->dev,
1702 OV4688_NUM_SUPPLIES,
1703 ov4688->supplies);
1704 }
1705
ov4688_probe(struct i2c_client * client,const struct i2c_device_id * id)1706 static int ov4688_probe(struct i2c_client *client,
1707 const struct i2c_device_id *id)
1708 {
1709 struct device *dev = &client->dev;
1710 struct device_node *node = dev->of_node;
1711 struct ov4688 *ov4688;
1712 struct v4l2_subdev *sd;
1713 char facing[2];
1714 int ret;
1715 u32 i, hdr_mode = 0;
1716
1717 dev_info(dev, "driver version: %02x.%02x.%02x",
1718 DRIVER_VERSION >> 16,
1719 (DRIVER_VERSION & 0xff00) >> 8,
1720 DRIVER_VERSION & 0x00ff);
1721
1722 ov4688 = devm_kzalloc(dev, sizeof(*ov4688), GFP_KERNEL);
1723 if (!ov4688)
1724 return -ENOMEM;
1725
1726 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1727 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1728 &ov4688->module_index);
1729 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1730 &ov4688->module_facing);
1731 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1732 &ov4688->module_name);
1733 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1734 &ov4688->len_name);
1735 if (ret) {
1736 dev_err(dev, "could not get module information!\n");
1737 return -EINVAL;
1738 }
1739
1740 ov4688->client = client;
1741 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1742 if (hdr_mode == supported_modes[i].hdr_mode) {
1743 ov4688->cur_mode = &supported_modes[i];
1744 break;
1745 }
1746 }
1747 if (i == ARRAY_SIZE(supported_modes))
1748 ov4688->cur_mode = &supported_modes[0];
1749
1750 ov4688->xvclk = devm_clk_get(dev, "xvclk");
1751 if (IS_ERR(ov4688->xvclk)) {
1752 dev_err(dev, "Failed to get xvclk\n");
1753 return -EINVAL;
1754 }
1755
1756 ov4688->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1757 if (IS_ERR(ov4688->reset_gpio))
1758 dev_warn(dev, "Failed to get reset-gpios\n");
1759
1760 ov4688->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1761 if (IS_ERR(ov4688->pwdn_gpio))
1762 dev_warn(dev, "Failed to get pwdn-gpios\n");
1763
1764 ov4688->pinctrl = devm_pinctrl_get(dev);
1765 if (!IS_ERR(ov4688->pinctrl)) {
1766 ov4688->pins_default =
1767 pinctrl_lookup_state(ov4688->pinctrl,
1768 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1769 if (IS_ERR(ov4688->pins_default))
1770 dev_err(dev, "could not get default pinstate\n");
1771
1772 ov4688->pins_sleep =
1773 pinctrl_lookup_state(ov4688->pinctrl,
1774 OF_CAMERA_PINCTRL_STATE_SLEEP);
1775 if (IS_ERR(ov4688->pins_sleep))
1776 dev_err(dev, "could not get sleep pinstate\n");
1777 } else {
1778 dev_err(dev, "no pinctrl\n");
1779 }
1780
1781 ret = ov4688_configure_regulators(ov4688);
1782 if (ret) {
1783 dev_err(dev, "Failed to get power regulators\n");
1784 return ret;
1785 }
1786
1787 mutex_init(&ov4688->mutex);
1788
1789 sd = &ov4688->subdev;
1790 v4l2_i2c_subdev_init(sd, client, &ov4688_subdev_ops);
1791 ret = ov4688_initialize_controls(ov4688);
1792 if (ret)
1793 goto err_destroy_mutex;
1794
1795 ret = __ov4688_power_on(ov4688);
1796 if (ret)
1797 goto err_free_handler;
1798
1799 ret = ov4688_check_sensor_id(ov4688, client);
1800 if (ret)
1801 goto err_power_off;
1802
1803 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1804 sd->internal_ops = &ov4688_internal_ops;
1805 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1806 V4L2_SUBDEV_FL_HAS_EVENTS;
1807 #endif
1808 #if defined(CONFIG_MEDIA_CONTROLLER)
1809 ov4688->pad.flags = MEDIA_PAD_FL_SOURCE;
1810 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1811 ret = media_entity_pads_init(&sd->entity, 1, &ov4688->pad);
1812 if (ret < 0)
1813 goto err_power_off;
1814 #endif
1815
1816 memset(facing, 0, sizeof(facing));
1817 if (strcmp(ov4688->module_facing, "back") == 0)
1818 facing[0] = 'b';
1819 else
1820 facing[0] = 'f';
1821
1822 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1823 ov4688->module_index, facing,
1824 OV4688_NAME, dev_name(sd->dev));
1825 ret = v4l2_async_register_subdev_sensor_common(sd);
1826 if (ret) {
1827 dev_err(dev, "v4l2 async register subdev failed\n");
1828 goto err_clean_entity;
1829 }
1830
1831 pm_runtime_set_active(dev);
1832 pm_runtime_enable(dev);
1833 pm_runtime_idle(dev);
1834
1835 return 0;
1836
1837 err_clean_entity:
1838 #if defined(CONFIG_MEDIA_CONTROLLER)
1839 media_entity_cleanup(&sd->entity);
1840 #endif
1841 err_power_off:
1842 __ov4688_power_off(ov4688);
1843 err_free_handler:
1844 v4l2_ctrl_handler_free(&ov4688->ctrl_handler);
1845 err_destroy_mutex:
1846 mutex_destroy(&ov4688->mutex);
1847
1848 return ret;
1849 }
1850
ov4688_remove(struct i2c_client * client)1851 static int ov4688_remove(struct i2c_client *client)
1852 {
1853 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1854 struct ov4688 *ov4688 = to_ov4688(sd);
1855
1856 v4l2_async_unregister_subdev(sd);
1857 #if defined(CONFIG_MEDIA_CONTROLLER)
1858 media_entity_cleanup(&sd->entity);
1859 #endif
1860 v4l2_ctrl_handler_free(&ov4688->ctrl_handler);
1861 mutex_destroy(&ov4688->mutex);
1862
1863 pm_runtime_disable(&client->dev);
1864 if (!pm_runtime_status_suspended(&client->dev))
1865 __ov4688_power_off(ov4688);
1866 pm_runtime_set_suspended(&client->dev);
1867
1868 return 0;
1869 }
1870
1871 #if IS_ENABLED(CONFIG_OF)
1872 static const struct of_device_id ov4688_of_match[] = {
1873 { .compatible = "ovti,ov4688" },
1874 {},
1875 };
1876 MODULE_DEVICE_TABLE(of, ov4688_of_match);
1877 #endif
1878
1879 static const struct i2c_device_id ov4688_match_id[] = {
1880 { "ovti,ov4688", 0 },
1881 { },
1882 };
1883
1884 static struct i2c_driver ov4688_i2c_driver = {
1885 .driver = {
1886 .name = OV4688_NAME,
1887 .pm = &ov4688_pm_ops,
1888 .of_match_table = of_match_ptr(ov4688_of_match),
1889 },
1890 .probe = &ov4688_probe,
1891 .remove = &ov4688_remove,
1892 .id_table = ov4688_match_id,
1893 };
1894
sensor_mod_init(void)1895 static int __init sensor_mod_init(void)
1896 {
1897 return i2c_add_driver(&ov4688_i2c_driver);
1898 }
1899
sensor_mod_exit(void)1900 static void __exit sensor_mod_exit(void)
1901 {
1902 i2c_del_driver(&ov4688_i2c_driver);
1903 }
1904
1905 device_initcall_sync(sensor_mod_init);
1906 module_exit(sensor_mod_exit);
1907
1908 MODULE_DESCRIPTION("OmniVision ov4688 sensor driver");
1909 MODULE_LICENSE("GPL v2");
1910