1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov16a1q camera driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 *
9 */
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/compat.h>
23 #include <linux/rk-camera-module.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29
30 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
31
32 #ifndef V4L2_CID_DIGITAL_GAIN
33 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34 #endif
35
36 #define OV16A1Q_LINK_FREQ_726MHZ 726000000U
37 #define OV16A1Q_LINK_FREQ_378MHZ 378000000U
38
39 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
40 #define OV16A1Q_PIXEL_RATE (OV16A1Q_LINK_FREQ_726MHZ * 2LL * 4LL / 10LL)
41 #define OV16A1Q_XVCLK_FREQ 24000000
42
43 #define CHIP_ID 0x561641
44 #define OV16A1Q_REG_CHIP_ID 0x300a
45
46 #define OV16A1Q_REG_CTRL_MODE 0x0100
47 #define OV16A1Q_MODE_SW_STANDBY 0x0
48 #define OV16A1Q_MODE_STREAMING BIT(0)
49
50 #define OV16A1Q_REG_EXPOSURE_H 0x3500
51 #define OV16A1Q_REG_EXPOSURE_M 0x3501
52 #define OV16A1Q_REG_EXPOSURE_L 0x3502
53 #define OV16A1Q_EXPOSURE_MIN 4
54 #define OV16A1Q_EXPOSURE_STEP 1
55 #define OV16A1Q_VTS_MAX 0x7ff7
56
57 #define OV16A1Q_REG_AGAIN_H 0x3508
58 #define OV16A1Q_REG_AGAIN_L 0x3509
59 #define OV16A1Q_REG_DAGAIN_H_B 0x350A
60 #define OV16A1Q_REG_DAGAIN_M_B 0x350B
61 #define OV16A1Q_REG_DAGAIN_L_B 0x350C
62 #define OV16A1Q_GAIN_MIN 0x80
63 #define OV16A1Q_GAIN_MAX 0x3df61
64 #define OV16A1Q_GAIN_STEP 1
65 #define OV16A1Q_GAIN_DEFAULT 0x80
66
67 #define OV16A1Q_SOFTWARE_RESET_REG 0x0103
68 #define OV16A1Q_REG_ISP_X_WIN 0x3810
69 #define OV16A1Q_REG_ISP_Y_WIN 0x3812
70
71 #define OV16A1Q_GROUP_UPDATE_ADDRESS 0x3208
72 #define OV16A1Q_GROUP_UPDATE_START_DATA 0x00
73 #define OV16A1Q_GROUP_UPDATE_END_DATA 0x10
74 #define OV16A1Q_GROUP_UPDATE_LAUNCH 0xA0
75
76 #define OV16A1Q_REG_TEST_PATTERN 0x5081
77 #define OV16A1Q_TEST_PATTERN_ENABLE 0x01
78 #define OV16A1Q_TEST_PATTERN_DISABLE 0x0
79
80 #define OV16A1Q_REG_VTS_H 0x380e
81 #define OV16A1Q_REG_VTS_L 0x380f
82
83 #define OV16A1Q_FLIP_REG 0x3820
84 #define OV16A1Q_MIRROR_REG 0x3821
85 #define MIRROR_BIT_MASK BIT(2)
86 #define FLIP_BIT_MASK BIT(2)
87
88 #define OV16A1Q_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x7F)
89 #define OV16A1Q_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
90 #define OV16A1Q_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
91
92 #define OV16A1Q_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x7F)
93 #define OV16A1Q_FETCH_AGAIN_L(VAL) ((VAL) & 0xFE)
94
95 #define OV16A1Q_FETCH_DGAIN_H(VAL) (((VAL) >> 16) & 0x0F)
96 #define OV16A1Q_FETCH_DGAIN_M(VAL) (((VAL) >> 8) & 0xFF)
97 #define OV16A1Q_FETCH_DGAIN_L(VAL) ((VAL) & 0xC0)
98
99 #define OV16A1Q_FETCH_VTS_H(VAL) (((VAL) >> 8) & 0x7F)
100 #define OV16A1Q_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
101
102 #define REG_NULL 0xFFFF
103
104 #define OV16A1Q_REG_VALUE_08BIT 1
105 #define OV16A1Q_REG_VALUE_16BIT 2
106 #define OV16A1Q_REG_VALUE_24BIT 3
107
108 #define OV16A1Q_LANES 4
109 #define OV16A1Q_BITS_PER_SAMPLE 10
110
111 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
112 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
113 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
114
115 #define OV16A1Q_NAME "ov16a1q"
116 #define OV16A1Q_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
117
118 static const char * const ov16a1q_supply_names[] = {
119 "avdd", /* Analog power */
120 "dovdd", /* Digital I/O power */
121 "dvdd", /* Digital core power */
122 };
123
124 #define OV16A1Q_NUM_SUPPLIES ARRAY_SIZE(ov16a1q_supply_names)
125
126 struct regval {
127 u16 addr;
128 u8 val;
129 };
130
131 struct ov16a1q_mode {
132 u32 width;
133 u32 height;
134 struct v4l2_fract max_fps;
135 u32 hts_def;
136 u32 vts_def;
137 u32 exp_def;
138 u32 link_freq_idx;
139 u32 bpp;
140 const struct regval *reg_list;
141 u32 hdr_mode;
142 u32 vc[PAD_MAX];
143 };
144
145 struct ov16a1q {
146 struct i2c_client *client;
147 struct clk *xvclk;
148 struct gpio_desc *power_gpio;
149 struct gpio_desc *reset_gpio;
150 struct gpio_desc *pwdn_gpio;
151 struct regulator_bulk_data supplies[OV16A1Q_NUM_SUPPLIES];
152
153 struct pinctrl *pinctrl;
154 struct pinctrl_state *pins_default;
155 struct pinctrl_state *pins_sleep;
156
157 struct v4l2_subdev subdev;
158 struct media_pad pad;
159 struct v4l2_ctrl_handler ctrl_handler;
160 struct v4l2_ctrl *exposure;
161 struct v4l2_ctrl *anal_gain;
162 struct v4l2_ctrl *digi_gain;
163 struct v4l2_ctrl *hblank;
164 struct v4l2_ctrl *vblank;
165 struct v4l2_ctrl *pixel_rate;
166 struct v4l2_ctrl *link_freq;
167 struct v4l2_ctrl *test_pattern;
168 struct v4l2_ctrl *h_flip;
169 struct v4l2_ctrl *v_flip;
170 struct mutex mutex;
171 bool streaming;
172 bool power_on;
173 const struct ov16a1q_mode *cur_mode;
174 u32 cfg_num;
175 u32 module_index;
176 const char *module_facing;
177 const char *module_name;
178 const char *len_name;
179 };
180
181 #define to_ov16a1q(sd) container_of(sd, struct ov16a1q, subdev)
182
183 /*
184 * Xclk 24Mhz
185 */
186 static const struct regval ov16a1q_global_regs[] = {
187 {0x0103, 0x01},
188 {0x0102, 0x00},
189 {0x0301, 0x48},
190 {0x0302, 0x31},
191 {0x0303, 0x04},
192 {0x0305, 0xc2},
193 {0x0306, 0x00},
194 {0x0320, 0x02},
195 {0x0323, 0x04},
196 {0x0326, 0xd8},
197 {0x0327, 0x0b},
198 {0x0329, 0x01},
199 {0x0343, 0x04},
200 {0x0344, 0x01},
201 {0x0345, 0x2c},
202 {0x0346, 0xc0},
203 {0x034a, 0x07},
204 {0x300e, 0x22},
205 {0x3012, 0x41},
206 {0x3016, 0xd2},
207 {0x3018, 0x70},
208 {0x301e, 0x98},
209 {0x3025, 0x03},
210 {0x3026, 0x10},
211 {0x3027, 0x08},
212 {0x3102, 0x00},
213 {0x3400, 0x04},
214 {0x3406, 0x04},
215 {0x3408, 0x04},
216 {0x3421, 0x09},
217 {0x3422, 0x20},
218 {0x3423, 0x15},
219 {0x3424, 0x40},
220 {0x3425, 0x14},
221 {0x3426, 0x04},
222 {0x3504, 0x08},
223 {0x3508, 0x01},
224 {0x3509, 0x00},
225 {0x350a, 0x01},
226 {0x350b, 0x00},
227 {0x350c, 0x00},
228 {0x3548, 0x01},
229 {0x3549, 0x00},
230 {0x354a, 0x01},
231 {0x354b, 0x00},
232 {0x354c, 0x00},
233 {0x3600, 0xff},
234 {0x3602, 0x42},
235 {0x3603, 0x7b},
236 {0x3608, 0x9b},
237 {0x360a, 0x69},
238 {0x360b, 0x53},
239 {0x3618, 0xc0},
240 {0x361a, 0x8b},
241 {0x361d, 0x20},
242 {0x361e, 0x30},
243 {0x361f, 0x01},
244 {0x3620, 0x89},
245 {0x3624, 0x8f},
246 {0x3629, 0x09},
247 {0x362e, 0x50},
248 {0x3631, 0xe2},
249 {0x3632, 0xe2},
250 {0x3634, 0x10},
251 {0x3635, 0x10},
252 {0x3636, 0x10},
253 {0x3639, 0xa6},
254 {0x363a, 0xaa},
255 {0x363b, 0x0c},
256 {0x363c, 0x16},
257 {0x363d, 0x29},
258 {0x363e, 0x4f},
259 {0x3642, 0xa8},
260 {0x3652, 0x00},
261 {0x3653, 0x00},
262 {0x3654, 0x8a},
263 {0x3656, 0x0c},
264 {0x3657, 0x8e},
265 {0x3660, 0x80},
266 {0x3663, 0x00},
267 {0x3664, 0x00},
268 {0x3668, 0x05},
269 {0x3669, 0x05},
270 {0x370d, 0x10},
271 {0x370e, 0x05},
272 {0x370f, 0x10},
273 {0x3711, 0x01},
274 {0x3712, 0x09},
275 {0x3713, 0x40},
276 {0x3714, 0xe4},
277 {0x3716, 0x04},
278 {0x3717, 0x01},
279 {0x3718, 0x02},
280 {0x3719, 0x01},
281 {0x371a, 0x02},
282 {0x371b, 0x02},
283 {0x371c, 0x01},
284 {0x371d, 0x02},
285 {0x371e, 0x12},
286 {0x371f, 0x02},
287 {0x3720, 0x14},
288 {0x3721, 0x12},
289 {0x3722, 0x44},
290 {0x3723, 0x60},
291 {0x372f, 0x34},
292 {0x3726, 0x21},
293 {0x37d0, 0x02},
294 {0x37d1, 0x10},
295 {0x37db, 0x08},
296 {0x3808, 0x12},
297 {0x3809, 0x30},
298 {0x380a, 0x0d},
299 {0x380b, 0xa8},
300 {0x380c, 0x03},
301 {0x380d, 0x52},
302 {0x380e, 0x0f},
303 {0x380f, 0x51},
304 {0x3814, 0x11},
305 {0x3815, 0x11},
306 {0x3820, 0x00},
307 {0x3821, 0x06},
308 {0x3822, 0x00},
309 {0x3823, 0x04},
310 {0x3837, 0x10},
311 {0x383c, 0x34},
312 {0x383d, 0xff},
313 {0x383e, 0x0d},
314 {0x383f, 0x22},
315 {0x3857, 0x00},
316 {0x388f, 0x00},
317 {0x3890, 0x00},
318 {0x3891, 0x00},
319 {0x3d81, 0x10},
320 {0x3d83, 0x0c},
321 {0x3d84, 0x00},
322 {0x3d85, 0x1b},
323 {0x3d88, 0x00},
324 {0x3d89, 0x00},
325 {0x3d8a, 0x00},
326 {0x3d8b, 0x01},
327 {0x3d8c, 0x77},
328 {0x3d8d, 0xa0},
329 {0x3f00, 0x02},
330 {0x3f0c, 0x07},
331 {0x3f0d, 0x2f},
332 {0x4012, 0x0d},
333 {0x4015, 0x04},
334 {0x4016, 0x1b},
335 {0x4017, 0x04},
336 {0x4018, 0x0b},
337 {0x401b, 0x1f},
338 {0x401e, 0x01},
339 {0x401f, 0x38},
340 {0x4500, 0x20},
341 {0x4501, 0x6a},
342 {0x4502, 0xb4},
343 {0x4586, 0x00},
344 {0x4588, 0x02},
345 {0x4640, 0x01},
346 {0x4641, 0x04},
347 {0x4643, 0x00},
348 {0x4645, 0x03},
349 {0x4806, 0x40},
350 {0x480e, 0x00},
351 {0x4815, 0x2b},
352 {0x481b, 0x3c},
353 {0x4833, 0x18},
354 {0x4837, 0x08},
355 {0x484b, 0x07},
356 {0x4850, 0x41},
357 {0x4860, 0x00},
358 {0x4861, 0xec},
359 {0x4864, 0x00},
360 {0x4883, 0x00},
361 {0x4888, 0x10},
362 {0x4a00, 0x10},
363 {0x4e00, 0x00},
364 {0x4e01, 0x04},
365 {0x4e02, 0x01},
366 {0x4e03, 0x00},
367 {0x4e04, 0x08},
368 {0x4e05, 0x04},
369 {0x4e06, 0x00},
370 {0x4e07, 0x13},
371 {0x4e08, 0x01},
372 {0x4e09, 0x00},
373 {0x4e0a, 0x15},
374 {0x4e0b, 0x0e},
375 {0x4e0c, 0x00},
376 {0x4e0d, 0x17},
377 {0x4e0e, 0x07},
378 {0x4e0f, 0x00},
379 {0x4e10, 0x19},
380 {0x4e11, 0x06},
381 {0x4e12, 0x00},
382 {0x4e13, 0x1b},
383 {0x4e14, 0x08},
384 {0x4e15, 0x00},
385 {0x4e16, 0x1f},
386 {0x4e17, 0x08},
387 {0x4e18, 0x00},
388 {0x4e19, 0x21},
389 {0x4e1a, 0x0e},
390 {0x4e1b, 0x00},
391 {0x4e1c, 0x2d},
392 {0x4e1d, 0x30},
393 {0x4e1e, 0x00},
394 {0x4e1f, 0x6a},
395 {0x4e20, 0x05},
396 {0x4e21, 0x00},
397 {0x4e22, 0x6c},
398 {0x4e23, 0x05},
399 {0x4e24, 0x00},
400 {0x4e25, 0x6e},
401 {0x4e26, 0x39},
402 {0x4e27, 0x00},
403 {0x4e28, 0x7a},
404 {0x4e29, 0x6d},
405 {0x4e2a, 0x00},
406 {0x4e2b, 0x00},
407 {0x4e2c, 0x00},
408 {0x4e2d, 0x00},
409 {0x4e2e, 0x00},
410 {0x4e2f, 0x00},
411 {0x4e30, 0x00},
412 {0x4e31, 0x00},
413 {0x4e32, 0x00},
414 {0x4e33, 0x00},
415 {0x4e34, 0x00},
416 {0x4e35, 0x00},
417 {0x4e36, 0x00},
418 {0x4e37, 0x00},
419 {0x4e38, 0x00},
420 {0x4e39, 0x00},
421 {0x4e3a, 0x00},
422 {0x4e3b, 0x00},
423 {0x4e3c, 0x00},
424 {0x4e3d, 0x00},
425 {0x4e3e, 0x00},
426 {0x4e3f, 0x00},
427 {0x4e40, 0x00},
428 {0x4e41, 0x00},
429 {0x4e42, 0x00},
430 {0x4e43, 0x00},
431 {0x4e44, 0x00},
432 {0x4e45, 0x00},
433 {0x4e46, 0x00},
434 {0x4e47, 0x00},
435 {0x4e48, 0x00},
436 {0x4e49, 0x00},
437 {0x4e4a, 0x00},
438 {0x4e4b, 0x00},
439 {0x4e4c, 0x00},
440 {0x4e4d, 0x00},
441 {0x4e4e, 0x00},
442 {0x4e4f, 0x00},
443 {0x4e50, 0x00},
444 {0x4e51, 0x00},
445 {0x4e52, 0x00},
446 {0x4e53, 0x00},
447 {0x4e54, 0x00},
448 {0x4e55, 0x00},
449 {0x4e56, 0x00},
450 {0x4e57, 0x00},
451 {0x4e58, 0x00},
452 {0x4e59, 0x00},
453 {0x4e5a, 0x00},
454 {0x4e5b, 0x00},
455 {0x4e5c, 0x00},
456 {0x4e5d, 0x00},
457 {0x4e5e, 0x00},
458 {0x4e5f, 0x00},
459 {0x4e60, 0x00},
460 {0x4e61, 0x00},
461 {0x4e62, 0x00},
462 {0x4e63, 0x00},
463 {0x4e64, 0x00},
464 {0x4e65, 0x00},
465 {0x4e66, 0x00},
466 {0x4e67, 0x00},
467 {0x4e68, 0x00},
468 {0x4e69, 0x00},
469 {0x4e6a, 0x00},
470 {0x4e6b, 0x00},
471 {0x4e6c, 0x00},
472 {0x4e6d, 0x00},
473 {0x4e6e, 0x00},
474 {0x4e6f, 0x00},
475 {0x4e70, 0x00},
476 {0x4e71, 0x00},
477 {0x4e72, 0x00},
478 {0x4e73, 0x00},
479 {0x4e74, 0x00},
480 {0x4e75, 0x00},
481 {0x4e76, 0x00},
482 {0x4e77, 0x00},
483 {0x4e78, 0x1c},
484 {0x4e79, 0x1e},
485 {0x4e7a, 0x00},
486 {0x4e7b, 0x00},
487 {0x4e7c, 0x2c},
488 {0x4e7d, 0x2f},
489 {0x4e7e, 0x79},
490 {0x4e7f, 0x7b},
491 {0x4e80, 0x0a},
492 {0x4e81, 0x31},
493 {0x4e82, 0x66},
494 {0x4e83, 0x81},
495 {0x4e84, 0x03},
496 {0x4e85, 0x40},
497 {0x4e86, 0x02},
498 {0x4e87, 0x09},
499 {0x4e88, 0x43},
500 {0x4e89, 0x53},
501 {0x4e8a, 0x32},
502 {0x4e8b, 0x67},
503 {0x4e8c, 0x05},
504 {0x4e8d, 0x83},
505 {0x4e8e, 0x00},
506 {0x4e8f, 0x00},
507 {0x4e90, 0x00},
508 {0x4e91, 0x00},
509 {0x4e92, 0x00},
510 {0x4e93, 0x00},
511 {0x4e94, 0x00},
512 {0x4e95, 0x00},
513 {0x4e96, 0x00},
514 {0x4e97, 0x00},
515 {0x4e98, 0x00},
516 {0x4e99, 0x00},
517 {0x4e9a, 0x00},
518 {0x4e9b, 0x00},
519 {0x4e9c, 0x00},
520 {0x4e9d, 0x00},
521 {0x4e9e, 0x00},
522 {0x4e9f, 0x00},
523 {0x4ea0, 0x00},
524 {0x4ea1, 0x00},
525 {0x4ea2, 0x00},
526 {0x4ea3, 0x00},
527 {0x4ea4, 0x00},
528 {0x4ea5, 0x00},
529 {0x4ea6, 0x1e},
530 {0x4ea7, 0x20},
531 {0x4ea8, 0x32},
532 {0x4ea9, 0x6d},
533 {0x4eaa, 0x18},
534 {0x4eab, 0x7f},
535 {0x4eac, 0x00},
536 {0x4ead, 0x00},
537 {0x4eae, 0x7c},
538 {0x4eaf, 0x07},
539 {0x4eb0, 0x7c},
540 {0x4eb1, 0x07},
541 {0x4eb2, 0x07},
542 {0x4eb3, 0x1c},
543 {0x4eb4, 0x07},
544 {0x4eb5, 0x1c},
545 {0x4eb6, 0x07},
546 {0x4eb7, 0x1c},
547 {0x4eb8, 0x07},
548 {0x4eb9, 0x1c},
549 {0x4eba, 0x07},
550 {0x4ebb, 0x14},
551 {0x4ebc, 0x07},
552 {0x4ebd, 0x1c},
553 {0x4ebe, 0x07},
554 {0x4ebf, 0x1c},
555 {0x4ec0, 0x07},
556 {0x4ec1, 0x1c},
557 {0x4ec2, 0x07},
558 {0x4ec3, 0x1c},
559 {0x4ec4, 0x2c},
560 {0x4ec5, 0x2f},
561 {0x4ec6, 0x79},
562 {0x4ec7, 0x7b},
563 {0x4ec8, 0x7c},
564 {0x4ec9, 0x07},
565 {0x4eca, 0x7c},
566 {0x4ecb, 0x07},
567 {0x4ecc, 0x00},
568 {0x4ecd, 0x00},
569 {0x4ece, 0x07},
570 {0x4ecf, 0x31},
571 {0x4ed0, 0x69},
572 {0x4ed1, 0x7f},
573 {0x4ed2, 0x67},
574 {0x4ed3, 0x00},
575 {0x4ed4, 0x00},
576 {0x4ed5, 0x00},
577 {0x4ed6, 0x7c},
578 {0x4ed7, 0x07},
579 {0x4ed8, 0x7c},
580 {0x4ed9, 0x07},
581 {0x4eda, 0x33},
582 {0x4edb, 0x7f},
583 {0x4edc, 0x00},
584 {0x4edd, 0x16},
585 {0x4ede, 0x00},
586 {0x4edf, 0x00},
587 {0x4ee0, 0x32},
588 {0x4ee1, 0x70},
589 {0x4ee2, 0x01},
590 {0x4ee3, 0x30},
591 {0x4ee4, 0x22},
592 {0x4ee5, 0x28},
593 {0x4ee6, 0x6f},
594 {0x4ee7, 0x75},
595 {0x4ee8, 0x00},
596 {0x4ee9, 0x00},
597 {0x4eea, 0x30},
598 {0x4eeb, 0x7f},
599 {0x4eec, 0x00},
600 {0x4eed, 0x00},
601 {0x4eee, 0x00},
602 {0x4eef, 0x00},
603 {0x4ef0, 0x69},
604 {0x4ef1, 0x7f},
605 {0x4ef2, 0x07},
606 {0x4ef3, 0x30},
607 {0x4ef4, 0x32},
608 {0x4ef5, 0x09},
609 {0x4ef6, 0x7d},
610 {0x4ef7, 0x65},
611 {0x4ef8, 0x00},
612 {0x4ef9, 0x00},
613 {0x4efa, 0x00},
614 {0x4efb, 0x00},
615 {0x4efc, 0x7f},
616 {0x4efd, 0x09},
617 {0x4efe, 0x7f},
618 {0x4eff, 0x09},
619 {0x4f00, 0x1e},
620 {0x4f01, 0x7c},
621 {0x4f02, 0x7f},
622 {0x4f03, 0x09},
623 {0x4f04, 0x7f},
624 {0x4f05, 0x0b},
625 {0x4f06, 0x7c},
626 {0x4f07, 0x02},
627 {0x4f08, 0x7c},
628 {0x4f09, 0x02},
629 {0x4f0a, 0x32},
630 {0x4f0b, 0x64},
631 {0x4f0c, 0x32},
632 {0x4f0d, 0x64},
633 {0x4f0e, 0x32},
634 {0x4f0f, 0x64},
635 {0x4f10, 0x32},
636 {0x4f11, 0x64},
637 {0x4f12, 0x31},
638 {0x4f13, 0x4f},
639 {0x4f14, 0x83},
640 {0x4f15, 0x84},
641 {0x4f16, 0x63},
642 {0x4f17, 0x64},
643 {0x4f18, 0x83},
644 {0x4f19, 0x84},
645 {0x4f1a, 0x31},
646 {0x4f1b, 0x32},
647 {0x4f1c, 0x7b},
648 {0x4f1d, 0x7c},
649 {0x4f1e, 0x2f},
650 {0x4f1f, 0x30},
651 {0x4f20, 0x30},
652 {0x4f21, 0x69},
653 {0x4d06, 0x08},
654 {0x5000, 0x01},
655 {0x5001, 0x40},
656 {0x5002, 0x53},
657 {0x5003, 0x42},
658 {0x5004, 0x08},
659 {0x5005, 0x00},
660 {0x5012, 0x60},
661 {0x5038, 0x00},
662 {0x5081, 0x00},
663 {0x5180, 0x00},
664 {0x5181, 0x10},
665 {0x5182, 0x07},
666 {0x5183, 0x8f},
667 {0x5184, 0x03},
668 {0x5208, 0xC2},
669 {0x5820, 0xc5},
670 {0x5854, 0x00},
671 {0x58cb, 0x03},
672 {0x5bd0, 0x15},
673 {0x5bd1, 0x02},
674 {0x5c0e, 0x11},
675 {0x5c11, 0x00},
676 {0x5c16, 0x02},
677 {0x5c17, 0x01},
678 {0x5c1a, 0x04},
679 {0x5c1b, 0x03},
680 {0x5c21, 0x10},
681 {0x5c22, 0x10},
682 {0x5c23, 0x04},
683 {0x5c24, 0x0c},
684 {0x5c25, 0x04},
685 {0x5c26, 0x0c},
686 {0x5c27, 0x04},
687 {0x5c28, 0x0c},
688 {0x5c29, 0x04},
689 {0x5c2a, 0x0c},
690 {0x5c2b, 0x01},
691 {0x5c2c, 0x01},
692 {0x5c2e, 0x08},
693 {0x5c30, 0x04},
694 {0x5c35, 0x03},
695 {0x5c36, 0x03},
696 {0x5c37, 0x03},
697 {0x5c38, 0x03},
698 {0x5d00, 0xff},
699 {0x5d01, 0x0f},
700 {0x5d02, 0x80},
701 {0x5d03, 0x44},
702 {0x5d05, 0xfc},
703 {0x5d06, 0x0b},
704 {0x5d08, 0x10},
705 {0x5d09, 0x10},
706 {0x5d0a, 0x04},
707 {0x5d0b, 0x0c},
708 {0x5d0c, 0x04},
709 {0x5d0d, 0x0c},
710 {0x5d0e, 0x04},
711 {0x5d0f, 0x0c},
712 {0x5d10, 0x04},
713 {0x5d11, 0x0c},
714 {0x5d12, 0x01},
715 {0x5d13, 0x01},
716 {0x5d15, 0x10},
717 {0x5d16, 0x10},
718 {0x5d17, 0x10},
719 {0x5d18, 0x10},
720 {0x5d1a, 0x10},
721 {0x5d1b, 0x10},
722 {0x5d1c, 0x10},
723 {0x5d1d, 0x10},
724 {0x5d1e, 0x04},
725 {0x5d1f, 0x04},
726 {0x5d20, 0x04},
727 {0x5d27, 0x64},
728 {0x5d28, 0xc8},
729 {0x5d29, 0x96},
730 {0x5d2a, 0xff},
731 {0x5d2b, 0xc8},
732 {0x5d2c, 0xff},
733 {0x5d2d, 0x04},
734 {0x5d34, 0x00},
735 {0x5d35, 0x08},
736 {0x5d36, 0x00},
737 {0x5d37, 0x04},
738 {0x5d4a, 0x00},
739 {0x5d4c, 0x00},
740 {REG_NULL, 0x00},
741 };
742
743 /*
744 * Xclk 24Mhz
745 * max_framerate 30fps
746 */
747 static const struct regval ov16a1q_4656x3496_30fps_regs[] = {
748 {0x0100, 0x00},
749 {0x0305, 0x6b},
750 {0x0307, 0x00},
751 {0x4837, 0x0b},
752 {0x0329, 0x01},
753 {0x0344, 0x01},
754 {0x0345, 0x2c},
755 {0x034a, 0x07},
756 {0x3608, 0x9b},
757 {0x360a, 0x69},
758 {0x361a, 0x8b},
759 {0x361e, 0x30},
760 {0x3639, 0xa6},
761 {0x363a, 0xaa},
762 {0x3642, 0xa8},
763 {0x3654, 0x8a},
764 {0x3656, 0x0c},
765 {0x3663, 0x00},
766 {0x370e, 0x05},
767 {0x3712, 0x09},
768 {0x3713, 0x40},
769 {0x3714, 0xe4},
770 {0x37d0, 0x02},
771 {0x37d1, 0x10},
772 {0x37db, 0x08},
773 {0x3808, 0x12},
774 {0x3809, 0x30},
775 {0x380a, 0x0d},
776 {0x380b, 0xa8},
777 {0x380c, 0x03},
778 {0x380d, 0x52},
779 {0x380e, 0x0f},
780 {0x380f, 0x50},
781 {0x3814, 0x11},
782 {0x3815, 0x11},
783 {0x3820, 0x00},
784 {0x3821, 0x06},
785 {0x3822, 0x00},
786 {0x383c, 0x34},
787 {0x383f, 0x22},
788 {0x4015, 0x04},
789 {0x4016, 0x1b},
790 {0x4017, 0x04},
791 {0x4018, 0x0b},
792 {0x401b, 0x1f},
793 {0x401f, 0x38},
794 {0x4500, 0x20},
795 {0x4501, 0x6a},
796 {0x4502, 0xb4},
797 {0x4e05, 0x04},
798 {0x4e11, 0x06},
799 {0x4e1d, 0x30},
800 {0x4e26, 0x39},
801 {0x4e29, 0x6d},
802 {0x5000, 0x01},
803 {0x5001, 0x40},
804 {0x5003, 0x42},
805 {0x5820, 0xc5},
806 {0x5854, 0x00},
807 {0x5bd0, 0x15},
808 {0x5c0e, 0x11},
809 {0x5c11, 0x00},
810 {0x5c16, 0x02},
811 {0x5c17, 0x01},
812 {0x5c1a, 0x04},
813 {0x5c1b, 0x03},
814 {0x5c21, 0x10},
815 {0x5c22, 0x10},
816 {0x5c23, 0x04},
817 {0x5c24, 0x0c},
818 {0x5c25, 0x04},
819 {0x5c26, 0x0c},
820 {0x5c27, 0x04},
821 {0x5c28, 0x0c},
822 {0x5c29, 0x04},
823 {0x5c2a, 0x0c},
824 {0x5c2b, 0x01},
825 {0x5c2c, 0x01},
826 {0x5d01, 0x0f},
827 {0x5d08, 0x10},
828 {0x5d09, 0x10},
829 {0x5d0a, 0x04},
830 {0x5d0b, 0x0c},
831 {0x5d0c, 0x04},
832 {0x5d0d, 0x0c},
833 {0x5d0e, 0x04},
834 {0x5d0f, 0x0c},
835 {0x5d10, 0x04},
836 {0x5d11, 0x0c},
837 {0x5d12, 0x01},
838 {0x5d13, 0x01},
839 {0x3500, 0x00},
840 {0x3501, 0x0f},
841 {0x3502, 0x48},
842 {0x3508, 0x01},
843 {0x3509, 0x00},
844 {0x0100, 0x01},
845 {REG_NULL, 0x00},
846 };
847
848 static const struct regval ov16a1q_2328x1748_30fps_regs[] = {
849 {0x0100, 0x00},
850 {0x0305, 0x7a},
851 {0x0307, 0x01},
852 {0x4837, 0x15},
853 {0x0329, 0x01},
854 {0x0344, 0x01},
855 {0x0345, 0x2c},
856 {0x034a, 0x07},
857 {0x3608, 0x75},
858 {0x360a, 0x69},
859 {0x361a, 0x8b},
860 {0x361e, 0x30},
861 {0x3639, 0x93},
862 {0x363a, 0x99},
863 {0x3642, 0x98},
864 {0x3654, 0x8a},
865 {0x3656, 0x0c},
866 {0x3663, 0x00},
867 {0x370e, 0x05},
868 {0x3712, 0x08},
869 {0x3713, 0xc0},
870 {0x3714, 0xe2},
871 {0x37d0, 0x02},
872 {0x37d1, 0x10},
873 {0x37db, 0x04},
874 {0x3808, 0x09},
875 {0x3809, 0x18},
876 {0x380a, 0x06},
877 {0x380b, 0xd4},
878 {0x380c, 0x03},
879 {0x380d, 0x52},
880 {0x380e, 0x0f},
881 {0x380f, 0x50},
882 {0x3814, 0x22},
883 {0x3815, 0x22},
884 {0x3820, 0x01},
885 {0x3821, 0x0c},
886 {0x3822, 0x00},
887 {0x383c, 0x22},
888 {0x383f, 0x33},
889 {0x4015, 0x02},
890 {0x4016, 0x0d},
891 {0x4017, 0x00},
892 {0x4018, 0x07},
893 {0x401b, 0x1f},
894 {0x401f, 0xfe},
895 {0x4500, 0x20},
896 {0x4501, 0x6a},
897 {0x4502, 0xe4},
898 {0x4e05, 0x04},
899 {0x4e11, 0x06},
900 {0x4e1d, 0x25},
901 {0x4e26, 0x44},
902 {0x4e29, 0x6d},
903 {0x5000, 0x09},
904 {0x5001, 0x42},
905 {0x5003, 0x42},
906 {0x5820, 0xc5},
907 {0x5854, 0x00},
908 {0x5bd0, 0x19},
909 {0x5c0e, 0x13},
910 {0x5c11, 0x00},
911 {0x5c16, 0x01},
912 {0x5c17, 0x00},
913 {0x5c1a, 0x00},
914 {0x5c1b, 0x00},
915 {0x5c21, 0x08},
916 {0x5c22, 0x08},
917 {0x5c23, 0x02},
918 {0x5c24, 0x06},
919 {0x5c25, 0x02},
920 {0x5c26, 0x06},
921 {0x5c27, 0x02},
922 {0x5c28, 0x06},
923 {0x5c29, 0x02},
924 {0x5c2a, 0x06},
925 {0x5c2b, 0x00},
926 {0x5c2c, 0x00},
927 {0x5d01, 0x07},
928 {0x5d08, 0x08},
929 {0x5d09, 0x08},
930 {0x5d0a, 0x02},
931 {0x5d0b, 0x06},
932 {0x5d0c, 0x02},
933 {0x5d0d, 0x06},
934 {0x5d0e, 0x02},
935 {0x5d0f, 0x06},
936 {0x5d10, 0x02},
937 {0x5d11, 0x06},
938 {0x5d12, 0x00},
939 {0x5d13, 0x00},
940 {0x3500, 0x00},
941 {0x3501, 0x0f},
942 {0x3502, 0x48},
943 {0x3508, 0x01},
944 {0x3509, 0x00},
945 {0x0100, 0x01},
946 //{0x0100, 0x01},
947 {REG_NULL, 0x00},
948 };
949
950 static const struct ov16a1q_mode supported_modes[] = {
951 {
952 .width = 4656,
953 .height = 3496,
954 .max_fps = {
955 .numerator = 10000,
956 .denominator = 300000,
957 },
958 .exp_def = 0x0f4a,
959 .hts_def = 0x0352 * 6,
960 .vts_def = 0x0f51,
961 .bpp = 10,
962 .reg_list = ov16a1q_4656x3496_30fps_regs,
963 .link_freq_idx = 0,
964 .hdr_mode = NO_HDR,
965 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
966 },
967 {
968 .width = 2328,
969 .height = 1748,
970 .max_fps = {
971 .numerator = 10000,
972 .denominator = 300000,
973 },
974 .exp_def = 0x0f4a,
975 .hts_def = 0x0352 * 3,
976 .vts_def = 0x0f50,
977 .bpp = 10,
978 .reg_list = ov16a1q_2328x1748_30fps_regs,
979 .link_freq_idx = 1,
980 .hdr_mode = NO_HDR,
981 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
982 },
983 };
984
985 static const s64 link_freq_items[] = {
986 OV16A1Q_LINK_FREQ_726MHZ,
987 OV16A1Q_LINK_FREQ_378MHZ,
988 };
989
990 static const char * const ov16a1q_test_pattern_menu[] = {
991 "Disabled",
992 "Vertical Color Bar Type 1",
993 "Vertical Color Bar Type 2",
994 "Vertical Color Bar Type 3",
995 "Vertical Color Bar Type 4"
996 };
997
998 /* Write registers up to 4 at a time */
ov16a1q_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)999 static int ov16a1q_write_reg(struct i2c_client *client, u16 reg,
1000 u32 len, u32 val)
1001 {
1002 u32 buf_i, val_i;
1003 u8 buf[6];
1004 u8 *val_p;
1005 __be32 val_be;
1006
1007 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
1008
1009 if (len > 4)
1010 return -EINVAL;
1011
1012 buf[0] = reg >> 8;
1013 buf[1] = reg & 0xff;
1014
1015 val_be = cpu_to_be32(val);
1016 val_p = (u8 *)&val_be;
1017 buf_i = 2;
1018 val_i = 4 - len;
1019
1020 while (val_i < 4)
1021 buf[buf_i++] = val_p[val_i++];
1022
1023 if (i2c_master_send(client, buf, len + 2) != len + 2)
1024 return -EIO;
1025
1026 return 0;
1027 }
1028
ov16a1q_write_array(struct i2c_client * client,const struct regval * regs)1029 static int ov16a1q_write_array(struct i2c_client *client,
1030 const struct regval *regs)
1031 {
1032 u32 i;
1033 int ret = 0;
1034
1035 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1036 ret = ov16a1q_write_reg(client, regs[i].addr,
1037 OV16A1Q_REG_VALUE_08BIT,
1038 regs[i].val);
1039
1040 return ret;
1041 }
1042
1043 /* Read registers up to 4 at a time */
ov16a1q_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1044 static int ov16a1q_read_reg(struct i2c_client *client, u16 reg,
1045 unsigned int len, u32 *val)
1046 {
1047 struct i2c_msg msgs[2];
1048 u8 *data_be_p;
1049 __be32 data_be = 0;
1050 __be16 reg_addr_be = cpu_to_be16(reg);
1051 int ret;
1052
1053 if (len > 4 || !len)
1054 return -EINVAL;
1055
1056 data_be_p = (u8 *)&data_be;
1057 /* Write register address */
1058 msgs[0].addr = client->addr;
1059 msgs[0].flags = 0;
1060 msgs[0].len = 2;
1061 msgs[0].buf = (u8 *)®_addr_be;
1062
1063 /* Read data from register */
1064 msgs[1].addr = client->addr;
1065 msgs[1].flags = I2C_M_RD;
1066 msgs[1].len = len;
1067 msgs[1].buf = &data_be_p[4 - len];
1068
1069 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1070 if (ret != ARRAY_SIZE(msgs))
1071 return -EIO;
1072
1073 *val = be32_to_cpu(data_be);
1074
1075 return 0;
1076 }
1077
ov16a1q_get_reso_dist(const struct ov16a1q_mode * mode,struct v4l2_mbus_framefmt * framefmt)1078 static int ov16a1q_get_reso_dist(const struct ov16a1q_mode *mode,
1079 struct v4l2_mbus_framefmt *framefmt)
1080 {
1081 return abs(mode->width - framefmt->width) +
1082 abs(mode->height - framefmt->height);
1083 }
1084
1085 static const struct ov16a1q_mode *
ov16a1q_find_best_fit(struct v4l2_subdev_format * fmt)1086 ov16a1q_find_best_fit(struct v4l2_subdev_format *fmt)
1087 {
1088 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1089 int dist;
1090 int cur_best_fit = 0;
1091 int cur_best_fit_dist = -1;
1092 unsigned int i;
1093
1094 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1095 dist = ov16a1q_get_reso_dist(&supported_modes[i], framefmt);
1096 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1097 cur_best_fit_dist = dist;
1098 cur_best_fit = i;
1099 }
1100 }
1101
1102 return &supported_modes[cur_best_fit];
1103 }
1104
ov16a1q_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1105 static int ov16a1q_set_fmt(struct v4l2_subdev *sd,
1106 struct v4l2_subdev_pad_config *cfg,
1107 struct v4l2_subdev_format *fmt)
1108 {
1109 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1110 const struct ov16a1q_mode *mode;
1111 s64 h_blank, vblank_def;
1112 u64 pixel_rate = 0;
1113 u32 lane_num = OV16A1Q_LANES;
1114
1115 mutex_lock(&ov16a1q->mutex);
1116
1117 mode = ov16a1q_find_best_fit(fmt);
1118 fmt->format.code = OV16A1Q_MEDIA_BUS_FMT;
1119 fmt->format.width = mode->width;
1120 fmt->format.height = mode->height;
1121 fmt->format.field = V4L2_FIELD_NONE;
1122 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1123 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1124 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1125 #else
1126 mutex_unlock(&ov16a1q->mutex);
1127 return -ENOTTY;
1128 #endif
1129 } else {
1130 ov16a1q->cur_mode = mode;
1131 h_blank = mode->hts_def - mode->width;
1132 __v4l2_ctrl_modify_range(ov16a1q->hblank, h_blank,
1133 h_blank, 1, h_blank);
1134 vblank_def = mode->vts_def - mode->height;
1135 __v4l2_ctrl_modify_range(ov16a1q->vblank, vblank_def,
1136 OV16A1Q_VTS_MAX - mode->height,
1137 1, vblank_def);
1138 __v4l2_ctrl_s_ctrl(ov16a1q->vblank, vblank_def);
1139 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1140
1141 __v4l2_ctrl_s_ctrl_int64(ov16a1q->pixel_rate,
1142 pixel_rate);
1143 __v4l2_ctrl_s_ctrl(ov16a1q->link_freq,
1144 mode->link_freq_idx);
1145 }
1146 dev_info(&ov16a1q->client->dev, "%s: mode->link_freq_idx(%d)",
1147 __func__, mode->link_freq_idx);
1148
1149 mutex_unlock(&ov16a1q->mutex);
1150
1151 return 0;
1152 }
1153
ov16a1q_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1154 static int ov16a1q_get_fmt(struct v4l2_subdev *sd,
1155 struct v4l2_subdev_pad_config *cfg,
1156 struct v4l2_subdev_format *fmt)
1157 {
1158 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1159 const struct ov16a1q_mode *mode = ov16a1q->cur_mode;
1160
1161 mutex_lock(&ov16a1q->mutex);
1162 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1163 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1164 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1165 #else
1166 mutex_unlock(&ov16a1q->mutex);
1167 return -ENOTTY;
1168 #endif
1169 } else {
1170 fmt->format.width = mode->width;
1171 fmt->format.height = mode->height;
1172 fmt->format.code = OV16A1Q_MEDIA_BUS_FMT;
1173 fmt->format.field = V4L2_FIELD_NONE;
1174 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1175 fmt->reserved[0] = mode->vc[fmt->pad];
1176 else
1177 fmt->reserved[0] = mode->vc[PAD0];
1178 }
1179 mutex_unlock(&ov16a1q->mutex);
1180
1181 return 0;
1182 }
1183
ov16a1q_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1184 static int ov16a1q_enum_mbus_code(struct v4l2_subdev *sd,
1185 struct v4l2_subdev_pad_config *cfg,
1186 struct v4l2_subdev_mbus_code_enum *code)
1187 {
1188 if (code->index != 0)
1189 return -EINVAL;
1190 code->code = OV16A1Q_MEDIA_BUS_FMT;
1191
1192 return 0;
1193 }
1194
ov16a1q_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1195 static int ov16a1q_enum_frame_sizes(struct v4l2_subdev *sd,
1196 struct v4l2_subdev_pad_config *cfg,
1197 struct v4l2_subdev_frame_size_enum *fse)
1198 {
1199 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1200
1201 if (fse->index >= ov16a1q->cfg_num)
1202 return -EINVAL;
1203
1204 if (fse->code != OV16A1Q_MEDIA_BUS_FMT)
1205 return -EINVAL;
1206
1207 fse->min_width = supported_modes[fse->index].width;
1208 fse->max_width = supported_modes[fse->index].width;
1209 fse->max_height = supported_modes[fse->index].height;
1210 fse->min_height = supported_modes[fse->index].height;
1211
1212 return 0;
1213 }
1214
ov16a1q_enable_test_pattern(struct ov16a1q * ov16a1q,u32 pattern)1215 static int ov16a1q_enable_test_pattern(struct ov16a1q *ov16a1q, u32 pattern)
1216 {
1217 u32 val;
1218
1219 if (pattern)
1220 val = ((pattern - 1) << 4) | OV16A1Q_TEST_PATTERN_ENABLE;
1221 else
1222 val = OV16A1Q_TEST_PATTERN_DISABLE;
1223
1224 return ov16a1q_write_reg(ov16a1q->client,
1225 OV16A1Q_REG_TEST_PATTERN,
1226 OV16A1Q_REG_VALUE_08BIT,
1227 val);
1228 }
1229
ov16a1q_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1230 static int ov16a1q_g_frame_interval(struct v4l2_subdev *sd,
1231 struct v4l2_subdev_frame_interval *fi)
1232 {
1233 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1234 const struct ov16a1q_mode *mode = ov16a1q->cur_mode;
1235
1236 fi->interval = mode->max_fps;
1237
1238 return 0;
1239 }
1240
ov16a1q_get_module_inf(struct ov16a1q * ov16a1q,struct rkmodule_inf * inf)1241 static void ov16a1q_get_module_inf(struct ov16a1q *ov16a1q,
1242 struct rkmodule_inf *inf)
1243 {
1244 memset(inf, 0, sizeof(*inf));
1245 strscpy(inf->base.sensor, OV16A1Q_NAME, sizeof(inf->base.sensor));
1246 strscpy(inf->base.module, ov16a1q->module_name,
1247 sizeof(inf->base.module));
1248 strscpy(inf->base.lens, ov16a1q->len_name, sizeof(inf->base.lens));
1249 }
1250
ov16a1q_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1251 static long ov16a1q_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1252 {
1253 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1254 struct rkmodule_hdr_cfg *hdr_cfg;
1255 long ret = 0;
1256 u32 i, h, w;
1257 u32 stream = 0;
1258
1259 switch (cmd) {
1260 case RKMODULE_SET_HDR_CFG:
1261 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1262 w = ov16a1q->cur_mode->width;
1263 h = ov16a1q->cur_mode->height;
1264 for (i = 0; i < ov16a1q->cfg_num; i++) {
1265 if (w == supported_modes[i].width &&
1266 h == supported_modes[i].height &&
1267 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1268 ov16a1q->cur_mode = &supported_modes[i];
1269 break;
1270 }
1271 }
1272 if (i == ov16a1q->cfg_num) {
1273 dev_err(&ov16a1q->client->dev,
1274 "not find hdr mode:%d %dx%d config\n",
1275 hdr_cfg->hdr_mode, w, h);
1276 ret = -EINVAL;
1277 } else {
1278 w = ov16a1q->cur_mode->hts_def - ov16a1q->cur_mode->width;
1279 h = ov16a1q->cur_mode->vts_def - ov16a1q->cur_mode->height;
1280 __v4l2_ctrl_modify_range(ov16a1q->hblank, w, w, 1, w);
1281 __v4l2_ctrl_modify_range(ov16a1q->vblank, h,
1282 OV16A1Q_VTS_MAX - ov16a1q->cur_mode->height,
1283 1, h);
1284 dev_info(&ov16a1q->client->dev,
1285 "sensor mode: %d\n",
1286 ov16a1q->cur_mode->hdr_mode);
1287 }
1288 break;
1289 case RKMODULE_GET_HDR_CFG:
1290 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1291 hdr_cfg->esp.mode = HDR_NORMAL_VC;
1292 hdr_cfg->hdr_mode = ov16a1q->cur_mode->hdr_mode;
1293 break;
1294 case RKMODULE_GET_MODULE_INFO:
1295 ov16a1q_get_module_inf(ov16a1q, (struct rkmodule_inf *)arg);
1296 break;
1297 case RKMODULE_SET_QUICK_STREAM:
1298
1299 stream = *((u32 *)arg);
1300
1301 if (stream)
1302 ret = ov16a1q_write_reg(ov16a1q->client,
1303 OV16A1Q_REG_CTRL_MODE,
1304 OV16A1Q_REG_VALUE_08BIT,
1305 OV16A1Q_MODE_STREAMING);
1306 else
1307 ret = ov16a1q_write_reg(ov16a1q->client,
1308 OV16A1Q_REG_CTRL_MODE,
1309 OV16A1Q_REG_VALUE_08BIT,
1310 OV16A1Q_MODE_SW_STANDBY);
1311 break;
1312 default:
1313 ret = -ENOIOCTLCMD;
1314 break;
1315 }
1316
1317 return ret;
1318 }
1319
1320 #ifdef CONFIG_COMPAT
ov16a1q_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1321 static long ov16a1q_compat_ioctl32(struct v4l2_subdev *sd,
1322 unsigned int cmd, unsigned long arg)
1323 {
1324 void __user *up = compat_ptr(arg);
1325 struct rkmodule_inf *inf;
1326 struct rkmodule_awb_cfg *cfg;
1327 struct rkmodule_hdr_cfg *hdr;
1328 long ret = 0;
1329 u32 stream = 0;
1330
1331 switch (cmd) {
1332 case RKMODULE_GET_MODULE_INFO:
1333 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1334 if (!inf) {
1335 ret = -ENOMEM;
1336 return ret;
1337 }
1338
1339 ret = ov16a1q_ioctl(sd, cmd, inf);
1340 if (!ret) {
1341 ret = copy_to_user(up, inf, sizeof(*inf));
1342 if (ret)
1343 ret = -EFAULT;
1344 }
1345 kfree(inf);
1346 break;
1347 case RKMODULE_AWB_CFG:
1348 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1349 if (!cfg) {
1350 ret = -ENOMEM;
1351 return ret;
1352 }
1353
1354 ret = copy_from_user(cfg, up, sizeof(*cfg));
1355 if (!ret)
1356 ret = ov16a1q_ioctl(sd, cmd, cfg);
1357 else
1358 ret = -EFAULT;
1359 kfree(cfg);
1360 break;
1361 case RKMODULE_GET_HDR_CFG:
1362 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1363 if (!hdr) {
1364 ret = -ENOMEM;
1365 return ret;
1366 }
1367
1368 ret = ov16a1q_ioctl(sd, cmd, hdr);
1369 if (!ret) {
1370 if (copy_to_user(up, hdr, sizeof(*hdr))) {
1371 kfree(hdr);
1372 return -EFAULT;
1373 }
1374 }
1375 kfree(hdr);
1376 break;
1377 case RKMODULE_SET_HDR_CFG:
1378 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1379 if (!hdr) {
1380 ret = -ENOMEM;
1381 return ret;
1382 }
1383
1384 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1385 kfree(hdr);
1386 return -EFAULT;
1387 }
1388 ret = ov16a1q_ioctl(sd, cmd, hdr);
1389 kfree(hdr);
1390 break;
1391 case RKMODULE_SET_QUICK_STREAM:
1392 ret = copy_from_user(&stream, up, sizeof(u32));
1393 if (!ret)
1394 ret = ov16a1q_ioctl(sd, cmd, &stream);
1395 else
1396 ret = -EFAULT;
1397 break;
1398 default:
1399 ret = -ENOIOCTLCMD;
1400 break;
1401 }
1402
1403 return ret;
1404 }
1405 #endif
1406
__ov16a1q_start_stream(struct ov16a1q * ov16a1q)1407 static int __ov16a1q_start_stream(struct ov16a1q *ov16a1q)
1408 {
1409 int ret;
1410
1411 ret = ov16a1q_write_array(ov16a1q->client, ov16a1q->cur_mode->reg_list);
1412 if (ret)
1413 return ret;
1414
1415 /* In case these controls are set before streaming */
1416 mutex_unlock(&ov16a1q->mutex);
1417 ret = v4l2_ctrl_handler_setup(&ov16a1q->ctrl_handler);
1418 mutex_lock(&ov16a1q->mutex);
1419 if (ret)
1420 return ret;
1421
1422 return ov16a1q_write_reg(ov16a1q->client,
1423 OV16A1Q_REG_CTRL_MODE,
1424 OV16A1Q_REG_VALUE_08BIT,
1425 OV16A1Q_MODE_STREAMING);
1426 }
1427
__ov16a1q_stop_stream(struct ov16a1q * ov16a1q)1428 static int __ov16a1q_stop_stream(struct ov16a1q *ov16a1q)
1429 {
1430 return ov16a1q_write_reg(ov16a1q->client,
1431 OV16A1Q_REG_CTRL_MODE,
1432 OV16A1Q_REG_VALUE_08BIT,
1433 OV16A1Q_MODE_SW_STANDBY);
1434 }
1435
ov16a1q_s_stream(struct v4l2_subdev * sd,int on)1436 static int ov16a1q_s_stream(struct v4l2_subdev *sd, int on)
1437 {
1438 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1439 struct i2c_client *client = ov16a1q->client;
1440 int ret = 0;
1441
1442 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1443 ov16a1q->cur_mode->width,
1444 ov16a1q->cur_mode->height,
1445 DIV_ROUND_CLOSEST(ov16a1q->cur_mode->max_fps.denominator,
1446 ov16a1q->cur_mode->max_fps.numerator));
1447
1448 mutex_lock(&ov16a1q->mutex);
1449 on = !!on;
1450 if (on == ov16a1q->streaming)
1451 goto unlock_and_return;
1452
1453 if (on) {
1454 ret = pm_runtime_get_sync(&client->dev);
1455 if (ret < 0) {
1456 pm_runtime_put_noidle(&client->dev);
1457 goto unlock_and_return;
1458 }
1459
1460 ret = __ov16a1q_start_stream(ov16a1q);
1461 if (ret) {
1462 v4l2_err(sd, "start stream failed while write regs\n");
1463 pm_runtime_put(&client->dev);
1464 goto unlock_and_return;
1465 }
1466 } else {
1467 __ov16a1q_stop_stream(ov16a1q);
1468 pm_runtime_put(&client->dev);
1469 }
1470
1471 ov16a1q->streaming = on;
1472
1473 unlock_and_return:
1474 mutex_unlock(&ov16a1q->mutex);
1475
1476 return ret;
1477 }
1478
ov16a1q_s_power(struct v4l2_subdev * sd,int on)1479 static int ov16a1q_s_power(struct v4l2_subdev *sd, int on)
1480 {
1481 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1482 struct i2c_client *client = ov16a1q->client;
1483 int ret = 0;
1484
1485 mutex_lock(&ov16a1q->mutex);
1486
1487 /* If the power state is not modified - no work to do. */
1488 if (ov16a1q->power_on == !!on)
1489 goto unlock_and_return;
1490
1491 if (on) {
1492 ret = pm_runtime_get_sync(&client->dev);
1493 if (ret < 0) {
1494 pm_runtime_put_noidle(&client->dev);
1495 goto unlock_and_return;
1496 }
1497
1498 ret = ov16a1q_write_array(ov16a1q->client, ov16a1q_global_regs);
1499 if (ret) {
1500 v4l2_err(sd, "could not set init registers\n");
1501 pm_runtime_put_noidle(&client->dev);
1502 goto unlock_and_return;
1503 }
1504
1505 ov16a1q->power_on = true;
1506 } else {
1507 pm_runtime_put(&client->dev);
1508 ov16a1q->power_on = false;
1509 }
1510
1511 unlock_and_return:
1512 mutex_unlock(&ov16a1q->mutex);
1513
1514 return ret;
1515 }
1516
1517 /* Calculate the delay in us by clock rate and clock cycles */
ov16a1q_cal_delay(u32 cycles)1518 static inline u32 ov16a1q_cal_delay(u32 cycles)
1519 {
1520 return DIV_ROUND_UP(cycles, OV16A1Q_XVCLK_FREQ / 1000 / 1000);
1521 }
1522
__ov16a1q_power_on(struct ov16a1q * ov16a1q)1523 static int __ov16a1q_power_on(struct ov16a1q *ov16a1q)
1524 {
1525 int ret;
1526 u32 delay_us;
1527 struct device *dev = &ov16a1q->client->dev;
1528
1529 if (!IS_ERR(ov16a1q->power_gpio))
1530 gpiod_set_value_cansleep(ov16a1q->power_gpio, 1);
1531
1532 usleep_range(1000, 2000);
1533
1534 if (!IS_ERR_OR_NULL(ov16a1q->pins_default)) {
1535 ret = pinctrl_select_state(ov16a1q->pinctrl,
1536 ov16a1q->pins_default);
1537 if (ret < 0)
1538 dev_err(dev, "could not set pins\n");
1539 }
1540 ret = clk_set_rate(ov16a1q->xvclk, OV16A1Q_XVCLK_FREQ);
1541 if (ret < 0)
1542 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1543 if (clk_get_rate(ov16a1q->xvclk) != OV16A1Q_XVCLK_FREQ)
1544 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1545 ret = clk_prepare_enable(ov16a1q->xvclk);
1546 if (ret < 0) {
1547 dev_err(dev, "Failed to enable xvclk\n");
1548 return ret;
1549 }
1550 if (!IS_ERR(ov16a1q->reset_gpio))
1551 gpiod_set_value_cansleep(ov16a1q->reset_gpio, 0);
1552
1553 ret = regulator_bulk_enable(OV16A1Q_NUM_SUPPLIES, ov16a1q->supplies);
1554 if (ret < 0) {
1555 dev_err(dev, "Failed to enable regulators\n");
1556 goto disable_clk;
1557 }
1558
1559 if (!IS_ERR(ov16a1q->reset_gpio))
1560 gpiod_set_value_cansleep(ov16a1q->reset_gpio, 1);
1561
1562 usleep_range(5000, 6000);
1563 if (!IS_ERR(ov16a1q->pwdn_gpio))
1564 gpiod_set_value_cansleep(ov16a1q->pwdn_gpio, 1);
1565
1566 /* 8192 cycles prior to first SCCB transaction */
1567 delay_us = ov16a1q_cal_delay(8192);
1568 usleep_range(delay_us * 2, delay_us * 3);
1569
1570 return 0;
1571
1572 disable_clk:
1573 clk_disable_unprepare(ov16a1q->xvclk);
1574
1575 return ret;
1576 }
1577
__ov16a1q_power_off(struct ov16a1q * ov16a1q)1578 static void __ov16a1q_power_off(struct ov16a1q *ov16a1q)
1579 {
1580 int ret;
1581 struct device *dev = &ov16a1q->client->dev;
1582
1583 if (!IS_ERR(ov16a1q->pwdn_gpio))
1584 gpiod_set_value_cansleep(ov16a1q->pwdn_gpio, 0);
1585 clk_disable_unprepare(ov16a1q->xvclk);
1586 if (!IS_ERR(ov16a1q->reset_gpio))
1587 gpiod_set_value_cansleep(ov16a1q->reset_gpio, 0);
1588
1589 if (!IS_ERR_OR_NULL(ov16a1q->pins_sleep)) {
1590 ret = pinctrl_select_state(ov16a1q->pinctrl,
1591 ov16a1q->pins_sleep);
1592 if (ret < 0)
1593 dev_dbg(dev, "could not set pins\n");
1594 }
1595 if (!IS_ERR(ov16a1q->power_gpio))
1596 gpiod_set_value_cansleep(ov16a1q->power_gpio, 0);
1597
1598 regulator_bulk_disable(OV16A1Q_NUM_SUPPLIES, ov16a1q->supplies);
1599 }
1600
ov16a1q_runtime_resume(struct device * dev)1601 static int ov16a1q_runtime_resume(struct device *dev)
1602 {
1603 struct i2c_client *client = to_i2c_client(dev);
1604 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1605 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1606
1607 return __ov16a1q_power_on(ov16a1q);
1608 }
1609
ov16a1q_runtime_suspend(struct device * dev)1610 static int ov16a1q_runtime_suspend(struct device *dev)
1611 {
1612 struct i2c_client *client = to_i2c_client(dev);
1613 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1614 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1615
1616 __ov16a1q_power_off(ov16a1q);
1617
1618 return 0;
1619 }
1620
1621 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov16a1q_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1622 static int ov16a1q_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1623 {
1624 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1625 struct v4l2_mbus_framefmt *try_fmt =
1626 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1627 const struct ov16a1q_mode *def_mode = &supported_modes[0];
1628
1629 mutex_lock(&ov16a1q->mutex);
1630 /* Initialize try_fmt */
1631 try_fmt->width = def_mode->width;
1632 try_fmt->height = def_mode->height;
1633 try_fmt->code = OV16A1Q_MEDIA_BUS_FMT;
1634 try_fmt->field = V4L2_FIELD_NONE;
1635
1636 mutex_unlock(&ov16a1q->mutex);
1637 /* No crop or compose */
1638
1639 return 0;
1640 }
1641 #endif
1642
ov16a1q_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1643 static int ov16a1q_enum_frame_interval(struct v4l2_subdev *sd,
1644 struct v4l2_subdev_pad_config *cfg,
1645 struct v4l2_subdev_frame_interval_enum *fie)
1646 {
1647 if (fie->index >= ARRAY_SIZE(supported_modes))
1648 return -EINVAL;
1649
1650 fie->code = OV16A1Q_MEDIA_BUS_FMT;
1651 fie->width = supported_modes[fie->index].width;
1652 fie->height = supported_modes[fie->index].height;
1653 fie->interval = supported_modes[fie->index].max_fps;
1654 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1655
1656 return 0;
1657 }
1658
ov16a1q_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1659 static int ov16a1q_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1660 struct v4l2_mbus_config *config)
1661 {
1662 if (2 == OV16A1Q_LANES) {
1663 config->type = V4L2_MBUS_CSI2_DPHY;
1664 config->flags = V4L2_MBUS_CSI2_2_LANE |
1665 V4L2_MBUS_CSI2_CHANNEL_0 |
1666 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1667 } else if (4 == OV16A1Q_LANES) {
1668 config->type = V4L2_MBUS_CSI2_DPHY;
1669 config->flags = V4L2_MBUS_CSI2_4_LANE |
1670 V4L2_MBUS_CSI2_CHANNEL_0 |
1671 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1672 }
1673
1674 return 0;
1675 }
1676
1677 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1678 #define DST_WIDTH_2320 2320
1679 #define DST_HEIGHT_1744 1744
1680 /*
1681 * The resolution of the driver configuration needs to be exactly
1682 * the same as the current output resolution of the sensor,
1683 * the input width of the isp needs to be 16 aligned,
1684 * the input height of the isp needs to be 8 aligned.
1685 * Can be cropped to standard resolution by this function,
1686 * otherwise it will crop out strange resolution according
1687 * to the alignment rules.
1688 */
ov16a1q_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1689 static int ov16a1q_get_selection(struct v4l2_subdev *sd,
1690 struct v4l2_subdev_pad_config *cfg,
1691 struct v4l2_subdev_selection *sel)
1692 {
1693 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
1694
1695 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1696 if (ov16a1q->cur_mode->width == 2328) {
1697 sel->r.left = CROP_START(ov16a1q->cur_mode->width, DST_WIDTH_2320);
1698 sel->r.width = DST_WIDTH_2320;
1699 sel->r.top = CROP_START(ov16a1q->cur_mode->height, DST_HEIGHT_1744);
1700 sel->r.height = DST_HEIGHT_1744;
1701 } else {
1702 sel->r.left = 0;
1703 sel->r.width = ov16a1q->cur_mode->width;
1704 sel->r.top = 0;
1705 sel->r.height = ov16a1q->cur_mode->height;
1706 }
1707 return 0;
1708 }
1709
1710 return -EINVAL;
1711 }
1712
1713 static const struct dev_pm_ops ov16a1q_pm_ops = {
1714 SET_RUNTIME_PM_OPS(ov16a1q_runtime_suspend,
1715 ov16a1q_runtime_resume, NULL)
1716 };
1717
1718 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1719 static const struct v4l2_subdev_internal_ops ov16a1q_internal_ops = {
1720 .open = ov16a1q_open,
1721 };
1722 #endif
1723
1724 static const struct v4l2_subdev_core_ops ov16a1q_core_ops = {
1725 .s_power = ov16a1q_s_power,
1726 .ioctl = ov16a1q_ioctl,
1727 #ifdef CONFIG_COMPAT
1728 .compat_ioctl32 = ov16a1q_compat_ioctl32,
1729 #endif
1730 };
1731
1732 static const struct v4l2_subdev_video_ops ov16a1q_video_ops = {
1733 .s_stream = ov16a1q_s_stream,
1734 .g_frame_interval = ov16a1q_g_frame_interval,
1735 };
1736
1737 static const struct v4l2_subdev_pad_ops ov16a1q_pad_ops = {
1738 .enum_mbus_code = ov16a1q_enum_mbus_code,
1739 .enum_frame_size = ov16a1q_enum_frame_sizes,
1740 .enum_frame_interval = ov16a1q_enum_frame_interval,
1741 .get_fmt = ov16a1q_get_fmt,
1742 .set_fmt = ov16a1q_set_fmt,
1743 .get_selection = ov16a1q_get_selection,
1744 .get_mbus_config = ov16a1q_g_mbus_config,
1745 };
1746
1747 static const struct v4l2_subdev_ops ov16a1q_subdev_ops = {
1748 .core = &ov16a1q_core_ops,
1749 .video = &ov16a1q_video_ops,
1750 .pad = &ov16a1q_pad_ops,
1751 };
1752
ov16a1q_set_ctrl(struct v4l2_ctrl * ctrl)1753 static int ov16a1q_set_ctrl(struct v4l2_ctrl *ctrl)
1754 {
1755 struct ov16a1q *ov16a1q = container_of(ctrl->handler,
1756 struct ov16a1q, ctrl_handler);
1757 struct i2c_client *client = ov16a1q->client;
1758 s64 max;
1759 int ret = 0;
1760 u32 again, dgain;
1761 u32 val = 0, x_win = 0, y_win = 0;
1762
1763 /* Propagate change of current control to all related controls */
1764 switch (ctrl->id) {
1765 case V4L2_CID_VBLANK:
1766 /* Update max exposure while meeting expected vblanking */
1767 max = ov16a1q->cur_mode->height + ctrl->val - 4;
1768 __v4l2_ctrl_modify_range(ov16a1q->exposure,
1769 ov16a1q->exposure->minimum, max,
1770 ov16a1q->exposure->step,
1771 ov16a1q->exposure->default_value);
1772 break;
1773 }
1774
1775 if (!pm_runtime_get_if_in_use(&client->dev))
1776 return 0;
1777
1778 switch (ctrl->id) {
1779 case V4L2_CID_EXPOSURE:
1780 /* 4 least significant bits of expsoure are fractional part */
1781 ret |= ov16a1q_write_reg(ov16a1q->client,
1782 OV16A1Q_REG_EXPOSURE_H,
1783 OV16A1Q_REG_VALUE_24BIT,
1784 ctrl->val & 0x7fffff);
1785 dev_dbg(&client->dev, "set exposure 0x%x\n",
1786 ctrl->val);
1787 break;
1788 case V4L2_CID_ANALOGUE_GAIN:
1789 if (ctrl->val > 1984) {// >15.5x
1790 dgain = ctrl->val * 10 / 155;
1791 again = 1984;
1792 } else {
1793 dgain = 1024;
1794 again = ctrl->val;
1795 }
1796 ret |= ov16a1q_write_reg(ov16a1q->client,
1797 OV16A1Q_REG_AGAIN_H,
1798 OV16A1Q_REG_VALUE_16BIT,
1799 (again << 1) & 0x7ffe);
1800 ret |= ov16a1q_write_reg(ov16a1q->client,
1801 OV16A1Q_REG_DAGAIN_H_B,
1802 OV16A1Q_REG_VALUE_24BIT,
1803 (dgain << 6) & 0xfffc0);
1804
1805 dev_dbg(&client->dev, "set gain 0x%x set analog gain 0x%x digital gain 0x%x\n",
1806 ctrl->val, again, dgain);
1807 break;
1808 case V4L2_CID_VBLANK:
1809 ret = ov16a1q_write_reg(ov16a1q->client,
1810 OV16A1Q_REG_VTS_H,
1811 OV16A1Q_REG_VALUE_16BIT,
1812 ctrl->val + ov16a1q->cur_mode->height);
1813 break;
1814 case V4L2_CID_TEST_PATTERN:
1815 ret = ov16a1q_enable_test_pattern(ov16a1q, ctrl->val);
1816 break;
1817 case V4L2_CID_HFLIP:
1818 ret = ov16a1q_read_reg(ov16a1q->client, OV16A1Q_MIRROR_REG,
1819 OV16A1Q_REG_VALUE_08BIT,
1820 &val);
1821 if (ctrl->val)
1822 val |= MIRROR_BIT_MASK;
1823 else
1824 val &= ~MIRROR_BIT_MASK;
1825
1826 ret |= ov16a1q_read_reg(ov16a1q->client, OV16A1Q_REG_ISP_X_WIN,
1827 OV16A1Q_REG_VALUE_16BIT,
1828 &x_win);
1829
1830 if ((x_win == 0x0010) && (val & 0x04))
1831 x_win = 0x0011;
1832 else if ((x_win == 0x0011) && (!(val & 0x04)))
1833 x_win = 0x0010;
1834
1835 ret |= ov16a1q_write_reg(ov16a1q->client,
1836 OV16A1Q_GROUP_UPDATE_ADDRESS,
1837 OV16A1Q_REG_VALUE_08BIT,
1838 OV16A1Q_GROUP_UPDATE_START_DATA);
1839
1840 ret |= ov16a1q_write_reg(ov16a1q->client, OV16A1Q_MIRROR_REG,
1841 OV16A1Q_REG_VALUE_08BIT,
1842 val);
1843 ret |= ov16a1q_write_reg(ov16a1q->client, OV16A1Q_REG_ISP_X_WIN,
1844 OV16A1Q_REG_VALUE_16BIT,
1845 x_win);
1846
1847 ret |= ov16a1q_write_reg(ov16a1q->client,
1848 OV16A1Q_GROUP_UPDATE_ADDRESS,
1849 OV16A1Q_REG_VALUE_08BIT,
1850 OV16A1Q_GROUP_UPDATE_END_DATA);
1851 ret |= ov16a1q_write_reg(ov16a1q->client,
1852 OV16A1Q_GROUP_UPDATE_ADDRESS,
1853 OV16A1Q_REG_VALUE_08BIT,
1854 OV16A1Q_GROUP_UPDATE_LAUNCH);
1855 break;
1856 case V4L2_CID_VFLIP:
1857 ret = ov16a1q_read_reg(ov16a1q->client, OV16A1Q_FLIP_REG,
1858 OV16A1Q_REG_VALUE_08BIT,
1859 &val);
1860 if (ctrl->val)
1861 val |= FLIP_BIT_MASK;
1862 else
1863 val &= ~FLIP_BIT_MASK;
1864
1865 ret |= ov16a1q_read_reg(ov16a1q->client, OV16A1Q_REG_ISP_Y_WIN,
1866 OV16A1Q_REG_VALUE_16BIT,
1867 &y_win);
1868
1869 if ((y_win == 0x0004) && (val & 0x04))
1870 y_win = 0x0005;
1871 else if ((y_win == 0x0005) && (!(val & 0x04)))
1872 y_win = 0x0004;
1873
1874 ret |= ov16a1q_write_reg(ov16a1q->client,
1875 OV16A1Q_GROUP_UPDATE_ADDRESS,
1876 OV16A1Q_REG_VALUE_08BIT,
1877 OV16A1Q_GROUP_UPDATE_START_DATA);
1878
1879 ret |= ov16a1q_write_reg(ov16a1q->client, OV16A1Q_FLIP_REG,
1880 OV16A1Q_REG_VALUE_08BIT,
1881 val);
1882 ret |= ov16a1q_write_reg(ov16a1q->client, OV16A1Q_REG_ISP_Y_WIN,
1883 OV16A1Q_REG_VALUE_16BIT,
1884 y_win);
1885
1886 ret |= ov16a1q_write_reg(ov16a1q->client,
1887 OV16A1Q_GROUP_UPDATE_ADDRESS,
1888 OV16A1Q_REG_VALUE_08BIT,
1889 OV16A1Q_GROUP_UPDATE_END_DATA);
1890 ret |= ov16a1q_write_reg(ov16a1q->client,
1891 OV16A1Q_GROUP_UPDATE_ADDRESS,
1892 OV16A1Q_REG_VALUE_08BIT,
1893 OV16A1Q_GROUP_UPDATE_LAUNCH);
1894 break;
1895 default:
1896 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1897 __func__, ctrl->id, ctrl->val);
1898 break;
1899 }
1900
1901 pm_runtime_put(&client->dev);
1902
1903 return ret;
1904 }
1905
1906 static const struct v4l2_ctrl_ops ov16a1q_ctrl_ops = {
1907 .s_ctrl = ov16a1q_set_ctrl,
1908 };
1909
ov16a1q_initialize_controls(struct ov16a1q * ov16a1q)1910 static int ov16a1q_initialize_controls(struct ov16a1q *ov16a1q)
1911 {
1912 const struct ov16a1q_mode *mode;
1913 struct v4l2_ctrl_handler *handler;
1914 s64 exposure_max, vblank_def;
1915 u32 h_blank;
1916 int ret;
1917 u64 dst_pixel_rate = 0;
1918 u32 lane_num = OV16A1Q_LANES;
1919
1920 handler = &ov16a1q->ctrl_handler;
1921 mode = ov16a1q->cur_mode;
1922 ret = v4l2_ctrl_handler_init(handler, 9);
1923 if (ret)
1924 return ret;
1925 handler->lock = &ov16a1q->mutex;
1926
1927 ov16a1q->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1928 V4L2_CID_LINK_FREQ,
1929 0, 0, link_freq_items);
1930
1931 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1932
1933 ov16a1q->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1934 V4L2_CID_PIXEL_RATE,
1935 0, OV16A1Q_PIXEL_RATE,
1936 1, dst_pixel_rate);
1937
1938 __v4l2_ctrl_s_ctrl(ov16a1q->link_freq,
1939 mode->link_freq_idx);
1940
1941 h_blank = mode->hts_def - mode->width;
1942 ov16a1q->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1943 h_blank, h_blank, 1, h_blank);
1944 if (ov16a1q->hblank)
1945 ov16a1q->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1946
1947 vblank_def = mode->vts_def - mode->height;
1948 ov16a1q->vblank = v4l2_ctrl_new_std(handler, &ov16a1q_ctrl_ops,
1949 V4L2_CID_VBLANK, vblank_def,
1950 OV16A1Q_VTS_MAX - mode->height,
1951 1, vblank_def);
1952
1953 exposure_max = mode->vts_def - 4;
1954 ov16a1q->exposure = v4l2_ctrl_new_std(handler, &ov16a1q_ctrl_ops,
1955 V4L2_CID_EXPOSURE, OV16A1Q_EXPOSURE_MIN,
1956 exposure_max, OV16A1Q_EXPOSURE_STEP,
1957 mode->exp_def);
1958
1959 ov16a1q->anal_gain = v4l2_ctrl_new_std(handler, &ov16a1q_ctrl_ops,
1960 V4L2_CID_ANALOGUE_GAIN, OV16A1Q_GAIN_MIN,
1961 OV16A1Q_GAIN_MAX, OV16A1Q_GAIN_STEP,
1962 OV16A1Q_GAIN_DEFAULT);
1963
1964 ov16a1q->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1965 &ov16a1q_ctrl_ops, V4L2_CID_TEST_PATTERN,
1966 ARRAY_SIZE(ov16a1q_test_pattern_menu) - 1,
1967 0, 0, ov16a1q_test_pattern_menu);
1968
1969 ov16a1q->h_flip = v4l2_ctrl_new_std(handler, &ov16a1q_ctrl_ops,
1970 V4L2_CID_HFLIP, 0, 1, 1, 0);
1971
1972 ov16a1q->v_flip = v4l2_ctrl_new_std(handler, &ov16a1q_ctrl_ops,
1973 V4L2_CID_VFLIP, 0, 1, 1, 0);
1974
1975 if (handler->error) {
1976 ret = handler->error;
1977 dev_err(&ov16a1q->client->dev,
1978 "Failed to init controls(%d)\n", ret);
1979 goto err_free_handler;
1980 }
1981
1982 ov16a1q->subdev.ctrl_handler = handler;
1983
1984 return 0;
1985
1986 err_free_handler:
1987 v4l2_ctrl_handler_free(handler);
1988
1989 return ret;
1990 }
1991
ov16a1q_check_sensor_id(struct ov16a1q * ov16a1q,struct i2c_client * client)1992 static int ov16a1q_check_sensor_id(struct ov16a1q *ov16a1q,
1993 struct i2c_client *client)
1994 {
1995 struct device *dev = &ov16a1q->client->dev;
1996 u32 id = 0;
1997 int ret;
1998
1999 ret = ov16a1q_read_reg(client, OV16A1Q_REG_CHIP_ID,
2000 OV16A1Q_REG_VALUE_24BIT, &id);
2001 if (id != CHIP_ID) {
2002 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2003 return -ENODEV;
2004 }
2005
2006 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
2007
2008 return 0;
2009 }
2010
ov16a1q_configure_regulators(struct ov16a1q * ov16a1q)2011 static int ov16a1q_configure_regulators(struct ov16a1q *ov16a1q)
2012 {
2013 unsigned int i;
2014
2015 for (i = 0; i < OV16A1Q_NUM_SUPPLIES; i++)
2016 ov16a1q->supplies[i].supply = ov16a1q_supply_names[i];
2017
2018 return devm_regulator_bulk_get(&ov16a1q->client->dev,
2019 OV16A1Q_NUM_SUPPLIES,
2020 ov16a1q->supplies);
2021 }
2022
ov16a1q_probe(struct i2c_client * client,const struct i2c_device_id * id)2023 static int ov16a1q_probe(struct i2c_client *client,
2024 const struct i2c_device_id *id)
2025 {
2026 struct device *dev = &client->dev;
2027 struct device_node *node = dev->of_node;
2028 struct ov16a1q *ov16a1q;
2029 struct v4l2_subdev *sd;
2030 char facing[2];
2031 int ret;
2032 u32 i, hdr_mode = 0;
2033
2034 dev_info(dev, "driver version: %02x.%02x.%02x",
2035 DRIVER_VERSION >> 16,
2036 (DRIVER_VERSION & 0xff00) >> 8,
2037 DRIVER_VERSION & 0x00ff);
2038
2039 ov16a1q = devm_kzalloc(dev, sizeof(*ov16a1q), GFP_KERNEL);
2040 if (!ov16a1q)
2041 return -ENOMEM;
2042
2043 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2044 &ov16a1q->module_index);
2045 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2046 &ov16a1q->module_facing);
2047 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2048 &ov16a1q->module_name);
2049 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2050 &ov16a1q->len_name);
2051 if (ret) {
2052 dev_err(dev, "could not get module information!\n");
2053 return -EINVAL;
2054 }
2055
2056 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
2057 &hdr_mode);
2058 if (ret) {
2059 hdr_mode = NO_HDR;
2060 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2061 }
2062 ov16a1q->cfg_num = ARRAY_SIZE(supported_modes);
2063 for (i = 0; i < ov16a1q->cfg_num; i++) {
2064 if (hdr_mode == supported_modes[i].hdr_mode) {
2065 ov16a1q->cur_mode = &supported_modes[i];
2066 break;
2067 }
2068 }
2069
2070 ov16a1q->client = client;
2071
2072 ov16a1q->xvclk = devm_clk_get(dev, "xvclk");
2073 if (IS_ERR(ov16a1q->xvclk)) {
2074 dev_err(dev, "Failed to get xvclk\n");
2075 return -EINVAL;
2076 }
2077
2078 ov16a1q->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
2079 if (IS_ERR(ov16a1q->power_gpio))
2080 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
2081
2082 ov16a1q->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2083 if (IS_ERR(ov16a1q->reset_gpio))
2084 dev_warn(dev, "Failed to get reset-gpios\n");
2085
2086 ov16a1q->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2087 if (IS_ERR(ov16a1q->pwdn_gpio))
2088 dev_warn(dev, "Failed to get pwdn-gpios\n");
2089
2090 ret = ov16a1q_configure_regulators(ov16a1q);
2091 if (ret) {
2092 dev_err(dev, "Failed to get power regulators\n");
2093 return ret;
2094 }
2095
2096 ov16a1q->pinctrl = devm_pinctrl_get(dev);
2097 if (!IS_ERR(ov16a1q->pinctrl)) {
2098 ov16a1q->pins_default =
2099 pinctrl_lookup_state(ov16a1q->pinctrl,
2100 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2101 if (IS_ERR(ov16a1q->pins_default))
2102 dev_err(dev, "could not get default pinstate\n");
2103
2104 ov16a1q->pins_sleep =
2105 pinctrl_lookup_state(ov16a1q->pinctrl,
2106 OF_CAMERA_PINCTRL_STATE_SLEEP);
2107 if (IS_ERR(ov16a1q->pins_sleep))
2108 dev_err(dev, "could not get sleep pinstate\n");
2109 }
2110
2111 mutex_init(&ov16a1q->mutex);
2112
2113 sd = &ov16a1q->subdev;
2114 v4l2_i2c_subdev_init(sd, client, &ov16a1q_subdev_ops);
2115 ret = ov16a1q_initialize_controls(ov16a1q);
2116 if (ret)
2117 goto err_destroy_mutex;
2118
2119 ret = __ov16a1q_power_on(ov16a1q);
2120 if (ret)
2121 goto err_free_handler;
2122
2123 ret = ov16a1q_check_sensor_id(ov16a1q, client);
2124 if (ret)
2125 goto err_power_off;
2126
2127 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2128 sd->internal_ops = &ov16a1q_internal_ops;
2129 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2130 #endif
2131 #if defined(CONFIG_MEDIA_CONTROLLER)
2132 ov16a1q->pad.flags = MEDIA_PAD_FL_SOURCE;
2133 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2134 ret = media_entity_pads_init(&sd->entity, 1, &ov16a1q->pad);
2135 if (ret < 0)
2136 goto err_power_off;
2137 #endif
2138
2139 memset(facing, 0, sizeof(facing));
2140 if (strcmp(ov16a1q->module_facing, "back") == 0)
2141 facing[0] = 'b';
2142 else
2143 facing[0] = 'f';
2144
2145 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2146 ov16a1q->module_index, facing,
2147 OV16A1Q_NAME, dev_name(sd->dev));
2148 ret = v4l2_async_register_subdev_sensor_common(sd);
2149 if (ret) {
2150 dev_err(dev, "v4l2 async register subdev failed\n");
2151 goto err_clean_entity;
2152 }
2153
2154 pm_runtime_set_active(dev);
2155 pm_runtime_enable(dev);
2156 pm_runtime_idle(dev);
2157
2158 return 0;
2159
2160 err_clean_entity:
2161 #if defined(CONFIG_MEDIA_CONTROLLER)
2162 media_entity_cleanup(&sd->entity);
2163 #endif
2164 err_power_off:
2165 __ov16a1q_power_off(ov16a1q);
2166 err_free_handler:
2167 v4l2_ctrl_handler_free(&ov16a1q->ctrl_handler);
2168 err_destroy_mutex:
2169 mutex_destroy(&ov16a1q->mutex);
2170
2171 return ret;
2172 }
2173
ov16a1q_remove(struct i2c_client * client)2174 static int ov16a1q_remove(struct i2c_client *client)
2175 {
2176 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2177 struct ov16a1q *ov16a1q = to_ov16a1q(sd);
2178
2179 v4l2_async_unregister_subdev(sd);
2180 #if defined(CONFIG_MEDIA_CONTROLLER)
2181 media_entity_cleanup(&sd->entity);
2182 #endif
2183 v4l2_ctrl_handler_free(&ov16a1q->ctrl_handler);
2184 mutex_destroy(&ov16a1q->mutex);
2185
2186 pm_runtime_disable(&client->dev);
2187 if (!pm_runtime_status_suspended(&client->dev))
2188 __ov16a1q_power_off(ov16a1q);
2189 pm_runtime_set_suspended(&client->dev);
2190
2191 return 0;
2192 }
2193
2194 #if IS_ENABLED(CONFIG_OF)
2195 static const struct of_device_id ov16a1q_of_match[] = {
2196 { .compatible = "ovti,ov16a1q" },
2197 {},
2198 };
2199 MODULE_DEVICE_TABLE(of, ov16a1q_of_match);
2200 #endif
2201
2202 static const struct i2c_device_id ov16a1q_match_id[] = {
2203 { "ovti,ov16a1q", 0 },
2204 {},
2205 };
2206
2207 static struct i2c_driver ov16a1q_i2c_driver = {
2208 .driver = {
2209 .name = OV16A1Q_NAME,
2210 .pm = &ov16a1q_pm_ops,
2211 .of_match_table = of_match_ptr(ov16a1q_of_match),
2212 },
2213 .probe = &ov16a1q_probe,
2214 .remove = &ov16a1q_remove,
2215 .id_table = ov16a1q_match_id,
2216 };
2217
sensor_mod_init(void)2218 static int __init sensor_mod_init(void)
2219 {
2220 return i2c_add_driver(&ov16a1q_i2c_driver);
2221 }
2222
sensor_mod_exit(void)2223 static void __exit sensor_mod_exit(void)
2224 {
2225 i2c_del_driver(&ov16a1q_i2c_driver);
2226 }
2227
2228 device_initcall_sync(sensor_mod_init);
2229 module_exit(sensor_mod_exit);
2230
2231 MODULE_DESCRIPTION("OmniVision ov16a1q sensor driver");
2232 MODULE_LICENSE("GPL");
2233