1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov16a10 camera driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 *
9 */
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/compat.h>
23 #include <linux/rk-camera-module.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29
30 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
31
32 #ifndef V4L2_CID_DIGITAL_GAIN
33 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34 #endif
35
36 #define OV16A10_LINK_FREQ_726MHZ 726000000U
37
38 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
39 #define OV16A10_PIXEL_RATE (OV16A10_LINK_FREQ_726MHZ * 2LL * 4LL / 10LL)
40 #define OV16A10_XVCLK_FREQ 24000000
41
42 #define CHIP_ID 0x561641
43 #define OV16A10_REG_CHIP_ID 0x300a
44
45 #define OV16A10_REG_CTRL_MODE 0x0100
46 #define OV16A10_MODE_SW_STANDBY 0x0
47 #define OV16A10_MODE_STREAMING BIT(0)
48
49 #define OV16A10_REG_EXPOSURE_H 0x3500
50 #define OV16A10_REG_EXPOSURE_M 0x3501
51 #define OV16A10_REG_EXPOSURE_L 0x3502
52 #define OV16A10_EXPOSURE_MIN 4
53 #define OV16A10_EXPOSURE_STEP 1
54 #define OV16A10_VTS_MAX 0x7fff
55
56 #define OV16A10_REG_AGAIN_H 0x3508
57 #define OV16A10_REG_AGAIN_L 0x3509
58 #define OV16A10_REG_DAGAIN_H_B 0x350A
59 #define OV16A10_REG_DAGAIN_M_B 0x350B
60 #define OV16A10_REG_DAGAIN_L_B 0x350C
61 #define OV16A10_GAIN_MIN 0x80
62 #define OV16A10_GAIN_MAX 0x3df61
63 #define OV16A10_GAIN_STEP 1
64 #define OV16A10_GAIN_DEFAULT 0x80
65
66 #define OV16A10_SOFTWARE_RESET_REG 0x0103
67 #define OV16A10_REG_ISP_X_WIN 0x3810
68 #define OV16A10_REG_ISP_Y_WIN 0x3812
69
70 #define OV16A10_GROUP_UPDATE_ADDRESS 0x3208
71 #define OV16A10_GROUP_UPDATE_START_DATA 0x00
72 #define OV16A10_GROUP_UPDATE_END_DATA 0x10
73 #define OV16A10_GROUP_UPDATE_LAUNCH 0xA0
74
75 #define OV16A10_REG_TEST_PATTERN 0x5081
76 #define OV16A10_TEST_PATTERN_ENABLE 0x01
77 #define OV16A10_TEST_PATTERN_DISABLE 0x0
78
79 #define OV16A10_REG_VTS_H 0x380e
80 #define OV16A10_REG_VTS_L 0x380f
81
82 #define OV16A10_FLIP_REG 0x3820
83 #define OV16A10_MIRROR_REG 0x3821
84 #define MIRROR_BIT_MASK BIT(2)
85 #define FLIP_BIT_MASK BIT(2)
86
87 #define OV16A10_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x7F)
88 #define OV16A10_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
89 #define OV16A10_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
90
91 #define OV16A10_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x7F)
92 #define OV16A10_FETCH_AGAIN_L(VAL) ((VAL) & 0xFE)
93
94 #define OV16A10_FETCH_DGAIN_H(VAL) (((VAL) >> 16) & 0x0F)
95 #define OV16A10_FETCH_DGAIN_M(VAL) (((VAL) >> 8) & 0xFF)
96 #define OV16A10_FETCH_DGAIN_L(VAL) ((VAL) & 0xC0)
97
98 #define OV16A10_FETCH_VTS_H(VAL) (((VAL) >> 8) & 0x7F)
99 #define OV16A10_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
100
101 #define REG_NULL 0xFFFF
102
103 #define OV16A10_REG_VALUE_08BIT 1
104 #define OV16A10_REG_VALUE_16BIT 2
105 #define OV16A10_REG_VALUE_24BIT 3
106
107 #define OV16A10_LANES 4
108 #define OV16A10_BITS_PER_SAMPLE 10
109
110 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
111 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
112 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
113
114 #define OV16A10_NAME "ov16a10"
115 #define OV16A10_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
116
117 static const char * const ov16a10_supply_names[] = {
118 "avdd", /* Analog power */
119 "dovdd", /* Digital I/O power */
120 "dvdd", /* Digital core power */
121 };
122
123 #define OV16A10_NUM_SUPPLIES ARRAY_SIZE(ov16a10_supply_names)
124
125 struct regval {
126 u16 addr;
127 u8 val;
128 };
129
130 struct ov16a10_mode {
131 u32 width;
132 u32 height;
133 struct v4l2_fract max_fps;
134 u32 hts_def;
135 u32 vts_def;
136 u32 exp_def;
137 u32 link_freq_idx;
138 u32 bpp;
139 const struct regval *reg_list;
140 u32 hdr_mode;
141 u32 vc[PAD_MAX];
142 };
143
144 struct ov16a10 {
145 struct i2c_client *client;
146 struct clk *xvclk;
147 struct gpio_desc *power_gpio;
148 struct gpio_desc *reset_gpio;
149 struct gpio_desc *pwdn_gpio;
150 struct regulator_bulk_data supplies[OV16A10_NUM_SUPPLIES];
151
152 struct pinctrl *pinctrl;
153 struct pinctrl_state *pins_default;
154 struct pinctrl_state *pins_sleep;
155
156 struct v4l2_subdev subdev;
157 struct media_pad pad;
158 struct v4l2_ctrl_handler ctrl_handler;
159 struct v4l2_ctrl *exposure;
160 struct v4l2_ctrl *anal_gain;
161 struct v4l2_ctrl *digi_gain;
162 struct v4l2_ctrl *hblank;
163 struct v4l2_ctrl *vblank;
164 struct v4l2_ctrl *pixel_rate;
165 struct v4l2_ctrl *link_freq;
166 struct v4l2_ctrl *test_pattern;
167 struct v4l2_ctrl *h_flip;
168 struct v4l2_ctrl *v_flip;
169 struct mutex mutex;
170 bool streaming;
171 bool power_on;
172 const struct ov16a10_mode *cur_mode;
173 u32 cfg_num;
174 u32 module_index;
175 const char *module_facing;
176 const char *module_name;
177 const char *len_name;
178 };
179
180 #define to_ov16a10(sd) container_of(sd, struct ov16a10, subdev)
181
182 /*
183 * Xclk 24Mhz
184 */
185 static const struct regval ov16a10_global_regs[] = {
186 {0x0103, 0x01},
187 {0x0102, 0x00},
188 {0x0301, 0x48},
189 {0x0302, 0x31},
190 {0x0303, 0x04},
191 {0x0305, 0x6b},
192 {0x0306, 0x00},
193 {0x0320, 0x02},
194 {0x0323, 0x04},
195 {0x0326, 0xd8},
196 {0x0327, 0x0b},
197 {0x0329, 0x01},
198 {0x0343, 0x04},
199 {0x0344, 0x01},
200 {0x0345, 0x2c},
201 {0x0346, 0xc0},
202 {0x034a, 0x07},
203 {0x300e, 0x22},
204 {0x3012, 0x41},
205 {0x3016, 0xd2},
206 {0x3018, 0x70},
207 {0x301e, 0x98},
208 {0x3025, 0x03},
209 {0x3026, 0x10},
210 {0x3027, 0x08},
211 {0x3102, 0x00},
212 {0x3400, 0x04},
213 {0x3406, 0x04},
214 {0x3408, 0x04},
215 {0x3421, 0x09},
216 {0x3422, 0x20},
217 {0x3423, 0x15},
218 {0x3424, 0x40},
219 {0x3425, 0x14},
220 {0x3426, 0x04},
221 {0x3504, 0x08},
222 {0x3508, 0x01},
223 {0x3509, 0x00},
224 {0x350a, 0x01},
225 {0x350b, 0x00},
226 {0x350c, 0x00},
227 {0x3548, 0x01},
228 {0x3549, 0x00},
229 {0x354a, 0x01},
230 {0x354b, 0x00},
231 {0x354c, 0x00},
232 {0x3600, 0xff},
233 {0x3602, 0x42},
234 {0x3603, 0x7b},
235 {0x3608, 0x9b},
236 {0x360a, 0x69},
237 {0x360b, 0x53},
238 {0x3618, 0xc0},
239 {0x361a, 0x8b},
240 {0x361d, 0x20},
241 {0x361e, 0x10},
242 {0x361f, 0x01},
243 {0x3620, 0x89},
244 {0x3624, 0x8f},
245 {0x3629, 0x09},
246 {0x362e, 0x50},
247 {0x3631, 0xe2},
248 {0x3632, 0xe2},
249 {0x3634, 0x10},
250 {0x3635, 0x10},
251 {0x3636, 0x10},
252 {0x3639, 0xa6},
253 {0x363a, 0xaa},
254 {0x363b, 0x0c},
255 {0x363c, 0x16},
256 {0x363d, 0x29},
257 {0x363e, 0x4f},
258 {0x3642, 0xa8},
259 {0x3652, 0x00},
260 {0x3653, 0x00},
261 {0x3654, 0x8a},
262 {0x3656, 0x0c},
263 {0x3657, 0x8e},
264 {0x3660, 0x80},
265 {0x3663, 0x00},
266 {0x3664, 0x00},
267 {0x3668, 0x05},
268 {0x3669, 0x05},
269 {0x370d, 0x10},
270 {0x370e, 0x05},
271 {0x370f, 0x10},
272 {0x3711, 0x01},
273 {0x3712, 0x09},
274 {0x3713, 0x40},
275 {0x3714, 0xe4},
276 {0x3716, 0x04},
277 {0x3717, 0x01},
278 {0x3718, 0x02},
279 {0x3719, 0x01},
280 {0x371a, 0x02},
281 {0x371b, 0x02},
282 {0x371c, 0x01},
283 {0x371d, 0x02},
284 {0x371e, 0x12},
285 {0x371f, 0x02},
286 {0x3720, 0x14},
287 {0x3721, 0x12},
288 {0x3722, 0x44},
289 {0x3723, 0x60},
290 {0x372f, 0x34},
291 {0x3726, 0x21},
292 {0x37d0, 0x02},
293 {0x37d1, 0x10},
294 {0x37db, 0x08},
295 {0x3808, 0x12},
296 {0x3809, 0x30},
297 {0x380a, 0x0d},
298 {0x380b, 0xa8},
299 {0x380c, 0x03},
300 {0x380d, 0x52},
301 {0x380e, 0x0f},
302 {0x380f, 0x50},
303 {0x3814, 0x11},
304 {0x3815, 0x11},
305 {0x3820, 0x00},
306 {0x3821, 0x06},
307 {0x3822, 0x00},
308 {0x3823, 0x00},
309 {0x3837, 0x10},
310 {0x383c, 0x22},
311 {0x383d, 0xff},
312 {0x383e, 0x0d},
313 {0x383f, 0x33},
314 {0x3857, 0x00},
315 {0x388f, 0x00},
316 {0x3890, 0x00},
317 {0x3891, 0x00},
318 {0x3d81, 0x10},
319 {0x3d83, 0x0c},
320 {0x3d84, 0x00},
321 {0x3d85, 0x1b},
322 {0x3d88, 0x00},
323 {0x3d89, 0x00},
324 {0x3d8a, 0x00},
325 {0x3d8b, 0x01},
326 {0x3d8c, 0x77},
327 {0x3d8d, 0xa0},
328 {0x3f00, 0x02},
329 {0x3f0c, 0x07},
330 {0x3f0d, 0x2f},
331 {0x4012, 0x0d},
332 {0x4015, 0x04},
333 {0x4016, 0x1b},
334 {0x4017, 0x04},
335 {0x4018, 0x0b},
336 {0x401b, 0x10},
337 {0x401e, 0x01},
338 {0x401f, 0x38},
339 {0x4500, 0x20},
340 {0x4501, 0x6a},
341 {0x4502, 0xb4},
342 {0x4586, 0x00},
343 {0x4588, 0x02},
344 {0x4640, 0x00},
345 {0x4641, 0x28},
346 {0x4643, 0x08},
347 {0x4645, 0x04},
348 {0x4806, 0x40},
349 {0x480e, 0x00},
350 {0x4815, 0x2b},
351 {0x481b, 0x3c},
352 {0x4833, 0x18},
353 {0x4837, 0x08},
354 {0x484b, 0x07},
355 {0x4850, 0x41},
356 {0x4860, 0x00},
357 {0x4861, 0xec},
358 {0x4864, 0x00},
359 {0x4883, 0x00},
360 {0x4888, 0x10},
361 {0x4a00, 0x10},
362 {0x4e00, 0x00},
363 {0x4e01, 0x04},
364 {0x4e02, 0x01},
365 {0x4e03, 0x00},
366 {0x4e04, 0x08},
367 {0x4e05, 0x04},
368 {0x4e06, 0x00},
369 {0x4e07, 0x13},
370 {0x4e08, 0x01},
371 {0x4e09, 0x00},
372 {0x4e0a, 0x15},
373 {0x4e0b, 0x0e},
374 {0x4e0c, 0x00},
375 {0x4e0d, 0x17},
376 {0x4e0e, 0x07},
377 {0x4e0f, 0x00},
378 {0x4e10, 0x19},
379 {0x4e11, 0x06},
380 {0x4e12, 0x00},
381 {0x4e13, 0x1b},
382 {0x4e14, 0x08},
383 {0x4e15, 0x00},
384 {0x4e16, 0x1f},
385 {0x4e17, 0x08},
386 {0x4e18, 0x00},
387 {0x4e19, 0x21},
388 {0x4e1a, 0x0e},
389 {0x4e1b, 0x00},
390 {0x4e1c, 0x2d},
391 {0x4e1d, 0x30},
392 {0x4e1e, 0x00},
393 {0x4e1f, 0x6a},
394 {0x4e20, 0x05},
395 {0x4e21, 0x00},
396 {0x4e22, 0x6c},
397 {0x4e23, 0x05},
398 {0x4e24, 0x00},
399 {0x4e25, 0x6e},
400 {0x4e26, 0x39},
401 {0x4e27, 0x00},
402 {0x4e28, 0x7a},
403 {0x4e29, 0x6d},
404 {0x4e2a, 0x00},
405 {0x4e2b, 0x00},
406 {0x4e2c, 0x00},
407 {0x4e2d, 0x00},
408 {0x4e2e, 0x00},
409 {0x4e2f, 0x00},
410 {0x4e30, 0x00},
411 {0x4e31, 0x00},
412 {0x4e32, 0x00},
413 {0x4e33, 0x00},
414 {0x4e34, 0x00},
415 {0x4e35, 0x00},
416 {0x4e36, 0x00},
417 {0x4e37, 0x00},
418 {0x4e38, 0x00},
419 {0x4e39, 0x00},
420 {0x4e3a, 0x00},
421 {0x4e3b, 0x00},
422 {0x4e3c, 0x00},
423 {0x4e3d, 0x00},
424 {0x4e3e, 0x00},
425 {0x4e3f, 0x00},
426 {0x4e40, 0x00},
427 {0x4e41, 0x00},
428 {0x4e42, 0x00},
429 {0x4e43, 0x00},
430 {0x4e44, 0x00},
431 {0x4e45, 0x00},
432 {0x4e46, 0x00},
433 {0x4e47, 0x00},
434 {0x4e48, 0x00},
435 {0x4e49, 0x00},
436 {0x4e4a, 0x00},
437 {0x4e4b, 0x00},
438 {0x4e4c, 0x00},
439 {0x4e4d, 0x00},
440 {0x4e4e, 0x00},
441 {0x4e4f, 0x00},
442 {0x4e50, 0x00},
443 {0x4e51, 0x00},
444 {0x4e52, 0x00},
445 {0x4e53, 0x00},
446 {0x4e54, 0x00},
447 {0x4e55, 0x00},
448 {0x4e56, 0x00},
449 {0x4e57, 0x00},
450 {0x4e58, 0x00},
451 {0x4e59, 0x00},
452 {0x4e5a, 0x00},
453 {0x4e5b, 0x00},
454 {0x4e5c, 0x00},
455 {0x4e5d, 0x00},
456 {0x4e5e, 0x00},
457 {0x4e5f, 0x00},
458 {0x4e60, 0x00},
459 {0x4e61, 0x00},
460 {0x4e62, 0x00},
461 {0x4e63, 0x00},
462 {0x4e64, 0x00},
463 {0x4e65, 0x00},
464 {0x4e66, 0x00},
465 {0x4e67, 0x00},
466 {0x4e68, 0x00},
467 {0x4e69, 0x00},
468 {0x4e6a, 0x00},
469 {0x4e6b, 0x00},
470 {0x4e6c, 0x00},
471 {0x4e6d, 0x00},
472 {0x4e6e, 0x00},
473 {0x4e6f, 0x00},
474 {0x4e70, 0x00},
475 {0x4e71, 0x00},
476 {0x4e72, 0x00},
477 {0x4e73, 0x00},
478 {0x4e74, 0x00},
479 {0x4e75, 0x00},
480 {0x4e76, 0x00},
481 {0x4e77, 0x00},
482 {0x4e78, 0x1c},
483 {0x4e79, 0x1e},
484 {0x4e7a, 0x00},
485 {0x4e7b, 0x00},
486 {0x4e7c, 0x2c},
487 {0x4e7d, 0x2f},
488 {0x4e7e, 0x79},
489 {0x4e7f, 0x7b},
490 {0x4e80, 0x0a},
491 {0x4e81, 0x31},
492 {0x4e82, 0x66},
493 {0x4e83, 0x81},
494 {0x4e84, 0x03},
495 {0x4e85, 0x40},
496 {0x4e86, 0x02},
497 {0x4e87, 0x09},
498 {0x4e88, 0x43},
499 {0x4e89, 0x53},
500 {0x4e8a, 0x32},
501 {0x4e8b, 0x67},
502 {0x4e8c, 0x05},
503 {0x4e8d, 0x83},
504 {0x4e8e, 0x00},
505 {0x4e8f, 0x00},
506 {0x4e90, 0x00},
507 {0x4e91, 0x00},
508 {0x4e92, 0x00},
509 {0x4e93, 0x00},
510 {0x4e94, 0x00},
511 {0x4e95, 0x00},
512 {0x4e96, 0x00},
513 {0x4e97, 0x00},
514 {0x4e98, 0x00},
515 {0x4e99, 0x00},
516 {0x4e9a, 0x00},
517 {0x4e9b, 0x00},
518 {0x4e9c, 0x00},
519 {0x4e9d, 0x00},
520 {0x4e9e, 0x00},
521 {0x4e9f, 0x00},
522 {0x4ea0, 0x00},
523 {0x4ea1, 0x00},
524 {0x4ea2, 0x00},
525 {0x4ea3, 0x00},
526 {0x4ea4, 0x00},
527 {0x4ea5, 0x00},
528 {0x4ea6, 0x1e},
529 {0x4ea7, 0x20},
530 {0x4ea8, 0x32},
531 {0x4ea9, 0x6d},
532 {0x4eaa, 0x18},
533 {0x4eab, 0x7f},
534 {0x4eac, 0x00},
535 {0x4ead, 0x00},
536 {0x4eae, 0x7c},
537 {0x4eaf, 0x07},
538 {0x4eb0, 0x7c},
539 {0x4eb1, 0x07},
540 {0x4eb2, 0x07},
541 {0x4eb3, 0x1c},
542 {0x4eb4, 0x07},
543 {0x4eb5, 0x1c},
544 {0x4eb6, 0x07},
545 {0x4eb7, 0x1c},
546 {0x4eb8, 0x07},
547 {0x4eb9, 0x1c},
548 {0x4eba, 0x07},
549 {0x4ebb, 0x14},
550 {0x4ebc, 0x07},
551 {0x4ebd, 0x1c},
552 {0x4ebe, 0x07},
553 {0x4ebf, 0x1c},
554 {0x4ec0, 0x07},
555 {0x4ec1, 0x1c},
556 {0x4ec2, 0x07},
557 {0x4ec3, 0x1c},
558 {0x4ec4, 0x2c},
559 {0x4ec5, 0x2f},
560 {0x4ec6, 0x79},
561 {0x4ec7, 0x7b},
562 {0x4ec8, 0x7c},
563 {0x4ec9, 0x07},
564 {0x4eca, 0x7c},
565 {0x4ecb, 0x07},
566 {0x4ecc, 0x00},
567 {0x4ecd, 0x00},
568 {0x4ece, 0x07},
569 {0x4ecf, 0x31},
570 {0x4ed0, 0x69},
571 {0x4ed1, 0x7f},
572 {0x4ed2, 0x67},
573 {0x4ed3, 0x00},
574 {0x4ed4, 0x00},
575 {0x4ed5, 0x00},
576 {0x4ed6, 0x7c},
577 {0x4ed7, 0x07},
578 {0x4ed8, 0x7c},
579 {0x4ed9, 0x07},
580 {0x4eda, 0x33},
581 {0x4edb, 0x7f},
582 {0x4edc, 0x00},
583 {0x4edd, 0x16},
584 {0x4ede, 0x00},
585 {0x4edf, 0x00},
586 {0x4ee0, 0x32},
587 {0x4ee1, 0x70},
588 {0x4ee2, 0x01},
589 {0x4ee3, 0x30},
590 {0x4ee4, 0x22},
591 {0x4ee5, 0x28},
592 {0x4ee6, 0x6f},
593 {0x4ee7, 0x75},
594 {0x4ee8, 0x00},
595 {0x4ee9, 0x00},
596 {0x4eea, 0x30},
597 {0x4eeb, 0x7f},
598 {0x4eec, 0x00},
599 {0x4eed, 0x00},
600 {0x4eee, 0x00},
601 {0x4eef, 0x00},
602 {0x4ef0, 0x69},
603 {0x4ef1, 0x7f},
604 {0x4ef2, 0x07},
605 {0x4ef3, 0x30},
606 {0x4ef4, 0x32},
607 {0x4ef5, 0x09},
608 {0x4ef6, 0x7d},
609 {0x4ef7, 0x65},
610 {0x4ef8, 0x00},
611 {0x4ef9, 0x00},
612 {0x4efa, 0x00},
613 {0x4efb, 0x00},
614 {0x4efc, 0x7f},
615 {0x4efd, 0x09},
616 {0x4efe, 0x7f},
617 {0x4eff, 0x09},
618 {0x4f00, 0x1e},
619 {0x4f01, 0x7c},
620 {0x4f02, 0x7f},
621 {0x4f03, 0x09},
622 {0x4f04, 0x7f},
623 {0x4f05, 0x0b},
624 {0x4f06, 0x7c},
625 {0x4f07, 0x02},
626 {0x4f08, 0x7c},
627 {0x4f09, 0x02},
628 {0x4f0a, 0x32},
629 {0x4f0b, 0x64},
630 {0x4f0c, 0x32},
631 {0x4f0d, 0x64},
632 {0x4f0e, 0x32},
633 {0x4f0f, 0x64},
634 {0x4f10, 0x32},
635 {0x4f11, 0x64},
636 {0x4f12, 0x31},
637 {0x4f13, 0x4f},
638 {0x4f14, 0x83},
639 {0x4f15, 0x84},
640 {0x4f16, 0x63},
641 {0x4f17, 0x64},
642 {0x4f18, 0x83},
643 {0x4f19, 0x84},
644 {0x4f1a, 0x31},
645 {0x4f1b, 0x32},
646 {0x4f1c, 0x7b},
647 {0x4f1d, 0x7c},
648 {0x4f1e, 0x2f},
649 {0x4f1f, 0x30},
650 {0x4f20, 0x30},
651 {0x4f21, 0x69},
652 {0x4d06, 0x08},
653 {0x5000, 0x0b},
654 {0x5001, 0x4b},
655 {0x5002, 0x57},
656 {0x5003, 0x42},
657 {0x5005, 0x00},
658 {0x5038, 0x00},
659 {0x5081, 0x00},
660 {0x5180, 0x00},
661 {0x5181, 0x10},
662 {0x5182, 0x07},
663 {0x5183, 0x8f},
664 {0x5184, 0x03},
665 {0x5820, 0xc5},
666 {0x5854, 0x00},
667 {0x58cb, 0x03},
668 {0x5bd0, 0x01},
669 {0x5bd1, 0x02},
670 {0x5c0e, 0x11},
671 {0x5c11, 0x01},
672 {0x5c16, 0x02},
673 {0x5c17, 0x00},
674 {0x5c1a, 0x00},
675 {0x5c1b, 0x00},
676 {0x5c21, 0x10},
677 {0x5c22, 0x10},
678 {0x5c23, 0x02},
679 {0x5c24, 0x0a},
680 {0x5c25, 0x06},
681 {0x5c26, 0x0e},
682 {0x5c27, 0x02},
683 {0x5c28, 0x02},
684 {0x5c29, 0x0a},
685 {0x5c2a, 0x0a},
686 {0x5c2b, 0x01},
687 {0x5c2c, 0x00},
688 {0x5c2e, 0x08},
689 {0x5c30, 0x04},
690 {0x5c35, 0x03},
691 {0x5c36, 0x03},
692 {0x5c37, 0x03},
693 {0x5c38, 0x03},
694 {0x5d00, 0xff},
695 {0x5d01, 0x07},
696 {0x5d02, 0x80},
697 {0x5d03, 0x44},
698 {0x5d05, 0xfc},
699 {0x5d06, 0x0b},
700 {0x5d08, 0x10},
701 {0x5d09, 0x10},
702 {0x5d0a, 0x02},
703 {0x5d0b, 0x0a},
704 {0x5d0c, 0x06},
705 {0x5d0d, 0x0e},
706 {0x5d0e, 0x02},
707 {0x5d0f, 0x02},
708 {0x5d10, 0x0a},
709 {0x5d11, 0x0a},
710 {0x5d12, 0x01},
711 {0x5d13, 0x00},
712 {0x5d15, 0x10},
713 {0x5d16, 0x10},
714 {0x5d17, 0x10},
715 {0x5d18, 0x10},
716 {0x5d1a, 0x10},
717 {0x5d1b, 0x10},
718 {0x5d1c, 0x10},
719 {0x5d1d, 0x10},
720 {0x5d1e, 0x04},
721 {0x5d1f, 0x04},
722 {0x5d20, 0x04},
723 {0x5d27, 0x64},
724 {0x5d28, 0xc8},
725 {0x5d29, 0x96},
726 {0x5d2a, 0xff},
727 {0x5d2b, 0xc8},
728 {0x5d2c, 0xff},
729 {0x5d2d, 0x04},
730 {0x5d34, 0x00},
731 {0x5d35, 0x08},
732 {0x5d36, 0x00},
733 {0x5d37, 0x04},
734 {0x5d4a, 0x00},
735 {0x5d4c, 0x00},
736 {REG_NULL, 0x00},
737 };
738
739 /*
740 * Xclk 24Mhz
741 * max_framerate 30fps
742 */
743 static const struct regval ov16a10_4656x3496_30fps_regs[] = {
744 {0x0305, 0x6b},
745 {0x0307, 0x00},
746 {0x4837, 0x0b},
747 {0x0100, 0x00},
748 {0x0329, 0x01},
749 {0x0344, 0x01},
750 {0x0345, 0x2c},
751 {0x034a, 0x07},
752 {0x360a, 0x69},
753 {0x361a, 0x8b},
754 {0x3639, 0xa6},
755 {0x3654, 0x8a},
756 {0x3656, 0x0c},
757 {0x37d0, 0x02},
758 {0x37d1, 0x10},
759 {0x37db, 0x08},
760 {0x3808, 0x12},
761 {0x3809, 0x30},
762 {0x380a, 0x0d},
763 {0x380b, 0xa8},
764 {0x380c, 0x03},
765 {0x380d, 0x52},
766 {0x380e, 0x0f},
767 {0x380f, 0x50},
768 {0x3814, 0x11},
769 {0x3815, 0x11},
770 {0x3820, 0x00},
771 {0x3821, 0x06},
772 {0x3822, 0x00},
773 {0x383c, 0x22},
774 {0x4015, 0x04},
775 {0x4016, 0x1b},
776 {0x4017, 0x04},
777 {0x4018, 0x0b},
778 {0x401e, 0x01},
779 {0x401f, 0x38},
780 {0x4500, 0x20},
781 {0x4501, 0x6a},
782 {0x4586, 0x00},
783 {0x4588, 0x02},
784 {0x4e05, 0x04},
785 {0x4e11, 0x06},
786 {0x4e1d, 0x30},
787 {0x4e26, 0x39},
788 {0x4e29, 0x6d},
789 {0x5000, 0x0b},
790 {0x5001, 0x4b},
791 {0x5002, 0x57},
792 {0x5820, 0xc5},
793 {0x5bd0, 0x01},
794 {0x5c0e, 0x11},
795 {0x5c21, 0x10},
796 {0x5c22, 0x10},
797 {0x5c23, 0x02},
798 {0x5c24, 0x0a},
799 {0x5c25, 0x06},
800 {0x5c26, 0x0e},
801 {0x5c27, 0x02},
802 {0x5c28, 0x02},
803 {0x5c29, 0x0a},
804 {0x5c2a, 0x0a},
805 {0x5d08, 0x10},
806 {0x5d09, 0x10},
807 {0x5d0a, 0x02},
808 {0x5d0b, 0x0a},
809 {0x5d0c, 0x06},
810 {0x5d0d, 0x0e},
811 {0x5d0e, 0x02},
812 {0x5d0f, 0x02},
813 {0x5d10, 0x0a},
814 {0x5d11, 0x0a},
815 {0x3501, 0x0f},
816 {0x3502, 0x48},
817 {0x3508, 0x01},
818 {0x3509, 0x00},
819 //{0x0100, 0x01},
820 {REG_NULL, 0x00},
821 };
822
823 static const struct regval ov16a10_2328x1748_30fps_regs[] = {
824 {0x0305, 0x6b},
825 {0x0307, 0x00},
826 {0x4837, 0x0b},
827 {0x0100, 0x00},
828 {0x0329, 0x01},
829 {0x0344, 0x01},
830 {0x0345, 0x2c},
831 {0x034a, 0x07},
832 {0x360a, 0x69},
833 {0x361a, 0x8b},
834 {0x3639, 0xa6},
835 {0x3654, 0x8a},
836 {0x3656, 0x0c},
837 {0x37d0, 0x01},
838 {0x37d1, 0x10},
839 {0x37db, 0x08},
840 {0x3808, 0x09},
841 {0x3809, 0x18},
842 {0x380a, 0x06},
843 {0x380b, 0xd4},
844 {0x380c, 0x03},
845 {0x380d, 0x52},
846 {0x380e, 0x0f},
847 {0x380f, 0x50},
848 {0x3814, 0x11},
849 {0x3815, 0x11},
850 {0x3820, 0x00},
851 {0x3821, 0x06},
852 {0x3822, 0x11},
853 {0x383c, 0x22},
854 {0x4015, 0x04},
855 {0x4016, 0x1b},
856 {0x4017, 0x00},
857 {0x4018, 0x07},
858 {0x401e, 0x01},
859 {0x401f, 0x38},
860 {0x4500, 0x20},
861 {0x4501, 0x6a},
862 {0x4586, 0x00},
863 {0x4588, 0x02},
864 {0x4e05, 0x04},
865 {0x4e11, 0x06},
866 {0x4e1d, 0x30},
867 {0x4e26, 0x39},
868 {0x4e29, 0x6d},
869 {0x5000, 0x2b},
870 {0x5001, 0x4b},
871 {0x5002, 0x17},
872 {0x5820, 0xc3},
873 {0x5bd0, 0x01},
874 {0x5c0e, 0x11},
875 {0x5c21, 0x10},
876 {0x5c22, 0x10},
877 {0x5c23, 0x02},
878 {0x5c24, 0x0a},
879 {0x5c25, 0x06},
880 {0x5c26, 0x0e},
881 {0x5c27, 0x02},
882 {0x5c28, 0x02},
883 {0x5c29, 0x0a},
884 {0x5c2a, 0x0a},
885 {0x5d08, 0x10},
886 {0x5d09, 0x10},
887 {0x5d0a, 0x02},
888 {0x5d0b, 0x0a},
889 {0x5d0c, 0x06},
890 {0x5d0d, 0x0e},
891 {0x5d0e, 0x02},
892 {0x5d0f, 0x02},
893 {0x5d10, 0x0a},
894 {0x5d11, 0x0a},
895 {0x3501, 0x07},
896 {0x3502, 0xa0},
897 {0x3508, 0x01},
898 {0x3509, 0x00},
899 //{0x0100, 0x01},
900 {REG_NULL, 0x00},
901 };
902
903 static const struct ov16a10_mode supported_modes[] = {
904 {
905 .width = 4656,
906 .height = 3496,
907 .max_fps = {
908 .numerator = 10000,
909 .denominator = 300000,
910 },
911 .exp_def = 0x0f4a,
912 .hts_def = 0x0352 * 6,
913 .vts_def = 0x0f50,
914 .bpp = 10,
915 .reg_list = ov16a10_4656x3496_30fps_regs,
916 .link_freq_idx = 0,
917 .hdr_mode = NO_HDR,
918 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
919 },
920 {
921 .width = 2328,
922 .height = 1748,
923 .max_fps = {
924 .numerator = 10000,
925 .denominator = 300000,
926 },
927 .exp_def = 0x0f4a,
928 .hts_def = 0x0352 * 3,
929 .vts_def = 0x0f50,
930 .bpp = 10,
931 .reg_list = ov16a10_2328x1748_30fps_regs,
932 .link_freq_idx = 0,
933 .hdr_mode = NO_HDR,
934 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
935 },
936 };
937
938 static const s64 link_freq_items[] = {
939 OV16A10_LINK_FREQ_726MHZ,
940 };
941
942 static const char * const ov16a10_test_pattern_menu[] = {
943 "Disabled",
944 "Vertical Color Bar Type 1",
945 "Vertical Color Bar Type 2",
946 "Vertical Color Bar Type 3",
947 "Vertical Color Bar Type 4"
948 };
949
950 /* Write registers up to 4 at a time */
ov16a10_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)951 static int ov16a10_write_reg(struct i2c_client *client, u16 reg,
952 u32 len, u32 val)
953 {
954 u32 buf_i, val_i;
955 u8 buf[6];
956 u8 *val_p;
957 __be32 val_be;
958
959 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
960
961 if (len > 4)
962 return -EINVAL;
963
964 buf[0] = reg >> 8;
965 buf[1] = reg & 0xff;
966
967 val_be = cpu_to_be32(val);
968 val_p = (u8 *)&val_be;
969 buf_i = 2;
970 val_i = 4 - len;
971
972 while (val_i < 4)
973 buf[buf_i++] = val_p[val_i++];
974
975 if (i2c_master_send(client, buf, len + 2) != len + 2)
976 return -EIO;
977
978 return 0;
979 }
980
ov16a10_write_array(struct i2c_client * client,const struct regval * regs)981 static int ov16a10_write_array(struct i2c_client *client,
982 const struct regval *regs)
983 {
984 u32 i;
985 int ret = 0;
986
987 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
988 ret = ov16a10_write_reg(client, regs[i].addr,
989 OV16A10_REG_VALUE_08BIT,
990 regs[i].val);
991
992 return ret;
993 }
994
995 /* Read registers up to 4 at a time */
ov16a10_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)996 static int ov16a10_read_reg(struct i2c_client *client, u16 reg,
997 unsigned int len, u32 *val)
998 {
999 struct i2c_msg msgs[2];
1000 u8 *data_be_p;
1001 __be32 data_be = 0;
1002 __be16 reg_addr_be = cpu_to_be16(reg);
1003 int ret;
1004
1005 if (len > 4 || !len)
1006 return -EINVAL;
1007
1008 data_be_p = (u8 *)&data_be;
1009 /* Write register address */
1010 msgs[0].addr = client->addr;
1011 msgs[0].flags = 0;
1012 msgs[0].len = 2;
1013 msgs[0].buf = (u8 *)®_addr_be;
1014
1015 /* Read data from register */
1016 msgs[1].addr = client->addr;
1017 msgs[1].flags = I2C_M_RD;
1018 msgs[1].len = len;
1019 msgs[1].buf = &data_be_p[4 - len];
1020
1021 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1022 if (ret != ARRAY_SIZE(msgs))
1023 return -EIO;
1024
1025 *val = be32_to_cpu(data_be);
1026
1027 return 0;
1028 }
1029
ov16a10_get_reso_dist(const struct ov16a10_mode * mode,struct v4l2_mbus_framefmt * framefmt)1030 static int ov16a10_get_reso_dist(const struct ov16a10_mode *mode,
1031 struct v4l2_mbus_framefmt *framefmt)
1032 {
1033 return abs(mode->width - framefmt->width) +
1034 abs(mode->height - framefmt->height);
1035 }
1036
1037 static const struct ov16a10_mode *
ov16a10_find_best_fit(struct v4l2_subdev_format * fmt)1038 ov16a10_find_best_fit(struct v4l2_subdev_format *fmt)
1039 {
1040 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1041 int dist;
1042 int cur_best_fit = 0;
1043 int cur_best_fit_dist = -1;
1044 unsigned int i;
1045
1046 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1047 dist = ov16a10_get_reso_dist(&supported_modes[i], framefmt);
1048 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1049 cur_best_fit_dist = dist;
1050 cur_best_fit = i;
1051 }
1052 }
1053
1054 return &supported_modes[cur_best_fit];
1055 }
1056
ov16a10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1057 static int ov16a10_set_fmt(struct v4l2_subdev *sd,
1058 struct v4l2_subdev_pad_config *cfg,
1059 struct v4l2_subdev_format *fmt)
1060 {
1061 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1062 const struct ov16a10_mode *mode;
1063 s64 h_blank, vblank_def;
1064 u64 pixel_rate = 0;
1065 u32 lane_num = OV16A10_LANES;
1066
1067 mutex_lock(&ov16a10->mutex);
1068
1069 mode = ov16a10_find_best_fit(fmt);
1070 fmt->format.code = OV16A10_MEDIA_BUS_FMT;
1071 fmt->format.width = mode->width;
1072 fmt->format.height = mode->height;
1073 fmt->format.field = V4L2_FIELD_NONE;
1074 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1075 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1076 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1077 #else
1078 mutex_unlock(&ov16a10->mutex);
1079 return -ENOTTY;
1080 #endif
1081 } else {
1082 ov16a10->cur_mode = mode;
1083 h_blank = mode->hts_def - mode->width;
1084 __v4l2_ctrl_modify_range(ov16a10->hblank, h_blank,
1085 h_blank, 1, h_blank);
1086 vblank_def = mode->vts_def - mode->height;
1087 __v4l2_ctrl_modify_range(ov16a10->vblank, vblank_def,
1088 OV16A10_VTS_MAX - mode->height,
1089 1, vblank_def);
1090 __v4l2_ctrl_s_ctrl(ov16a10->vblank, vblank_def);
1091 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1092
1093 __v4l2_ctrl_s_ctrl_int64(ov16a10->pixel_rate,
1094 pixel_rate);
1095 __v4l2_ctrl_s_ctrl(ov16a10->link_freq,
1096 mode->link_freq_idx);
1097 }
1098 dev_info(&ov16a10->client->dev, "%s: mode->link_freq_idx(%d)",
1099 __func__, mode->link_freq_idx);
1100
1101 mutex_unlock(&ov16a10->mutex);
1102
1103 return 0;
1104 }
1105
ov16a10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1106 static int ov16a10_get_fmt(struct v4l2_subdev *sd,
1107 struct v4l2_subdev_pad_config *cfg,
1108 struct v4l2_subdev_format *fmt)
1109 {
1110 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1111 const struct ov16a10_mode *mode = ov16a10->cur_mode;
1112
1113 mutex_lock(&ov16a10->mutex);
1114 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1115 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1116 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1117 #else
1118 mutex_unlock(&ov16a10->mutex);
1119 return -ENOTTY;
1120 #endif
1121 } else {
1122 fmt->format.width = mode->width;
1123 fmt->format.height = mode->height;
1124 fmt->format.code = OV16A10_MEDIA_BUS_FMT;
1125 fmt->format.field = V4L2_FIELD_NONE;
1126 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1127 fmt->reserved[0] = mode->vc[fmt->pad];
1128 else
1129 fmt->reserved[0] = mode->vc[PAD0];
1130 }
1131 mutex_unlock(&ov16a10->mutex);
1132
1133 return 0;
1134 }
1135
ov16a10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1136 static int ov16a10_enum_mbus_code(struct v4l2_subdev *sd,
1137 struct v4l2_subdev_pad_config *cfg,
1138 struct v4l2_subdev_mbus_code_enum *code)
1139 {
1140 if (code->index != 0)
1141 return -EINVAL;
1142 code->code = OV16A10_MEDIA_BUS_FMT;
1143
1144 return 0;
1145 }
1146
ov16a10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1147 static int ov16a10_enum_frame_sizes(struct v4l2_subdev *sd,
1148 struct v4l2_subdev_pad_config *cfg,
1149 struct v4l2_subdev_frame_size_enum *fse)
1150 {
1151 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1152
1153 if (fse->index >= ov16a10->cfg_num)
1154 return -EINVAL;
1155
1156 if (fse->code != OV16A10_MEDIA_BUS_FMT)
1157 return -EINVAL;
1158
1159 fse->min_width = supported_modes[fse->index].width;
1160 fse->max_width = supported_modes[fse->index].width;
1161 fse->max_height = supported_modes[fse->index].height;
1162 fse->min_height = supported_modes[fse->index].height;
1163
1164 return 0;
1165 }
1166
ov16a10_enable_test_pattern(struct ov16a10 * ov16a10,u32 pattern)1167 static int ov16a10_enable_test_pattern(struct ov16a10 *ov16a10, u32 pattern)
1168 {
1169 u32 val;
1170
1171 if (pattern)
1172 val = ((pattern - 1) << 4) | OV16A10_TEST_PATTERN_ENABLE;
1173 else
1174 val = OV16A10_TEST_PATTERN_DISABLE;
1175
1176 return ov16a10_write_reg(ov16a10->client,
1177 OV16A10_REG_TEST_PATTERN,
1178 OV16A10_REG_VALUE_08BIT,
1179 val);
1180 }
1181
ov16a10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1182 static int ov16a10_g_frame_interval(struct v4l2_subdev *sd,
1183 struct v4l2_subdev_frame_interval *fi)
1184 {
1185 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1186 const struct ov16a10_mode *mode = ov16a10->cur_mode;
1187
1188 fi->interval = mode->max_fps;
1189
1190 return 0;
1191 }
1192
ov16a10_get_module_inf(struct ov16a10 * ov16a10,struct rkmodule_inf * inf)1193 static void ov16a10_get_module_inf(struct ov16a10 *ov16a10,
1194 struct rkmodule_inf *inf)
1195 {
1196 memset(inf, 0, sizeof(*inf));
1197 strscpy(inf->base.sensor, OV16A10_NAME, sizeof(inf->base.sensor));
1198 strscpy(inf->base.module, ov16a10->module_name,
1199 sizeof(inf->base.module));
1200 strscpy(inf->base.lens, ov16a10->len_name, sizeof(inf->base.lens));
1201 }
1202
ov16a10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1203 static long ov16a10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1204 {
1205 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1206 struct rkmodule_hdr_cfg *hdr_cfg;
1207 long ret = 0;
1208 u32 i, h, w;
1209 u32 stream = 0;
1210
1211 switch (cmd) {
1212 case RKMODULE_SET_HDR_CFG:
1213 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1214 w = ov16a10->cur_mode->width;
1215 h = ov16a10->cur_mode->height;
1216 for (i = 0; i < ov16a10->cfg_num; i++) {
1217 if (w == supported_modes[i].width &&
1218 h == supported_modes[i].height &&
1219 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1220 ov16a10->cur_mode = &supported_modes[i];
1221 break;
1222 }
1223 }
1224 if (i == ov16a10->cfg_num) {
1225 dev_err(&ov16a10->client->dev,
1226 "not find hdr mode:%d %dx%d config\n",
1227 hdr_cfg->hdr_mode, w, h);
1228 ret = -EINVAL;
1229 } else {
1230 w = ov16a10->cur_mode->hts_def - ov16a10->cur_mode->width;
1231 h = ov16a10->cur_mode->vts_def - ov16a10->cur_mode->height;
1232 __v4l2_ctrl_modify_range(ov16a10->hblank, w, w, 1, w);
1233 __v4l2_ctrl_modify_range(ov16a10->vblank, h,
1234 OV16A10_VTS_MAX - ov16a10->cur_mode->height,
1235 1, h);
1236 dev_info(&ov16a10->client->dev,
1237 "sensor mode: %d\n",
1238 ov16a10->cur_mode->hdr_mode);
1239 }
1240 break;
1241 case RKMODULE_GET_HDR_CFG:
1242 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1243 hdr_cfg->esp.mode = HDR_NORMAL_VC;
1244 hdr_cfg->hdr_mode = ov16a10->cur_mode->hdr_mode;
1245 break;
1246 case RKMODULE_GET_MODULE_INFO:
1247 ov16a10_get_module_inf(ov16a10, (struct rkmodule_inf *)arg);
1248 break;
1249 case RKMODULE_SET_QUICK_STREAM:
1250
1251 stream = *((u32 *)arg);
1252
1253 if (stream)
1254 ret = ov16a10_write_reg(ov16a10->client,
1255 OV16A10_REG_CTRL_MODE,
1256 OV16A10_REG_VALUE_08BIT,
1257 OV16A10_MODE_STREAMING);
1258 else
1259 ret = ov16a10_write_reg(ov16a10->client,
1260 OV16A10_REG_CTRL_MODE,
1261 OV16A10_REG_VALUE_08BIT,
1262 OV16A10_MODE_SW_STANDBY);
1263 break;
1264 default:
1265 ret = -ENOIOCTLCMD;
1266 break;
1267 }
1268
1269 return ret;
1270 }
1271
1272 #ifdef CONFIG_COMPAT
ov16a10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1273 static long ov16a10_compat_ioctl32(struct v4l2_subdev *sd,
1274 unsigned int cmd, unsigned long arg)
1275 {
1276 void __user *up = compat_ptr(arg);
1277 struct rkmodule_inf *inf;
1278 struct rkmodule_awb_cfg *cfg;
1279 struct rkmodule_hdr_cfg *hdr;
1280 long ret = 0;
1281 u32 stream = 0;
1282
1283 switch (cmd) {
1284 case RKMODULE_GET_MODULE_INFO:
1285 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1286 if (!inf) {
1287 ret = -ENOMEM;
1288 return ret;
1289 }
1290
1291 ret = ov16a10_ioctl(sd, cmd, inf);
1292 if (!ret) {
1293 ret = copy_to_user(up, inf, sizeof(*inf));
1294 if (ret)
1295 ret = -EFAULT;
1296 }
1297 kfree(inf);
1298 break;
1299 case RKMODULE_AWB_CFG:
1300 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1301 if (!cfg) {
1302 ret = -ENOMEM;
1303 return ret;
1304 }
1305
1306 ret = copy_from_user(cfg, up, sizeof(*cfg));
1307 if (!ret)
1308 ret = ov16a10_ioctl(sd, cmd, cfg);
1309 else
1310 ret = -EFAULT;
1311 kfree(cfg);
1312 break;
1313 case RKMODULE_GET_HDR_CFG:
1314 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1315 if (!hdr) {
1316 ret = -ENOMEM;
1317 return ret;
1318 }
1319
1320 ret = ov16a10_ioctl(sd, cmd, hdr);
1321 if (!ret) {
1322 if (copy_to_user(up, hdr, sizeof(*hdr))) {
1323 kfree(hdr);
1324 return -EFAULT;
1325 }
1326 }
1327 kfree(hdr);
1328 break;
1329 case RKMODULE_SET_HDR_CFG:
1330 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1331 if (!hdr) {
1332 ret = -ENOMEM;
1333 return ret;
1334 }
1335
1336 if (copy_from_user(hdr, up, sizeof(*hdr))) {
1337 kfree(hdr);
1338 return -EFAULT;
1339 }
1340 ret = ov16a10_ioctl(sd, cmd, hdr);
1341 kfree(hdr);
1342 break;
1343 case RKMODULE_SET_QUICK_STREAM:
1344 ret = copy_from_user(&stream, up, sizeof(u32));
1345 if (!ret)
1346 ret = ov16a10_ioctl(sd, cmd, &stream);
1347 else
1348 ret = -EFAULT;
1349 break;
1350 default:
1351 ret = -ENOIOCTLCMD;
1352 break;
1353 }
1354
1355 return ret;
1356 }
1357 #endif
1358
__ov16a10_start_stream(struct ov16a10 * ov16a10)1359 static int __ov16a10_start_stream(struct ov16a10 *ov16a10)
1360 {
1361 int ret;
1362
1363 ret = ov16a10_write_array(ov16a10->client, ov16a10->cur_mode->reg_list);
1364 if (ret)
1365 return ret;
1366
1367 /* In case these controls are set before streaming */
1368 mutex_unlock(&ov16a10->mutex);
1369 ret = v4l2_ctrl_handler_setup(&ov16a10->ctrl_handler);
1370 mutex_lock(&ov16a10->mutex);
1371 if (ret)
1372 return ret;
1373
1374 return ov16a10_write_reg(ov16a10->client,
1375 OV16A10_REG_CTRL_MODE,
1376 OV16A10_REG_VALUE_08BIT,
1377 OV16A10_MODE_STREAMING);
1378 }
1379
__ov16a10_stop_stream(struct ov16a10 * ov16a10)1380 static int __ov16a10_stop_stream(struct ov16a10 *ov16a10)
1381 {
1382 return ov16a10_write_reg(ov16a10->client,
1383 OV16A10_REG_CTRL_MODE,
1384 OV16A10_REG_VALUE_08BIT,
1385 OV16A10_MODE_SW_STANDBY);
1386 }
1387
ov16a10_s_stream(struct v4l2_subdev * sd,int on)1388 static int ov16a10_s_stream(struct v4l2_subdev *sd, int on)
1389 {
1390 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1391 struct i2c_client *client = ov16a10->client;
1392 int ret = 0;
1393
1394 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1395 ov16a10->cur_mode->width,
1396 ov16a10->cur_mode->height,
1397 DIV_ROUND_CLOSEST(ov16a10->cur_mode->max_fps.denominator,
1398 ov16a10->cur_mode->max_fps.numerator));
1399
1400 mutex_lock(&ov16a10->mutex);
1401 on = !!on;
1402 if (on == ov16a10->streaming)
1403 goto unlock_and_return;
1404
1405 if (on) {
1406 ret = pm_runtime_get_sync(&client->dev);
1407 if (ret < 0) {
1408 pm_runtime_put_noidle(&client->dev);
1409 goto unlock_and_return;
1410 }
1411
1412 ret = __ov16a10_start_stream(ov16a10);
1413 if (ret) {
1414 v4l2_err(sd, "start stream failed while write regs\n");
1415 pm_runtime_put(&client->dev);
1416 goto unlock_and_return;
1417 }
1418 } else {
1419 __ov16a10_stop_stream(ov16a10);
1420 pm_runtime_put(&client->dev);
1421 }
1422
1423 ov16a10->streaming = on;
1424
1425 unlock_and_return:
1426 mutex_unlock(&ov16a10->mutex);
1427
1428 return ret;
1429 }
1430
ov16a10_s_power(struct v4l2_subdev * sd,int on)1431 static int ov16a10_s_power(struct v4l2_subdev *sd, int on)
1432 {
1433 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1434 struct i2c_client *client = ov16a10->client;
1435 int ret = 0;
1436
1437 mutex_lock(&ov16a10->mutex);
1438
1439 /* If the power state is not modified - no work to do. */
1440 if (ov16a10->power_on == !!on)
1441 goto unlock_and_return;
1442
1443 if (on) {
1444 ret = pm_runtime_get_sync(&client->dev);
1445 if (ret < 0) {
1446 pm_runtime_put_noidle(&client->dev);
1447 goto unlock_and_return;
1448 }
1449
1450 ret = ov16a10_write_array(ov16a10->client, ov16a10_global_regs);
1451 if (ret) {
1452 v4l2_err(sd, "could not set init registers\n");
1453 pm_runtime_put_noidle(&client->dev);
1454 goto unlock_and_return;
1455 }
1456
1457 ov16a10->power_on = true;
1458 } else {
1459 pm_runtime_put(&client->dev);
1460 ov16a10->power_on = false;
1461 }
1462
1463 unlock_and_return:
1464 mutex_unlock(&ov16a10->mutex);
1465
1466 return ret;
1467 }
1468
1469 /* Calculate the delay in us by clock rate and clock cycles */
ov16a10_cal_delay(u32 cycles)1470 static inline u32 ov16a10_cal_delay(u32 cycles)
1471 {
1472 return DIV_ROUND_UP(cycles, OV16A10_XVCLK_FREQ / 1000 / 1000);
1473 }
1474
__ov16a10_power_on(struct ov16a10 * ov16a10)1475 static int __ov16a10_power_on(struct ov16a10 *ov16a10)
1476 {
1477 int ret;
1478 u32 delay_us;
1479 struct device *dev = &ov16a10->client->dev;
1480
1481 if (!IS_ERR(ov16a10->power_gpio))
1482 gpiod_set_value_cansleep(ov16a10->power_gpio, 1);
1483
1484 usleep_range(1000, 2000);
1485
1486 if (!IS_ERR_OR_NULL(ov16a10->pins_default)) {
1487 ret = pinctrl_select_state(ov16a10->pinctrl,
1488 ov16a10->pins_default);
1489 if (ret < 0)
1490 dev_err(dev, "could not set pins\n");
1491 }
1492 ret = clk_set_rate(ov16a10->xvclk, OV16A10_XVCLK_FREQ);
1493 if (ret < 0)
1494 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1495 if (clk_get_rate(ov16a10->xvclk) != OV16A10_XVCLK_FREQ)
1496 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1497 ret = clk_prepare_enable(ov16a10->xvclk);
1498 if (ret < 0) {
1499 dev_err(dev, "Failed to enable xvclk\n");
1500 return ret;
1501 }
1502 if (!IS_ERR(ov16a10->reset_gpio))
1503 gpiod_set_value_cansleep(ov16a10->reset_gpio, 0);
1504
1505 ret = regulator_bulk_enable(OV16A10_NUM_SUPPLIES, ov16a10->supplies);
1506 if (ret < 0) {
1507 dev_err(dev, "Failed to enable regulators\n");
1508 goto disable_clk;
1509 }
1510
1511 if (!IS_ERR(ov16a10->reset_gpio))
1512 gpiod_set_value_cansleep(ov16a10->reset_gpio, 1);
1513
1514 usleep_range(5000, 6000);
1515 if (!IS_ERR(ov16a10->pwdn_gpio))
1516 gpiod_set_value_cansleep(ov16a10->pwdn_gpio, 1);
1517
1518 /* 8192 cycles prior to first SCCB transaction */
1519 delay_us = ov16a10_cal_delay(8192);
1520 usleep_range(delay_us * 2, delay_us * 3);
1521
1522 return 0;
1523
1524 disable_clk:
1525 clk_disable_unprepare(ov16a10->xvclk);
1526
1527 return ret;
1528 }
1529
__ov16a10_power_off(struct ov16a10 * ov16a10)1530 static void __ov16a10_power_off(struct ov16a10 *ov16a10)
1531 {
1532 int ret;
1533 struct device *dev = &ov16a10->client->dev;
1534
1535 if (!IS_ERR(ov16a10->pwdn_gpio))
1536 gpiod_set_value_cansleep(ov16a10->pwdn_gpio, 0);
1537 clk_disable_unprepare(ov16a10->xvclk);
1538 if (!IS_ERR(ov16a10->reset_gpio))
1539 gpiod_set_value_cansleep(ov16a10->reset_gpio, 0);
1540
1541 if (!IS_ERR_OR_NULL(ov16a10->pins_sleep)) {
1542 ret = pinctrl_select_state(ov16a10->pinctrl,
1543 ov16a10->pins_sleep);
1544 if (ret < 0)
1545 dev_dbg(dev, "could not set pins\n");
1546 }
1547 if (!IS_ERR(ov16a10->power_gpio))
1548 gpiod_set_value_cansleep(ov16a10->power_gpio, 0);
1549
1550 regulator_bulk_disable(OV16A10_NUM_SUPPLIES, ov16a10->supplies);
1551 }
1552
ov16a10_runtime_resume(struct device * dev)1553 static int ov16a10_runtime_resume(struct device *dev)
1554 {
1555 struct i2c_client *client = to_i2c_client(dev);
1556 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1557 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1558
1559 return __ov16a10_power_on(ov16a10);
1560 }
1561
ov16a10_runtime_suspend(struct device * dev)1562 static int ov16a10_runtime_suspend(struct device *dev)
1563 {
1564 struct i2c_client *client = to_i2c_client(dev);
1565 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1566 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1567
1568 __ov16a10_power_off(ov16a10);
1569
1570 return 0;
1571 }
1572
1573 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov16a10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1574 static int ov16a10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1575 {
1576 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1577 struct v4l2_mbus_framefmt *try_fmt =
1578 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1579 const struct ov16a10_mode *def_mode = &supported_modes[0];
1580
1581 mutex_lock(&ov16a10->mutex);
1582 /* Initialize try_fmt */
1583 try_fmt->width = def_mode->width;
1584 try_fmt->height = def_mode->height;
1585 try_fmt->code = OV16A10_MEDIA_BUS_FMT;
1586 try_fmt->field = V4L2_FIELD_NONE;
1587
1588 mutex_unlock(&ov16a10->mutex);
1589 /* No crop or compose */
1590
1591 return 0;
1592 }
1593 #endif
1594
ov16a10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1595 static int ov16a10_enum_frame_interval(struct v4l2_subdev *sd,
1596 struct v4l2_subdev_pad_config *cfg,
1597 struct v4l2_subdev_frame_interval_enum *fie)
1598 {
1599 if (fie->index >= ARRAY_SIZE(supported_modes))
1600 return -EINVAL;
1601
1602 fie->code = OV16A10_MEDIA_BUS_FMT;
1603 fie->width = supported_modes[fie->index].width;
1604 fie->height = supported_modes[fie->index].height;
1605 fie->interval = supported_modes[fie->index].max_fps;
1606 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1607
1608 return 0;
1609 }
1610
ov16a10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1611 static int ov16a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1612 struct v4l2_mbus_config *config)
1613 {
1614 if (2 == OV16A10_LANES) {
1615 config->type = V4L2_MBUS_CSI2_DPHY;
1616 config->flags = V4L2_MBUS_CSI2_2_LANE |
1617 V4L2_MBUS_CSI2_CHANNEL_0 |
1618 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1619 } else if (4 == OV16A10_LANES) {
1620 config->type = V4L2_MBUS_CSI2_DPHY;
1621 config->flags = V4L2_MBUS_CSI2_4_LANE |
1622 V4L2_MBUS_CSI2_CHANNEL_0 |
1623 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1624 }
1625
1626 return 0;
1627 }
1628
1629 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1630 #define DST_WIDTH_2320 2320
1631 #define DST_HEIGHT_1744 1744
1632 /*
1633 * The resolution of the driver configuration needs to be exactly
1634 * the same as the current output resolution of the sensor,
1635 * the input width of the isp needs to be 16 aligned,
1636 * the input height of the isp needs to be 8 aligned.
1637 * Can be cropped to standard resolution by this function,
1638 * otherwise it will crop out strange resolution according
1639 * to the alignment rules.
1640 */
ov16a10_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1641 static int ov16a10_get_selection(struct v4l2_subdev *sd,
1642 struct v4l2_subdev_pad_config *cfg,
1643 struct v4l2_subdev_selection *sel)
1644 {
1645 struct ov16a10 *ov16a10 = to_ov16a10(sd);
1646
1647 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1648 if (ov16a10->cur_mode->width == 2328) {
1649 sel->r.left = CROP_START(ov16a10->cur_mode->width, DST_WIDTH_2320);
1650 sel->r.width = DST_WIDTH_2320;
1651 sel->r.top = CROP_START(ov16a10->cur_mode->height, DST_HEIGHT_1744);
1652 sel->r.height = DST_HEIGHT_1744;
1653 } else {
1654 sel->r.left = 0;
1655 sel->r.width = ov16a10->cur_mode->width;
1656 sel->r.top = 0;
1657 sel->r.height = ov16a10->cur_mode->height;
1658 }
1659 return 0;
1660 }
1661
1662 return -EINVAL;
1663 }
1664
1665 static const struct dev_pm_ops ov16a10_pm_ops = {
1666 SET_RUNTIME_PM_OPS(ov16a10_runtime_suspend,
1667 ov16a10_runtime_resume, NULL)
1668 };
1669
1670 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1671 static const struct v4l2_subdev_internal_ops ov16a10_internal_ops = {
1672 .open = ov16a10_open,
1673 };
1674 #endif
1675
1676 static const struct v4l2_subdev_core_ops ov16a10_core_ops = {
1677 .s_power = ov16a10_s_power,
1678 .ioctl = ov16a10_ioctl,
1679 #ifdef CONFIG_COMPAT
1680 .compat_ioctl32 = ov16a10_compat_ioctl32,
1681 #endif
1682 };
1683
1684 static const struct v4l2_subdev_video_ops ov16a10_video_ops = {
1685 .s_stream = ov16a10_s_stream,
1686 .g_frame_interval = ov16a10_g_frame_interval,
1687 };
1688
1689 static const struct v4l2_subdev_pad_ops ov16a10_pad_ops = {
1690 .enum_mbus_code = ov16a10_enum_mbus_code,
1691 .enum_frame_size = ov16a10_enum_frame_sizes,
1692 .enum_frame_interval = ov16a10_enum_frame_interval,
1693 .get_fmt = ov16a10_get_fmt,
1694 .set_fmt = ov16a10_set_fmt,
1695 .get_selection = ov16a10_get_selection,
1696 .get_mbus_config = ov16a10_g_mbus_config,
1697 };
1698
1699 static const struct v4l2_subdev_ops ov16a10_subdev_ops = {
1700 .core = &ov16a10_core_ops,
1701 .video = &ov16a10_video_ops,
1702 .pad = &ov16a10_pad_ops,
1703 };
1704
ov16a10_set_ctrl(struct v4l2_ctrl * ctrl)1705 static int ov16a10_set_ctrl(struct v4l2_ctrl *ctrl)
1706 {
1707 struct ov16a10 *ov16a10 = container_of(ctrl->handler,
1708 struct ov16a10, ctrl_handler);
1709 struct i2c_client *client = ov16a10->client;
1710 s64 max;
1711 int ret = 0;
1712 u32 again, dgain;
1713 u32 val = 0, x_win = 0, y_win = 0;
1714
1715 /* Propagate change of current control to all related controls */
1716 switch (ctrl->id) {
1717 case V4L2_CID_VBLANK:
1718 /* Update max exposure while meeting expected vblanking */
1719 max = ov16a10->cur_mode->height + ctrl->val - 4;
1720 __v4l2_ctrl_modify_range(ov16a10->exposure,
1721 ov16a10->exposure->minimum, max,
1722 ov16a10->exposure->step,
1723 ov16a10->exposure->default_value);
1724 break;
1725 }
1726
1727 if (!pm_runtime_get_if_in_use(&client->dev))
1728 return 0;
1729
1730 switch (ctrl->id) {
1731 case V4L2_CID_EXPOSURE:
1732 /* 4 least significant bits of expsoure are fractional part */
1733 ret |= ov16a10_write_reg(ov16a10->client,
1734 OV16A10_REG_EXPOSURE_H,
1735 OV16A10_REG_VALUE_24BIT,
1736 ctrl->val & 0x7fffff);
1737 dev_dbg(&client->dev, "set exposure 0x%x\n",
1738 ctrl->val);
1739 break;
1740 case V4L2_CID_ANALOGUE_GAIN:
1741 if (ctrl->val > 1984) {// >15.5x
1742 dgain = ctrl->val * 10 / 155;
1743 again = 1984;
1744 } else {
1745 dgain = 1024;
1746 again = ctrl->val;
1747 }
1748 ret |= ov16a10_write_reg(ov16a10->client,
1749 OV16A10_REG_AGAIN_H,
1750 OV16A10_REG_VALUE_16BIT,
1751 (again << 1) & 0x7ffe);
1752 ret |= ov16a10_write_reg(ov16a10->client,
1753 OV16A10_REG_DAGAIN_H_B,
1754 OV16A10_REG_VALUE_24BIT,
1755 (dgain << 6) & 0xfffc0);
1756
1757 dev_dbg(&client->dev, "set gain 0x%x set analog gain 0x%x digital gain 0x%x\n",
1758 ctrl->val, again, dgain);
1759 break;
1760 case V4L2_CID_VBLANK:
1761 ret = ov16a10_write_reg(ov16a10->client,
1762 OV16A10_REG_VTS_H,
1763 OV16A10_REG_VALUE_16BIT,
1764 ctrl->val + ov16a10->cur_mode->height);
1765 break;
1766 case V4L2_CID_TEST_PATTERN:
1767 ret = ov16a10_enable_test_pattern(ov16a10, ctrl->val);
1768 break;
1769 case V4L2_CID_HFLIP:
1770 ret = ov16a10_read_reg(ov16a10->client, OV16A10_MIRROR_REG,
1771 OV16A10_REG_VALUE_08BIT,
1772 &val);
1773 if (ctrl->val)
1774 val |= MIRROR_BIT_MASK;
1775 else
1776 val &= ~MIRROR_BIT_MASK;
1777
1778 ret |= ov16a10_read_reg(ov16a10->client, OV16A10_REG_ISP_X_WIN,
1779 OV16A10_REG_VALUE_16BIT,
1780 &x_win);
1781
1782 if ((x_win == 0x0010) && (val & 0x04))
1783 x_win = 0x0011;
1784 else if ((x_win == 0x0011) && (!(val & 0x04)))
1785 x_win = 0x0010;
1786
1787 ret |= ov16a10_write_reg(ov16a10->client,
1788 OV16A10_GROUP_UPDATE_ADDRESS,
1789 OV16A10_REG_VALUE_08BIT,
1790 OV16A10_GROUP_UPDATE_START_DATA);
1791
1792 ret |= ov16a10_write_reg(ov16a10->client, OV16A10_MIRROR_REG,
1793 OV16A10_REG_VALUE_08BIT,
1794 val);
1795 ret |= ov16a10_write_reg(ov16a10->client, OV16A10_REG_ISP_X_WIN,
1796 OV16A10_REG_VALUE_16BIT,
1797 x_win);
1798
1799 ret |= ov16a10_write_reg(ov16a10->client,
1800 OV16A10_GROUP_UPDATE_ADDRESS,
1801 OV16A10_REG_VALUE_08BIT,
1802 OV16A10_GROUP_UPDATE_END_DATA);
1803 ret |= ov16a10_write_reg(ov16a10->client,
1804 OV16A10_GROUP_UPDATE_ADDRESS,
1805 OV16A10_REG_VALUE_08BIT,
1806 OV16A10_GROUP_UPDATE_LAUNCH);
1807 break;
1808 case V4L2_CID_VFLIP:
1809 ret = ov16a10_read_reg(ov16a10->client, OV16A10_FLIP_REG,
1810 OV16A10_REG_VALUE_08BIT,
1811 &val);
1812 if (ctrl->val)
1813 val |= FLIP_BIT_MASK;
1814 else
1815 val &= ~FLIP_BIT_MASK;
1816
1817 ret |= ov16a10_read_reg(ov16a10->client, OV16A10_REG_ISP_Y_WIN,
1818 OV16A10_REG_VALUE_16BIT,
1819 &y_win);
1820
1821 if ((y_win == 0x0004) && (val & 0x04))
1822 y_win = 0x0005;
1823 else if ((y_win == 0x0005) && (!(val & 0x04)))
1824 y_win = 0x0004;
1825
1826 ret |= ov16a10_write_reg(ov16a10->client,
1827 OV16A10_GROUP_UPDATE_ADDRESS,
1828 OV16A10_REG_VALUE_08BIT,
1829 OV16A10_GROUP_UPDATE_START_DATA);
1830
1831 ret |= ov16a10_write_reg(ov16a10->client, OV16A10_FLIP_REG,
1832 OV16A10_REG_VALUE_08BIT,
1833 val);
1834 ret |= ov16a10_write_reg(ov16a10->client, OV16A10_REG_ISP_Y_WIN,
1835 OV16A10_REG_VALUE_16BIT,
1836 y_win);
1837
1838 ret |= ov16a10_write_reg(ov16a10->client,
1839 OV16A10_GROUP_UPDATE_ADDRESS,
1840 OV16A10_REG_VALUE_08BIT,
1841 OV16A10_GROUP_UPDATE_END_DATA);
1842 ret |= ov16a10_write_reg(ov16a10->client,
1843 OV16A10_GROUP_UPDATE_ADDRESS,
1844 OV16A10_REG_VALUE_08BIT,
1845 OV16A10_GROUP_UPDATE_LAUNCH);
1846 break;
1847 default:
1848 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1849 __func__, ctrl->id, ctrl->val);
1850 break;
1851 }
1852
1853 pm_runtime_put(&client->dev);
1854
1855 return ret;
1856 }
1857
1858 static const struct v4l2_ctrl_ops ov16a10_ctrl_ops = {
1859 .s_ctrl = ov16a10_set_ctrl,
1860 };
1861
ov16a10_initialize_controls(struct ov16a10 * ov16a10)1862 static int ov16a10_initialize_controls(struct ov16a10 *ov16a10)
1863 {
1864 const struct ov16a10_mode *mode;
1865 struct v4l2_ctrl_handler *handler;
1866 s64 exposure_max, vblank_def;
1867 u32 h_blank;
1868 int ret;
1869 u64 dst_pixel_rate = 0;
1870 u32 lane_num = OV16A10_LANES;
1871
1872 handler = &ov16a10->ctrl_handler;
1873 mode = ov16a10->cur_mode;
1874 ret = v4l2_ctrl_handler_init(handler, 9);
1875 if (ret)
1876 return ret;
1877 handler->lock = &ov16a10->mutex;
1878
1879 ov16a10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1880 V4L2_CID_LINK_FREQ,
1881 0, 0, link_freq_items);
1882
1883 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1884
1885 ov16a10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1886 V4L2_CID_PIXEL_RATE,
1887 0, OV16A10_PIXEL_RATE,
1888 1, dst_pixel_rate);
1889
1890 __v4l2_ctrl_s_ctrl(ov16a10->link_freq,
1891 mode->link_freq_idx);
1892
1893 h_blank = mode->hts_def - mode->width;
1894 ov16a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1895 h_blank, h_blank, 1, h_blank);
1896 if (ov16a10->hblank)
1897 ov16a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1898
1899 vblank_def = mode->vts_def - mode->height;
1900 ov16a10->vblank = v4l2_ctrl_new_std(handler, &ov16a10_ctrl_ops,
1901 V4L2_CID_VBLANK, vblank_def,
1902 OV16A10_VTS_MAX - mode->height,
1903 1, vblank_def);
1904
1905 exposure_max = mode->vts_def - 4;
1906 ov16a10->exposure = v4l2_ctrl_new_std(handler, &ov16a10_ctrl_ops,
1907 V4L2_CID_EXPOSURE, OV16A10_EXPOSURE_MIN,
1908 exposure_max, OV16A10_EXPOSURE_STEP,
1909 mode->exp_def);
1910
1911 ov16a10->anal_gain = v4l2_ctrl_new_std(handler, &ov16a10_ctrl_ops,
1912 V4L2_CID_ANALOGUE_GAIN, OV16A10_GAIN_MIN,
1913 OV16A10_GAIN_MAX, OV16A10_GAIN_STEP,
1914 OV16A10_GAIN_DEFAULT);
1915
1916 ov16a10->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1917 &ov16a10_ctrl_ops, V4L2_CID_TEST_PATTERN,
1918 ARRAY_SIZE(ov16a10_test_pattern_menu) - 1,
1919 0, 0, ov16a10_test_pattern_menu);
1920
1921 ov16a10->h_flip = v4l2_ctrl_new_std(handler, &ov16a10_ctrl_ops,
1922 V4L2_CID_HFLIP, 0, 1, 1, 0);
1923
1924 ov16a10->v_flip = v4l2_ctrl_new_std(handler, &ov16a10_ctrl_ops,
1925 V4L2_CID_VFLIP, 0, 1, 1, 0);
1926
1927 if (handler->error) {
1928 ret = handler->error;
1929 dev_err(&ov16a10->client->dev,
1930 "Failed to init controls(%d)\n", ret);
1931 goto err_free_handler;
1932 }
1933
1934 ov16a10->subdev.ctrl_handler = handler;
1935
1936 return 0;
1937
1938 err_free_handler:
1939 v4l2_ctrl_handler_free(handler);
1940
1941 return ret;
1942 }
1943
ov16a10_check_sensor_id(struct ov16a10 * ov16a10,struct i2c_client * client)1944 static int ov16a10_check_sensor_id(struct ov16a10 *ov16a10,
1945 struct i2c_client *client)
1946 {
1947 struct device *dev = &ov16a10->client->dev;
1948 u32 id = 0;
1949 int ret;
1950
1951 ret = ov16a10_read_reg(client, OV16A10_REG_CHIP_ID,
1952 OV16A10_REG_VALUE_24BIT, &id);
1953 if (id != CHIP_ID) {
1954 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1955 return -ENODEV;
1956 }
1957
1958 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1959
1960 return 0;
1961 }
1962
ov16a10_configure_regulators(struct ov16a10 * ov16a10)1963 static int ov16a10_configure_regulators(struct ov16a10 *ov16a10)
1964 {
1965 unsigned int i;
1966
1967 for (i = 0; i < OV16A10_NUM_SUPPLIES; i++)
1968 ov16a10->supplies[i].supply = ov16a10_supply_names[i];
1969
1970 return devm_regulator_bulk_get(&ov16a10->client->dev,
1971 OV16A10_NUM_SUPPLIES,
1972 ov16a10->supplies);
1973 }
1974
ov16a10_probe(struct i2c_client * client,const struct i2c_device_id * id)1975 static int ov16a10_probe(struct i2c_client *client,
1976 const struct i2c_device_id *id)
1977 {
1978 struct device *dev = &client->dev;
1979 struct device_node *node = dev->of_node;
1980 struct ov16a10 *ov16a10;
1981 struct v4l2_subdev *sd;
1982 char facing[2];
1983 int ret;
1984 u32 i, hdr_mode = 0;
1985
1986 dev_info(dev, "driver version: %02x.%02x.%02x",
1987 DRIVER_VERSION >> 16,
1988 (DRIVER_VERSION & 0xff00) >> 8,
1989 DRIVER_VERSION & 0x00ff);
1990
1991 ov16a10 = devm_kzalloc(dev, sizeof(*ov16a10), GFP_KERNEL);
1992 if (!ov16a10)
1993 return -ENOMEM;
1994
1995 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1996 &ov16a10->module_index);
1997 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1998 &ov16a10->module_facing);
1999 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2000 &ov16a10->module_name);
2001 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2002 &ov16a10->len_name);
2003 if (ret) {
2004 dev_err(dev, "could not get module information!\n");
2005 return -EINVAL;
2006 }
2007
2008 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
2009 &hdr_mode);
2010 if (ret) {
2011 hdr_mode = NO_HDR;
2012 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2013 }
2014 ov16a10->cfg_num = ARRAY_SIZE(supported_modes);
2015 for (i = 0; i < ov16a10->cfg_num; i++) {
2016 if (hdr_mode == supported_modes[i].hdr_mode) {
2017 ov16a10->cur_mode = &supported_modes[i];
2018 break;
2019 }
2020 }
2021
2022 ov16a10->client = client;
2023
2024 ov16a10->xvclk = devm_clk_get(dev, "xvclk");
2025 if (IS_ERR(ov16a10->xvclk)) {
2026 dev_err(dev, "Failed to get xvclk\n");
2027 return -EINVAL;
2028 }
2029
2030 ov16a10->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
2031 if (IS_ERR(ov16a10->power_gpio))
2032 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
2033
2034 ov16a10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2035 if (IS_ERR(ov16a10->reset_gpio))
2036 dev_warn(dev, "Failed to get reset-gpios\n");
2037
2038 ov16a10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2039 if (IS_ERR(ov16a10->pwdn_gpio))
2040 dev_warn(dev, "Failed to get pwdn-gpios\n");
2041
2042 ret = ov16a10_configure_regulators(ov16a10);
2043 if (ret) {
2044 dev_err(dev, "Failed to get power regulators\n");
2045 return ret;
2046 }
2047
2048 ov16a10->pinctrl = devm_pinctrl_get(dev);
2049 if (!IS_ERR(ov16a10->pinctrl)) {
2050 ov16a10->pins_default =
2051 pinctrl_lookup_state(ov16a10->pinctrl,
2052 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2053 if (IS_ERR(ov16a10->pins_default))
2054 dev_err(dev, "could not get default pinstate\n");
2055
2056 ov16a10->pins_sleep =
2057 pinctrl_lookup_state(ov16a10->pinctrl,
2058 OF_CAMERA_PINCTRL_STATE_SLEEP);
2059 if (IS_ERR(ov16a10->pins_sleep))
2060 dev_err(dev, "could not get sleep pinstate\n");
2061 }
2062
2063 mutex_init(&ov16a10->mutex);
2064
2065 sd = &ov16a10->subdev;
2066 v4l2_i2c_subdev_init(sd, client, &ov16a10_subdev_ops);
2067 ret = ov16a10_initialize_controls(ov16a10);
2068 if (ret)
2069 goto err_destroy_mutex;
2070
2071 ret = __ov16a10_power_on(ov16a10);
2072 if (ret)
2073 goto err_free_handler;
2074
2075 ret = ov16a10_check_sensor_id(ov16a10, client);
2076 if (ret)
2077 goto err_power_off;
2078
2079 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2080 sd->internal_ops = &ov16a10_internal_ops;
2081 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2082 #endif
2083 #if defined(CONFIG_MEDIA_CONTROLLER)
2084 ov16a10->pad.flags = MEDIA_PAD_FL_SOURCE;
2085 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2086 ret = media_entity_pads_init(&sd->entity, 1, &ov16a10->pad);
2087 if (ret < 0)
2088 goto err_power_off;
2089 #endif
2090
2091 memset(facing, 0, sizeof(facing));
2092 if (strcmp(ov16a10->module_facing, "back") == 0)
2093 facing[0] = 'b';
2094 else
2095 facing[0] = 'f';
2096
2097 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2098 ov16a10->module_index, facing,
2099 OV16A10_NAME, dev_name(sd->dev));
2100 ret = v4l2_async_register_subdev_sensor_common(sd);
2101 if (ret) {
2102 dev_err(dev, "v4l2 async register subdev failed\n");
2103 goto err_clean_entity;
2104 }
2105
2106 pm_runtime_set_active(dev);
2107 pm_runtime_enable(dev);
2108 pm_runtime_idle(dev);
2109
2110 return 0;
2111
2112 err_clean_entity:
2113 #if defined(CONFIG_MEDIA_CONTROLLER)
2114 media_entity_cleanup(&sd->entity);
2115 #endif
2116 err_power_off:
2117 __ov16a10_power_off(ov16a10);
2118 err_free_handler:
2119 v4l2_ctrl_handler_free(&ov16a10->ctrl_handler);
2120 err_destroy_mutex:
2121 mutex_destroy(&ov16a10->mutex);
2122
2123 return ret;
2124 }
2125
ov16a10_remove(struct i2c_client * client)2126 static int ov16a10_remove(struct i2c_client *client)
2127 {
2128 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2129 struct ov16a10 *ov16a10 = to_ov16a10(sd);
2130
2131 v4l2_async_unregister_subdev(sd);
2132 #if defined(CONFIG_MEDIA_CONTROLLER)
2133 media_entity_cleanup(&sd->entity);
2134 #endif
2135 v4l2_ctrl_handler_free(&ov16a10->ctrl_handler);
2136 mutex_destroy(&ov16a10->mutex);
2137
2138 pm_runtime_disable(&client->dev);
2139 if (!pm_runtime_status_suspended(&client->dev))
2140 __ov16a10_power_off(ov16a10);
2141 pm_runtime_set_suspended(&client->dev);
2142
2143 return 0;
2144 }
2145
2146 #if IS_ENABLED(CONFIG_OF)
2147 static const struct of_device_id ov16a10_of_match[] = {
2148 { .compatible = "ovti,ov16a10" },
2149 {},
2150 };
2151 MODULE_DEVICE_TABLE(of, ov16a10_of_match);
2152 #endif
2153
2154 static const struct i2c_device_id ov16a10_match_id[] = {
2155 { "ovti,ov16a10", 0 },
2156 {},
2157 };
2158
2159 static struct i2c_driver ov16a10_i2c_driver = {
2160 .driver = {
2161 .name = OV16A10_NAME,
2162 .pm = &ov16a10_pm_ops,
2163 .of_match_table = of_match_ptr(ov16a10_of_match),
2164 },
2165 .probe = &ov16a10_probe,
2166 .remove = &ov16a10_remove,
2167 .id_table = ov16a10_match_id,
2168 };
2169
sensor_mod_init(void)2170 static int __init sensor_mod_init(void)
2171 {
2172 return i2c_add_driver(&ov16a10_i2c_driver);
2173 }
2174
sensor_mod_exit(void)2175 static void __exit sensor_mod_exit(void)
2176 {
2177 i2c_del_driver(&ov16a10_i2c_driver);
2178 }
2179
2180 device_initcall_sync(sensor_mod_init);
2181 module_exit(sensor_mod_exit);
2182
2183 MODULE_DESCRIPTION("OmniVision ov16a10 sensor driver");
2184 MODULE_LICENSE("GPL");
2185