1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov13855 camera driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 fix some errors.
9 * V0.0X01.0X02 add get_selection.
10 * V0.0X01.0X03
11 * 1. 4224x3136@15fps & 2114x1568@60fps only enable for debug.
12 * 2. fix some regs setting.
13 * V0.0X01.0X04 fix power on sequence
14 */
15 //#define DEBUG
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/version.h>
27 #include <linux/compat.h>
28 #include <linux/rk-camera-module.h>
29 #include <media/media-entity.h>
30 #include <media/v4l2-async.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-subdev.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
36
37 #ifndef V4L2_CID_DIGITAL_GAIN
38 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
39 #endif
40
41 #define OV13855_LINK_FREQ_540MHZ 540000000U
42 #define OV13855_LINK_FREQ_270MHZ 270000000U
43 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
44 #define OV13855_PIXEL_RATE (OV13855_LINK_FREQ_540MHZ * 2LL * 4LL / 10LL)
45 #define OV13855_XVCLK_FREQ 24000000
46
47 #define CHIP_ID 0x00d855
48 #define OV13855_REG_CHIP_ID 0x300a
49
50 #define OV13855_REG_CTRL_MODE 0x0100
51 #define OV13855_MODE_SW_STANDBY 0x0
52 #define OV13855_MODE_STREAMING BIT(0)
53
54 #define OV13855_REG_EXPOSURE 0x3500
55 #define OV13855_EXPOSURE_MIN 4
56 #define OV13855_EXPOSURE_STEP 1
57 #define OV13855_VTS_MAX 0x7fff
58
59 #define OV13855_REG_GAIN_H 0x3508
60 #define OV13855_REG_GAIN_L 0x3509
61 #define OV13855_GAIN_H_MASK 0x1f
62 #define OV13855_GAIN_H_SHIFT 8
63 #define OV13855_GAIN_L_MASK 0xff
64 #define OV13855_GAIN_MIN 0x80
65 #define OV13855_GAIN_MAX 0x7c0
66 #define OV13855_GAIN_STEP 1
67 #define OV13855_GAIN_DEFAULT 0x80
68
69 #define OV13855_REG_TEST_PATTERN 0x5e00
70 #define OV13855_TEST_PATTERN_ENABLE 0x80
71 #define OV13855_TEST_PATTERN_DISABLE 0x0
72
73 #define OV13855_REG_VTS 0x380e
74
75 #define REG_NULL 0xFFFF
76
77 #define OV13855_REG_VALUE_08BIT 1
78 #define OV13855_REG_VALUE_16BIT 2
79 #define OV13855_REG_VALUE_24BIT 3
80
81 #define OV13855_LANES 4
82 #define OV13855_BITS_PER_SAMPLE 10
83
84 #define OV13855_CHIP_REVISION_REG 0x302A
85
86 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
87 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
88
89 #define OV13855_NAME "ov13855"
90 #define OV13855_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
91
92 static const char * const ov13855_supply_names[] = {
93 "avdd", /* Analog power */
94 "dovdd", /* Digital I/O power */
95 "dvdd", /* Digital core power */
96 };
97
98 #define OV13855_NUM_SUPPLIES ARRAY_SIZE(ov13855_supply_names)
99
100 struct regval {
101 u16 addr;
102 u8 val;
103 };
104
105 struct ov13855_mode {
106 u32 width;
107 u32 height;
108 struct v4l2_fract max_fps;
109 u32 hts_def;
110 u32 vts_def;
111 u32 exp_def;
112 u32 link_freq_idx;
113 u32 bpp;
114 const struct regval *reg_list;
115 };
116
117 struct ov13855 {
118 struct i2c_client *client;
119 struct clk *xvclk;
120 struct gpio_desc *power_gpio;
121 struct gpio_desc *reset_gpio;
122 struct gpio_desc *pwdn_gpio;
123 struct regulator_bulk_data supplies[OV13855_NUM_SUPPLIES];
124
125 struct pinctrl *pinctrl;
126 struct pinctrl_state *pins_default;
127 struct pinctrl_state *pins_sleep;
128
129 struct v4l2_subdev subdev;
130 struct media_pad pad;
131 struct v4l2_ctrl_handler ctrl_handler;
132 struct v4l2_ctrl *exposure;
133 struct v4l2_ctrl *anal_gain;
134 struct v4l2_ctrl *digi_gain;
135 struct v4l2_ctrl *hblank;
136 struct v4l2_ctrl *vblank;
137 struct v4l2_ctrl *pixel_rate;
138 struct v4l2_ctrl *link_freq;
139 struct v4l2_ctrl *test_pattern;
140 struct mutex mutex;
141 bool streaming;
142 bool power_on;
143 const struct ov13855_mode *cur_mode;
144 u32 module_index;
145 const char *module_facing;
146 const char *module_name;
147 const char *len_name;
148 };
149
150 #define to_ov13855(sd) container_of(sd, struct ov13855, subdev)
151
152 /*
153 * Xclk 24Mhz
154 */
155 static const struct regval ov13855_global_regs[] = {
156 {0x0103, 0x01},
157 {0x0300, 0x02},
158 {0x0301, 0x00},
159 {0x0302, 0x5a},
160 {0x0303, 0x00},
161 {0x0304, 0x00},
162 {0x0305, 0x01},
163 {0x030b, 0x06},
164 {0x030c, 0x02},
165 {0x030d, 0x88},
166 {0x0312, 0x11},
167 {0x3022, 0x01},
168 {0x3013, 0x32},
169 {0x3016, 0x72},
170 {0x301b, 0xF0},
171 {0x301f, 0xd0},
172 {0x3106, 0x15},
173 {0x3107, 0x23},
174 {0x3500, 0x00},
175 {0x3501, 0x80},
176 {0x3502, 0x00},
177 {0x3508, 0x02},
178 {0x3509, 0x00},
179 {0x350a, 0x00},
180 {0x350e, 0x00},
181 {0x3510, 0x00},
182 {0x3511, 0x02},
183 {0x3512, 0x00},
184 {0x3600, 0x2b},
185 {0x3601, 0x52},
186 {0x3602, 0x60},
187 {0x3612, 0x05},
188 {0x3613, 0xa4},
189 {0x3620, 0x80},
190 {0x3621, 0x10},
191 {0x3622, 0x30},
192 {0x3624, 0x1c},
193 {0x3640, 0x10},
194 {0x3641, 0x70},
195 {0x3661, 0x80},
196 {0x3662, 0x12},
197 {0x3664, 0x73},
198 {0x3665, 0xa7},
199 {0x366e, 0xff},
200 {0x366f, 0xf4},
201 {0x3674, 0x00},
202 {0x3679, 0x0c},
203 {0x367f, 0x01},
204 {0x3680, 0x0c},
205 {0x3681, 0x50},
206 {0x3682, 0x50},
207 {0x3683, 0xa9},
208 {0x3684, 0xa9},
209 {0x3709, 0x5f},
210 {0x3714, 0x24},
211 {0x371a, 0x3e},
212 {0x3737, 0x04},
213 {0x3738, 0xcc},
214 {0x3739, 0x12},
215 {0x373d, 0x26},
216 {0x3764, 0x20},
217 {0x3765, 0x20},
218 {0x37a1, 0x36},
219 {0x37a8, 0x3b},
220 {0x37ab, 0x31},
221 {0x37c2, 0x04},
222 {0x37c3, 0xf1},
223 {0x37c5, 0x00},
224 {0x37d8, 0x03},
225 {0x37d9, 0x0c},
226 {0x37da, 0xc2},
227 {0x37dc, 0x02},
228 {0x37e0, 0x00},
229 {0x37e1, 0x0a},
230 {0x37e2, 0x14},
231 {0x37e3, 0x04},
232 {0x37e4, 0x2a},
233 {0x37e5, 0x03},
234 {0x37e6, 0x04},
235 {0x3800, 0x00},
236 {0x3801, 0x00},
237 {0x3802, 0x00},
238 {0x3803, 0x08},
239 {0x3804, 0x10},
240 {0x3805, 0x9f},
241 {0x3806, 0x0c},
242 {0x3807, 0x57},
243 {0x3808, 0x10},
244 {0x3809, 0x80},
245 {0x380a, 0x0c},
246 {0x380b, 0x40},
247 {0x380c, 0x04},
248 {0x380d, 0x62},
249 {0x380e, 0x0c},
250 {0x380f, 0x8e},
251 {0x3811, 0x10},
252 {0x3813, 0x08},
253 {0x3814, 0x01},
254 {0x3815, 0x01},
255 {0x3816, 0x01},
256 {0x3817, 0x01},
257 {0x3820, 0xa8},
258 {0x3821, 0x00},
259 {0x3822, 0xc2},
260 {0x3823, 0x18},
261 {0x3826, 0x11},
262 {0x3827, 0x1c},
263 {0x3829, 0x03},
264 {0x3832, 0x00},
265 {0x3c80, 0x00},
266 {0x3c87, 0x01},
267 {0x3c8c, 0x19},
268 {0x3c8d, 0x1c},
269 {0x3c90, 0x00},
270 {0x3c91, 0x00},
271 {0x3c92, 0x00},
272 {0x3c93, 0x00},
273 {0x3c94, 0x40},
274 {0x3c95, 0x54},
275 {0x3c96, 0x34},
276 {0x3c97, 0x04},
277 {0x3c98, 0x00},
278 {0x3d8c, 0x73},
279 {0x3d8d, 0xc0},
280 {0x3f00, 0x0b},
281 {0x3f03, 0x00},
282 {0x4001, 0xe0},
283 {0x4008, 0x00},
284 {0x4009, 0x0f},
285 {0x4011, 0xf0},
286 {0x4050, 0x04},
287 {0x4051, 0x0b},
288 {0x4052, 0x00},
289 {0x4053, 0x80},
290 {0x4054, 0x00},
291 {0x4055, 0x80},
292 {0x4056, 0x00},
293 {0x4057, 0x80},
294 {0x4058, 0x00},
295 {0x4059, 0x80},
296 {0x405e, 0x00},
297 {0x4500, 0x07},
298 {0x4503, 0x00},
299 {0x450a, 0x04},
300 {0x4809, 0x04},
301 {0x480c, 0x12},
302 {0x481f, 0x30},
303 {0x4833, 0x10},
304 {0x4837, 0x0e},
305 {0x4902, 0x01},
306 {0x4d00, 0x03},
307 {0x4d01, 0xc9},
308 {0x4d02, 0xbc},
309 {0x4d03, 0xd7},
310 {0x4d04, 0xf0},
311 {0x4d05, 0xa2},
312 {0x5000, 0xff},
313 {0x5001, 0x07},
314 {0x5040, 0x39},
315 {0x5041, 0x10},
316 {0x5042, 0x10},
317 {0x5043, 0x84},
318 {0x5044, 0x62},
319 {0x5180, 0x00},
320 {0x5181, 0x10},
321 {0x5182, 0x02},
322 {0x5183, 0x0f},
323 {0x5200, 0x1b},
324 {0x520b, 0x07},
325 {0x520c, 0x0f},
326 {0x5300, 0x04},
327 {0x5301, 0x0C},
328 {0x5302, 0x0C},
329 {0x5303, 0x0f},
330 {0x5304, 0x00},
331 {0x5305, 0x70},
332 {0x5306, 0x00},
333 {0x5307, 0x80},
334 {0x5308, 0x00},
335 {0x5309, 0xa5},
336 {0x530a, 0x00},
337 {0x530b, 0xd3},
338 {0x530c, 0x00},
339 {0x530d, 0xf0},
340 {0x530e, 0x01},
341 {0x530f, 0x10},
342 {0x5310, 0x01},
343 {0x5311, 0x20},
344 {0x5312, 0x01},
345 {0x5313, 0x20},
346 {0x5314, 0x01},
347 {0x5315, 0x20},
348 {0x5316, 0x08},
349 {0x5317, 0x08},
350 {0x5318, 0x10},
351 {0x5319, 0x88},
352 {0x531a, 0x88},
353 {0x531b, 0xa9},
354 {0x531c, 0xaa},
355 {0x531d, 0x0a},
356 {0x5405, 0x02},
357 {0x5406, 0x67},
358 {0x5407, 0x01},
359 {0x5408, 0x4a},
360 {REG_NULL, 0x00},
361 };
362
363 #ifdef DEBUG
364 /*
365 * Xclk 24Mhz
366 * max_framerate 30fps
367 * mipi_datarate per lane 540Mbps
368 */
369 static const struct regval ov13855_2112x1568_60fps_regs[] = {
370 {0x0300, 0x02},
371 {0x0301, 0x00},
372 {0x0302, 0x5a},
373 {0x0303, 0x01},
374 {0x0304, 0x00},
375 {0x0305, 0x01},
376 {0x3022, 0x01},
377 {0x3013, 0x32},
378 {0x3016, 0x72},
379 {0x301b, 0xf0},
380 {0x301f, 0xd0},
381 {0x3106, 0x15},
382 {0x3107, 0x23},
383 {0x3500, 0x00},
384 {0x3501, 0x64},
385 {0x3502, 0x00},
386 {0x3622, 0x30},
387 {0x3624, 0x1c},
388 {0x3662, 0x10},
389 {0x3709, 0x5f},
390 {0x3714, 0x28},
391 {0x3737, 0x08},
392 {0x3739, 0x20},
393 {0x37a1, 0x36},
394 {0x37a8, 0x3b},
395 {0x37ab, 0x31},
396 {0x37c2, 0x14},
397 {0x37d9, 0x0c},
398 {0x37e1, 0x0a},
399 {0x37e2, 0x14},
400 {0x37e3, 0x08},
401 {0x37e4, 0x38},
402 {0x37e5, 0x03},
403 {0x37e6, 0x08},
404 {0x3800, 0x00},
405 {0x3801, 0x00},
406 {0x3802, 0x00},
407
408 {0x3803, 0x08},
409 {0x3804, 0x10},
410 {0x3805, 0x9f},
411 {0x3806, 0x0c},
412 {0x3807, 0x4f},
413 {0x3808, 0x08},
414 {0x3809, 0x40},
415 {0x380a, 0x06},
416 {0x380b, 0x20},
417 {0x380c, 0x04},
418 {0x380d, 0x62},
419 {0x380e, 0x0c},
420 {0x380f, 0x89},
421 {0x3811, 0x08},
422 {0x3812, 0x00},
423 {0x3813, 0x02},
424 {0x3814, 0x03},
425 {0x3815, 0x01},
426 {0x3816, 0x03},
427 {0x3817, 0x01},
428 {0x3820, 0xab},
429 {0x3821, 0x00},
430 {0x3826, 0x04},
431 {0x3827, 0x90},
432 {0x3829, 0x07},
433 {0x3f03, 0x00},
434 {0x4009, 0x0d},
435 {0x4011, 0xf0},
436 {0x4050, 0x04},
437 {0x4051, 0x0b},
438 {0x4500, 0x07},
439 {0x4837, 0x1c},
440 {0x4902, 0x01},
441 {0x4d00, 0x03},
442 {0x4d01, 0xc9},
443 {0x4d02, 0xbc},
444 {0x4d03, 0xd7},
445 {0x4d04, 0xf0},
446 {0x4d05, 0xa2},
447 {0x5000, 0xff},
448
449 {0x5041, 0x10},
450 {0x5042, 0x10},
451 {0x5043, 0x84},
452 {0x5044, 0x62},
453 {0x5300, 0x04},
454 {0x5301, 0x0C},
455 {0x5302, 0x0C},
456 {0x5303, 0x0f},
457 {0x5305, 0x70},
458 {0x5307, 0x80},
459 {0x5309, 0xa5},
460 {0x530b, 0xd3},
461 {0x5319, 0x88},
462 {0x531a, 0x88},
463 {0x531b, 0xa9},
464 {0x531c, 0xaa},
465 {0x531d, 0x0a},
466 {0x5405, 0x02},
467 {0x5406, 0x67},
468 {0x5407, 0x01},
469 {0x5408, 0x4a},
470
471 {REG_NULL, 0x00},
472 };
473
474 /*
475 * Xclk 24Mhz
476 * max_framerate 15fps
477 * mipi_datarate per lane 1080Mbps
478 */
479 static const struct regval ov13855_4224x3136_15fps_regs[] = {
480 {0x0300, 0x02},
481 {0x0301, 0x00},
482 {0x0302, 0x5a},
483 {0x0303, 0x00},
484 {0x0304, 0x00},
485 {0x0305, 0x01},
486 {0x030b, 0x06},
487 {0x030c, 0x02},
488 {0x030d, 0x88},
489 {0x0312, 0x11},
490 {0x3022, 0x01},
491 {0x3012, 0x40},
492 {0x3013, 0x72},
493 {0x3016, 0x72},
494 {0x301b, 0xF0},
495 {0x301f, 0xd0},
496 {0x3106, 0x15},
497 {0x3107, 0x23},
498 {0x3500, 0x00},
499 {0x3501, 0x80},
500 {0x3502, 0x00},
501 {0x3508, 0x02},
502 {0x3509, 0x00},
503 {0x350a, 0x00},
504 {0x350e, 0x00},
505 {0x3510, 0x00},
506 {0x3511, 0x02},
507 {0x3512, 0x00},
508 {0x3600, 0x2b},
509 {0x3601, 0x52},
510 {0x3602, 0x60},
511 {0x3612, 0x05},
512 {0x3613, 0xa4},
513 {0x3620, 0x80},
514 {0x3621, 0x10},
515 {0x3622, 0x30},
516 {0x3624, 0x1c},
517 {0x3640, 0x10},
518 {0x3641, 0x70},
519 {0x3660, 0x04},
520 {0x3661, 0x80},
521 {0x3662, 0x12},
522 {0x3664, 0x73},
523 {0x3665, 0xa7},
524 {0x366e, 0xff},
525 {0x366f, 0xf4},
526 {0x3674, 0x00},
527 {0x3679, 0x0c},
528 {0x367f, 0x01},
529 {0x3680, 0x0c},
530 {0x3681, 0x50},
531 {0x3682, 0x50},
532 {0x3683, 0xa9},
533 {0x3684, 0xa9},
534 {0x3706, 0x40},
535 {0x3709, 0x5f},
536 {0x3714, 0x24},
537 {0x371a, 0x3e},
538 {0x3737, 0x04},
539 {0x3738, 0xcc},
540 {0x3739, 0x12},
541 {0x373d, 0x26},
542 {0x3764, 0x20},
543 {0x3765, 0x20},
544 {0x37a1, 0x36},
545 {0x37a8, 0x3b},
546 {0x37ab, 0x31},
547 {0x37c2, 0x04},
548 {0x37c3, 0xf1},
549 {0x37c5, 0x00},
550 {0x37d8, 0x03},
551 {0x37d9, 0x0c},
552 {0x37da, 0xc2},
553 {0x37dc, 0x02},
554 {0x37e0, 0x00},
555 {0x37e1, 0x0a},
556 {0x37e2, 0x14},
557 {0x37e3, 0x04},
558 {0x37e4, 0x2A},
559 {0x37e5, 0x03},
560 {0x37e6, 0x04},
561 {0x3800, 0x00},
562 {0x3801, 0x00},
563 {0x3802, 0x00},
564 {0x3803, 0x08},
565 {0x3804, 0x10},
566 {0x3805, 0x9f},
567 {0x3806, 0x0c},
568 {0x3807, 0x57},
569 {0x3808, 0x10},
570 {0x3809, 0x80},
571 {0x380a, 0x0c},
572 {0x380b, 0x40},
573 {0x380c, 0x04},
574 {0x380d, 0x62},
575 {0x380e, 0x0c},
576 {0x380f, 0x8e},
577 {0x3811, 0x10},
578 {0x3813, 0x08},
579 {0x3814, 0x01},
580 {0x3815, 0x01},
581 {0x3816, 0x01},
582 {0x3817, 0x01},
583 {0x3820, 0xa8},
584 {0x3821, 0x00},
585 {0x3822, 0xd2},
586 {0x3823, 0x18},
587 {0x3826, 0x11},
588 {0x3827, 0x1c},
589 {0x3829, 0x03},
590 {0x3832, 0x00},
591 {0x3c80, 0x00},
592 {0x3c87, 0x01},
593 {0x3c8c, 0x19},
594 {0x3c8d, 0x1c},
595 {0x3c90, 0x00},
596 {0x3c91, 0x00},
597 {0x3c92, 0x00},
598 {0x3c93, 0x00},
599 {0x3c94, 0x40},
600 {0x3c95, 0x54},
601 {0x3c96, 0x34},
602 {0x3c97, 0x04},
603 {0x3c98, 0x00},
604 {0x3d8c, 0x73},
605 {0x3d8d, 0xc0},
606 {0x3f00, 0x0b},
607 {0x3f03, 0x00},
608 {0x4001, 0xe0},
609 {0x4008, 0x00},
610 {0x4009, 0x0f},
611 {0x4011, 0xf0},
612 {0x4017, 0x08},
613 {0x4050, 0x04},
614 {0x4051, 0x0b},
615 {0x4052, 0x00},
616 {0x4053, 0x80},
617 {0x4054, 0x00},
618 {0x4055, 0x80},
619 {0x4056, 0x00},
620 {0x4057, 0x80},
621 {0x4058, 0x00},
622 {0x4059, 0x80},
623 {0x405e, 0x00},
624 {0x4500, 0x07},
625 {0x4503, 0x00},
626 {0x450a, 0x04},
627 {0x4800, 0x60},
628 {0x4809, 0x04},
629 {0x480c, 0x12},
630 {0x481f, 0x30},
631 {0x4833, 0x10},
632 {0x4837, 0x0e},
633 {0x4902, 0x01},
634 {0x4d00, 0x03},
635 {0x4d01, 0xc9},
636 {0x4d02, 0xbc},
637 {0x4d03, 0xd7},
638 {0x4d04, 0xf0},
639 {0x4d05, 0xa2},
640 {0x5000, 0xff},
641 {0x5001, 0x07},
642 {0x5040, 0x39},
643 {0x5041, 0x10},
644 {0x5042, 0x10},
645 {0x5043, 0x84},
646 {0x5044, 0x62},
647 {0x5180, 0x00},
648 {0x5181, 0x10},
649 {0x5182, 0x02},
650 {0x5183, 0x0f},
651 {0x5200, 0x1b},
652 {0x520b, 0x07},
653 {0x520c, 0x0f},
654 {0x5300, 0x04},
655 {0x5301, 0x0C},
656 {0x5302, 0x0C},
657 {0x5303, 0x0f},
658 {0x5304, 0x00},
659 {0x5305, 0x70},
660 {0x5306, 0x00},
661 {0x5307, 0x80},
662 {0x5308, 0x00},
663 {0x5309, 0xa5},
664 {0x530a, 0x00},
665 {0x530b, 0xd3},
666 {0x530c, 0x00},
667 {0x530d, 0xf0},
668 {0x530e, 0x01},
669 {0x530f, 0x10},
670 {0x5310, 0x01},
671 {0x5311, 0x20},
672 {0x5312, 0x01},
673 {0x5313, 0x20},
674 {0x5314, 0x01},
675 {0x5315, 0x20},
676 {0x5316, 0x08},
677 {0x5317, 0x08},
678 {0x5318, 0x10},
679 {0x5319, 0x88},
680 {0x531a, 0x88},
681 {0x531b, 0xa9},
682 {0x531c, 0xaa},
683 {0x531d, 0x0a},
684 {0x5405, 0x02},
685 {0x5406, 0x67},
686 {0x5407, 0x01},
687 {0x5408, 0x4a},
688 {0x0100, 0x01},
689 {0x0100, 0x00},
690 {0x380c, 0x08},
691 {0x380d, 0xc4},
692 {0x0303, 0x01},
693 {0x4837, 0x1c},
694 //{0x0100, 0x01},
695 {REG_NULL, 0x00},
696 };
697 #endif
698
699 /*
700 * Xclk 24Mhz
701 * max_framerate 30fps
702 * mipi_datarate per lane 1080Mbps
703 */
704 static const struct regval ov13855_4224x3136_30fps_regs[] = {
705 {0x0300, 0x02},
706 {0x0301, 0x00},
707 {0x0302, 0x5a},
708 {0x0303, 0x00},
709 {0x0304, 0x00},
710 {0x0305, 0x01},
711 {0x030b, 0x06},
712 {0x030c, 0x02},
713 {0x030d, 0x88},
714 {0x0312, 0x11},
715 {0x3022, 0x01},
716 {0x3012, 0x40},
717 {0x3013, 0x72},
718 {0x3016, 0x72},
719 {0x301b, 0xF0},
720 {0x301f, 0xd0},
721 {0x3106, 0x15},
722 {0x3107, 0x23},
723 {0x3500, 0x00},
724 {0x3501, 0x80},
725 {0x3502, 0x00},
726 {0x3508, 0x02},
727 {0x3509, 0x00},
728 {0x350a, 0x00},
729 {0x350e, 0x00},
730 {0x3510, 0x00},
731 {0x3511, 0x02},
732 {0x3512, 0x00},
733 {0x3600, 0x2b},
734 {0x3601, 0x52},
735 {0x3602, 0x60},
736 {0x3612, 0x05},
737 {0x3613, 0xa4},
738 {0x3620, 0x80},
739 {0x3621, 0x10},
740 {0x3622, 0x30},
741 {0x3624, 0x1c},
742 {0x3640, 0x10},
743 {0x3641, 0x70},
744 {0x3660, 0x04},
745 {0x3661, 0x80},
746 {0x3662, 0x12},
747 {0x3664, 0x73},
748 {0x3665, 0xa7},
749 {0x366e, 0xff},
750 {0x366f, 0xf4},
751 {0x3674, 0x00},
752 {0x3679, 0x0c},
753 {0x367f, 0x01},
754 {0x3680, 0x0c},
755 {0x3681, 0x50},
756 {0x3682, 0x50},
757 {0x3683, 0xa9},
758 {0x3684, 0xa9},
759 {0x3706, 0x40},
760 {0x3709, 0x5f},
761 {0x3714, 0x24},
762 {0x371a, 0x3e},
763 {0x3737, 0x04},
764 {0x3738, 0xcc},
765 {0x3739, 0x12},
766 {0x373d, 0x26},
767 {0x3764, 0x20},
768 {0x3765, 0x20},
769 {0x37a1, 0x36},
770 {0x37a8, 0x3b},
771 {0x37ab, 0x31},
772 {0x37c2, 0x04},
773 {0x37c3, 0xf1},
774 {0x37c5, 0x00},
775 {0x37d8, 0x03},
776 {0x37d9, 0x0c},
777 {0x37da, 0xc2},
778 {0x37dc, 0x02},
779 {0x37e0, 0x00},
780 {0x37e1, 0x0a},
781 {0x37e2, 0x14},
782 {0x37e3, 0x04},
783 {0x37e4, 0x2A},
784 {0x37e5, 0x03},
785 {0x37e6, 0x04},
786 {0x3800, 0x00},
787 {0x3801, 0x00},
788 {0x3802, 0x00},
789 {0x3803, 0x08},
790 {0x3804, 0x10},
791 {0x3805, 0x9f},
792 {0x3806, 0x0c},
793 {0x3807, 0x57},
794 {0x3808, 0x10},
795 {0x3809, 0x80},
796 {0x380a, 0x0c},
797 {0x380b, 0x40},
798 {0x380c, 0x04},
799 {0x380d, 0x62},
800 {0x380e, 0x0c},
801 {0x380f, 0x8e},
802 {0x3811, 0x10},
803 {0x3813, 0x08},
804 {0x3814, 0x01},
805 {0x3815, 0x01},
806 {0x3816, 0x01},
807 {0x3817, 0x01},
808 {0x3820, 0xa8},
809 {0x3821, 0x00},
810 {0x3822, 0xd2},
811 {0x3823, 0x18},
812 {0x3826, 0x11},
813 {0x3827, 0x1c},
814 {0x3829, 0x03},
815 {0x3832, 0x00},
816 {0x3c80, 0x00},
817 {0x3c87, 0x01},
818 {0x3c8c, 0x19},
819 {0x3c8d, 0x1c},
820 {0x3c90, 0x00},
821 {0x3c91, 0x00},
822 {0x3c92, 0x00},
823 {0x3c93, 0x00},
824 {0x3c94, 0x40},
825 {0x3c95, 0x54},
826 {0x3c96, 0x34},
827 {0x3c97, 0x04},
828 {0x3c98, 0x00},
829 {0x3d8c, 0x73},
830 {0x3d8d, 0xc0},
831 {0x3f00, 0x0b},
832 {0x3f03, 0x00},
833 {0x4001, 0xe0},
834 {0x4008, 0x00},
835 {0x4009, 0x0f},
836 {0x4011, 0xf0},
837 {0x4017, 0x08},
838 {0x4050, 0x04},
839 {0x4051, 0x0b},
840 {0x4052, 0x00},
841 {0x4053, 0x80},
842 {0x4054, 0x00},
843 {0x4055, 0x80},
844 {0x4056, 0x00},
845 {0x4057, 0x80},
846 {0x4058, 0x00},
847 {0x4059, 0x80},
848 {0x405e, 0x00},
849 {0x4500, 0x07},
850 {0x4503, 0x00},
851 {0x450a, 0x04},
852 {0x4800, 0x60},
853 {0x4809, 0x04},
854 {0x480c, 0x12},
855 {0x481f, 0x30},
856 {0x4833, 0x10},
857 {0x4837, 0x0e},
858 {0x4902, 0x01},
859 {0x4d00, 0x03},
860 {0x4d01, 0xc9},
861 {0x4d02, 0xbc},
862 {0x4d03, 0xd7},
863 {0x4d04, 0xf0},
864 {0x4d05, 0xa2},
865 {0x5000, 0xff},
866 {0x5001, 0x07},
867 {0x5040, 0x39},
868 {0x5041, 0x10},
869 {0x5042, 0x10},
870 {0x5043, 0x84},
871 {0x5044, 0x62},
872 {0x5180, 0x00},
873 {0x5181, 0x10},
874 {0x5182, 0x02},
875 {0x5183, 0x0f},
876 {0x5200, 0x1b},
877 {0x520b, 0x07},
878 {0x520c, 0x0f},
879 {0x5300, 0x04},
880 {0x5301, 0x0C},
881 {0x5302, 0x0C},
882 {0x5303, 0x0f},
883 {0x5304, 0x00},
884 {0x5305, 0x70},
885 {0x5306, 0x00},
886 {0x5307, 0x80},
887 {0x5308, 0x00},
888 {0x5309, 0xa5},
889 {0x530a, 0x00},
890 {0x530b, 0xd3},
891 {0x530c, 0x00},
892 {0x530d, 0xf0},
893 {0x530e, 0x01},
894 {0x530f, 0x10},
895 {0x5310, 0x01},
896 {0x5311, 0x20},
897 {0x5312, 0x01},
898 {0x5313, 0x20},
899 {0x5314, 0x01},
900 {0x5315, 0x20},
901 {0x5316, 0x08},
902 {0x5317, 0x08},
903 {0x5318, 0x10},
904 {0x5319, 0x88},
905 {0x531a, 0x88},
906 {0x531b, 0xa9},
907 {0x531c, 0xaa},
908 {0x531d, 0x0a},
909 {0x5405, 0x02},
910 {0x5406, 0x67},
911 {0x5407, 0x01},
912 {0x5408, 0x4a},
913 {0x0100, 0x01},
914 {0x0100, 0x00},
915 {0x380c, 0x04},
916 {0x380d, 0x62},
917 {0x0303, 0x00},
918 {0x4837, 0x0e},
919 //{0x0100, 0x01},
920 {REG_NULL, 0x00},
921 };
922
923 static const struct ov13855_mode supported_modes[] = {
924 {
925 .width = 4224,
926 .height = 3136,
927 .max_fps = {
928 .numerator = 10000,
929 .denominator = 300000,
930 },
931 .exp_def = 0x0800,
932 .hts_def = 0x0462,
933 .vts_def = 0x0c8e,
934 .bpp = 10,
935 .reg_list = ov13855_4224x3136_30fps_regs,
936 .link_freq_idx = 0,
937 },
938 #ifdef DEBUG
939 {
940 .width = 2112,
941 .height = 1568,
942 .max_fps = {
943 .numerator = 10000,
944 .denominator = 600000,
945 },
946 .exp_def = 0x0400,
947 .hts_def = 0x0462,
948 .vts_def = 0x0c89,
949 .bpp = 10,
950 .reg_list = ov13855_2112x1568_60fps_regs,
951 .link_freq_idx = 1,
952 },
953 {
954 .width = 4224,
955 .height = 3136,
956 .max_fps = {
957 .numerator = 10000,
958 .denominator = 150000,
959 },
960 .exp_def = 0x0800,
961 .hts_def = 0x08c4,
962 .vts_def = 0x0c8e,
963 .bpp = 10,
964 .reg_list = ov13855_4224x3136_15fps_regs,
965 .link_freq_idx = 0,
966 },
967 #endif
968 };
969
970 static const s64 link_freq_items[] = {
971 OV13855_LINK_FREQ_540MHZ,
972 OV13855_LINK_FREQ_270MHZ,
973 };
974
975 static const char * const ov13855_test_pattern_menu[] = {
976 "Disabled",
977 "Vertical Color Bar Type 1",
978 "Vertical Color Bar Type 2",
979 "Vertical Color Bar Type 3",
980 "Vertical Color Bar Type 4"
981 };
982
983 /* Write registers up to 4 at a time */
ov13855_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)984 static int ov13855_write_reg(struct i2c_client *client, u16 reg,
985 u32 len, u32 val)
986 {
987 u32 buf_i, val_i;
988 u8 buf[6];
989 u8 *val_p;
990 __be32 val_be;
991
992 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
993
994 if (len > 4)
995 return -EINVAL;
996
997 buf[0] = reg >> 8;
998 buf[1] = reg & 0xff;
999
1000 val_be = cpu_to_be32(val);
1001 val_p = (u8 *)&val_be;
1002 buf_i = 2;
1003 val_i = 4 - len;
1004
1005 while (val_i < 4)
1006 buf[buf_i++] = val_p[val_i++];
1007
1008 if (i2c_master_send(client, buf, len + 2) != len + 2)
1009 return -EIO;
1010
1011 return 0;
1012 }
1013
ov13855_write_array(struct i2c_client * client,const struct regval * regs)1014 static int ov13855_write_array(struct i2c_client *client,
1015 const struct regval *regs)
1016 {
1017 u32 i;
1018 int ret = 0;
1019
1020 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
1021 ret = ov13855_write_reg(client, regs[i].addr,
1022 OV13855_REG_VALUE_08BIT,
1023 regs[i].val);
1024
1025 return ret;
1026 }
1027
1028 /* Read registers up to 4 at a time */
ov13855_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1029 static int ov13855_read_reg(struct i2c_client *client, u16 reg,
1030 unsigned int len, u32 *val)
1031 {
1032 struct i2c_msg msgs[2];
1033 u8 *data_be_p;
1034 __be32 data_be = 0;
1035 __be16 reg_addr_be = cpu_to_be16(reg);
1036 int ret;
1037
1038 if (len > 4 || !len)
1039 return -EINVAL;
1040
1041 data_be_p = (u8 *)&data_be;
1042 /* Write register address */
1043 msgs[0].addr = client->addr;
1044 msgs[0].flags = 0;
1045 msgs[0].len = 2;
1046 msgs[0].buf = (u8 *)®_addr_be;
1047
1048 /* Read data from register */
1049 msgs[1].addr = client->addr;
1050 msgs[1].flags = I2C_M_RD;
1051 msgs[1].len = len;
1052 msgs[1].buf = &data_be_p[4 - len];
1053
1054 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1055 if (ret != ARRAY_SIZE(msgs))
1056 return -EIO;
1057
1058 *val = be32_to_cpu(data_be);
1059
1060 return 0;
1061 }
1062
ov13855_get_reso_dist(const struct ov13855_mode * mode,struct v4l2_mbus_framefmt * framefmt)1063 static int ov13855_get_reso_dist(const struct ov13855_mode *mode,
1064 struct v4l2_mbus_framefmt *framefmt)
1065 {
1066 return abs(mode->width - framefmt->width) +
1067 abs(mode->height - framefmt->height);
1068 }
1069
1070 static const struct ov13855_mode *
ov13855_find_best_fit(struct v4l2_subdev_format * fmt)1071 ov13855_find_best_fit(struct v4l2_subdev_format *fmt)
1072 {
1073 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1074 int dist;
1075 int cur_best_fit = 0;
1076 int cur_best_fit_dist = -1;
1077 unsigned int i;
1078
1079 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1080 dist = ov13855_get_reso_dist(&supported_modes[i], framefmt);
1081 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1082 cur_best_fit_dist = dist;
1083 cur_best_fit = i;
1084 }
1085 }
1086
1087 return &supported_modes[cur_best_fit];
1088 }
1089
ov13855_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1090 static int ov13855_set_fmt(struct v4l2_subdev *sd,
1091 struct v4l2_subdev_pad_config *cfg,
1092 struct v4l2_subdev_format *fmt)
1093 {
1094 struct ov13855 *ov13855 = to_ov13855(sd);
1095 const struct ov13855_mode *mode;
1096 s64 h_blank, vblank_def;
1097 u64 pixel_rate = 0;
1098 u32 lane_num = OV13855_LANES;
1099
1100 mutex_lock(&ov13855->mutex);
1101
1102 mode = ov13855_find_best_fit(fmt);
1103 fmt->format.code = OV13855_MEDIA_BUS_FMT;
1104 fmt->format.width = mode->width;
1105 fmt->format.height = mode->height;
1106 fmt->format.field = V4L2_FIELD_NONE;
1107 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1108 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1109 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1110 #else
1111 mutex_unlock(&ov13855->mutex);
1112 return -ENOTTY;
1113 #endif
1114 } else {
1115 ov13855->cur_mode = mode;
1116 h_blank = mode->hts_def - mode->width;
1117 __v4l2_ctrl_modify_range(ov13855->hblank, h_blank,
1118 h_blank, 1, h_blank);
1119 vblank_def = mode->vts_def - mode->height;
1120 __v4l2_ctrl_modify_range(ov13855->vblank, vblank_def,
1121 OV13855_VTS_MAX - mode->height,
1122 1, vblank_def);
1123 __v4l2_ctrl_s_ctrl(ov13855->vblank, vblank_def);
1124 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1125
1126 __v4l2_ctrl_s_ctrl_int64(ov13855->pixel_rate,
1127 pixel_rate);
1128 __v4l2_ctrl_s_ctrl(ov13855->link_freq,
1129 mode->link_freq_idx);
1130 }
1131 dev_info(&ov13855->client->dev, "%s: mode->link_freq_idx(%d)",
1132 __func__, mode->link_freq_idx);
1133
1134 mutex_unlock(&ov13855->mutex);
1135
1136 return 0;
1137 }
1138
ov13855_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1139 static int ov13855_get_fmt(struct v4l2_subdev *sd,
1140 struct v4l2_subdev_pad_config *cfg,
1141 struct v4l2_subdev_format *fmt)
1142 {
1143 struct ov13855 *ov13855 = to_ov13855(sd);
1144 const struct ov13855_mode *mode = ov13855->cur_mode;
1145
1146 mutex_lock(&ov13855->mutex);
1147 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1148 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1149 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1150 #else
1151 mutex_unlock(&ov13855->mutex);
1152 return -ENOTTY;
1153 #endif
1154 } else {
1155 fmt->format.width = mode->width;
1156 fmt->format.height = mode->height;
1157 fmt->format.code = OV13855_MEDIA_BUS_FMT;
1158 fmt->format.field = V4L2_FIELD_NONE;
1159 }
1160 mutex_unlock(&ov13855->mutex);
1161
1162 return 0;
1163 }
1164
ov13855_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1165 static int ov13855_enum_mbus_code(struct v4l2_subdev *sd,
1166 struct v4l2_subdev_pad_config *cfg,
1167 struct v4l2_subdev_mbus_code_enum *code)
1168 {
1169 if (code->index != 0)
1170 return -EINVAL;
1171 code->code = OV13855_MEDIA_BUS_FMT;
1172
1173 return 0;
1174 }
1175
ov13855_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1176 static int ov13855_enum_frame_sizes(struct v4l2_subdev *sd,
1177 struct v4l2_subdev_pad_config *cfg,
1178 struct v4l2_subdev_frame_size_enum *fse)
1179 {
1180 if (fse->index >= ARRAY_SIZE(supported_modes))
1181 return -EINVAL;
1182
1183 if (fse->code != OV13855_MEDIA_BUS_FMT)
1184 return -EINVAL;
1185
1186 fse->min_width = supported_modes[fse->index].width;
1187 fse->max_width = supported_modes[fse->index].width;
1188 fse->max_height = supported_modes[fse->index].height;
1189 fse->min_height = supported_modes[fse->index].height;
1190
1191 return 0;
1192 }
1193
ov13855_enable_test_pattern(struct ov13855 * ov13855,u32 pattern)1194 static int ov13855_enable_test_pattern(struct ov13855 *ov13855, u32 pattern)
1195 {
1196 u32 val;
1197
1198 if (pattern)
1199 val = (pattern - 1) | OV13855_TEST_PATTERN_ENABLE;
1200 else
1201 val = OV13855_TEST_PATTERN_DISABLE;
1202
1203 return ov13855_write_reg(ov13855->client,
1204 OV13855_REG_TEST_PATTERN,
1205 OV13855_REG_VALUE_08BIT,
1206 val);
1207 }
1208
ov13855_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1209 static int ov13855_g_frame_interval(struct v4l2_subdev *sd,
1210 struct v4l2_subdev_frame_interval *fi)
1211 {
1212 struct ov13855 *ov13855 = to_ov13855(sd);
1213 const struct ov13855_mode *mode = ov13855->cur_mode;
1214
1215 fi->interval = mode->max_fps;
1216
1217 return 0;
1218 }
1219
ov13855_get_module_inf(struct ov13855 * ov13855,struct rkmodule_inf * inf)1220 static void ov13855_get_module_inf(struct ov13855 *ov13855,
1221 struct rkmodule_inf *inf)
1222 {
1223 memset(inf, 0, sizeof(*inf));
1224 strscpy(inf->base.sensor, OV13855_NAME, sizeof(inf->base.sensor));
1225 strscpy(inf->base.module, ov13855->module_name,
1226 sizeof(inf->base.module));
1227 strscpy(inf->base.lens, ov13855->len_name, sizeof(inf->base.lens));
1228 }
1229
ov13855_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1230 static long ov13855_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1231 {
1232 struct ov13855 *ov13855 = to_ov13855(sd);
1233 long ret = 0;
1234 u32 stream = 0;
1235
1236 switch (cmd) {
1237 case RKMODULE_GET_MODULE_INFO:
1238 ov13855_get_module_inf(ov13855, (struct rkmodule_inf *)arg);
1239 break;
1240 case RKMODULE_SET_QUICK_STREAM:
1241
1242 stream = *((u32 *)arg);
1243
1244 if (stream)
1245 ret = ov13855_write_reg(ov13855->client,
1246 OV13855_REG_CTRL_MODE,
1247 OV13855_REG_VALUE_08BIT,
1248 OV13855_MODE_STREAMING);
1249 else
1250 ret = ov13855_write_reg(ov13855->client,
1251 OV13855_REG_CTRL_MODE,
1252 OV13855_REG_VALUE_08BIT,
1253 OV13855_MODE_SW_STANDBY);
1254 break;
1255 default:
1256 ret = -ENOIOCTLCMD;
1257 break;
1258 }
1259
1260 return ret;
1261 }
1262
1263 #ifdef CONFIG_COMPAT
ov13855_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1264 static long ov13855_compat_ioctl32(struct v4l2_subdev *sd,
1265 unsigned int cmd, unsigned long arg)
1266 {
1267 void __user *up = compat_ptr(arg);
1268 struct rkmodule_inf *inf;
1269 struct rkmodule_awb_cfg *cfg;
1270 long ret = 0;
1271 u32 stream = 0;
1272
1273 switch (cmd) {
1274 case RKMODULE_GET_MODULE_INFO:
1275 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1276 if (!inf) {
1277 ret = -ENOMEM;
1278 return ret;
1279 }
1280
1281 ret = ov13855_ioctl(sd, cmd, inf);
1282 if (!ret) {
1283 ret = copy_to_user(up, inf, sizeof(*inf));
1284 if (ret)
1285 ret = -EFAULT;
1286 }
1287 kfree(inf);
1288 break;
1289 case RKMODULE_AWB_CFG:
1290 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1291 if (!cfg) {
1292 ret = -ENOMEM;
1293 return ret;
1294 }
1295
1296 ret = copy_from_user(cfg, up, sizeof(*cfg));
1297 if (!ret)
1298 ret = ov13855_ioctl(sd, cmd, cfg);
1299 else
1300 ret = -EFAULT;
1301 kfree(cfg);
1302 break;
1303 case RKMODULE_SET_QUICK_STREAM:
1304 ret = copy_from_user(&stream, up, sizeof(u32));
1305 if (!ret)
1306 ret = ov13855_ioctl(sd, cmd, &stream);
1307 else
1308 ret = -EFAULT;
1309 break;
1310 default:
1311 ret = -ENOIOCTLCMD;
1312 break;
1313 }
1314
1315 return ret;
1316 }
1317 #endif
1318
__ov13855_start_stream(struct ov13855 * ov13855)1319 static int __ov13855_start_stream(struct ov13855 *ov13855)
1320 {
1321 int ret;
1322
1323 ret = ov13855_write_array(ov13855->client, ov13855->cur_mode->reg_list);
1324 if (ret)
1325 return ret;
1326
1327 /* In case these controls are set before streaming */
1328 mutex_unlock(&ov13855->mutex);
1329 ret = v4l2_ctrl_handler_setup(&ov13855->ctrl_handler);
1330 mutex_lock(&ov13855->mutex);
1331 if (ret)
1332 return ret;
1333
1334 return ov13855_write_reg(ov13855->client,
1335 OV13855_REG_CTRL_MODE,
1336 OV13855_REG_VALUE_08BIT,
1337 OV13855_MODE_STREAMING);
1338 }
1339
__ov13855_stop_stream(struct ov13855 * ov13855)1340 static int __ov13855_stop_stream(struct ov13855 *ov13855)
1341 {
1342 return ov13855_write_reg(ov13855->client,
1343 OV13855_REG_CTRL_MODE,
1344 OV13855_REG_VALUE_08BIT,
1345 OV13855_MODE_SW_STANDBY);
1346 }
1347
ov13855_s_stream(struct v4l2_subdev * sd,int on)1348 static int ov13855_s_stream(struct v4l2_subdev *sd, int on)
1349 {
1350 struct ov13855 *ov13855 = to_ov13855(sd);
1351 struct i2c_client *client = ov13855->client;
1352 int ret = 0;
1353
1354 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1355 ov13855->cur_mode->width,
1356 ov13855->cur_mode->height,
1357 DIV_ROUND_CLOSEST(ov13855->cur_mode->max_fps.denominator,
1358 ov13855->cur_mode->max_fps.numerator));
1359
1360 mutex_lock(&ov13855->mutex);
1361 on = !!on;
1362 if (on == ov13855->streaming)
1363 goto unlock_and_return;
1364
1365 if (on) {
1366 ret = pm_runtime_get_sync(&client->dev);
1367 if (ret < 0) {
1368 pm_runtime_put_noidle(&client->dev);
1369 goto unlock_and_return;
1370 }
1371
1372 ret = __ov13855_start_stream(ov13855);
1373 if (ret) {
1374 v4l2_err(sd, "start stream failed while write regs\n");
1375 pm_runtime_put(&client->dev);
1376 goto unlock_and_return;
1377 }
1378 } else {
1379 __ov13855_stop_stream(ov13855);
1380 pm_runtime_put(&client->dev);
1381 }
1382
1383 ov13855->streaming = on;
1384
1385 unlock_and_return:
1386 mutex_unlock(&ov13855->mutex);
1387
1388 return ret;
1389 }
1390
ov13855_s_power(struct v4l2_subdev * sd,int on)1391 static int ov13855_s_power(struct v4l2_subdev *sd, int on)
1392 {
1393 struct ov13855 *ov13855 = to_ov13855(sd);
1394 struct i2c_client *client = ov13855->client;
1395 int ret = 0;
1396
1397 mutex_lock(&ov13855->mutex);
1398
1399 /* If the power state is not modified - no work to do. */
1400 if (ov13855->power_on == !!on)
1401 goto unlock_and_return;
1402
1403 if (on) {
1404 ret = pm_runtime_get_sync(&client->dev);
1405 if (ret < 0) {
1406 pm_runtime_put_noidle(&client->dev);
1407 goto unlock_and_return;
1408 }
1409
1410 ret = ov13855_write_array(ov13855->client, ov13855_global_regs);
1411 if (ret) {
1412 v4l2_err(sd, "could not set init registers\n");
1413 pm_runtime_put_noidle(&client->dev);
1414 goto unlock_and_return;
1415 }
1416
1417 ov13855->power_on = true;
1418 } else {
1419 pm_runtime_put(&client->dev);
1420 ov13855->power_on = false;
1421 }
1422
1423 unlock_and_return:
1424 mutex_unlock(&ov13855->mutex);
1425
1426 return ret;
1427 }
1428
1429 /* Calculate the delay in us by clock rate and clock cycles */
ov13855_cal_delay(u32 cycles)1430 static inline u32 ov13855_cal_delay(u32 cycles)
1431 {
1432 return DIV_ROUND_UP(cycles, OV13855_XVCLK_FREQ / 1000 / 1000);
1433 }
1434
__ov13855_power_on(struct ov13855 * ov13855)1435 static int __ov13855_power_on(struct ov13855 *ov13855)
1436 {
1437 int ret;
1438 u32 delay_us;
1439 struct device *dev = &ov13855->client->dev;
1440
1441 if (!IS_ERR(ov13855->power_gpio))
1442 gpiod_set_value_cansleep(ov13855->power_gpio, 1);
1443
1444 usleep_range(1000, 2000);
1445
1446 if (!IS_ERR_OR_NULL(ov13855->pins_default)) {
1447 ret = pinctrl_select_state(ov13855->pinctrl,
1448 ov13855->pins_default);
1449 if (ret < 0)
1450 dev_err(dev, "could not set pins\n");
1451 }
1452 ret = clk_set_rate(ov13855->xvclk, OV13855_XVCLK_FREQ);
1453 if (ret < 0)
1454 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1455 if (clk_get_rate(ov13855->xvclk) != OV13855_XVCLK_FREQ)
1456 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1457 ret = clk_prepare_enable(ov13855->xvclk);
1458 if (ret < 0) {
1459 dev_err(dev, "Failed to enable xvclk\n");
1460 return ret;
1461 }
1462 if (!IS_ERR(ov13855->reset_gpio))
1463 gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
1464
1465 ret = regulator_bulk_enable(OV13855_NUM_SUPPLIES, ov13855->supplies);
1466 if (ret < 0) {
1467 dev_err(dev, "Failed to enable regulators\n");
1468 goto disable_clk;
1469 }
1470
1471 if (!IS_ERR(ov13855->reset_gpio))
1472 gpiod_set_value_cansleep(ov13855->reset_gpio, 1);
1473
1474 usleep_range(5000, 6000);
1475 if (!IS_ERR(ov13855->pwdn_gpio))
1476 gpiod_set_value_cansleep(ov13855->pwdn_gpio, 1);
1477
1478 /* 8192 cycles prior to first SCCB transaction */
1479 delay_us = ov13855_cal_delay(8192);
1480 usleep_range(delay_us * 2, delay_us * 3);
1481
1482 return 0;
1483
1484 disable_clk:
1485 clk_disable_unprepare(ov13855->xvclk);
1486
1487 return ret;
1488 }
1489
__ov13855_power_off(struct ov13855 * ov13855)1490 static void __ov13855_power_off(struct ov13855 *ov13855)
1491 {
1492 int ret;
1493 struct device *dev = &ov13855->client->dev;
1494
1495 if (!IS_ERR(ov13855->pwdn_gpio))
1496 gpiod_set_value_cansleep(ov13855->pwdn_gpio, 0);
1497 clk_disable_unprepare(ov13855->xvclk);
1498 if (!IS_ERR(ov13855->reset_gpio))
1499 gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
1500
1501 if (!IS_ERR_OR_NULL(ov13855->pins_sleep)) {
1502 ret = pinctrl_select_state(ov13855->pinctrl,
1503 ov13855->pins_sleep);
1504 if (ret < 0)
1505 dev_dbg(dev, "could not set pins\n");
1506 }
1507 if (!IS_ERR(ov13855->power_gpio))
1508 gpiod_set_value_cansleep(ov13855->power_gpio, 0);
1509
1510 regulator_bulk_disable(OV13855_NUM_SUPPLIES, ov13855->supplies);
1511 }
1512
ov13855_runtime_resume(struct device * dev)1513 static int __maybe_unused ov13855_runtime_resume(struct device *dev)
1514 {
1515 struct i2c_client *client = to_i2c_client(dev);
1516 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1517 struct ov13855 *ov13855 = to_ov13855(sd);
1518
1519 return __ov13855_power_on(ov13855);
1520 }
1521
ov13855_runtime_suspend(struct device * dev)1522 static int __maybe_unused ov13855_runtime_suspend(struct device *dev)
1523 {
1524 struct i2c_client *client = to_i2c_client(dev);
1525 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1526 struct ov13855 *ov13855 = to_ov13855(sd);
1527
1528 __ov13855_power_off(ov13855);
1529
1530 return 0;
1531 }
1532
1533 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov13855_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1534 static int ov13855_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1535 {
1536 struct ov13855 *ov13855 = to_ov13855(sd);
1537 struct v4l2_mbus_framefmt *try_fmt =
1538 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1539 const struct ov13855_mode *def_mode = &supported_modes[0];
1540
1541 mutex_lock(&ov13855->mutex);
1542 /* Initialize try_fmt */
1543 try_fmt->width = def_mode->width;
1544 try_fmt->height = def_mode->height;
1545 try_fmt->code = OV13855_MEDIA_BUS_FMT;
1546 try_fmt->field = V4L2_FIELD_NONE;
1547
1548 mutex_unlock(&ov13855->mutex);
1549 /* No crop or compose */
1550
1551 return 0;
1552 }
1553 #endif
1554
ov13855_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1555 static int ov13855_enum_frame_interval(struct v4l2_subdev *sd,
1556 struct v4l2_subdev_pad_config *cfg,
1557 struct v4l2_subdev_frame_interval_enum *fie)
1558 {
1559 if (fie->index >= ARRAY_SIZE(supported_modes))
1560 return -EINVAL;
1561
1562 fie->code = OV13855_MEDIA_BUS_FMT;
1563 fie->width = supported_modes[fie->index].width;
1564 fie->height = supported_modes[fie->index].height;
1565 fie->interval = supported_modes[fie->index].max_fps;
1566
1567 return 0;
1568 }
1569
ov13855_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1570 static int ov13855_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1571 struct v4l2_mbus_config *config)
1572 {
1573 if (2 == OV13855_LANES) {
1574 config->type = V4L2_MBUS_CSI2_DPHY;
1575 config->flags = V4L2_MBUS_CSI2_2_LANE |
1576 V4L2_MBUS_CSI2_CHANNEL_0 |
1577 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1578 } else if (4 == OV13855_LANES) {
1579 config->type = V4L2_MBUS_CSI2_DPHY;
1580 config->flags = V4L2_MBUS_CSI2_4_LANE |
1581 V4L2_MBUS_CSI2_CHANNEL_0 |
1582 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1583 }
1584
1585 return 0;
1586 }
1587
ov13855_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1588 static int ov13855_get_selection(struct v4l2_subdev *sd,
1589 struct v4l2_subdev_pad_config *cfg,
1590 struct v4l2_subdev_selection *sel)
1591 {
1592 struct ov13855 *ov13855 = to_ov13855(sd);
1593
1594 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1595 sel->r.left = 0;
1596 sel->r.width = ov13855->cur_mode->width;
1597 sel->r.top = 0;
1598 sel->r.height = ov13855->cur_mode->height;
1599 return 0;
1600 }
1601
1602 return -EINVAL;
1603 }
1604
1605 static const struct dev_pm_ops ov13855_pm_ops = {
1606 SET_RUNTIME_PM_OPS(ov13855_runtime_suspend,
1607 ov13855_runtime_resume, NULL)
1608 };
1609
1610 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1611 static const struct v4l2_subdev_internal_ops ov13855_internal_ops = {
1612 .open = ov13855_open,
1613 };
1614 #endif
1615
1616 static const struct v4l2_subdev_core_ops ov13855_core_ops = {
1617 .s_power = ov13855_s_power,
1618 .ioctl = ov13855_ioctl,
1619 #ifdef CONFIG_COMPAT
1620 .compat_ioctl32 = ov13855_compat_ioctl32,
1621 #endif
1622 };
1623
1624 static const struct v4l2_subdev_video_ops ov13855_video_ops = {
1625 .s_stream = ov13855_s_stream,
1626 .g_frame_interval = ov13855_g_frame_interval,
1627 };
1628
1629 static const struct v4l2_subdev_pad_ops ov13855_pad_ops = {
1630 .enum_mbus_code = ov13855_enum_mbus_code,
1631 .enum_frame_size = ov13855_enum_frame_sizes,
1632 .enum_frame_interval = ov13855_enum_frame_interval,
1633 .get_fmt = ov13855_get_fmt,
1634 .set_fmt = ov13855_set_fmt,
1635 .get_selection = ov13855_get_selection,
1636 .get_mbus_config = ov13855_g_mbus_config,
1637 };
1638
1639 static const struct v4l2_subdev_ops ov13855_subdev_ops = {
1640 .core = &ov13855_core_ops,
1641 .video = &ov13855_video_ops,
1642 .pad = &ov13855_pad_ops,
1643 };
1644
ov13855_set_ctrl(struct v4l2_ctrl * ctrl)1645 static int ov13855_set_ctrl(struct v4l2_ctrl *ctrl)
1646 {
1647 struct ov13855 *ov13855 = container_of(ctrl->handler,
1648 struct ov13855, ctrl_handler);
1649 struct i2c_client *client = ov13855->client;
1650 s64 max;
1651 int ret = 0;
1652
1653 /* Propagate change of current control to all related controls */
1654 switch (ctrl->id) {
1655 case V4L2_CID_VBLANK:
1656 /* Update max exposure while meeting expected vblanking */
1657 max = ov13855->cur_mode->height + ctrl->val - 4;
1658 __v4l2_ctrl_modify_range(ov13855->exposure,
1659 ov13855->exposure->minimum, max,
1660 ov13855->exposure->step,
1661 ov13855->exposure->default_value);
1662 break;
1663 }
1664
1665 if (!pm_runtime_get_if_in_use(&client->dev))
1666 return 0;
1667
1668 switch (ctrl->id) {
1669 case V4L2_CID_EXPOSURE:
1670 /* 4 least significant bits of expsoure are fractional part */
1671 ret = ov13855_write_reg(ov13855->client,
1672 OV13855_REG_EXPOSURE,
1673 OV13855_REG_VALUE_24BIT,
1674 ctrl->val << 4);
1675 break;
1676 case V4L2_CID_ANALOGUE_GAIN:
1677 ret = ov13855_write_reg(ov13855->client,
1678 OV13855_REG_GAIN_H,
1679 OV13855_REG_VALUE_08BIT,
1680 (ctrl->val >> OV13855_GAIN_H_SHIFT) &
1681 OV13855_GAIN_H_MASK);
1682 ret |= ov13855_write_reg(ov13855->client,
1683 OV13855_REG_GAIN_L,
1684 OV13855_REG_VALUE_08BIT,
1685 ctrl->val & OV13855_GAIN_L_MASK);
1686 break;
1687 case V4L2_CID_VBLANK:
1688 ret = ov13855_write_reg(ov13855->client,
1689 OV13855_REG_VTS,
1690 OV13855_REG_VALUE_16BIT,
1691 ctrl->val + ov13855->cur_mode->height);
1692 break;
1693 case V4L2_CID_TEST_PATTERN:
1694 ret = ov13855_enable_test_pattern(ov13855, ctrl->val);
1695 break;
1696 default:
1697 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1698 __func__, ctrl->id, ctrl->val);
1699 break;
1700 }
1701
1702 pm_runtime_put(&client->dev);
1703
1704 return ret;
1705 }
1706
1707 static const struct v4l2_ctrl_ops ov13855_ctrl_ops = {
1708 .s_ctrl = ov13855_set_ctrl,
1709 };
1710
ov13855_initialize_controls(struct ov13855 * ov13855)1711 static int ov13855_initialize_controls(struct ov13855 *ov13855)
1712 {
1713 const struct ov13855_mode *mode;
1714 struct v4l2_ctrl_handler *handler;
1715 s64 exposure_max, vblank_def;
1716 u32 h_blank;
1717 int ret;
1718 u64 dst_pixel_rate = 0;
1719 u32 lane_num = OV13855_LANES;
1720
1721 handler = &ov13855->ctrl_handler;
1722 mode = ov13855->cur_mode;
1723 ret = v4l2_ctrl_handler_init(handler, 8);
1724 if (ret)
1725 return ret;
1726 handler->lock = &ov13855->mutex;
1727
1728 ov13855->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1729 V4L2_CID_LINK_FREQ,
1730 1, 0, link_freq_items);
1731
1732 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1733
1734 ov13855->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1735 V4L2_CID_PIXEL_RATE,
1736 0, OV13855_PIXEL_RATE,
1737 1, dst_pixel_rate);
1738
1739 __v4l2_ctrl_s_ctrl(ov13855->link_freq,
1740 mode->link_freq_idx);
1741
1742 h_blank = mode->hts_def - mode->width;
1743 ov13855->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1744 h_blank, h_blank, 1, h_blank);
1745 if (ov13855->hblank)
1746 ov13855->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1747
1748 vblank_def = mode->vts_def - mode->height;
1749 ov13855->vblank = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1750 V4L2_CID_VBLANK, vblank_def,
1751 OV13855_VTS_MAX - mode->height,
1752 1, vblank_def);
1753
1754 exposure_max = mode->vts_def - 4;
1755 ov13855->exposure = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1756 V4L2_CID_EXPOSURE, OV13855_EXPOSURE_MIN,
1757 exposure_max, OV13855_EXPOSURE_STEP,
1758 mode->exp_def);
1759
1760 ov13855->anal_gain = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
1761 V4L2_CID_ANALOGUE_GAIN, OV13855_GAIN_MIN,
1762 OV13855_GAIN_MAX, OV13855_GAIN_STEP,
1763 OV13855_GAIN_DEFAULT);
1764
1765 ov13855->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1766 &ov13855_ctrl_ops, V4L2_CID_TEST_PATTERN,
1767 ARRAY_SIZE(ov13855_test_pattern_menu) - 1,
1768 0, 0, ov13855_test_pattern_menu);
1769
1770 if (handler->error) {
1771 ret = handler->error;
1772 dev_err(&ov13855->client->dev,
1773 "Failed to init controls(%d)\n", ret);
1774 goto err_free_handler;
1775 }
1776
1777 ov13855->subdev.ctrl_handler = handler;
1778
1779 return 0;
1780
1781 err_free_handler:
1782 v4l2_ctrl_handler_free(handler);
1783
1784 return ret;
1785 }
1786
ov13855_check_sensor_id(struct ov13855 * ov13855,struct i2c_client * client)1787 static int ov13855_check_sensor_id(struct ov13855 *ov13855,
1788 struct i2c_client *client)
1789 {
1790 struct device *dev = &ov13855->client->dev;
1791 u32 id = 0;
1792 int ret;
1793
1794 ret = ov13855_read_reg(client, OV13855_REG_CHIP_ID,
1795 OV13855_REG_VALUE_24BIT, &id);
1796 if (id != CHIP_ID) {
1797 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1798 return -ENODEV;
1799 }
1800
1801 ret = ov13855_read_reg(client, OV13855_CHIP_REVISION_REG,
1802 OV13855_REG_VALUE_08BIT, &id);
1803 if (ret) {
1804 dev_err(dev, "Read chip revision register error\n");
1805 return ret;
1806 }
1807
1808 dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id);
1809
1810 return 0;
1811 }
1812
ov13855_configure_regulators(struct ov13855 * ov13855)1813 static int ov13855_configure_regulators(struct ov13855 *ov13855)
1814 {
1815 unsigned int i;
1816
1817 for (i = 0; i < OV13855_NUM_SUPPLIES; i++)
1818 ov13855->supplies[i].supply = ov13855_supply_names[i];
1819
1820 return devm_regulator_bulk_get(&ov13855->client->dev,
1821 OV13855_NUM_SUPPLIES,
1822 ov13855->supplies);
1823 }
1824
ov13855_probe(struct i2c_client * client,const struct i2c_device_id * id)1825 static int ov13855_probe(struct i2c_client *client,
1826 const struct i2c_device_id *id)
1827 {
1828 struct device *dev = &client->dev;
1829 struct device_node *node = dev->of_node;
1830 struct ov13855 *ov13855;
1831 struct v4l2_subdev *sd;
1832 char facing[2];
1833 int ret;
1834
1835 dev_info(dev, "driver version: %02x.%02x.%02x",
1836 DRIVER_VERSION >> 16,
1837 (DRIVER_VERSION & 0xff00) >> 8,
1838 DRIVER_VERSION & 0x00ff);
1839
1840 ov13855 = devm_kzalloc(dev, sizeof(*ov13855), GFP_KERNEL);
1841 if (!ov13855)
1842 return -ENOMEM;
1843
1844 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1845 &ov13855->module_index);
1846 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1847 &ov13855->module_facing);
1848 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1849 &ov13855->module_name);
1850 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1851 &ov13855->len_name);
1852 if (ret) {
1853 dev_err(dev, "could not get module information!\n");
1854 return -EINVAL;
1855 }
1856
1857 ov13855->client = client;
1858 ov13855->cur_mode = &supported_modes[0];
1859
1860 ov13855->xvclk = devm_clk_get(dev, "xvclk");
1861 if (IS_ERR(ov13855->xvclk)) {
1862 dev_err(dev, "Failed to get xvclk\n");
1863 return -EINVAL;
1864 }
1865
1866 ov13855->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1867 if (IS_ERR(ov13855->power_gpio))
1868 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1869
1870 ov13855->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1871 if (IS_ERR(ov13855->reset_gpio))
1872 dev_warn(dev, "Failed to get reset-gpios\n");
1873
1874 ov13855->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1875 if (IS_ERR(ov13855->pwdn_gpio))
1876 dev_warn(dev, "Failed to get pwdn-gpios\n");
1877
1878 ret = ov13855_configure_regulators(ov13855);
1879 if (ret) {
1880 dev_err(dev, "Failed to get power regulators\n");
1881 return ret;
1882 }
1883
1884 ov13855->pinctrl = devm_pinctrl_get(dev);
1885 if (!IS_ERR(ov13855->pinctrl)) {
1886 ov13855->pins_default =
1887 pinctrl_lookup_state(ov13855->pinctrl,
1888 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1889 if (IS_ERR(ov13855->pins_default))
1890 dev_err(dev, "could not get default pinstate\n");
1891
1892 ov13855->pins_sleep =
1893 pinctrl_lookup_state(ov13855->pinctrl,
1894 OF_CAMERA_PINCTRL_STATE_SLEEP);
1895 if (IS_ERR(ov13855->pins_sleep))
1896 dev_err(dev, "could not get sleep pinstate\n");
1897 }
1898
1899 mutex_init(&ov13855->mutex);
1900
1901 sd = &ov13855->subdev;
1902 v4l2_i2c_subdev_init(sd, client, &ov13855_subdev_ops);
1903 ret = ov13855_initialize_controls(ov13855);
1904 if (ret)
1905 goto err_destroy_mutex;
1906
1907 ret = __ov13855_power_on(ov13855);
1908 if (ret)
1909 goto err_free_handler;
1910
1911 ret = ov13855_check_sensor_id(ov13855, client);
1912 if (ret)
1913 goto err_power_off;
1914
1915 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1916 sd->internal_ops = &ov13855_internal_ops;
1917 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1918 #endif
1919 #if defined(CONFIG_MEDIA_CONTROLLER)
1920 ov13855->pad.flags = MEDIA_PAD_FL_SOURCE;
1921 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1922 ret = media_entity_pads_init(&sd->entity, 1, &ov13855->pad);
1923 if (ret < 0)
1924 goto err_power_off;
1925 #endif
1926
1927 memset(facing, 0, sizeof(facing));
1928 if (strcmp(ov13855->module_facing, "back") == 0)
1929 facing[0] = 'b';
1930 else
1931 facing[0] = 'f';
1932
1933 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1934 ov13855->module_index, facing,
1935 OV13855_NAME, dev_name(sd->dev));
1936 ret = v4l2_async_register_subdev_sensor_common(sd);
1937 if (ret) {
1938 dev_err(dev, "v4l2 async register subdev failed\n");
1939 goto err_clean_entity;
1940 }
1941
1942 pm_runtime_set_active(dev);
1943 pm_runtime_enable(dev);
1944 pm_runtime_idle(dev);
1945
1946 return 0;
1947
1948 err_clean_entity:
1949 #if defined(CONFIG_MEDIA_CONTROLLER)
1950 media_entity_cleanup(&sd->entity);
1951 #endif
1952 err_power_off:
1953 __ov13855_power_off(ov13855);
1954 err_free_handler:
1955 v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
1956 err_destroy_mutex:
1957 mutex_destroy(&ov13855->mutex);
1958
1959 return ret;
1960 }
1961
ov13855_remove(struct i2c_client * client)1962 static int ov13855_remove(struct i2c_client *client)
1963 {
1964 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1965 struct ov13855 *ov13855 = to_ov13855(sd);
1966
1967 v4l2_async_unregister_subdev(sd);
1968 #if defined(CONFIG_MEDIA_CONTROLLER)
1969 media_entity_cleanup(&sd->entity);
1970 #endif
1971 v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
1972 mutex_destroy(&ov13855->mutex);
1973
1974 pm_runtime_disable(&client->dev);
1975 if (!pm_runtime_status_suspended(&client->dev))
1976 __ov13855_power_off(ov13855);
1977 pm_runtime_set_suspended(&client->dev);
1978
1979 return 0;
1980 }
1981
1982 #if IS_ENABLED(CONFIG_OF)
1983 static const struct of_device_id ov13855_of_match[] = {
1984 { .compatible = "ovti,ov13855" },
1985 {},
1986 };
1987 MODULE_DEVICE_TABLE(of, ov13855_of_match);
1988 #endif
1989
1990 static const struct i2c_device_id ov13855_match_id[] = {
1991 { "ovti,ov13855", 0 },
1992 {},
1993 };
1994
1995 static struct i2c_driver ov13855_i2c_driver = {
1996 .driver = {
1997 .name = OV13855_NAME,
1998 .pm = &ov13855_pm_ops,
1999 .of_match_table = of_match_ptr(ov13855_of_match),
2000 },
2001 .probe = &ov13855_probe,
2002 .remove = &ov13855_remove,
2003 .id_table = ov13855_match_id,
2004 };
2005
sensor_mod_init(void)2006 static int __init sensor_mod_init(void)
2007 {
2008 return i2c_add_driver(&ov13855_i2c_driver);
2009 }
2010
sensor_mod_exit(void)2011 static void __exit sensor_mod_exit(void)
2012 {
2013 i2c_del_driver(&ov13855_i2c_driver);
2014 }
2015
2016 device_initcall_sync(sensor_mod_init);
2017 module_exit(sensor_mod_exit);
2018
2019 MODULE_DESCRIPTION("OmniVision ov13855 sensor driver");
2020 MODULE_LICENSE("GPL v2");
2021