1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov13850 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 * V0.0X01.0X05 add function g_mbus_config
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/version.h>
25 #include <linux/rk-camera-module.h>
26 #include <media/media-entity.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-subdev.h>
30 #include <linux/pinctrl/consumer.h>
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define OV13850_LINK_FREQ_300MHZ 300000000
39 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
40 #define OV13850_PIXEL_RATE (OV13850_LINK_FREQ_300MHZ * 2 * 2 / 10)
41 #define OV13850_XVCLK_FREQ 24000000
42
43 #define CHIP_ID 0x00d850
44 #define OV13850_REG_CHIP_ID 0x300a
45
46 #define OV13850_REG_CTRL_MODE 0x0100
47 #define OV13850_MODE_SW_STANDBY 0x0
48 #define OV13850_MODE_STREAMING BIT(0)
49
50 #define OV13850_REG_EXPOSURE 0x3500
51 #define OV13850_EXPOSURE_MIN 4
52 #define OV13850_EXPOSURE_STEP 1
53 #define OV13850_VTS_MAX 0x7fff
54
55 #define OV13850_REG_GAIN_H 0x350a
56 #define OV13850_REG_GAIN_L 0x350b
57 #define OV13850_GAIN_H_MASK 0x07
58 #define OV13850_GAIN_H_SHIFT 8
59 #define OV13850_GAIN_L_MASK 0xff
60 #define OV13850_GAIN_MIN 0x10
61 #define OV13850_GAIN_MAX 0xf8
62 #define OV13850_GAIN_STEP 1
63 #define OV13850_GAIN_DEFAULT 0x10
64
65 #define OV13850_REG_TEST_PATTERN 0x5e00
66 #define OV13850_TEST_PATTERN_ENABLE 0x80
67 #define OV13850_TEST_PATTERN_DISABLE 0x0
68
69 #define OV13850_REG_VTS 0x380e
70
71 #define REG_NULL 0xFFFF
72
73 #define OV13850_REG_VALUE_08BIT 1
74 #define OV13850_REG_VALUE_16BIT 2
75 #define OV13850_REG_VALUE_24BIT 3
76
77 #define OV13850_LANES 2
78 #define OV13850_BITS_PER_SAMPLE 10
79
80 #define OV13850_CHIP_REVISION_REG 0x302A
81 #define OV13850_R1A 0xb1
82 #define OV13850_R2A 0xb2
83
84 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
85 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
86
87 #define OV13850_NAME "ov13850"
88
89 static const struct regval *ov13850_global_regs;
90
91 static const char * const ov13850_supply_names[] = {
92 "avdd", /* Analog power */
93 "dovdd", /* Digital I/O power */
94 "dvdd", /* Digital core power */
95 };
96
97 #define OV13850_NUM_SUPPLIES ARRAY_SIZE(ov13850_supply_names)
98
99 struct regval {
100 u16 addr;
101 u8 val;
102 };
103
104 struct ov13850_mode {
105 u32 width;
106 u32 height;
107 struct v4l2_fract max_fps;
108 u32 hts_def;
109 u32 vts_def;
110 u32 exp_def;
111 const struct regval *reg_list;
112 };
113
114 struct ov13850 {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *power_gpio;
118 struct gpio_desc *reset_gpio;
119 struct gpio_desc *pwdn_gpio;
120 struct regulator_bulk_data supplies[OV13850_NUM_SUPPLIES];
121
122 struct pinctrl *pinctrl;
123 struct pinctrl_state *pins_default;
124 struct pinctrl_state *pins_sleep;
125
126 struct v4l2_subdev subdev;
127 struct media_pad pad;
128 struct v4l2_ctrl_handler ctrl_handler;
129 struct v4l2_ctrl *exposure;
130 struct v4l2_ctrl *anal_gain;
131 struct v4l2_ctrl *digi_gain;
132 struct v4l2_ctrl *hblank;
133 struct v4l2_ctrl *vblank;
134 struct v4l2_ctrl *test_pattern;
135 struct mutex mutex;
136 bool streaming;
137 bool power_on;
138 const struct ov13850_mode *cur_mode;
139 u32 module_index;
140 const char *module_facing;
141 const char *module_name;
142 const char *len_name;
143 };
144
145 #define to_ov13850(sd) container_of(sd, struct ov13850, subdev)
146
147 /*
148 * Xclk 24Mhz
149 */
150 static const struct regval ov13850_global_regs_r1a[] = {
151 {0x0103, 0x01},
152 {0x0300, 0x00},
153 {0x0301, 0x00},
154 {0x0302, 0x32},
155 {0x0303, 0x01},
156 {0x030a, 0x00},
157 {0x300f, 0x11},
158 {0x3010, 0x01},
159 {0x3011, 0x76},
160 {0x3012, 0x21},
161 {0x3013, 0x12},
162 {0x3014, 0x11},
163 {0x3015, 0xc0},
164 {0x301f, 0x03},
165 {0x3106, 0x00},
166 {0x3210, 0x47},
167 {0x3500, 0x00},
168 {0x3501, 0x60},
169 {0x3502, 0x00},
170 {0x3506, 0x00},
171 {0x3507, 0x02},
172 {0x3508, 0x00},
173 {0x350a, 0x00},
174 {0x350b, 0x80},
175 {0x350e, 0x00},
176 {0x350f, 0x10},
177 {0x3600, 0x40},
178 {0x3601, 0xfc},
179 {0x3602, 0x02},
180 {0x3603, 0x48},
181 {0x3604, 0xa5},
182 {0x3605, 0x9f},
183 {0x3607, 0x00},
184 {0x360a, 0x40},
185 {0x360b, 0x91},
186 {0x360c, 0x49},
187 {0x360f, 0x8a},
188 {0x3611, 0x10},
189 {0x3612, 0x27},
190 {0x3613, 0x33},
191 {0x3615, 0x08},
192 {0x3641, 0x02},
193 {0x3660, 0x82},
194 {0x3668, 0x54},
195 {0x3669, 0x40},
196 {0x3667, 0xa0},
197 {0x3702, 0x40},
198 {0x3703, 0x44},
199 {0x3704, 0x2c},
200 {0x3705, 0x24},
201 {0x3706, 0x50},
202 {0x3707, 0x44},
203 {0x3708, 0x3c},
204 {0x3709, 0x1f},
205 {0x370a, 0x26},
206 {0x370b, 0x3c},
207 {0x3720, 0x66},
208 {0x3722, 0x84},
209 {0x3728, 0x40},
210 {0x372a, 0x00},
211 {0x372f, 0x90},
212 {0x3710, 0x28},
213 {0x3716, 0x03},
214 {0x3718, 0x10},
215 {0x3719, 0x08},
216 {0x371c, 0xfc},
217 {0x3760, 0x13},
218 {0x3761, 0x34},
219 {0x3767, 0x24},
220 {0x3768, 0x06},
221 {0x3769, 0x45},
222 {0x376c, 0x23},
223 {0x3d84, 0x00},
224 {0x3d85, 0x17},
225 {0x3d8c, 0x73},
226 {0x3d8d, 0xbf},
227 {0x3800, 0x00},
228 {0x3801, 0x08},
229 {0x3802, 0x00},
230 {0x3803, 0x04},
231 {0x3804, 0x10},
232 {0x3805, 0x97},
233 {0x3806, 0x0c},
234 {0x3807, 0x4b},
235 {0x3808, 0x08},
236 {0x3809, 0x40},
237 {0x380a, 0x06},
238 {0x380b, 0x20},
239 {0x380c, 0x12},
240 {0x380d, 0xc0},
241 {0x380e, 0x06},
242 {0x380f, 0x80},
243 {0x3810, 0x00},
244 {0x3811, 0x04},
245 {0x3812, 0x00},
246 {0x3813, 0x02},
247 {0x3814, 0x31},
248 {0x3815, 0x31},
249 {0x3820, 0x02},
250 {0x3821, 0x05},
251 {0x3834, 0x00},
252 {0x3835, 0x1c},
253 {0x3836, 0x08},
254 {0x3837, 0x02},
255 {0x4000, 0xf1},
256 {0x4001, 0x00},
257 {0x400b, 0x0c},
258 {0x4011, 0x00},
259 {0x401a, 0x00},
260 {0x401b, 0x00},
261 {0x401c, 0x00},
262 {0x401d, 0x00},
263 {0x4020, 0x00},
264 {0x4021, 0xE4},
265 {0x4022, 0x07},
266 {0x4023, 0x5F},
267 {0x4024, 0x08},
268 {0x4025, 0x44},
269 {0x4026, 0x08},
270 {0x4027, 0x47},
271 {0x4028, 0x00},
272 {0x4029, 0x02},
273 {0x402a, 0x04},
274 {0x402b, 0x08},
275 {0x402c, 0x02},
276 {0x402d, 0x02},
277 {0x402e, 0x0c},
278 {0x402f, 0x08},
279 {0x403d, 0x2c},
280 {0x403f, 0x7f},
281 {0x4500, 0x82},
282 {0x4501, 0x38},
283 {0x4601, 0x04},
284 {0x4602, 0x22},
285 {0x4603, 0x01},
286 {0x4800, 0x24}, //MIPI CLK control
287 {0x4837, 0x1b},
288 {0x4d00, 0x04},
289 {0x4d01, 0x42},
290 {0x4d02, 0xd1},
291 {0x4d03, 0x90},
292 {0x4d04, 0x66},
293 {0x4d05, 0x65},
294 {0x5000, 0x0e},
295 {0x5001, 0x01},
296 {0x5002, 0x07},
297 {0x5013, 0x40},
298 {0x501c, 0x00},
299 {0x501d, 0x10},
300 {0x5242, 0x00},
301 {0x5243, 0xb8},
302 {0x5244, 0x00},
303 {0x5245, 0xf9},
304 {0x5246, 0x00},
305 {0x5247, 0xf6},
306 {0x5248, 0x00},
307 {0x5249, 0xa6},
308 {0x5300, 0xfc},
309 {0x5301, 0xdf},
310 {0x5302, 0x3f},
311 {0x5303, 0x08},
312 {0x5304, 0x0c},
313 {0x5305, 0x10},
314 {0x5306, 0x20},
315 {0x5307, 0x40},
316 {0x5308, 0x08},
317 {0x5309, 0x08},
318 {0x530a, 0x02},
319 {0x530b, 0x01},
320 {0x530c, 0x01},
321 {0x530d, 0x0c},
322 {0x530e, 0x02},
323 {0x530f, 0x01},
324 {0x5310, 0x01},
325 {0x5400, 0x00},
326 {0x5401, 0x61},
327 {0x5402, 0x00},
328 {0x5403, 0x00},
329 {0x5404, 0x00},
330 {0x5405, 0x40},
331 {0x540c, 0x05},
332 {0x5b00, 0x00},
333 {0x5b01, 0x00},
334 {0x5b02, 0x01},
335 {0x5b03, 0xff},
336 {0x5b04, 0x02},
337 {0x5b05, 0x6c},
338 {0x5b09, 0x02},
339 {0x5e00, 0x00},
340 {0x5e10, 0x1c},
341 {0x0102, 0x01}, //Fast standby enable
342 {REG_NULL, 0x00},
343 };
344
345 /*
346 * Xclk 24Mhz
347 */
348 static const struct regval ov13850_global_regs_r2a[] = {
349 {0x0300, 0x01},
350 {0x0301, 0x00},
351 {0x0302, 0x28},
352 {0x0303, 0x00},
353 {0x030a, 0x00},
354 {0x300f, 0x11},
355 {0x3010, 0x01},
356 {0x3011, 0x76},
357 {0x3012, 0x21},
358 {0x3013, 0x12},
359 {0x3014, 0x11},
360 {0x301f, 0x03},
361 {0x3106, 0x00},
362 {0x3210, 0x47},
363 {0x3500, 0x00},
364 {0x3501, 0x60},
365 {0x3502, 0x00},
366 {0x3506, 0x00},
367 {0x3507, 0x02},
368 {0x3508, 0x00},
369 {0x350a, 0x00},
370 {0x350b, 0x80},
371 {0x350e, 0x00},
372 {0x350f, 0x10},
373 {0x351a, 0x00},
374 {0x351b, 0x10},
375 {0x351c, 0x00},
376 {0x351d, 0x20},
377 {0x351e, 0x00},
378 {0x351f, 0x40},
379 {0x3520, 0x00},
380 {0x3521, 0x80},
381 {0x3600, 0xc0},
382 {0x3601, 0xfc},
383 {0x3602, 0x02},
384 {0x3603, 0x78},
385 {0x3604, 0xb1},
386 {0x3605, 0xb5},
387 {0x3606, 0x73},
388 {0x3607, 0x07},
389 {0x3609, 0x40},
390 {0x360a, 0x30},
391 {0x360b, 0x91},
392 {0x360c, 0x09},
393 {0x360f, 0x02},
394 {0x3611, 0x10},
395 {0x3612, 0x27},
396 {0x3613, 0x33},
397 {0x3615, 0x0c},
398 {0x3616, 0x0e},
399 {0x3641, 0x02},
400 {0x3660, 0x82},
401 {0x3668, 0x54},
402 {0x3669, 0x00},
403 {0x366a, 0x3f},
404 {0x3667, 0xa0},
405 {0x3702, 0x40},
406 {0x3703, 0x44},
407 {0x3704, 0x2c},
408 {0x3705, 0x01},
409 {0x3706, 0x15},
410 {0x3707, 0x44},
411 {0x3708, 0x3c},
412 {0x3709, 0x1f},
413 {0x370a, 0x27},
414 {0x370b, 0x3c},
415 {0x3720, 0x55},
416 {0x3722, 0x84},
417 {0x3728, 0x40},
418 {0x372a, 0x00},
419 {0x372b, 0x02},
420 {0x372e, 0x22},
421 {0x372f, 0x90},
422 {0x3730, 0x00},
423 {0x3731, 0x00},
424 {0x3732, 0x00},
425 {0x3733, 0x00},
426 {0x3710, 0x28},
427 {0x3716, 0x03},
428 {0x3718, 0x10},
429 {0x3719, 0x0c},
430 {0x371a, 0x08},
431 {0x371c, 0xfc},
432 {0x3748, 0x00},
433 {0x3760, 0x13},
434 {0x3761, 0x33},
435 {0x3762, 0x86},
436 {0x3763, 0x16},
437 {0x3767, 0x24},
438 {0x3768, 0x06},
439 {0x3769, 0x45},
440 {0x376c, 0x23},
441 {0x376f, 0x80},
442 {0x3773, 0x06},
443 {0x3d84, 0x00},
444 {0x3d85, 0x17},
445 {0x3d8c, 0x73},
446 {0x3d8d, 0xbf},
447 {0x3800, 0x00},
448 {0x3801, 0x08},
449 {0x3802, 0x00},
450 {0x3803, 0x04},
451 {0x3804, 0x10},
452 {0x3805, 0x97},
453 {0x3806, 0x0c},
454 {0x3807, 0x4b},
455 {0x3808, 0x08},
456 {0x3809, 0x40},
457 {0x380a, 0x06},
458 {0x380b, 0x20},
459 {0x380c, 0x12},
460 {0x380d, 0xc0},
461 {0x380e, 0x06},
462 {0x380f, 0x80},
463 {0x3810, 0x00},
464 {0x3811, 0x04},
465 {0x3812, 0x00},
466 {0x3813, 0x02},
467 {0x3814, 0x31},
468 {0x3815, 0x31},
469 {0x3820, 0x02},
470 {0x3821, 0x06},
471 {0x3823, 0x00},
472 {0x3826, 0x00},
473 {0x3827, 0x02},
474 {0x3834, 0x00},
475 {0x3835, 0x1c},
476 {0x3836, 0x08},
477 {0x3837, 0x02},
478 {0x4000, 0xf1},
479 {0x4001, 0x00},
480 {0x4006, 0x04},
481 {0x4007, 0x04},
482 {0x400b, 0x0c},
483 {0x4011, 0x00},
484 {0x401a, 0x00},
485 {0x401b, 0x00},
486 {0x401c, 0x00},
487 {0x401d, 0x00},
488 {0x4020, 0x00},
489 {0x4021, 0xe4},
490 {0x4022, 0x04},
491 {0x4023, 0xd7},
492 {0x4024, 0x05},
493 {0x4025, 0xbc},
494 {0x4026, 0x05},
495 {0x4027, 0xbf},
496 {0x4028, 0x00},
497 {0x4029, 0x02},
498 {0x402a, 0x04},
499 {0x402b, 0x08},
500 {0x402c, 0x02},
501 {0x402d, 0x02},
502 {0x402e, 0x0c},
503 {0x402f, 0x08},
504 {0x403d, 0x2c},
505 {0x403f, 0x7f},
506 {0x4041, 0x07},
507 {0x4500, 0x82},
508 {0x4501, 0x3c},
509 {0x458b, 0x00},
510 {0x459c, 0x00},
511 {0x459d, 0x00},
512 {0x459e, 0x00},
513 {0x4601, 0x83},
514 {0x4602, 0x22},
515 {0x4603, 0x01},
516 {0x4800, 0x24}, //MIPI CLK control
517 {0x4837, 0x19},
518 {0x4d00, 0x04},
519 {0x4d01, 0x42},
520 {0x4d02, 0xd1},
521 {0x4d03, 0x90},
522 {0x4d04, 0x66},
523 {0x4d05, 0x65},
524 {0x4d0b, 0x00},
525 {0x5000, 0x0e},
526 {0x5001, 0x01},
527 {0x5002, 0x07},
528 {0x5013, 0x40},
529 {0x501c, 0x00},
530 {0x501d, 0x10},
531 {0x510f, 0xfc},
532 {0x5110, 0xf0},
533 {0x5111, 0x10},
534 {0x536d, 0x02},
535 {0x536e, 0x67},
536 {0x536f, 0x01},
537 {0x5370, 0x4c},
538 {0x5400, 0x00},
539 {0x5400, 0x00},
540 {0x5401, 0x61},
541 {0x5402, 0x00},
542 {0x5403, 0x00},
543 {0x5404, 0x00},
544 {0x5405, 0x40},
545 {0x540c, 0x05},
546 {0x5501, 0x00},
547 {0x5b00, 0x00},
548 {0x5b01, 0x00},
549 {0x5b02, 0x01},
550 {0x5b03, 0xff},
551 {0x5b04, 0x02},
552 {0x5b05, 0x6c},
553 {0x5b09, 0x02},
554 {0x5e00, 0x00},
555 {0x5e10, 0x1c},
556 {0x0102, 0x01}, //Fast standby enable
557 {REG_NULL, 0x00},
558 };
559
560 /*
561 * Xclk 24Mhz
562 * max_framerate 30fps
563 * mipi_datarate per lane 600Mbps
564 */
565 static const struct regval ov13850_2112x1568_regs[] = {
566 {0x3612, 0x27},
567 {0x370a, 0x26},
568 {0x372a, 0x00},
569 {0x372f, 0x90},
570 {0x3801, 0x08},
571 {0x3805, 0x97},
572 {0x3807, 0x4b},
573 {0x3808, 0x08},
574 {0x3809, 0x40},
575 {0x380a, 0x06},
576 {0x380b, 0x20},
577 {0x380c, 0x12},
578 {0x380d, 0xc0},
579 {0x380e, 0x06},
580 {0x380f, 0x80},
581 {0x3813, 0x02},
582 {0x3814, 0x31},
583 {0x3815, 0x31},
584 {0x3820, 0x06},
585 {0x3821, 0x01},
586 {0x3836, 0x08},
587 {0x3837, 0x02},
588 {0x4601, 0x04},
589 {0x4603, 0x00},
590 {0x4020, 0x00},
591 {0x4021, 0xE4},
592 {0x4022, 0x07},
593 {0x4023, 0x5F},
594 {0x4024, 0x08},
595 {0x4025, 0x44},
596 {0x4026, 0x08},
597 {0x4027, 0x47},
598 {0x4603, 0x01},
599 {0x5401, 0x61},
600 {0x5405, 0x40},
601 {REG_NULL, 0x00},
602 };
603
604 /*
605 * Xclk 24Mhz
606 * max_framerate 7fps
607 * mipi_datarate per lane 600Mbps
608 */
609 static const struct regval ov13850_4224x3136_regs[] = {
610 {0x3612, 0x2f},
611 {0x370a, 0x24},
612 {0x372a, 0x04},
613 {0x372f, 0xa0},
614 {0x3801, 0x0C},
615 {0x3805, 0x93},
616 {0x3807, 0x4B},
617 {0x3808, 0x10},
618 {0x3809, 0x80},
619 {0x380a, 0x0c},
620 {0x380b, 0x40},
621 {0x380e, 0x0d},
622 {0x380f, 0x00},
623 {0x3813, 0x04},
624 {0x3814, 0x11},
625 {0x3815, 0x11},
626 {0x3820, 0x00},
627 {0x3821, 0x04},
628 {0x3836, 0x04},
629 {0x3837, 0x01},
630 {0x4601, 0x87},
631 {0x4603, 0x01},
632 {0x4020, 0x02},
633 {0x4021, 0x4C},
634 {0x4022, 0x0E},
635 {0x4023, 0x37},
636 {0x4024, 0x0F},
637 {0x4025, 0x1C},
638 {0x4026, 0x0F},
639 {0x4027, 0x1F},
640 {0x4603, 0x00},
641 {0x5401, 0x71},
642 {0x5405, 0x80},
643 {REG_NULL, 0x00},
644 };
645
646 static const struct ov13850_mode supported_modes[] = {
647 {
648 .width = 2112,
649 .height = 1568,
650 .max_fps = {
651 .numerator = 10000,
652 .denominator = 300000,
653 },
654 .exp_def = 0x0600,
655 .hts_def = 0x12c0,
656 .vts_def = 0x0680,
657 .reg_list = ov13850_2112x1568_regs,
658 },{
659 .width = 4224,
660 .height = 3136,
661 .max_fps = {
662 .numerator = 20000,
663 .denominator = 150000,
664 },
665 .exp_def = 0x0600,
666 .hts_def = 0x12c0,
667 .vts_def = 0x0d00,
668 .reg_list = ov13850_4224x3136_regs,
669 },
670 };
671
672 static const s64 link_freq_menu_items[] = {
673 OV13850_LINK_FREQ_300MHZ
674 };
675
676 static const char * const ov13850_test_pattern_menu[] = {
677 "Disabled",
678 "Vertical Color Bar Type 1",
679 "Vertical Color Bar Type 2",
680 "Vertical Color Bar Type 3",
681 "Vertical Color Bar Type 4"
682 };
683
684 /* Write registers up to 4 at a time */
ov13850_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)685 static int ov13850_write_reg(struct i2c_client *client, u16 reg,
686 u32 len, u32 val)
687 {
688 u32 buf_i, val_i;
689 u8 buf[6];
690 u8 *val_p;
691 __be32 val_be;
692
693 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
694
695 if (len > 4)
696 return -EINVAL;
697
698 buf[0] = reg >> 8;
699 buf[1] = reg & 0xff;
700
701 val_be = cpu_to_be32(val);
702 val_p = (u8 *)&val_be;
703 buf_i = 2;
704 val_i = 4 - len;
705
706 while (val_i < 4)
707 buf[buf_i++] = val_p[val_i++];
708
709 if (i2c_master_send(client, buf, len + 2) != len + 2)
710 return -EIO;
711
712 return 0;
713 }
714
ov13850_write_array(struct i2c_client * client,const struct regval * regs)715 static int ov13850_write_array(struct i2c_client *client,
716 const struct regval *regs)
717 {
718 u32 i;
719 int ret = 0;
720
721 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
722 ret = ov13850_write_reg(client, regs[i].addr,
723 OV13850_REG_VALUE_08BIT,
724 regs[i].val);
725
726 return ret;
727 }
728
729 /* Read registers up to 4 at a time */
ov13850_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)730 static int ov13850_read_reg(struct i2c_client *client, u16 reg,
731 unsigned int len, u32 *val)
732 {
733 struct i2c_msg msgs[2];
734 u8 *data_be_p;
735 __be32 data_be = 0;
736 __be16 reg_addr_be = cpu_to_be16(reg);
737 int ret;
738
739 if (len > 4 || !len)
740 return -EINVAL;
741
742 data_be_p = (u8 *)&data_be;
743 /* Write register address */
744 msgs[0].addr = client->addr;
745 msgs[0].flags = 0;
746 msgs[0].len = 2;
747 msgs[0].buf = (u8 *)®_addr_be;
748
749 /* Read data from register */
750 msgs[1].addr = client->addr;
751 msgs[1].flags = I2C_M_RD;
752 msgs[1].len = len;
753 msgs[1].buf = &data_be_p[4 - len];
754
755 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
756 if (ret != ARRAY_SIZE(msgs))
757 return -EIO;
758
759 *val = be32_to_cpu(data_be);
760
761 return 0;
762 }
763
ov13850_get_reso_dist(const struct ov13850_mode * mode,struct v4l2_mbus_framefmt * framefmt)764 static int ov13850_get_reso_dist(const struct ov13850_mode *mode,
765 struct v4l2_mbus_framefmt *framefmt)
766 {
767 return abs(mode->width - framefmt->width) +
768 abs(mode->height - framefmt->height);
769 }
770
771 static const struct ov13850_mode *
ov13850_find_best_fit(struct v4l2_subdev_format * fmt)772 ov13850_find_best_fit(struct v4l2_subdev_format *fmt)
773 {
774 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
775 int dist;
776 int cur_best_fit = 0;
777 int cur_best_fit_dist = -1;
778 unsigned int i;
779
780 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
781 dist = ov13850_get_reso_dist(&supported_modes[i], framefmt);
782 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
783 cur_best_fit_dist = dist;
784 cur_best_fit = i;
785 }
786 }
787
788 return &supported_modes[cur_best_fit];
789 }
790
ov13850_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)791 static int ov13850_set_fmt(struct v4l2_subdev *sd,
792 struct v4l2_subdev_pad_config *cfg,
793 struct v4l2_subdev_format *fmt)
794 {
795 struct ov13850 *ov13850 = to_ov13850(sd);
796 const struct ov13850_mode *mode;
797 s64 h_blank, vblank_def;
798
799 mutex_lock(&ov13850->mutex);
800
801 mode = ov13850_find_best_fit(fmt);
802 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
803 fmt->format.width = mode->width;
804 fmt->format.height = mode->height;
805 fmt->format.field = V4L2_FIELD_NONE;
806 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
807 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
808 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
809 #else
810 mutex_unlock(&ov13850->mutex);
811 return -ENOTTY;
812 #endif
813 } else {
814 ov13850->cur_mode = mode;
815 h_blank = mode->hts_def - mode->width;
816 __v4l2_ctrl_modify_range(ov13850->hblank, h_blank,
817 h_blank, 1, h_blank);
818 vblank_def = mode->vts_def - mode->height;
819 __v4l2_ctrl_modify_range(ov13850->vblank, vblank_def,
820 OV13850_VTS_MAX - mode->height,
821 1, vblank_def);
822 }
823
824 mutex_unlock(&ov13850->mutex);
825
826 return 0;
827 }
828
ov13850_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)829 static int ov13850_get_fmt(struct v4l2_subdev *sd,
830 struct v4l2_subdev_pad_config *cfg,
831 struct v4l2_subdev_format *fmt)
832 {
833 struct ov13850 *ov13850 = to_ov13850(sd);
834 const struct ov13850_mode *mode = ov13850->cur_mode;
835
836 mutex_lock(&ov13850->mutex);
837 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
838 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
839 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
840 #else
841 mutex_unlock(&ov13850->mutex);
842 return -ENOTTY;
843 #endif
844 } else {
845 fmt->format.width = mode->width;
846 fmt->format.height = mode->height;
847 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
848 fmt->format.field = V4L2_FIELD_NONE;
849 }
850 mutex_unlock(&ov13850->mutex);
851
852 return 0;
853 }
854
ov13850_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)855 static int ov13850_enum_mbus_code(struct v4l2_subdev *sd,
856 struct v4l2_subdev_pad_config *cfg,
857 struct v4l2_subdev_mbus_code_enum *code)
858 {
859 if (code->index != 0)
860 return -EINVAL;
861 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
862
863 return 0;
864 }
865
ov13850_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)866 static int ov13850_enum_frame_sizes(struct v4l2_subdev *sd,
867 struct v4l2_subdev_pad_config *cfg,
868 struct v4l2_subdev_frame_size_enum *fse)
869 {
870 if (fse->index >= ARRAY_SIZE(supported_modes))
871 return -EINVAL;
872
873 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
874 return -EINVAL;
875
876 fse->min_width = supported_modes[fse->index].width;
877 fse->max_width = supported_modes[fse->index].width;
878 fse->max_height = supported_modes[fse->index].height;
879 fse->min_height = supported_modes[fse->index].height;
880
881 return 0;
882 }
883
ov13850_enable_test_pattern(struct ov13850 * ov13850,u32 pattern)884 static int ov13850_enable_test_pattern(struct ov13850 *ov13850, u32 pattern)
885 {
886 u32 val;
887
888 if (pattern)
889 val = (pattern - 1) | OV13850_TEST_PATTERN_ENABLE;
890 else
891 val = OV13850_TEST_PATTERN_DISABLE;
892
893 return ov13850_write_reg(ov13850->client,
894 OV13850_REG_TEST_PATTERN,
895 OV13850_REG_VALUE_08BIT,
896 val);
897 }
898
ov13850_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)899 static int ov13850_g_frame_interval(struct v4l2_subdev *sd,
900 struct v4l2_subdev_frame_interval *fi)
901 {
902 struct ov13850 *ov13850 = to_ov13850(sd);
903 const struct ov13850_mode *mode = ov13850->cur_mode;
904
905 fi->interval = mode->max_fps;
906
907 return 0;
908 }
909
ov13850_get_module_inf(struct ov13850 * ov13850,struct rkmodule_inf * inf)910 static void ov13850_get_module_inf(struct ov13850 *ov13850,
911 struct rkmodule_inf *inf)
912 {
913 memset(inf, 0, sizeof(*inf));
914 strlcpy(inf->base.sensor, OV13850_NAME, sizeof(inf->base.sensor));
915 strlcpy(inf->base.module, ov13850->module_name,
916 sizeof(inf->base.module));
917 strlcpy(inf->base.lens, ov13850->len_name, sizeof(inf->base.lens));
918 }
919
ov13850_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)920 static long ov13850_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
921 {
922 struct ov13850 *ov13850 = to_ov13850(sd);
923 long ret = 0;
924 u32 stream = 0;
925
926 switch (cmd) {
927 case RKMODULE_GET_MODULE_INFO:
928 ov13850_get_module_inf(ov13850, (struct rkmodule_inf *)arg);
929 break;
930 case RKMODULE_SET_QUICK_STREAM:
931
932 stream = *((u32 *)arg);
933
934 if (stream)
935 ret = ov13850_write_reg(ov13850->client,
936 OV13850_REG_CTRL_MODE,
937 OV13850_REG_VALUE_08BIT,
938 OV13850_MODE_STREAMING);
939 else
940 ret = ov13850_write_reg(ov13850->client,
941 OV13850_REG_CTRL_MODE,
942 OV13850_REG_VALUE_08BIT,
943 OV13850_MODE_SW_STANDBY);
944 break;
945 default:
946 ret = -ENOIOCTLCMD;
947 break;
948 }
949
950 return ret;
951 }
952
953 #ifdef CONFIG_COMPAT
ov13850_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)954 static long ov13850_compat_ioctl32(struct v4l2_subdev *sd,
955 unsigned int cmd, unsigned long arg)
956 {
957 void __user *up = compat_ptr(arg);
958 struct rkmodule_inf *inf;
959 struct rkmodule_awb_cfg *cfg;
960 long ret;
961 u32 stream = 0;
962
963 switch (cmd) {
964 case RKMODULE_GET_MODULE_INFO:
965 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
966 if (!inf) {
967 ret = -ENOMEM;
968 return ret;
969 }
970
971 ret = ov13850_ioctl(sd, cmd, inf);
972 if (!ret)
973 ret = copy_to_user(up, inf, sizeof(*inf));
974 kfree(inf);
975 break;
976 case RKMODULE_AWB_CFG:
977 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
978 if (!cfg) {
979 ret = -ENOMEM;
980 return ret;
981 }
982
983 ret = copy_from_user(cfg, up, sizeof(*cfg));
984 if (!ret)
985 ret = ov13850_ioctl(sd, cmd, cfg);
986 kfree(cfg);
987 break;
988 case RKMODULE_SET_QUICK_STREAM:
989 ret = copy_from_user(&stream, up, sizeof(u32));
990 if (!ret)
991 ret = ov13850_ioctl(sd, cmd, &stream);
992 break;
993 default:
994 ret = -ENOIOCTLCMD;
995 break;
996 }
997
998 return ret;
999 }
1000 #endif
1001
__ov13850_start_stream(struct ov13850 * ov13850)1002 static int __ov13850_start_stream(struct ov13850 *ov13850)
1003 {
1004 int ret;
1005
1006 ret = ov13850_write_array(ov13850->client, ov13850->cur_mode->reg_list);
1007 if (ret)
1008 return ret;
1009
1010 /* In case these controls are set before streaming */
1011 mutex_unlock(&ov13850->mutex);
1012 ret = v4l2_ctrl_handler_setup(&ov13850->ctrl_handler);
1013 mutex_lock(&ov13850->mutex);
1014 if (ret)
1015 return ret;
1016
1017 return ov13850_write_reg(ov13850->client,
1018 OV13850_REG_CTRL_MODE,
1019 OV13850_REG_VALUE_08BIT,
1020 OV13850_MODE_STREAMING);
1021 }
1022
__ov13850_stop_stream(struct ov13850 * ov13850)1023 static int __ov13850_stop_stream(struct ov13850 *ov13850)
1024 {
1025 return ov13850_write_reg(ov13850->client,
1026 OV13850_REG_CTRL_MODE,
1027 OV13850_REG_VALUE_08BIT,
1028 OV13850_MODE_SW_STANDBY);
1029 }
1030
ov13850_s_stream(struct v4l2_subdev * sd,int on)1031 static int ov13850_s_stream(struct v4l2_subdev *sd, int on)
1032 {
1033 struct ov13850 *ov13850 = to_ov13850(sd);
1034 struct i2c_client *client = ov13850->client;
1035 int ret = 0;
1036
1037 mutex_lock(&ov13850->mutex);
1038 on = !!on;
1039 if (on == ov13850->streaming)
1040 goto unlock_and_return;
1041
1042 if (on) {
1043 ret = pm_runtime_get_sync(&client->dev);
1044 if (ret < 0) {
1045 pm_runtime_put_noidle(&client->dev);
1046 goto unlock_and_return;
1047 }
1048
1049 ret = __ov13850_start_stream(ov13850);
1050 if (ret) {
1051 v4l2_err(sd, "start stream failed while write regs\n");
1052 pm_runtime_put(&client->dev);
1053 goto unlock_and_return;
1054 }
1055 } else {
1056 __ov13850_stop_stream(ov13850);
1057 pm_runtime_put(&client->dev);
1058 }
1059
1060 ov13850->streaming = on;
1061
1062 unlock_and_return:
1063 mutex_unlock(&ov13850->mutex);
1064
1065 return ret;
1066 }
1067
ov13850_s_power(struct v4l2_subdev * sd,int on)1068 static int ov13850_s_power(struct v4l2_subdev *sd, int on)
1069 {
1070 struct ov13850 *ov13850 = to_ov13850(sd);
1071 struct i2c_client *client = ov13850->client;
1072 int ret = 0;
1073
1074 mutex_lock(&ov13850->mutex);
1075
1076 /* If the power state is not modified - no work to do. */
1077 if (ov13850->power_on == !!on)
1078 goto unlock_and_return;
1079
1080 if (on) {
1081 ret = pm_runtime_get_sync(&client->dev);
1082 if (ret < 0) {
1083 pm_runtime_put_noidle(&client->dev);
1084 goto unlock_and_return;
1085 }
1086
1087 ret = ov13850_write_array(ov13850->client, ov13850_global_regs);
1088 if (ret) {
1089 v4l2_err(sd, "could not set init registers\n");
1090 pm_runtime_put_noidle(&client->dev);
1091 goto unlock_and_return;
1092 }
1093
1094 ov13850->power_on = true;
1095 } else {
1096 pm_runtime_put(&client->dev);
1097 ov13850->power_on = false;
1098 }
1099
1100 unlock_and_return:
1101 mutex_unlock(&ov13850->mutex);
1102
1103 return ret;
1104 }
1105
1106 /* Calculate the delay in us by clock rate and clock cycles */
ov13850_cal_delay(u32 cycles)1107 static inline u32 ov13850_cal_delay(u32 cycles)
1108 {
1109 return DIV_ROUND_UP(cycles, OV13850_XVCLK_FREQ / 1000 / 1000);
1110 }
1111
__ov13850_power_on(struct ov13850 * ov13850)1112 static int __ov13850_power_on(struct ov13850 *ov13850)
1113 {
1114 int ret;
1115 u32 delay_us;
1116 struct device *dev = &ov13850->client->dev;
1117
1118 if (!IS_ERR(ov13850->power_gpio))
1119 gpiod_set_value_cansleep(ov13850->power_gpio, 1);
1120
1121 usleep_range(1000, 2000);
1122
1123 if (!IS_ERR_OR_NULL(ov13850->pins_default)) {
1124 ret = pinctrl_select_state(ov13850->pinctrl,
1125 ov13850->pins_default);
1126 if (ret < 0)
1127 dev_err(dev, "could not set pins\n");
1128 }
1129 ret = clk_set_rate(ov13850->xvclk, OV13850_XVCLK_FREQ);
1130 if (ret < 0)
1131 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1132 if (clk_get_rate(ov13850->xvclk) != OV13850_XVCLK_FREQ)
1133 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1134 ret = clk_prepare_enable(ov13850->xvclk);
1135 if (ret < 0) {
1136 dev_err(dev, "Failed to enable xvclk\n");
1137 return ret;
1138 }
1139 if (!IS_ERR(ov13850->reset_gpio))
1140 gpiod_set_value_cansleep(ov13850->reset_gpio, 0);
1141
1142 ret = regulator_bulk_enable(OV13850_NUM_SUPPLIES, ov13850->supplies);
1143 if (ret < 0) {
1144 dev_err(dev, "Failed to enable regulators\n");
1145 goto disable_clk;
1146 }
1147
1148 if (!IS_ERR(ov13850->reset_gpio))
1149 gpiod_set_value_cansleep(ov13850->reset_gpio, 1);
1150
1151 usleep_range(500, 1000);
1152 if (!IS_ERR(ov13850->pwdn_gpio))
1153 gpiod_set_value_cansleep(ov13850->pwdn_gpio, 1);
1154
1155 /* 8192 cycles prior to first SCCB transaction */
1156 delay_us = ov13850_cal_delay(8192);
1157 usleep_range(delay_us, delay_us * 2);
1158
1159 return 0;
1160
1161 disable_clk:
1162 clk_disable_unprepare(ov13850->xvclk);
1163
1164 return ret;
1165 }
1166
__ov13850_power_off(struct ov13850 * ov13850)1167 static void __ov13850_power_off(struct ov13850 *ov13850)
1168 {
1169 int ret;
1170 struct device *dev = &ov13850->client->dev;
1171
1172 if (!IS_ERR(ov13850->pwdn_gpio))
1173 gpiod_set_value_cansleep(ov13850->pwdn_gpio, 0);
1174 clk_disable_unprepare(ov13850->xvclk);
1175 if (!IS_ERR(ov13850->reset_gpio))
1176 gpiod_set_value_cansleep(ov13850->reset_gpio, 0);
1177
1178 if (!IS_ERR_OR_NULL(ov13850->pins_sleep)) {
1179 ret = pinctrl_select_state(ov13850->pinctrl,
1180 ov13850->pins_sleep);
1181 if (ret < 0)
1182 dev_dbg(dev, "could not set pins\n");
1183 }
1184 if (!IS_ERR(ov13850->power_gpio))
1185 gpiod_set_value_cansleep(ov13850->power_gpio, 0);
1186
1187 regulator_bulk_disable(OV13850_NUM_SUPPLIES, ov13850->supplies);
1188 }
1189
ov13850_runtime_resume(struct device * dev)1190 static int __maybe_unused ov13850_runtime_resume(struct device *dev)
1191 {
1192 struct i2c_client *client = to_i2c_client(dev);
1193 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1194 struct ov13850 *ov13850 = to_ov13850(sd);
1195
1196 return __ov13850_power_on(ov13850);
1197 }
1198
ov13850_runtime_suspend(struct device * dev)1199 static int __maybe_unused ov13850_runtime_suspend(struct device *dev)
1200 {
1201 struct i2c_client *client = to_i2c_client(dev);
1202 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1203 struct ov13850 *ov13850 = to_ov13850(sd);
1204
1205 __ov13850_power_off(ov13850);
1206
1207 return 0;
1208 }
1209
1210 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov13850_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1211 static int ov13850_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1212 {
1213 struct ov13850 *ov13850 = to_ov13850(sd);
1214 struct v4l2_mbus_framefmt *try_fmt =
1215 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1216 const struct ov13850_mode *def_mode = &supported_modes[0];
1217
1218 mutex_lock(&ov13850->mutex);
1219 /* Initialize try_fmt */
1220 try_fmt->width = def_mode->width;
1221 try_fmt->height = def_mode->height;
1222 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1223 try_fmt->field = V4L2_FIELD_NONE;
1224
1225 mutex_unlock(&ov13850->mutex);
1226 /* No crop or compose */
1227
1228 return 0;
1229 }
1230 #endif
1231
ov13850_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1232 static int ov13850_enum_frame_interval(struct v4l2_subdev *sd,
1233 struct v4l2_subdev_pad_config *cfg,
1234 struct v4l2_subdev_frame_interval_enum *fie)
1235 {
1236 if (fie->index >= ARRAY_SIZE(supported_modes))
1237 return -EINVAL;
1238
1239 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1240 fie->width = supported_modes[fie->index].width;
1241 fie->height = supported_modes[fie->index].height;
1242 fie->interval = supported_modes[fie->index].max_fps;
1243 return 0;
1244 }
1245
ov13850_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1246 static int ov13850_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1247 struct v4l2_mbus_config *config)
1248 {
1249 u32 val = 0;
1250
1251 val = 1 << (OV13850_LANES - 1) |
1252 V4L2_MBUS_CSI2_CHANNEL_0 |
1253 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1254 config->type = V4L2_MBUS_CSI2_DPHY;
1255 config->flags = val;
1256
1257 return 0;
1258 }
1259
1260 static const struct dev_pm_ops ov13850_pm_ops = {
1261 SET_RUNTIME_PM_OPS(ov13850_runtime_suspend,
1262 ov13850_runtime_resume, NULL)
1263 };
1264
1265 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1266 static const struct v4l2_subdev_internal_ops ov13850_internal_ops = {
1267 .open = ov13850_open,
1268 };
1269 #endif
1270
1271 static const struct v4l2_subdev_core_ops ov13850_core_ops = {
1272 .s_power = ov13850_s_power,
1273 .ioctl = ov13850_ioctl,
1274 #ifdef CONFIG_COMPAT
1275 .compat_ioctl32 = ov13850_compat_ioctl32,
1276 #endif
1277 };
1278
1279 static const struct v4l2_subdev_video_ops ov13850_video_ops = {
1280 .s_stream = ov13850_s_stream,
1281 .g_frame_interval = ov13850_g_frame_interval,
1282 };
1283
1284 static const struct v4l2_subdev_pad_ops ov13850_pad_ops = {
1285 .enum_mbus_code = ov13850_enum_mbus_code,
1286 .enum_frame_size = ov13850_enum_frame_sizes,
1287 .enum_frame_interval = ov13850_enum_frame_interval,
1288 .get_fmt = ov13850_get_fmt,
1289 .set_fmt = ov13850_set_fmt,
1290 .get_mbus_config = ov13850_g_mbus_config,
1291 };
1292
1293 static const struct v4l2_subdev_ops ov13850_subdev_ops = {
1294 .core = &ov13850_core_ops,
1295 .video = &ov13850_video_ops,
1296 .pad = &ov13850_pad_ops,
1297 };
1298
ov13850_set_ctrl(struct v4l2_ctrl * ctrl)1299 static int ov13850_set_ctrl(struct v4l2_ctrl *ctrl)
1300 {
1301 struct ov13850 *ov13850 = container_of(ctrl->handler,
1302 struct ov13850, ctrl_handler);
1303 struct i2c_client *client = ov13850->client;
1304 s64 max;
1305 int ret = 0;
1306
1307 /* Propagate change of current control to all related controls */
1308 switch (ctrl->id) {
1309 case V4L2_CID_VBLANK:
1310 /* Update max exposure while meeting expected vblanking */
1311 max = ov13850->cur_mode->height + ctrl->val - 4;
1312 __v4l2_ctrl_modify_range(ov13850->exposure,
1313 ov13850->exposure->minimum, max,
1314 ov13850->exposure->step,
1315 ov13850->exposure->default_value);
1316 break;
1317 }
1318
1319 if (!pm_runtime_get_if_in_use(&client->dev))
1320 return 0;
1321
1322 switch (ctrl->id) {
1323 case V4L2_CID_EXPOSURE:
1324 /* 4 least significant bits of expsoure are fractional part */
1325 ret = ov13850_write_reg(ov13850->client,
1326 OV13850_REG_EXPOSURE,
1327 OV13850_REG_VALUE_24BIT,
1328 ctrl->val << 4);
1329 break;
1330 case V4L2_CID_ANALOGUE_GAIN:
1331 ret = ov13850_write_reg(ov13850->client,
1332 OV13850_REG_GAIN_H,
1333 OV13850_REG_VALUE_08BIT,
1334 (ctrl->val >> OV13850_GAIN_H_SHIFT) &
1335 OV13850_GAIN_H_MASK);
1336 ret |= ov13850_write_reg(ov13850->client,
1337 OV13850_REG_GAIN_L,
1338 OV13850_REG_VALUE_08BIT,
1339 ctrl->val & OV13850_GAIN_L_MASK);
1340 break;
1341 case V4L2_CID_VBLANK:
1342 ret = ov13850_write_reg(ov13850->client,
1343 OV13850_REG_VTS,
1344 OV13850_REG_VALUE_16BIT,
1345 ctrl->val + ov13850->cur_mode->height);
1346 break;
1347 case V4L2_CID_TEST_PATTERN:
1348 ret = ov13850_enable_test_pattern(ov13850, ctrl->val);
1349 break;
1350 default:
1351 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1352 __func__, ctrl->id, ctrl->val);
1353 break;
1354 }
1355
1356 pm_runtime_put(&client->dev);
1357
1358 return ret;
1359 }
1360
1361 static const struct v4l2_ctrl_ops ov13850_ctrl_ops = {
1362 .s_ctrl = ov13850_set_ctrl,
1363 };
1364
ov13850_initialize_controls(struct ov13850 * ov13850)1365 static int ov13850_initialize_controls(struct ov13850 *ov13850)
1366 {
1367 const struct ov13850_mode *mode;
1368 struct v4l2_ctrl_handler *handler;
1369 struct v4l2_ctrl *ctrl;
1370 s64 exposure_max, vblank_def;
1371 u32 h_blank;
1372 int ret;
1373
1374 handler = &ov13850->ctrl_handler;
1375 mode = ov13850->cur_mode;
1376 ret = v4l2_ctrl_handler_init(handler, 8);
1377 if (ret)
1378 return ret;
1379 handler->lock = &ov13850->mutex;
1380
1381 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1382 0, 0, link_freq_menu_items);
1383 if (ctrl)
1384 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1385
1386 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1387 0, OV13850_PIXEL_RATE, 1, OV13850_PIXEL_RATE);
1388
1389 h_blank = mode->hts_def - mode->width;
1390 ov13850->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1391 h_blank, h_blank, 1, h_blank);
1392 if (ov13850->hblank)
1393 ov13850->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1394
1395 vblank_def = mode->vts_def - mode->height;
1396 ov13850->vblank = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
1397 V4L2_CID_VBLANK, vblank_def,
1398 OV13850_VTS_MAX - mode->height,
1399 1, vblank_def);
1400
1401 exposure_max = mode->vts_def - 4;
1402 ov13850->exposure = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
1403 V4L2_CID_EXPOSURE, OV13850_EXPOSURE_MIN,
1404 exposure_max, OV13850_EXPOSURE_STEP,
1405 mode->exp_def);
1406
1407 ov13850->anal_gain = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
1408 V4L2_CID_ANALOGUE_GAIN, OV13850_GAIN_MIN,
1409 OV13850_GAIN_MAX, OV13850_GAIN_STEP,
1410 OV13850_GAIN_DEFAULT);
1411
1412 ov13850->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1413 &ov13850_ctrl_ops, V4L2_CID_TEST_PATTERN,
1414 ARRAY_SIZE(ov13850_test_pattern_menu) - 1,
1415 0, 0, ov13850_test_pattern_menu);
1416
1417 if (handler->error) {
1418 ret = handler->error;
1419 dev_err(&ov13850->client->dev,
1420 "Failed to init controls(%d)\n", ret);
1421 goto err_free_handler;
1422 }
1423
1424 ov13850->subdev.ctrl_handler = handler;
1425
1426 return 0;
1427
1428 err_free_handler:
1429 v4l2_ctrl_handler_free(handler);
1430
1431 return ret;
1432 }
1433
ov13850_check_sensor_id(struct ov13850 * ov13850,struct i2c_client * client)1434 static int ov13850_check_sensor_id(struct ov13850 *ov13850,
1435 struct i2c_client *client)
1436 {
1437 struct device *dev = &ov13850->client->dev;
1438 u32 id = 0;
1439 int ret;
1440
1441 ret = ov13850_read_reg(client, OV13850_REG_CHIP_ID,
1442 OV13850_REG_VALUE_16BIT, &id);
1443 if (id != CHIP_ID) {
1444 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1445 return -ENODEV;
1446 }
1447
1448 ret = ov13850_read_reg(client, OV13850_CHIP_REVISION_REG,
1449 OV13850_REG_VALUE_08BIT, &id);
1450 if (ret) {
1451 dev_err(dev, "Read chip revision register error\n");
1452 return ret;
1453 }
1454
1455 if (id == OV13850_R2A)
1456 ov13850_global_regs = ov13850_global_regs_r2a;
1457 else
1458 ov13850_global_regs = ov13850_global_regs_r1a;
1459 dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id);
1460
1461 return 0;
1462 }
1463
ov13850_configure_regulators(struct ov13850 * ov13850)1464 static int ov13850_configure_regulators(struct ov13850 *ov13850)
1465 {
1466 unsigned int i;
1467
1468 for (i = 0; i < OV13850_NUM_SUPPLIES; i++)
1469 ov13850->supplies[i].supply = ov13850_supply_names[i];
1470
1471 return devm_regulator_bulk_get(&ov13850->client->dev,
1472 OV13850_NUM_SUPPLIES,
1473 ov13850->supplies);
1474 }
1475
ov13850_probe(struct i2c_client * client,const struct i2c_device_id * id)1476 static int ov13850_probe(struct i2c_client *client,
1477 const struct i2c_device_id *id)
1478 {
1479 struct device *dev = &client->dev;
1480 struct device_node *node = dev->of_node;
1481 struct ov13850 *ov13850;
1482 struct v4l2_subdev *sd;
1483 char facing[2];
1484 int ret;
1485
1486 dev_info(dev, "driver version: %02x.%02x.%02x",
1487 DRIVER_VERSION >> 16,
1488 (DRIVER_VERSION & 0xff00) >> 8,
1489 DRIVER_VERSION & 0x00ff);
1490
1491 ov13850 = devm_kzalloc(dev, sizeof(*ov13850), GFP_KERNEL);
1492 if (!ov13850)
1493 return -ENOMEM;
1494
1495 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1496 &ov13850->module_index);
1497 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1498 &ov13850->module_facing);
1499 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1500 &ov13850->module_name);
1501 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1502 &ov13850->len_name);
1503 if (ret) {
1504 dev_err(dev, "could not get module information!\n");
1505 return -EINVAL;
1506 }
1507
1508 ov13850->client = client;
1509 ov13850->cur_mode = &supported_modes[0];
1510
1511 ov13850->xvclk = devm_clk_get(dev, "xvclk");
1512 if (IS_ERR(ov13850->xvclk)) {
1513 dev_err(dev, "Failed to get xvclk\n");
1514 return -EINVAL;
1515 }
1516
1517 ov13850->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1518 if (IS_ERR(ov13850->power_gpio))
1519 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1520
1521 ov13850->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1522 if (IS_ERR(ov13850->reset_gpio))
1523 dev_warn(dev, "Failed to get reset-gpios\n");
1524
1525 ov13850->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1526 if (IS_ERR(ov13850->pwdn_gpio))
1527 dev_warn(dev, "Failed to get pwdn-gpios\n");
1528
1529 ret = ov13850_configure_regulators(ov13850);
1530 if (ret) {
1531 dev_err(dev, "Failed to get power regulators\n");
1532 return ret;
1533 }
1534
1535 ov13850->pinctrl = devm_pinctrl_get(dev);
1536 if (!IS_ERR(ov13850->pinctrl)) {
1537 ov13850->pins_default =
1538 pinctrl_lookup_state(ov13850->pinctrl,
1539 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1540 if (IS_ERR(ov13850->pins_default))
1541 dev_err(dev, "could not get default pinstate\n");
1542
1543 ov13850->pins_sleep =
1544 pinctrl_lookup_state(ov13850->pinctrl,
1545 OF_CAMERA_PINCTRL_STATE_SLEEP);
1546 if (IS_ERR(ov13850->pins_sleep))
1547 dev_err(dev, "could not get sleep pinstate\n");
1548 }
1549
1550 mutex_init(&ov13850->mutex);
1551
1552 sd = &ov13850->subdev;
1553 v4l2_i2c_subdev_init(sd, client, &ov13850_subdev_ops);
1554 ret = ov13850_initialize_controls(ov13850);
1555 if (ret)
1556 goto err_destroy_mutex;
1557
1558 ret = __ov13850_power_on(ov13850);
1559 if (ret)
1560 goto err_free_handler;
1561
1562 ret = ov13850_check_sensor_id(ov13850, client);
1563 if (ret)
1564 goto err_power_off;
1565
1566 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1567 sd->internal_ops = &ov13850_internal_ops;
1568 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1569 #endif
1570 #if defined(CONFIG_MEDIA_CONTROLLER)
1571 ov13850->pad.flags = MEDIA_PAD_FL_SOURCE;
1572 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1573 ret = media_entity_pads_init(&sd->entity, 1, &ov13850->pad);
1574 if (ret < 0)
1575 goto err_power_off;
1576 #endif
1577
1578 memset(facing, 0, sizeof(facing));
1579 if (strcmp(ov13850->module_facing, "back") == 0)
1580 facing[0] = 'b';
1581 else
1582 facing[0] = 'f';
1583
1584 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1585 ov13850->module_index, facing,
1586 OV13850_NAME, dev_name(sd->dev));
1587 ret = v4l2_async_register_subdev_sensor_common(sd);
1588 if (ret) {
1589 dev_err(dev, "v4l2 async register subdev failed\n");
1590 goto err_clean_entity;
1591 }
1592
1593 pm_runtime_set_active(dev);
1594 pm_runtime_enable(dev);
1595 pm_runtime_idle(dev);
1596
1597 return 0;
1598
1599 err_clean_entity:
1600 #if defined(CONFIG_MEDIA_CONTROLLER)
1601 media_entity_cleanup(&sd->entity);
1602 #endif
1603 err_power_off:
1604 __ov13850_power_off(ov13850);
1605 err_free_handler:
1606 v4l2_ctrl_handler_free(&ov13850->ctrl_handler);
1607 err_destroy_mutex:
1608 mutex_destroy(&ov13850->mutex);
1609
1610 return ret;
1611 }
1612
ov13850_remove(struct i2c_client * client)1613 static int ov13850_remove(struct i2c_client *client)
1614 {
1615 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1616 struct ov13850 *ov13850 = to_ov13850(sd);
1617
1618 v4l2_async_unregister_subdev(sd);
1619 #if defined(CONFIG_MEDIA_CONTROLLER)
1620 media_entity_cleanup(&sd->entity);
1621 #endif
1622 v4l2_ctrl_handler_free(&ov13850->ctrl_handler);
1623 mutex_destroy(&ov13850->mutex);
1624
1625 pm_runtime_disable(&client->dev);
1626 if (!pm_runtime_status_suspended(&client->dev))
1627 __ov13850_power_off(ov13850);
1628 pm_runtime_set_suspended(&client->dev);
1629
1630 return 0;
1631 }
1632
1633 #if IS_ENABLED(CONFIG_OF)
1634 static const struct of_device_id ov13850_of_match[] = {
1635 { .compatible = "ovti,ov13850" },
1636 {},
1637 };
1638 MODULE_DEVICE_TABLE(of, ov13850_of_match);
1639 #endif
1640
1641 static const struct i2c_device_id ov13850_match_id[] = {
1642 { "ovti,ov13850", 0 },
1643 { },
1644 };
1645
1646 static struct i2c_driver ov13850_i2c_driver = {
1647 .driver = {
1648 .name = OV13850_NAME,
1649 .pm = &ov13850_pm_ops,
1650 .of_match_table = of_match_ptr(ov13850_of_match),
1651 },
1652 .probe = &ov13850_probe,
1653 .remove = &ov13850_remove,
1654 .id_table = ov13850_match_id,
1655 };
1656
sensor_mod_init(void)1657 static int __init sensor_mod_init(void)
1658 {
1659 return i2c_add_driver(&ov13850_i2c_driver);
1660 }
1661
sensor_mod_exit(void)1662 static void __exit sensor_mod_exit(void)
1663 {
1664 i2c_del_driver(&ov13850_i2c_driver);
1665 }
1666
1667 device_initcall_sync(sensor_mod_init);
1668 module_exit(sensor_mod_exit);
1669
1670 MODULE_DESCRIPTION("OmniVision ov13850 sensor driver");
1671 MODULE_LICENSE("GPL v2");
1672