1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov02k10 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version, only linear mode ready.
8 * V0.0X01.0X01 both linear and HDR modes are ready.
9 * V0.0X01.0X02 add quick stream on/off
10 */
11
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/slab.h>
22 #include <linux/version.h>
23 #include <linux/rk-camera-module.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/rk-preisp.h>
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define MIPI_FREQ_360M 360000000
38 #define MIPI_FREQ_480M 480000000
39
40 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 12 * 2)
41 #define PIXEL_RATE_WITH_480M (MIPI_FREQ_480M * 2 / 12 * 2)
42 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
43
44 #define OV02K10_XVCLK_FREQ 24000000
45
46 #define CHIP_ID 0x530243
47 #define OV02K10_REG_CHIP_ID 0x300a
48
49 #define OV02K10_REG_CTRL_MODE 0x0100
50 #define OV02K10_MODE_SW_STANDBY 0x0
51 #define OV02K10_MODE_STREAMING BIT(0)
52
53 #define OV02K10_EXPOSURE_MIN 1
54 #define OV02K10_EXPOSURE_STEP 1
55 #define OV02K10_VTS_MAX 0xffff
56
57 #define OV02K10_REG_EXP_LONG_H 0x3501
58 #define OV02K10_REG_EXP_MID_H 0x3541
59 #define OV02K10_REG_EXP_VS_H 0x3581
60
61 #define OV02K10_REG_HCG_SWITCH 0x376C
62 #define OV02K10_REG_AGAIN_LONG_H 0x3508
63 #define OV02K10_REG_AGAIN_MID_H 0x3548
64 #define OV02K10_REG_AGAIN_VS_H 0x3588
65 #define OV02K10_REG_DGAIN_LONG_H 0x350A
66 #define OV02K10_REG_DGAIN_MID_H 0x354A
67 #define OV02K10_REG_DGAIN_VS_H 0x358A
68 #define OV02K10_GAIN_MIN 0x10
69 #define OV02K10_GAIN_MAX 0xF7C
70 #define OV02K10_GAIN_STEP 1
71 #define OV02K10_GAIN_DEFAULT 0x10
72
73 #define OV02K10_GROUP_UPDATE_ADDRESS 0x3208
74 #define OV02K10_GROUP_UPDATE_START_DATA 0x00
75 #define OV02K10_GROUP_UPDATE_END_DATA 0x10
76 #define OV02K10_GROUP_UPDATE_LAUNCH 0xA0
77
78 #define OV02K10_SOFTWARE_RESET_REG 0x0103
79
80 #define OV02K10_FETCH_MSB_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */
81 #define OV02K10_FETCH_LSB_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
82
83 #define OV02K10_FETCH_LSB_GAIN(VAL) (((VAL) << 4) & 0xf0)
84 #define OV02K10_FETCH_MSB_GAIN(VAL) (((VAL) >> 4) & 0x1f)
85
86 #define OV02K10_REG_TEST_PATTERN 0x50C0
87 #define OV02K10_TEST_PATTERN_ENABLE 0x80
88 #define OV02K10_TEST_PATTERN_DISABLE 0x0
89
90 #define OV02K10_REG_VTS 0x380e
91
92 #define REG_NULL 0xFFFF
93
94 #define OV02K10_REG_VALUE_08BIT 1
95 #define OV02K10_REG_VALUE_16BIT 2
96 #define OV02K10_REG_VALUE_24BIT 3
97
98 #define OV02K10_LANES 2
99
100 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
101 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
102
103 #define OV02K10_NAME "ov02k10"
104
105 #define OV02K10_FLIP_REG 0x3820
106 #define MIRROR_BIT_MASK BIT(1)
107 #define FLIP_BIT_MASK (BIT(2) | BIT(3))
108
109 #define USED_SYS_DEBUG
110
111 static const char * const ov02k10_supply_names[] = {
112 "avdd", /* Analog power */
113 "dovdd", /* Digital I/O power */
114 "dvdd", /* Digital core power */
115 };
116
117 #define OV02K10_NUM_SUPPLIES ARRAY_SIZE(ov02k10_supply_names)
118
119 struct regval {
120 u16 addr;
121 u8 val;
122 };
123
124 struct ov02k10_mode {
125 u32 bus_fmt;
126 u32 width;
127 u32 height;
128 struct v4l2_fract max_fps;
129 u32 hts_def;
130 u32 vts_def;
131 u32 exp_def;
132 const struct regval *reg_list;
133 u32 hdr_mode;
134 u32 vc[PAD_MAX];
135 };
136
137 struct ov02k10 {
138 struct i2c_client *client;
139 struct clk *xvclk;
140 struct gpio_desc *power_gpio;
141 struct gpio_desc *reset_gpio;
142 struct gpio_desc *pwdn_gpio;
143 struct regulator_bulk_data supplies[OV02K10_NUM_SUPPLIES];
144
145 struct pinctrl *pinctrl;
146 struct pinctrl_state *pins_default;
147 struct pinctrl_state *pins_sleep;
148
149 struct v4l2_subdev subdev;
150 struct media_pad pad;
151 struct v4l2_ctrl_handler ctrl_handler;
152 struct v4l2_ctrl *exposure;
153 struct v4l2_ctrl *anal_gain;
154 struct v4l2_ctrl *digi_gain;
155 struct v4l2_ctrl *hblank;
156 struct v4l2_ctrl *vblank;
157 struct v4l2_ctrl *test_pattern;
158 struct v4l2_ctrl *pixel_rate;
159 struct v4l2_ctrl *link_freq;
160 struct v4l2_ctrl *h_flip;
161 struct v4l2_ctrl *v_flip;
162 struct mutex mutex;
163 bool streaming;
164 bool power_on;
165 const struct ov02k10_mode *cur_mode;
166 u32 cfg_num;
167 u32 module_index;
168 const char *module_facing;
169 const char *module_name;
170 const char *len_name;
171 bool has_init_exp;
172 struct preisp_hdrae_exp_s init_hdrae_exp;
173 bool long_hcg;
174 bool middle_hcg;
175 bool short_hcg;
176 u32 flip;
177 };
178
179 #define to_ov02k10(sd) container_of(sd, struct ov02k10, subdev)
180
181 /*
182 * Xclk 24Mhz
183 */
184 static const struct regval ov02k10_global_regs[] = {
185 {0x302a, 0x00},
186 {0x0103, 0x01},
187 {0x0109, 0x01},
188 {0x0104, 0x02},
189 {0x0306, 0x00},
190 {0x0307, 0x00},
191 {0x032d, 0x02},
192 {0x0317, 0x0a},
193 {0x0323, 0x07},
194 {0x0324, 0x01},
195 {0x0325, 0xb0},
196 {0x0327, 0x07},
197 {0x300f, 0x11},
198 {0x3012, 0x21},
199 {0x302d, 0x24},
200 {0x3400, 0x00},
201 {0x3406, 0x08},
202 {0x3504, 0x08},
203 {0x3508, 0x01},
204 {0x3509, 0x00},
205 {0x3544, 0x08},
206 {0x3548, 0x01},
207 {0x3549, 0x00},
208 {0x3584, 0x08},
209 {0x3588, 0x01},
210 {0x3589, 0x00},
211 {0x3601, 0x70},
212 {0x3604, 0xe3},
213 {0x3608, 0xa8},
214 {0x360a, 0xd0},
215 {0x360b, 0x08},
216 {0x360e, 0xc8},
217 {0x360f, 0x66},
218 {0x3610, 0x81},
219 {0x3611, 0x89},
220 {0x3612, 0x4e},
221 {0x3613, 0xbd},
222 {0x362a, 0x0e},
223 {0x362b, 0x0e},
224 {0x362c, 0x0e},
225 {0x362d, 0x0e},
226 {0x362e, 0x0c},
227 {0x362f, 0x1a},
228 {0x3630, 0x32},
229 {0x3631, 0x64},
230 {0x3638, 0x00},
231 {0x3643, 0x00},
232 {0x3644, 0x00},
233 {0x3645, 0x00},
234 {0x3646, 0x00},
235 {0x3647, 0x00},
236 {0x3648, 0x00},
237 {0x3649, 0x00},
238 {0x364a, 0x04},
239 {0x364c, 0x0e},
240 {0x364d, 0x0e},
241 {0x364e, 0x0e},
242 {0x364f, 0x0e},
243 {0x3650, 0xff},
244 {0x3651, 0xff},
245 {0x3661, 0x07},
246 {0x3662, 0x00},
247 {0x3663, 0x20},
248 {0x3665, 0x12},
249 {0x3667, 0xd4},
250 {0x3668, 0x80},
251 {0x3681, 0x80},
252 {0x3700, 0x26},
253 {0x3701, 0x1e},
254 {0x3702, 0x25},
255 {0x3703, 0x28},
256 {0x3790, 0x10},
257 {0x3793, 0x04},
258 {0x3794, 0x07},
259 {0x3796, 0x00},
260 {0x3797, 0x02},
261 {0x37a1, 0x80},
262 {0x37bb, 0x88},
263 {0x37be, 0x01},
264 {0x37bf, 0x00},
265 {0x37c0, 0x01},
266 {0x37c7, 0x56},
267 {0x37ca, 0x21},
268 {0x37cd, 0x90},
269 {0x37cf, 0x02},
270 {0x37da, 0x00},
271 {0x37db, 0x00},
272 {0x37dd, 0x00},
273 {0x3800, 0x00},
274 {0x3801, 0x00},
275 {0x3802, 0x00},
276 {0x3803, 0x04},
277 {0x3804, 0x07},
278 {0x3805, 0x8f},
279 {0x3806, 0x04},
280 {0x3807, 0x43},
281 {0x3808, 0x07},
282 {0x3809, 0x80},
283 {0x380a, 0x04},
284 {0x380b, 0x38},
285 {0x3811, 0x08},
286 {0x3813, 0x04},
287 {0x3814, 0x01},
288 {0x3815, 0x01},
289 {0x3816, 0x01},
290 {0x3817, 0x01},
291 {0x3821, 0x00},
292 {0x3822, 0x14},
293 {0x3865, 0x00},
294 {0x3866, 0xc0},
295 {0x3867, 0x00},
296 {0x3868, 0xc0},
297 {0x3900, 0x13},
298 {0x3940, 0x13},
299 {0x3980, 0x13},
300 {0x3c01, 0x11},
301 {0x3c05, 0x00},
302 {0x3c0f, 0x1c},
303 {0x3c12, 0x0d},
304 {0x3c19, 0x01},
305 {0x3c21, 0x40},
306 {0x3c3b, 0x18},
307 {0x3c3d, 0xc9},
308 {0x3c55, 0xcb},
309 {0x3ce0, 0x00},
310 {0x3ce1, 0x00},
311 {0x3ce2, 0x00},
312 {0x3ce3, 0x00},
313 {0x3d8c, 0x70},
314 {0x3d8d, 0x10},
315 {0x4033, 0x80},
316 {0x4008, 0x02},
317 {0x4009, 0x11},
318 {0x4004, 0x01},
319 {0x4005, 0x00},
320 {0x410f, 0x01},
321 {0x402e, 0x01},
322 {0x402f, 0x00},
323 {0x4030, 0x01},
324 {0x4031, 0x00},
325 {0x4032, 0x9f},
326 {0x4050, 0x00},
327 {0x4051, 0x07},
328 {0x4289, 0x03},
329 {0x428a, 0x46},
330 {0x430b, 0xff},
331 {0x430c, 0xff},
332 {0x430d, 0x00},
333 {0x430e, 0x00},
334 {0x4500, 0x18},
335 {0x4501, 0x18},
336 {0x4504, 0x00},
337 {0x4603, 0x00},
338 {0x4640, 0x62},
339 {0x4646, 0xaa},
340 {0x4647, 0x55},
341 {0x4648, 0x99},
342 {0x4649, 0x66},
343 {0x464d, 0x00},
344 {0x4654, 0x11},
345 {0x4655, 0x22},
346 {0x4800, 0x04},
347 {0x4810, 0xff},
348 {0x4811, 0xff},
349 {0x4837, 0x0c},
350 {0x4d00, 0x4e},
351 {0x4d01, 0x0c},
352 {0x4d09, 0x4f},
353 {0x5000, 0x1f},
354 {0x5080, 0x00},
355 {0x50c0, 0x00},
356 {0x5100, 0x00},
357 {0x5200, 0x00},
358 {0x5201, 0x70},
359 {0x5202, 0x03},
360 {0x5203, 0x7f},
361 {0x3707, 0x0a},
362 {0x3714, 0x01},
363 {0x371c, 0x00},
364 {0x371d, 0x08},
365 {0x3762, 0x1d},
366 {0x3777, 0x22},
367 {0x3779, 0x60},
368 {0x377c, 0x48},
369 {0x379c, 0x4d},
370 {0x3784, 0x06},
371 {0x3785, 0x0a},
372 {0x37d8, 0x01},
373 {0x37dc, 0x00},
374 {REG_NULL, 0x00},
375 };
376
377 static const struct regval ov02k10_linear12bit_1920x1080_regs[] = {
378 {0x0102, 0x00},
379 {0x0305, 0x6c},
380 {0x3026, 0x10},
381 {0x3027, 0x08},
382 {0x3103, 0x25},
383 {0x3106, 0x10},
384 {0x3408, 0x05},
385 {0x340c, 0x05},
386 {0x3425, 0x51},
387 {0x3426, 0x10},
388 {0x3427, 0x14},
389 {0x3428, 0x50},
390 {0x3429, 0x10},
391 {0x342a, 0x10},
392 {0x342b, 0x04},
393 {0x3605, 0xff},
394 {0x3606, 0x01},
395 {0x366f, 0x00},
396 {0x3670, 0x07},
397 {0x3671, 0x08},
398 {0x3673, 0x2a},
399 {0x3706, 0xb1},
400 {0x3708, 0x34},
401 {0x3709, 0x50},
402 {0x370a, 0x02},
403 {0x370b, 0x21},
404 {0x371b, 0x13},
405 {0x3756, 0xe7},
406 {0x3757, 0xe7},
407 {0x376c, 0x00},
408 {0x3776, 0x03},
409 {0x37cc, 0x10},
410 {0x37d1, 0xb1},
411 {0x37d2, 0x02},
412 {0x37d3, 0x21},
413 {0x37d5, 0xb1},
414 {0x37d6, 0x02},
415 {0x37d7, 0x21},
416 {0x380d, 0xc8},
417 {0x380e, 0x05},
418 {0x380f, 0xb4},
419 {0x381c, 0x00},
420 {0x3820, 0x00},
421 {0x384d, 0xc8},
422 {0x3858, 0x0d},
423 {0x3c5d, 0xec},
424 {0x3c5e, 0xec},
425 {0x4001, 0x2f},
426 {0x400a, 0x03},
427 {0x400b, 0x40},
428 {0x4011, 0xff},
429 {0x4288, 0xcf},
430 {0x4314, 0x00},
431 {0x4507, 0x02},
432 {0x480e, 0x00},
433 {0x4813, 0x00},
434 {0x484b, 0x27},
435 {0x5780, 0x19},
436 {0x5786, 0x02},
437 {0x032e, 0x05},
438 {0x032d, 0x02},
439 {0x3501, 0x02},
440 {0x380c, 0x04},
441 {0x380d, 0xc8},
442 {0x384c, 0x04},
443 {0x384d, 0xc8},
444 {0x380e, 0x0b},
445 {0x380f, 0x7c},
446 {0x3834, 0x00},
447 {0x3832, 0x08},
448 {0x3002, 0x00},
449 {REG_NULL, 0x00},
450 };
451
452 static const struct regval ov02k10_hdr12bit_1920x1080_regs[] = {
453 {0x0102, 0x01},
454 {0x0305, 0x6d},
455 {0x3026, 0x00},
456 {0x3027, 0x00},
457 {0x3103, 0x29},
458 {0x3106, 0x11},
459 {0x3408, 0x01},
460 {0x340c, 0x10},
461 {0x3425, 0x00},
462 {0x3426, 0x00},
463 {0x3427, 0x00},
464 {0x3428, 0x00},
465 {0x3429, 0x00},
466 {0x342a, 0x00},
467 {0x342b, 0x00},
468 {0x3605, 0x7f},
469 {0x3606, 0x00},
470 {0x366f, 0xc4},
471 {0x3670, 0xc7},
472 {0x3671, 0x0b},
473 {0x3673, 0x6a},
474 {0x3706, 0x3e},
475 {0x3708, 0x36},
476 {0x3709, 0x55},
477 {0x370a, 0x00},
478 {0x370b, 0xa3},
479 {0x371b, 0x16},
480 {0x3756, 0x9b},
481 {0x3757, 0x9b},
482 {0x376c, 0x30},
483 {0x3776, 0x05},
484 {0x37cc, 0x13},
485 {0x37d1, 0x3e},
486 {0x37d2, 0x00},
487 {0x37d3, 0xa3},
488 {0x37d5, 0x3e},
489 {0x37d6, 0x00},
490 {0x37d7, 0xa3},
491 {0x380d, 0x38},
492 {0x380e, 0x04},
493 {0x380f, 0xe2},
494 {0x381c, 0x08},
495 {0x3820, 0x01},
496 {0x384d, 0x38},
497 {0x3858, 0x01},
498 {0x3c5d, 0xcf},
499 {0x3c5e, 0xcf},
500 {0x4001, 0xef},
501 {0x400a, 0x04},
502 {0x400b, 0xf0},
503 {0x4011, 0xbb},
504 {0x4288, 0xce},
505 {0x4314, 0x04},
506 {0x4507, 0x03},
507 {0x4508, 0x1a},
508 {0x480e, 0x04},
509 {0x4813, 0x84},
510 {0x484b, 0x67},
511 {0x5780, 0x53},
512 {0x5786, 0x01},
513 {0x032e, 0x0c},
514 {0x032d, 0x01},
515 {0x3106, 0x10},
516 {0x380c, 0x04},
517 {0x380d, 0x20},
518 {0x384c, 0x04},
519 {0x384d, 0x20},
520 {0x380e, 0x06},
521 {0x380f, 0xa8},
522 {0x3834, 0xf0},
523 {0x3832, 0x28},
524 {0x3002, 0x83},
525 {REG_NULL, 0x00},
526 };
527
528
529
530 /*
531 * The width and height must be configured to be
532 * the same as the current output resolution of the sensor.
533 * The input width of the isp needs to be 16 aligned.
534 * The input height of the isp needs to be 8 aligned.
535 * If the width or height does not meet the alignment rules,
536 * you can configure the cropping parameters with the following function to
537 * crop out the appropriate resolution.
538 * struct v4l2_subdev_pad_ops {
539 * .get_selection
540 * }
541 */
542 static const struct ov02k10_mode supported_modes[] = {
543 {
544 .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
545 .width = 1920,
546 .height = 1080,
547 .max_fps = {
548 .numerator = 10000,
549 .denominator = 300000,
550 },
551 .exp_def = 0x067a,
552 .hts_def = 0x04c8 * 2,
553 .vts_def = 0x0b7c,
554 .reg_list = ov02k10_linear12bit_1920x1080_regs,
555 .hdr_mode = NO_HDR,
556 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
557 },
558 {
559 .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
560 .width = 1920,
561 .height = 1080,
562 .max_fps = {
563 .numerator = 10000,
564 .denominator = 300000,
565 },
566
567 .exp_def = 0x026c,
568 .hts_def = 0x0420 * 2,
569 .vts_def = 0x06a8,
570 .reg_list = ov02k10_hdr12bit_1920x1080_regs,
571 .hdr_mode = HDR_X2,
572 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
573 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
574 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
575 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
576 },
577 };
578
579 static const s64 link_freq_menu_items[] = {
580 MIPI_FREQ_360M,
581 MIPI_FREQ_480M,
582 };
583
584 static const char * const ov02k10_test_pattern_menu[] = {
585 "Disabled",
586 "Vertical Color Bar Type 1",
587 "Vertical Color Bar Type 2",
588 "Vertical Color Bar Type 3",
589 "Vertical Color Bar Type 4"
590 };
591
592 /* Write registers up to 4 at a time */
ov02k10_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)593 static int ov02k10_write_reg(struct i2c_client *client, u16 reg,
594 u32 len, u32 val)
595 {
596 u32 buf_i, val_i;
597 u8 buf[6];
598 u8 *val_p;
599 __be32 val_be;
600
601 if (len > 4)
602 return -EINVAL;
603
604 buf[0] = reg >> 8;
605 buf[1] = reg & 0xff;
606
607 val_be = cpu_to_be32(val);
608 val_p = (u8 *)&val_be;
609 buf_i = 2;
610 val_i = 4 - len;
611
612 while (val_i < 4)
613 buf[buf_i++] = val_p[val_i++];
614
615 if (i2c_master_send(client, buf, len + 2) != len + 2)
616 return -EIO;
617
618 return 0;
619 }
620
ov02k10_write_array(struct i2c_client * client,const struct regval * regs)621 static int ov02k10_write_array(struct i2c_client *client,
622 const struct regval *regs)
623 {
624 u32 i;
625 int ret = 0;
626
627 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
628 ret |= ov02k10_write_reg(client, regs[i].addr,
629 OV02K10_REG_VALUE_08BIT, regs[i].val);
630 }
631 return ret;
632 }
633
634 /* Read registers up to 4 at a time */
ov02k10_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)635 static int ov02k10_read_reg(struct i2c_client *client,
636 u16 reg,
637 unsigned int len,
638 u32 *val)
639 {
640 struct i2c_msg msgs[2];
641 u8 *data_be_p;
642 __be32 data_be = 0;
643 __be16 reg_addr_be = cpu_to_be16(reg);
644 int ret;
645
646 if (len > 4 || !len)
647 return -EINVAL;
648
649 data_be_p = (u8 *)&data_be;
650 /* Write register address */
651 msgs[0].addr = client->addr;
652 msgs[0].flags = 0;
653 msgs[0].len = 2;
654 msgs[0].buf = (u8 *)®_addr_be;
655
656 /* Read data from register */
657 msgs[1].addr = client->addr;
658 msgs[1].flags = I2C_M_RD;
659 msgs[1].len = len;
660 msgs[1].buf = &data_be_p[4 - len];
661
662 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
663 if (ret != ARRAY_SIZE(msgs))
664 return -EIO;
665
666 *val = be32_to_cpu(data_be);
667
668 return 0;
669 }
670
ov02k10_get_reso_dist(const struct ov02k10_mode * mode,struct v4l2_mbus_framefmt * framefmt)671 static int ov02k10_get_reso_dist(const struct ov02k10_mode *mode,
672 struct v4l2_mbus_framefmt *framefmt)
673 {
674 return abs(mode->width - framefmt->width) +
675 abs(mode->height - framefmt->height);
676 }
677
678 static const struct ov02k10_mode *
ov02k10_find_best_fit(struct ov02k10 * ov02k10,struct v4l2_subdev_format * fmt)679 ov02k10_find_best_fit(struct ov02k10 *ov02k10, struct v4l2_subdev_format *fmt)
680 {
681 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
682 int dist;
683 int cur_best_fit = 0;
684 int cur_best_fit_dist = -1;
685 unsigned int i;
686
687 for (i = 0; i < ov02k10->cfg_num; i++) {
688 dist = ov02k10_get_reso_dist(&supported_modes[i], framefmt);
689 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
690 (supported_modes[i].bus_fmt == framefmt->code)) {
691 cur_best_fit_dist = dist;
692 cur_best_fit = i;
693 }
694 }
695
696 return &supported_modes[cur_best_fit];
697 }
698
ov02k10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)699 static int ov02k10_set_fmt(struct v4l2_subdev *sd,
700 struct v4l2_subdev_pad_config *cfg,
701 struct v4l2_subdev_format *fmt)
702 {
703 struct ov02k10 *ov02k10 = to_ov02k10(sd);
704 const struct ov02k10_mode *mode;
705 s64 h_blank, vblank_def;
706 u64 dst_link_freq = 0;
707 u64 dst_pixel_rate = 0;
708
709 mutex_lock(&ov02k10->mutex);
710
711 mode = ov02k10_find_best_fit(ov02k10, fmt);
712 fmt->format.code = mode->bus_fmt;
713 fmt->format.width = mode->width;
714 fmt->format.height = mode->height;
715 fmt->format.field = V4L2_FIELD_NONE;
716 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
717 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
718 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
719 #else
720 mutex_unlock(&ov02k10->mutex);
721 return -ENOTTY;
722 #endif
723 } else {
724 ov02k10->cur_mode = mode;
725 h_blank = mode->hts_def - mode->width;
726 __v4l2_ctrl_modify_range(ov02k10->hblank, h_blank,
727 h_blank, 1, h_blank);
728 vblank_def = mode->vts_def - mode->height;
729 __v4l2_ctrl_modify_range(ov02k10->vblank, vblank_def,
730 OV02K10_VTS_MAX - mode->height,
731 1, vblank_def);
732 if (mode->hdr_mode == NO_HDR) {
733 dst_link_freq = 0;
734 dst_pixel_rate = PIXEL_RATE_WITH_360M;
735 } else if (mode->hdr_mode == HDR_X2) {
736 dst_link_freq = 1;
737 dst_pixel_rate = PIXEL_RATE_WITH_480M;
738 }
739 __v4l2_ctrl_s_ctrl_int64(ov02k10->pixel_rate,
740 dst_pixel_rate);
741 __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
742 dst_link_freq);
743 }
744
745 mutex_unlock(&ov02k10->mutex);
746
747 return 0;
748 }
749
ov02k10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)750 static int ov02k10_get_fmt(struct v4l2_subdev *sd,
751 struct v4l2_subdev_pad_config *cfg,
752 struct v4l2_subdev_format *fmt)
753 {
754 struct ov02k10 *ov02k10 = to_ov02k10(sd);
755 const struct ov02k10_mode *mode = ov02k10->cur_mode;
756
757 mutex_lock(&ov02k10->mutex);
758 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
759 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
760 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
761 #else
762 mutex_unlock(&ov02k10->mutex);
763 return -ENOTTY;
764 #endif
765 } else {
766 fmt->format.width = mode->width;
767 fmt->format.height = mode->height;
768 fmt->format.code = mode->bus_fmt;
769 fmt->format.field = V4L2_FIELD_NONE;
770 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
771 fmt->reserved[0] = mode->vc[fmt->pad];
772 else
773 fmt->reserved[0] = mode->vc[PAD0];
774 }
775 mutex_unlock(&ov02k10->mutex);
776
777 return 0;
778 }
779
ov02k10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)780 static int ov02k10_enum_mbus_code(struct v4l2_subdev *sd,
781 struct v4l2_subdev_pad_config *cfg,
782 struct v4l2_subdev_mbus_code_enum *code)
783 {
784 struct ov02k10 *ov02k10 = to_ov02k10(sd);
785
786 if (code->index != 0)
787 return -EINVAL;
788 code->code = ov02k10->cur_mode->bus_fmt;
789
790 return 0;
791 }
792
ov02k10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)793 static int ov02k10_enum_frame_sizes(struct v4l2_subdev *sd,
794 struct v4l2_subdev_pad_config *cfg,
795 struct v4l2_subdev_frame_size_enum *fse)
796 {
797 struct ov02k10 *ov02k10 = to_ov02k10(sd);
798
799 if (fse->index >= ov02k10->cfg_num)
800 return -EINVAL;
801
802 if (fse->code != supported_modes[fse->index].bus_fmt)
803 return -EINVAL;
804
805 fse->min_width = supported_modes[fse->index].width;
806 fse->max_width = supported_modes[fse->index].width;
807 fse->max_height = supported_modes[fse->index].height;
808 fse->min_height = supported_modes[fse->index].height;
809
810 return 0;
811 }
812
ov02k10_enable_test_pattern(struct ov02k10 * ov02k10,u32 pattern)813 static int ov02k10_enable_test_pattern(struct ov02k10 *ov02k10, u32 pattern)
814 {
815 u32 val;
816
817 if (pattern)
818 val = (pattern - 1) | OV02K10_TEST_PATTERN_ENABLE;
819 else
820 val = OV02K10_TEST_PATTERN_DISABLE;
821
822 return ov02k10_write_reg(ov02k10->client, OV02K10_REG_TEST_PATTERN,
823 OV02K10_REG_VALUE_08BIT, val);
824 }
825
ov02k10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)826 static int ov02k10_g_frame_interval(struct v4l2_subdev *sd,
827 struct v4l2_subdev_frame_interval *fi)
828 {
829 struct ov02k10 *ov02k10 = to_ov02k10(sd);
830 const struct ov02k10_mode *mode = ov02k10->cur_mode;
831
832 fi->interval = mode->max_fps;
833
834 return 0;
835 }
836
ov02k10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)837 static int ov02k10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
838 struct v4l2_mbus_config *config)
839 {
840 struct ov02k10 *ov02k10 = to_ov02k10(sd);
841 const struct ov02k10_mode *mode = ov02k10->cur_mode;
842 u32 val = 0;
843
844 if (mode->hdr_mode == NO_HDR)
845 val = 1 << (OV02K10_LANES - 1) |
846 V4L2_MBUS_CSI2_CHANNEL_0 |
847 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
848 if (mode->hdr_mode == HDR_X2)
849 val = 1 << (OV02K10_LANES - 1) |
850 V4L2_MBUS_CSI2_CHANNEL_0 |
851 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
852 V4L2_MBUS_CSI2_CHANNEL_1;
853
854 config->type = V4L2_MBUS_CSI2_DPHY;
855 config->flags = val;
856
857 return 0;
858 }
859
ov02k10_get_module_inf(struct ov02k10 * ov02k10,struct rkmodule_inf * inf)860 static void ov02k10_get_module_inf(struct ov02k10 *ov02k10,
861 struct rkmodule_inf *inf)
862 {
863 memset(inf, 0, sizeof(*inf));
864 strlcpy(inf->base.sensor, OV02K10_NAME, sizeof(inf->base.sensor));
865 strlcpy(inf->base.module, ov02k10->module_name,
866 sizeof(inf->base.module));
867 strlcpy(inf->base.lens, ov02k10->len_name, sizeof(inf->base.lens));
868 }
869
870
ov02k10_set_hdrae(struct ov02k10 * ov02k10,struct preisp_hdrae_exp_s * ae)871 static int ov02k10_set_hdrae(struct ov02k10 *ov02k10,
872 struct preisp_hdrae_exp_s *ae)
873 {
874 u32 l_exp_time, m_exp_time, s_exp_time;
875 u32 l_a_gain, m_a_gain, s_a_gain;
876 u32 l_d_gain = 1024;
877 u32 m_d_gain = 1024;
878 int ret = 0;
879 u8 l_cg_mode = 0;
880 u8 m_cg_mode = 0;
881 u8 s_cg_mode = 0;
882 u32 gain_switch = 0;
883 u8 is_need_switch = 0;
884
885 if (!ov02k10->has_init_exp && !ov02k10->streaming) {
886 ov02k10->init_hdrae_exp = *ae;
887 ov02k10->has_init_exp = true;
888 dev_dbg(&ov02k10->client->dev, "ov02k10 don't stream, record exp for hdr!\n");
889 return ret;
890 }
891 l_exp_time = ae->long_exp_reg;
892 m_exp_time = ae->middle_exp_reg;
893 s_exp_time = ae->short_exp_reg;
894 l_a_gain = ae->long_gain_reg;
895 m_a_gain = ae->middle_gain_reg;
896 s_a_gain = ae->short_gain_reg;
897 l_cg_mode = ae->long_cg_mode;
898 m_cg_mode = ae->middle_cg_mode;
899 s_cg_mode = ae->short_cg_mode;
900 dev_dbg(&ov02k10->client->dev,
901 "rev exp:M_exp:0x%x,0x%x,cg %d,S_exp:0x%x,0x%x,cg %d\n",
902 m_exp_time, m_a_gain, m_cg_mode,
903 s_exp_time, s_a_gain, s_cg_mode);
904
905 if (ov02k10->cur_mode->hdr_mode == HDR_X2) {
906 //2 stagger
907 l_a_gain = m_a_gain;
908 l_exp_time = m_exp_time;
909 l_cg_mode = m_cg_mode;
910 m_a_gain = s_a_gain;
911 m_exp_time = s_exp_time;
912 m_cg_mode = s_cg_mode;
913 }
914 ret = ov02k10_read_reg(ov02k10->client, OV02K10_REG_HCG_SWITCH,
915 OV02K10_REG_VALUE_08BIT, &gain_switch);
916
917 if (ov02k10->long_hcg && l_cg_mode == GAIN_MODE_LCG) {
918 gain_switch |= 0x10;
919 ov02k10->long_hcg = false;
920 is_need_switch++;
921 } else if (!ov02k10->long_hcg && l_cg_mode == GAIN_MODE_HCG) {
922 gain_switch &= 0xef;
923 ov02k10->long_hcg = true;
924 is_need_switch++;
925 }
926 if (ov02k10->middle_hcg && m_cg_mode == GAIN_MODE_LCG) {
927 gain_switch |= 0x20;
928 ov02k10->middle_hcg = false;
929 is_need_switch++;
930 } else if (!ov02k10->middle_hcg && m_cg_mode == GAIN_MODE_HCG) {
931 gain_switch &= 0xdf;
932 ov02k10->middle_hcg = true;
933 is_need_switch++;
934 }
935
936 if (l_a_gain > 248) {
937 l_d_gain = l_a_gain * 1024 / 248;
938 l_a_gain = 248;
939 }
940 if (m_a_gain > 248) {
941 m_d_gain = m_a_gain * 1024 / 248;
942 m_a_gain = 248;
943 }
944 ret |= ov02k10_write_reg(ov02k10->client,
945 OV02K10_REG_AGAIN_LONG_H,
946 OV02K10_REG_VALUE_16BIT,
947 (l_a_gain << 4) & 0xff0);
948 ret |= ov02k10_write_reg(ov02k10->client,
949 OV02K10_REG_DGAIN_LONG_H,
950 OV02K10_REG_VALUE_24BIT,
951 (l_d_gain << 6) & 0xfffc0);
952 ret |= ov02k10_write_reg(ov02k10->client,
953 OV02K10_REG_EXP_LONG_H,
954 OV02K10_REG_VALUE_16BIT,
955 l_exp_time);
956 ret |= ov02k10_write_reg(ov02k10->client,
957 OV02K10_REG_AGAIN_MID_H,
958 OV02K10_REG_VALUE_16BIT,
959 (m_a_gain << 4) & 0xff0);
960 ret |= ov02k10_write_reg(ov02k10->client,
961 OV02K10_REG_DGAIN_MID_H,
962 OV02K10_REG_VALUE_24BIT,
963 (m_d_gain << 6) & 0xfffc0);
964 ret |= ov02k10_write_reg(ov02k10->client,
965 OV02K10_REG_EXP_MID_H,
966 OV02K10_REG_VALUE_16BIT,
967 m_exp_time);
968 if (is_need_switch) {
969 ret |= ov02k10_write_reg(ov02k10->client,
970 OV02K10_GROUP_UPDATE_ADDRESS,
971 OV02K10_REG_VALUE_08BIT,
972 OV02K10_GROUP_UPDATE_START_DATA);
973 ret |= ov02k10_write_reg(ov02k10->client,
974 OV02K10_REG_HCG_SWITCH,
975 OV02K10_REG_VALUE_08BIT,
976 gain_switch);
977 ret |= ov02k10_write_reg(ov02k10->client,
978 OV02K10_GROUP_UPDATE_ADDRESS,
979 OV02K10_REG_VALUE_08BIT,
980 OV02K10_GROUP_UPDATE_END_DATA);
981 ret |= ov02k10_write_reg(ov02k10->client,
982 OV02K10_GROUP_UPDATE_ADDRESS,
983 OV02K10_REG_VALUE_08BIT,
984 OV02K10_GROUP_UPDATE_LAUNCH);
985 }
986 return ret;
987 }
988
ov02k10_set_conversion_gain(struct ov02k10 * ov02k10,u32 * cg)989 static int ov02k10_set_conversion_gain(struct ov02k10 *ov02k10, u32 *cg)
990 {
991 int ret = 0;
992 struct i2c_client *client = ov02k10->client;
993 u32 cur_cg = *cg;
994 u32 val = 0;
995 s32 is_need_change = 0;
996
997 dev_dbg(&ov02k10->client->dev, "set conversion gain %d\n", cur_cg);
998 mutex_lock(&ov02k10->mutex);
999 ret = ov02k10_read_reg(client,
1000 OV02K10_REG_HCG_SWITCH,
1001 OV02K10_REG_VALUE_08BIT,
1002 &val);
1003 if (ov02k10->long_hcg && cur_cg == GAIN_MODE_LCG) {
1004 val |= 0x10;
1005 is_need_change++;
1006 ov02k10->long_hcg = false;
1007 } else if (!ov02k10->long_hcg && cur_cg == GAIN_MODE_HCG) {
1008 val &= 0xef;
1009 is_need_change++;
1010 ov02k10->long_hcg = true;
1011 }
1012 if (is_need_change) {
1013 ret |= ov02k10_write_reg(client,
1014 OV02K10_GROUP_UPDATE_ADDRESS,
1015 OV02K10_REG_VALUE_08BIT,
1016 OV02K10_GROUP_UPDATE_START_DATA);
1017 ret |= ov02k10_write_reg(client,
1018 OV02K10_REG_HCG_SWITCH,
1019 OV02K10_REG_VALUE_08BIT,
1020 val);
1021 ret |= ov02k10_write_reg(client,
1022 OV02K10_GROUP_UPDATE_ADDRESS,
1023 OV02K10_REG_VALUE_08BIT,
1024 OV02K10_GROUP_UPDATE_END_DATA);
1025 ret |= ov02k10_write_reg(client,
1026 OV02K10_GROUP_UPDATE_ADDRESS,
1027 OV02K10_REG_VALUE_08BIT,
1028 OV02K10_GROUP_UPDATE_LAUNCH);
1029 }
1030 mutex_unlock(&ov02k10->mutex);
1031 dev_dbg(&client->dev, "set conversion gain %d, (reg,val)=(0x%x,0x%x)\n",
1032 cur_cg, OV02K10_REG_HCG_SWITCH, val);
1033 return ret;
1034 }
1035
1036 #ifdef USED_SYS_DEBUG
1037 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1038 static ssize_t set_conversion_gain_status(struct device *dev,
1039 struct device_attribute *attr,
1040 const char *buf,
1041 size_t count)
1042 {
1043 struct i2c_client *client = to_i2c_client(dev);
1044 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1045 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1046 int status = 0;
1047 int ret = 0;
1048
1049 ret = kstrtoint(buf, 0, &status);
1050 if (!ret && status >= 0 && status < 2)
1051 ov02k10_set_conversion_gain(ov02k10, &status);
1052 else
1053 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
1054 return count;
1055 }
1056
1057 static struct device_attribute attributes[] = {
1058 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
1059 };
1060
add_sysfs_interfaces(struct device * dev)1061 static int add_sysfs_interfaces(struct device *dev)
1062 {
1063 int i;
1064
1065 for (i = 0; i < ARRAY_SIZE(attributes); i++)
1066 if (device_create_file(dev, attributes + i))
1067 goto undo;
1068 return 0;
1069 undo:
1070 for (i--; i >= 0 ; i--)
1071 device_remove_file(dev, attributes + i);
1072 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
1073 return -ENODEV;
1074 }
1075 #endif
1076
ov02k10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1077 static long ov02k10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1078 {
1079 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1080 struct rkmodule_hdr_cfg *hdr_cfg;
1081 long ret = 0;
1082 u32 i, h, w;
1083 u64 dst_link_freq = 0;
1084 u64 dst_pixel_rate = 0;
1085 u32 stream = 0;
1086
1087 switch (cmd) {
1088 case PREISP_CMD_SET_HDRAE_EXP:
1089 return ov02k10_set_hdrae(ov02k10, arg);
1090 case RKMODULE_SET_HDR_CFG:
1091 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1092 w = ov02k10->cur_mode->width;
1093 h = ov02k10->cur_mode->height;
1094 for (i = 0; i < ov02k10->cfg_num; i++) {
1095 if (w == supported_modes[i].width &&
1096 h == supported_modes[i].height &&
1097 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1098 ov02k10->cur_mode = &supported_modes[i];
1099 break;
1100 }
1101 }
1102 if (i == ov02k10->cfg_num) {
1103 dev_err(&ov02k10->client->dev,
1104 "not find hdr mode:%d %dx%d config\n",
1105 hdr_cfg->hdr_mode, w, h);
1106 ret = -EINVAL;
1107 } else {
1108 w = ov02k10->cur_mode->hts_def - ov02k10->cur_mode->width;
1109 h = ov02k10->cur_mode->vts_def - ov02k10->cur_mode->height;
1110 __v4l2_ctrl_modify_range(ov02k10->hblank, w, w, 1, w);
1111 __v4l2_ctrl_modify_range(ov02k10->vblank, h,
1112 OV02K10_VTS_MAX - ov02k10->cur_mode->height,
1113 1, h);
1114 if (ov02k10->cur_mode->hdr_mode == NO_HDR) {
1115 dst_link_freq = 0;
1116 dst_pixel_rate = PIXEL_RATE_WITH_360M;
1117 } else if (ov02k10->cur_mode->hdr_mode == HDR_X2) {
1118 dst_link_freq = 1;
1119 dst_pixel_rate = PIXEL_RATE_WITH_480M;
1120 }
1121
1122 __v4l2_ctrl_s_ctrl_int64(ov02k10->pixel_rate,
1123 dst_pixel_rate);
1124 __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
1125 dst_link_freq);
1126
1127 dev_info(&ov02k10->client->dev,
1128 "sensor mode: %d\n",
1129 ov02k10->cur_mode->hdr_mode);
1130 }
1131 break;
1132 case RKMODULE_GET_MODULE_INFO:
1133 ov02k10_get_module_inf(ov02k10, (struct rkmodule_inf *)arg);
1134 break;
1135 case RKMODULE_GET_HDR_CFG:
1136 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1137 hdr_cfg->esp.mode = HDR_NORMAL_VC;
1138 hdr_cfg->hdr_mode = ov02k10->cur_mode->hdr_mode;
1139 break;
1140 case RKMODULE_SET_CONVERSION_GAIN:
1141 ret = ov02k10_set_conversion_gain(ov02k10, (u32 *)arg);
1142 break;
1143 case RKMODULE_SET_QUICK_STREAM:
1144
1145 stream = *((u32 *)arg);
1146
1147 if (stream)
1148 ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
1149 OV02K10_REG_VALUE_08BIT, OV02K10_MODE_STREAMING);
1150 else
1151 ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
1152 OV02K10_REG_VALUE_08BIT, OV02K10_MODE_SW_STANDBY);
1153 break;
1154 default:
1155 ret = -ENOIOCTLCMD;
1156 break;
1157 }
1158
1159 return ret;
1160 }
1161
1162 #ifdef CONFIG_COMPAT
ov02k10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1163 static long ov02k10_compat_ioctl32(struct v4l2_subdev *sd,
1164 unsigned int cmd, unsigned long arg)
1165 {
1166 void __user *up = compat_ptr(arg);
1167 struct rkmodule_inf *inf;
1168 struct rkmodule_awb_cfg *cfg;
1169 struct rkmodule_hdr_cfg *hdr;
1170 struct preisp_hdrae_exp_s *hdrae;
1171 long ret;
1172 u32 cg = 0;
1173 u32 stream = 0;
1174
1175 switch (cmd) {
1176 case RKMODULE_GET_MODULE_INFO:
1177 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1178 if (!inf) {
1179 ret = -ENOMEM;
1180 return ret;
1181 }
1182
1183 ret = ov02k10_ioctl(sd, cmd, inf);
1184 if (!ret)
1185 ret = copy_to_user(up, inf, sizeof(*inf));
1186 kfree(inf);
1187 break;
1188 case RKMODULE_AWB_CFG:
1189 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1190 if (!cfg) {
1191 ret = -ENOMEM;
1192 return ret;
1193 }
1194
1195 ret = copy_from_user(cfg, up, sizeof(*cfg));
1196 if (!ret)
1197 ret = ov02k10_ioctl(sd, cmd, cfg);
1198 kfree(cfg);
1199 break;
1200 case RKMODULE_GET_HDR_CFG:
1201 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1202 if (!hdr) {
1203 ret = -ENOMEM;
1204 return ret;
1205 }
1206
1207 ret = ov02k10_ioctl(sd, cmd, hdr);
1208 if (!ret)
1209 ret = copy_to_user(up, hdr, sizeof(*hdr));
1210 kfree(hdr);
1211 break;
1212 case RKMODULE_SET_HDR_CFG:
1213 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1214 if (!hdr) {
1215 ret = -ENOMEM;
1216 return ret;
1217 }
1218
1219 ret = copy_from_user(hdr, up, sizeof(*hdr));
1220 if (!ret)
1221 ret = ov02k10_ioctl(sd, cmd, hdr);
1222 kfree(hdr);
1223 break;
1224 case PREISP_CMD_SET_HDRAE_EXP:
1225 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1226 if (!hdrae) {
1227 ret = -ENOMEM;
1228 return ret;
1229 }
1230
1231 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1232 if (!ret)
1233 ret = ov02k10_ioctl(sd, cmd, hdrae);
1234 kfree(hdrae);
1235 break;
1236 case RKMODULE_SET_CONVERSION_GAIN:
1237 ret = copy_from_user(&cg, up, sizeof(cg));
1238 if (!ret)
1239 ret = ov02k10_ioctl(sd, cmd, &cg);
1240 break;
1241 case RKMODULE_SET_QUICK_STREAM:
1242 ret = copy_from_user(&stream, up, sizeof(u32));
1243 if (!ret)
1244 ret = ov02k10_ioctl(sd, cmd, &stream);
1245 break;
1246 default:
1247 ret = -ENOIOCTLCMD;
1248 break;
1249 }
1250
1251 return ret;
1252 }
1253 #endif
1254
ov02k10_init_conversion_gain(struct ov02k10 * ov02k10)1255 static int ov02k10_init_conversion_gain(struct ov02k10 *ov02k10)
1256 {
1257 int ret = 0;
1258 struct i2c_client *client = ov02k10->client;
1259 u32 val = 0;
1260
1261 ret = ov02k10_read_reg(client,
1262 OV02K10_REG_HCG_SWITCH,
1263 OV02K10_REG_VALUE_08BIT,
1264 &val);
1265 val |= 0x70;
1266 ret |= ov02k10_write_reg(client,
1267 OV02K10_REG_HCG_SWITCH,
1268 OV02K10_REG_VALUE_08BIT,
1269 val);
1270 ov02k10->long_hcg = false;
1271 ov02k10->middle_hcg = false;
1272 ov02k10->short_hcg = false;
1273 return ret;
1274 }
1275
__ov02k10_start_stream(struct ov02k10 * ov02k10)1276 static int __ov02k10_start_stream(struct ov02k10 *ov02k10)
1277 {
1278 int ret;
1279
1280 ret = ov02k10_write_array(ov02k10->client, ov02k10_global_regs);
1281 if (ret) {
1282 dev_err(&ov02k10->client->dev,
1283 "could not set init registers\n");
1284 return ret;
1285 }
1286 ret = ov02k10_write_array(ov02k10->client, ov02k10->cur_mode->reg_list);
1287 if (ret)
1288 return ret;
1289 ret = ov02k10_init_conversion_gain(ov02k10);
1290 if (ret)
1291 return ret;
1292 /* In case these controls are set before streaming */
1293 ret = __v4l2_ctrl_handler_setup(&ov02k10->ctrl_handler);
1294 if (ret)
1295 return ret;
1296 if (ov02k10->has_init_exp && ov02k10->cur_mode->hdr_mode != NO_HDR) {
1297 ret = ov02k10_ioctl(&ov02k10->subdev,
1298 PREISP_CMD_SET_HDRAE_EXP,
1299 &ov02k10->init_hdrae_exp);
1300 if (ret) {
1301 dev_err(&ov02k10->client->dev,
1302 "init exp fail in hdr mode\n");
1303 return ret;
1304 }
1305 }
1306 return ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
1307 OV02K10_REG_VALUE_08BIT, OV02K10_MODE_STREAMING);
1308 }
1309
__ov02k10_stop_stream(struct ov02k10 * ov02k10)1310 static int __ov02k10_stop_stream(struct ov02k10 *ov02k10)
1311 {
1312 ov02k10->has_init_exp = false;
1313 return ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
1314 OV02K10_REG_VALUE_08BIT, OV02K10_MODE_SW_STANDBY);
1315 }
1316
ov02k10_s_stream(struct v4l2_subdev * sd,int on)1317 static int ov02k10_s_stream(struct v4l2_subdev *sd, int on)
1318 {
1319 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1320 struct i2c_client *client = ov02k10->client;
1321 int ret = 0;
1322
1323 mutex_lock(&ov02k10->mutex);
1324 on = !!on;
1325 if (on == ov02k10->streaming)
1326 goto unlock_and_return;
1327
1328 if (on) {
1329 ret = pm_runtime_get_sync(&client->dev);
1330 if (ret < 0) {
1331 pm_runtime_put_noidle(&client->dev);
1332 goto unlock_and_return;
1333 }
1334
1335 ret = __ov02k10_start_stream(ov02k10);
1336 if (ret) {
1337 v4l2_err(sd, "start stream failed while write regs\n");
1338 pm_runtime_put(&client->dev);
1339 goto unlock_and_return;
1340 }
1341 } else {
1342 __ov02k10_stop_stream(ov02k10);
1343 pm_runtime_put(&client->dev);
1344 }
1345
1346 ov02k10->streaming = on;
1347
1348 unlock_and_return:
1349 mutex_unlock(&ov02k10->mutex);
1350
1351 return ret;
1352 }
1353
ov02k10_s_power(struct v4l2_subdev * sd,int on)1354 static int ov02k10_s_power(struct v4l2_subdev *sd, int on)
1355 {
1356 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1357 struct i2c_client *client = ov02k10->client;
1358 int ret = 0;
1359
1360 mutex_lock(&ov02k10->mutex);
1361
1362 /* If the power state is not modified - no work to do. */
1363 if (ov02k10->power_on == !!on)
1364 goto unlock_and_return;
1365
1366 if (on) {
1367 ret = pm_runtime_get_sync(&client->dev);
1368 if (ret < 0) {
1369 pm_runtime_put_noidle(&client->dev);
1370 goto unlock_and_return;
1371 }
1372
1373 ret |= ov02k10_write_reg(ov02k10->client,
1374 OV02K10_SOFTWARE_RESET_REG,
1375 OV02K10_REG_VALUE_08BIT,
1376 0x01);
1377 usleep_range(100, 200);
1378
1379 ov02k10->power_on = true;
1380 } else {
1381 pm_runtime_put(&client->dev);
1382 ov02k10->power_on = false;
1383 }
1384
1385 unlock_and_return:
1386 mutex_unlock(&ov02k10->mutex);
1387
1388 return ret;
1389 }
1390
1391 /* Calculate the delay in us by clock rate and clock cycles */
ov02k10_cal_delay(u32 cycles)1392 static inline u32 ov02k10_cal_delay(u32 cycles)
1393 {
1394 return DIV_ROUND_UP(cycles, OV02K10_XVCLK_FREQ / 1000 / 1000);
1395 }
1396
__ov02k10_power_on(struct ov02k10 * ov02k10)1397 static int __ov02k10_power_on(struct ov02k10 *ov02k10)
1398 {
1399 int ret;
1400 u32 delay_us;
1401 struct device *dev = &ov02k10->client->dev;
1402
1403 if (!IS_ERR_OR_NULL(ov02k10->pins_default)) {
1404 ret = pinctrl_select_state(ov02k10->pinctrl,
1405 ov02k10->pins_default);
1406 if (ret < 0)
1407 dev_err(dev, "could not set pins\n");
1408 }
1409 ret = clk_set_rate(ov02k10->xvclk, OV02K10_XVCLK_FREQ);
1410 if (ret < 0)
1411 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1412 if (clk_get_rate(ov02k10->xvclk) != OV02K10_XVCLK_FREQ)
1413 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1414 ret = clk_prepare_enable(ov02k10->xvclk);
1415 if (ret < 0) {
1416 dev_err(dev, "Failed to enable xvclk\n");
1417 return ret;
1418 }
1419 if (!IS_ERR(ov02k10->reset_gpio))
1420 gpiod_set_value_cansleep(ov02k10->reset_gpio, 0);
1421
1422 if (!IS_ERR(ov02k10->power_gpio)) {
1423 gpiod_set_value_cansleep(ov02k10->power_gpio, 1);
1424 usleep_range(5000, 5100);
1425 }
1426
1427 ret = regulator_bulk_enable(OV02K10_NUM_SUPPLIES, ov02k10->supplies);
1428 if (ret < 0) {
1429 dev_err(dev, "Failed to enable regulators\n");
1430 goto disable_clk;
1431 }
1432
1433 if (!IS_ERR(ov02k10->reset_gpio))
1434 gpiod_set_value_cansleep(ov02k10->reset_gpio, 1);
1435
1436 usleep_range(500, 1000);
1437 if (!IS_ERR(ov02k10->pwdn_gpio))
1438 gpiod_set_value_cansleep(ov02k10->pwdn_gpio, 1);
1439 usleep_range(12000, 16000);
1440 /* 8192 cycles prior to first SCCB transaction */
1441 delay_us = ov02k10_cal_delay(8192);
1442 usleep_range(delay_us, delay_us * 2);
1443
1444 return 0;
1445
1446 disable_clk:
1447 clk_disable_unprepare(ov02k10->xvclk);
1448
1449 return ret;
1450 }
1451
__ov02k10_power_off(struct ov02k10 * ov02k10)1452 static void __ov02k10_power_off(struct ov02k10 *ov02k10)
1453 {
1454 int ret;
1455 struct device *dev = &ov02k10->client->dev;
1456
1457 if (!IS_ERR(ov02k10->pwdn_gpio))
1458 gpiod_set_value_cansleep(ov02k10->pwdn_gpio, 0);
1459 clk_disable_unprepare(ov02k10->xvclk);
1460 if (!IS_ERR(ov02k10->reset_gpio))
1461 gpiod_set_value_cansleep(ov02k10->reset_gpio, 0);
1462 if (!IS_ERR_OR_NULL(ov02k10->pins_sleep)) {
1463 ret = pinctrl_select_state(ov02k10->pinctrl,
1464 ov02k10->pins_sleep);
1465 if (ret < 0)
1466 dev_dbg(dev, "could not set pins\n");
1467 }
1468 regulator_bulk_disable(OV02K10_NUM_SUPPLIES, ov02k10->supplies);
1469 }
1470
ov02k10_runtime_resume(struct device * dev)1471 static int ov02k10_runtime_resume(struct device *dev)
1472 {
1473 struct i2c_client *client = to_i2c_client(dev);
1474 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1475 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1476
1477 return __ov02k10_power_on(ov02k10);
1478 }
1479
ov02k10_runtime_suspend(struct device * dev)1480 static int ov02k10_runtime_suspend(struct device *dev)
1481 {
1482 struct i2c_client *client = to_i2c_client(dev);
1483 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1484 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1485
1486 __ov02k10_power_off(ov02k10);
1487
1488 return 0;
1489 }
1490
1491 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov02k10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1492 static int ov02k10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1493 {
1494 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1495 struct v4l2_mbus_framefmt *try_fmt =
1496 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1497 const struct ov02k10_mode *def_mode = &supported_modes[0];
1498
1499 mutex_lock(&ov02k10->mutex);
1500 /* Initialize try_fmt */
1501 try_fmt->width = def_mode->width;
1502 try_fmt->height = def_mode->height;
1503 try_fmt->code = def_mode->bus_fmt;
1504 try_fmt->field = V4L2_FIELD_NONE;
1505
1506 mutex_unlock(&ov02k10->mutex);
1507 /* No crop or compose */
1508
1509 return 0;
1510 }
1511 #endif
1512
ov02k10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1513 static int ov02k10_enum_frame_interval(struct v4l2_subdev *sd,
1514 struct v4l2_subdev_pad_config *cfg,
1515 struct v4l2_subdev_frame_interval_enum *fie)
1516 {
1517 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1518
1519 if (fie->index >= ov02k10->cfg_num)
1520 return -EINVAL;
1521
1522 fie->code = supported_modes[fie->index].bus_fmt;
1523 fie->width = supported_modes[fie->index].width;
1524 fie->height = supported_modes[fie->index].height;
1525 fie->interval = supported_modes[fie->index].max_fps;
1526 return 0;
1527 }
1528
ov02k10_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1529 static int ov02k10_get_selection(struct v4l2_subdev *sd,
1530 struct v4l2_subdev_pad_config *cfg,
1531 struct v4l2_subdev_selection *sel)
1532 {
1533
1534 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1535 sel->r.left = 0;
1536 sel->r.width = 1920;
1537 sel->r.top = 0;
1538 sel->r.height = 1080;
1539 return 0;
1540 }
1541 return -EINVAL;
1542 }
1543
1544 static const struct dev_pm_ops ov02k10_pm_ops = {
1545 SET_RUNTIME_PM_OPS(ov02k10_runtime_suspend,
1546 ov02k10_runtime_resume, NULL)
1547 };
1548
1549 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1550 static const struct v4l2_subdev_internal_ops ov02k10_internal_ops = {
1551 .open = ov02k10_open,
1552 };
1553 #endif
1554
1555 static const struct v4l2_subdev_core_ops ov02k10_core_ops = {
1556 .s_power = ov02k10_s_power,
1557 .ioctl = ov02k10_ioctl,
1558 #ifdef CONFIG_COMPAT
1559 .compat_ioctl32 = ov02k10_compat_ioctl32,
1560 #endif
1561 };
1562
1563 static const struct v4l2_subdev_video_ops ov02k10_video_ops = {
1564 .s_stream = ov02k10_s_stream,
1565 .g_frame_interval = ov02k10_g_frame_interval,
1566 };
1567
1568 static const struct v4l2_subdev_pad_ops ov02k10_pad_ops = {
1569 .enum_mbus_code = ov02k10_enum_mbus_code,
1570 .enum_frame_size = ov02k10_enum_frame_sizes,
1571 .enum_frame_interval = ov02k10_enum_frame_interval,
1572 .get_fmt = ov02k10_get_fmt,
1573 .set_fmt = ov02k10_set_fmt,
1574 .get_selection = ov02k10_get_selection,
1575 .get_mbus_config = ov02k10_g_mbus_config,
1576 };
1577
1578 static const struct v4l2_subdev_ops ov02k10_subdev_ops = {
1579 .core = &ov02k10_core_ops,
1580 .video = &ov02k10_video_ops,
1581 .pad = &ov02k10_pad_ops,
1582 };
1583
ov02k10_set_ctrl(struct v4l2_ctrl * ctrl)1584 static int ov02k10_set_ctrl(struct v4l2_ctrl *ctrl)
1585 {
1586 struct ov02k10 *ov02k10 = container_of(ctrl->handler,
1587 struct ov02k10, ctrl_handler);
1588 struct i2c_client *client = ov02k10->client;
1589 s64 max;
1590 int ret = 0;
1591 u32 again, dgain;
1592 u32 val = 0;
1593
1594 /* Propagate change of current control to all related controls */
1595 switch (ctrl->id) {
1596 case V4L2_CID_VBLANK:
1597 /* Update max exposure while meeting expected vblanking */
1598 max = ov02k10->cur_mode->height + ctrl->val - 8;
1599 __v4l2_ctrl_modify_range(ov02k10->exposure,
1600 ov02k10->exposure->minimum, max,
1601 ov02k10->exposure->step,
1602 ov02k10->exposure->default_value);
1603 break;
1604 }
1605
1606 if (!pm_runtime_get_if_in_use(&client->dev))
1607 return 0;
1608
1609 switch (ctrl->id) {
1610 case V4L2_CID_EXPOSURE:
1611 ret = ov02k10_write_reg(ov02k10->client,
1612 OV02K10_REG_EXP_LONG_H,
1613 OV02K10_REG_VALUE_16BIT,
1614 ctrl->val);
1615 dev_dbg(&client->dev, "set exposure 0x%x\n",
1616 ctrl->val);
1617 break;
1618 case V4L2_CID_ANALOGUE_GAIN:
1619 if (ctrl->val > 248) {
1620 dgain = ctrl->val * 1024 / 248;
1621 again = 248;
1622 } else {
1623 dgain = 1024;
1624 again = ctrl->val;
1625 }
1626 ret = ov02k10_write_reg(ov02k10->client,
1627 OV02K10_REG_AGAIN_LONG_H,
1628 OV02K10_REG_VALUE_16BIT,
1629 (again << 4) & 0xff0);
1630 ret |= ov02k10_write_reg(ov02k10->client,
1631 OV02K10_REG_DGAIN_LONG_H,
1632 OV02K10_REG_VALUE_24BIT,
1633 (dgain << 6) & 0xfffc0);
1634 dev_dbg(&client->dev, "set analog gain 0x%x\n",
1635 ctrl->val);
1636 break;
1637 case V4L2_CID_VBLANK:
1638 ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_VTS,
1639 OV02K10_REG_VALUE_16BIT,
1640 ctrl->val + ov02k10->cur_mode->height);
1641 dev_dbg(&client->dev, "set vblank 0x%x\n",
1642 ctrl->val);
1643 break;
1644 case V4L2_CID_TEST_PATTERN:
1645 ret = ov02k10_enable_test_pattern(ov02k10, ctrl->val);
1646 dev_dbg(&client->dev, "set test pattern 0x%x\n",
1647 ctrl->val);
1648 break;
1649 case V4L2_CID_HFLIP:
1650 ret = ov02k10_read_reg(ov02k10->client, OV02K10_FLIP_REG,
1651 OV02K10_REG_VALUE_08BIT,
1652 &val);
1653 if (ctrl->val)
1654 val |= MIRROR_BIT_MASK;
1655 else
1656 val &= ~MIRROR_BIT_MASK;
1657 ret = ov02k10_write_reg(ov02k10->client, OV02K10_FLIP_REG,
1658 OV02K10_REG_VALUE_08BIT,
1659 val);
1660 if (ret == 0)
1661 ov02k10->flip = val;
1662 dev_dbg(&client->dev, "set hflip 0x%x\n",
1663 ctrl->val);
1664 break;
1665 case V4L2_CID_VFLIP:
1666 ret = ov02k10_read_reg(ov02k10->client, OV02K10_FLIP_REG,
1667 OV02K10_REG_VALUE_08BIT,
1668 &val);
1669 if (ctrl->val)
1670 val |= FLIP_BIT_MASK;
1671 else
1672 val &= ~FLIP_BIT_MASK;
1673 ret = ov02k10_write_reg(ov02k10->client, OV02K10_FLIP_REG,
1674 OV02K10_REG_VALUE_08BIT,
1675 val);
1676 if (ret == 0)
1677 ov02k10->flip = val;
1678 dev_dbg(&client->dev, "set vflip 0x%x\n",
1679 ctrl->val);
1680 break;
1681 default:
1682 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1683 __func__, ctrl->id, ctrl->val);
1684 break;
1685 }
1686
1687 pm_runtime_put(&client->dev);
1688
1689 return ret;
1690 }
1691
1692 static const struct v4l2_ctrl_ops ov02k10_ctrl_ops = {
1693 .s_ctrl = ov02k10_set_ctrl,
1694 };
1695
ov02k10_initialize_controls(struct ov02k10 * ov02k10)1696 static int ov02k10_initialize_controls(struct ov02k10 *ov02k10)
1697 {
1698 const struct ov02k10_mode *mode;
1699 struct v4l2_ctrl_handler *handler;
1700 s64 exposure_max, vblank_def;
1701 u32 h_blank;
1702 int ret;
1703 u64 dst_link_freq = 0;
1704 u64 dst_pixel_rate = 0;
1705
1706 handler = &ov02k10->ctrl_handler;
1707 mode = ov02k10->cur_mode;
1708 ret = v4l2_ctrl_handler_init(handler, 9);
1709 if (ret)
1710 return ret;
1711 handler->lock = &ov02k10->mutex;
1712
1713 ov02k10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1714 V4L2_CID_LINK_FREQ,
1715 1, 0, link_freq_menu_items);
1716
1717 if (ov02k10->cur_mode->hdr_mode == NO_HDR) {
1718 dst_link_freq = 0;
1719 dst_pixel_rate = PIXEL_RATE_WITH_360M;
1720 } else {
1721 dst_link_freq = 1;
1722 dst_pixel_rate = PIXEL_RATE_WITH_480M;
1723 }
1724 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1725 ov02k10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1726 V4L2_CID_PIXEL_RATE,
1727 0, PIXEL_RATE_WITH_480M,
1728 1, dst_pixel_rate);
1729
1730 __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
1731 dst_link_freq);
1732
1733 h_blank = mode->hts_def - mode->width;
1734 ov02k10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1735 h_blank, h_blank, 1, h_blank);
1736 if (ov02k10->hblank)
1737 ov02k10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1738
1739 vblank_def = mode->vts_def - mode->height;
1740 ov02k10->vblank = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
1741 V4L2_CID_VBLANK, vblank_def,
1742 OV02K10_VTS_MAX - mode->height,
1743 1, vblank_def);
1744
1745 exposure_max = mode->vts_def - 8;
1746 ov02k10->exposure = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
1747 V4L2_CID_EXPOSURE, OV02K10_EXPOSURE_MIN,
1748 exposure_max, OV02K10_EXPOSURE_STEP,
1749 mode->exp_def);
1750
1751 ov02k10->anal_gain = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
1752 V4L2_CID_ANALOGUE_GAIN, OV02K10_GAIN_MIN,
1753 OV02K10_GAIN_MAX, OV02K10_GAIN_STEP,
1754 OV02K10_GAIN_DEFAULT);
1755
1756 ov02k10->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1757 &ov02k10_ctrl_ops, V4L2_CID_TEST_PATTERN,
1758 ARRAY_SIZE(ov02k10_test_pattern_menu) - 1,
1759 0, 0, ov02k10_test_pattern_menu);
1760 ov02k10->h_flip = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
1761 V4L2_CID_HFLIP, 0, 1, 1, 0);
1762
1763 ov02k10->v_flip = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
1764 V4L2_CID_VFLIP, 0, 1, 1, 0);
1765 ov02k10->flip = 0;
1766 if (handler->error) {
1767 ret = handler->error;
1768 dev_err(&ov02k10->client->dev,
1769 "Failed to init controls(%d)\n", ret);
1770 goto err_free_handler;
1771 }
1772
1773 ov02k10->subdev.ctrl_handler = handler;
1774 ov02k10->has_init_exp = false;
1775 ov02k10->long_hcg = false;
1776 ov02k10->middle_hcg = false;
1777 ov02k10->short_hcg = false;
1778
1779 return 0;
1780
1781 err_free_handler:
1782 v4l2_ctrl_handler_free(handler);
1783
1784 return ret;
1785 }
1786
ov02k10_check_sensor_id(struct ov02k10 * ov02k10,struct i2c_client * client)1787 static int ov02k10_check_sensor_id(struct ov02k10 *ov02k10,
1788 struct i2c_client *client)
1789 {
1790 struct device *dev = &ov02k10->client->dev;
1791 u32 id = 0;
1792 int ret;
1793
1794 ret = ov02k10_read_reg(client, OV02K10_REG_CHIP_ID,
1795 OV02K10_REG_VALUE_24BIT, &id);
1796
1797 if (id != CHIP_ID) {
1798 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1799 return -ENODEV;
1800 }
1801
1802 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1803
1804 return 0;
1805 }
1806
ov02k10_configure_regulators(struct ov02k10 * ov02k10)1807 static int ov02k10_configure_regulators(struct ov02k10 *ov02k10)
1808 {
1809 unsigned int i;
1810
1811 for (i = 0; i < OV02K10_NUM_SUPPLIES; i++)
1812 ov02k10->supplies[i].supply = ov02k10_supply_names[i];
1813
1814 return devm_regulator_bulk_get(&ov02k10->client->dev,
1815 OV02K10_NUM_SUPPLIES,
1816 ov02k10->supplies);
1817 }
1818
ov02k10_probe(struct i2c_client * client,const struct i2c_device_id * id)1819 static int ov02k10_probe(struct i2c_client *client,
1820 const struct i2c_device_id *id)
1821 {
1822 struct device *dev = &client->dev;
1823 struct device_node *node = dev->of_node;
1824 struct ov02k10 *ov02k10;
1825 struct v4l2_subdev *sd;
1826 char facing[2];
1827 int ret;
1828 u32 i, hdr_mode = 0;
1829
1830 dev_info(dev, "driver version: %02x.%02x.%02x",
1831 DRIVER_VERSION >> 16,
1832 (DRIVER_VERSION & 0xff00) >> 8,
1833 DRIVER_VERSION & 0x00ff);
1834
1835 ov02k10 = devm_kzalloc(dev, sizeof(*ov02k10), GFP_KERNEL);
1836 if (!ov02k10)
1837 return -ENOMEM;
1838
1839 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1840 &ov02k10->module_index);
1841 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1842 &ov02k10->module_facing);
1843 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1844 &ov02k10->module_name);
1845 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1846 &ov02k10->len_name);
1847 if (ret) {
1848 dev_err(dev, "could not get module information!\n");
1849 return -EINVAL;
1850 }
1851
1852 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
1853 &hdr_mode);
1854 if (ret) {
1855 hdr_mode = NO_HDR;
1856 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1857 }
1858
1859 ov02k10->cfg_num = ARRAY_SIZE(supported_modes);
1860 for (i = 0; i < ov02k10->cfg_num; i++) {
1861 if (hdr_mode == supported_modes[i].hdr_mode) {
1862 ov02k10->cur_mode = &supported_modes[i];
1863 break;
1864 }
1865 }
1866 ov02k10->client = client;
1867
1868 ov02k10->xvclk = devm_clk_get(dev, "xvclk");
1869 if (IS_ERR(ov02k10->xvclk)) {
1870 dev_err(dev, "Failed to get xvclk\n");
1871 return -EINVAL;
1872 }
1873
1874 ov02k10->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1875 if (IS_ERR(ov02k10->power_gpio))
1876 dev_warn(dev, "Failed to get power-gpios\n");
1877
1878 ov02k10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1879 if (IS_ERR(ov02k10->reset_gpio))
1880 dev_warn(dev, "Failed to get reset-gpios\n");
1881
1882 ov02k10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1883 if (IS_ERR(ov02k10->pwdn_gpio))
1884 dev_warn(dev, "Failed to get pwdn-gpios\n");
1885
1886 ov02k10->pinctrl = devm_pinctrl_get(dev);
1887 if (!IS_ERR(ov02k10->pinctrl)) {
1888 ov02k10->pins_default =
1889 pinctrl_lookup_state(ov02k10->pinctrl,
1890 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1891 if (IS_ERR(ov02k10->pins_default))
1892 dev_err(dev, "could not get default pinstate\n");
1893
1894 ov02k10->pins_sleep =
1895 pinctrl_lookup_state(ov02k10->pinctrl,
1896 OF_CAMERA_PINCTRL_STATE_SLEEP);
1897 if (IS_ERR(ov02k10->pins_sleep))
1898 dev_err(dev, "could not get sleep pinstate\n");
1899 } else {
1900 dev_err(dev, "no pinctrl\n");
1901 }
1902
1903 ret = ov02k10_configure_regulators(ov02k10);
1904 if (ret) {
1905 dev_err(dev, "Failed to get power regulators\n");
1906 return ret;
1907 }
1908
1909 mutex_init(&ov02k10->mutex);
1910
1911 sd = &ov02k10->subdev;
1912 v4l2_i2c_subdev_init(sd, client, &ov02k10_subdev_ops);
1913 ret = ov02k10_initialize_controls(ov02k10);
1914 if (ret)
1915 goto err_destroy_mutex;
1916
1917 ret = __ov02k10_power_on(ov02k10);
1918 if (ret)
1919 goto err_free_handler;
1920
1921 ret = ov02k10_check_sensor_id(ov02k10, client);
1922 if (ret)
1923 goto err_power_off;
1924
1925 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1926 sd->internal_ops = &ov02k10_internal_ops;
1927 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1928 #endif
1929 #if defined(CONFIG_MEDIA_CONTROLLER)
1930 ov02k10->pad.flags = MEDIA_PAD_FL_SOURCE;
1931 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1932 ret = media_entity_pads_init(&sd->entity, 1, &ov02k10->pad);
1933 if (ret < 0)
1934 goto err_power_off;
1935 #endif
1936
1937 memset(facing, 0, sizeof(facing));
1938 if (strcmp(ov02k10->module_facing, "back") == 0)
1939 facing[0] = 'b';
1940 else
1941 facing[0] = 'f';
1942
1943 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1944 ov02k10->module_index, facing,
1945 OV02K10_NAME, dev_name(sd->dev));
1946 ret = v4l2_async_register_subdev_sensor_common(sd);
1947 if (ret) {
1948 dev_err(dev, "v4l2 async register subdev failed\n");
1949 goto err_clean_entity;
1950 }
1951
1952 pm_runtime_set_active(dev);
1953 pm_runtime_enable(dev);
1954 pm_runtime_idle(dev);
1955 #ifdef USED_SYS_DEBUG
1956 add_sysfs_interfaces(dev);
1957 #endif
1958 return 0;
1959
1960 err_clean_entity:
1961 #if defined(CONFIG_MEDIA_CONTROLLER)
1962 media_entity_cleanup(&sd->entity);
1963 #endif
1964 err_power_off:
1965 __ov02k10_power_off(ov02k10);
1966 err_free_handler:
1967 v4l2_ctrl_handler_free(&ov02k10->ctrl_handler);
1968 err_destroy_mutex:
1969 mutex_destroy(&ov02k10->mutex);
1970
1971 return ret;
1972 }
1973
ov02k10_remove(struct i2c_client * client)1974 static int ov02k10_remove(struct i2c_client *client)
1975 {
1976 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1977 struct ov02k10 *ov02k10 = to_ov02k10(sd);
1978
1979 v4l2_async_unregister_subdev(sd);
1980 #if defined(CONFIG_MEDIA_CONTROLLER)
1981 media_entity_cleanup(&sd->entity);
1982 #endif
1983 v4l2_ctrl_handler_free(&ov02k10->ctrl_handler);
1984 mutex_destroy(&ov02k10->mutex);
1985
1986 pm_runtime_disable(&client->dev);
1987 if (!pm_runtime_status_suspended(&client->dev))
1988 __ov02k10_power_off(ov02k10);
1989 pm_runtime_set_suspended(&client->dev);
1990
1991 return 0;
1992 }
1993
1994 #if IS_ENABLED(CONFIG_OF)
1995 static const struct of_device_id ov02k10_of_match[] = {
1996 { .compatible = "ovti,ov02k10" },
1997 {},
1998 };
1999 MODULE_DEVICE_TABLE(of, ov02k10_of_match);
2000 #endif
2001
2002 static const struct i2c_device_id ov02k10_match_id[] = {
2003 { "ovti,ov02k10", 0 },
2004 { },
2005 };
2006
2007 static struct i2c_driver ov02k10_i2c_driver = {
2008 .driver = {
2009 .name = OV02K10_NAME,
2010 .pm = &ov02k10_pm_ops,
2011 .of_match_table = of_match_ptr(ov02k10_of_match),
2012 },
2013 .probe = &ov02k10_probe,
2014 .remove = &ov02k10_remove,
2015 .id_table = ov02k10_match_id,
2016 };
2017
2018 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
2019 module_i2c_driver(ov02k10_i2c_driver);
2020 #else
sensor_mod_init(void)2021 static int __init sensor_mod_init(void)
2022 {
2023 return i2c_add_driver(&ov02k10_i2c_driver);
2024 }
2025
sensor_mod_exit(void)2026 static void __exit sensor_mod_exit(void)
2027 {
2028 i2c_del_driver(&ov02k10_i2c_driver);
2029 }
2030
2031 device_initcall_sync(sensor_mod_init);
2032 module_exit(sensor_mod_exit);
2033 #endif
2034
2035 MODULE_DESCRIPTION("OmniVision ov02k10 sensor driver");
2036 MODULE_LICENSE("GPL v2");
2037