1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov02b10 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 fix power on & off sequence
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/rk-preisp.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define MIPI_FREQ_360M 360000000
38 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4)
39
40 #define OV02B10_XVCLK_FREQ 24000000
41
42 #define OV02B10_CHIP_ID 0x2B
43 #define OV02B10_REG_CHIP_ID_H 0x02
44 #define OV02B10_REG_CHIP_ID_L 0x03
45
46 #define OV02B10_VTS_MAX 0xFFFF
47
48 #define OV02B10_GAIN_MIN 0x10
49 #define OV02B10_GAIN_MAX 0x3FF
50 #define OV02B10_GAIN_STEP 1
51 #define OV02B10_GAIN_DEFAULT 0x10
52
53 #define OV02B10_EXPOSURE_MIN 4
54 #define OV02B10_EXPOSURE_STEP 1
55
56 #define OV02B10_REG_PAGE_SELECT 0xFD
57
58 #define OV02B10_REG_EXP_H 0x0E
59 #define OV02B10_REG_EXP_L 0x0F
60
61 #define OV02B10_REG_AGAIN 0x22
62 #define OV02B10_REG_DGAIN 0x9B
63 #define OV02B10_REG_RESTART 0xFE
64
65 #define OV02B10_REG_HTS_H 0x25
66 #define OV02B10_REG_HTS_L 0x26
67 #define OV02B10_REG_VTS_H 0x27
68 #define OV02B10_REG_VTS_L 0x28
69 #define OV02B10_REG_VBLANK_H 0x14
70 #define OV02B10_REG_VBLANK_L 0x15
71
72 #define OV02B10_REG_CTRL_MODE 0xFB
73 #define OV02B10_MODE_SW_STANDBY 0x0
74 #define OV02B10_MODE_STREAMING BIT(0)
75
76 #define OV02B10_REG_SOFTWARE_RESET 0xFC
77 #define OV02B10_SOFTWARE_RESET_VAL 0x1
78
79 #define OV02B10_FLIP_REG 0x12
80 #define MIRROR_BIT_MASK BIT(0)
81 #define FLIP_BIT_MASK BIT(1)
82
83 #define OV02B10_LANES 1
84 #define OV02B10_NAME "ov02b10"
85
86 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
87 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
88 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
89
90 #define REG_NULL 0xFF
91
92 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
93
94 static const char * const OV02B10_supply_names[] = {
95 "dovdd", /* Digital I/O power */
96 "avdd", /* Analog power */
97 };
98
99 #define OV02B10_NUM_SUPPLIES ARRAY_SIZE(OV02B10_supply_names)
100
101 struct regval {
102 u8 addr;
103 u8 val;
104 };
105
106 struct ov02b10_mode {
107 u32 bus_fmt;
108 u32 width;
109 u32 height;
110 struct v4l2_fract max_fps;
111 u32 hts_def;
112 u32 vts_def;
113 u32 exp_def;
114 const struct regval *reg_list;
115 u32 hdr_mode;
116 u32 vc[PAD_MAX];
117 };
118
119 struct ov02b10 {
120 struct i2c_client *client;
121 struct clk *xvclk;
122 struct gpio_desc *reset_gpio;
123 struct gpio_desc *pwdn_gpio;
124 struct regulator_bulk_data supplies[OV02B10_NUM_SUPPLIES];
125
126 struct pinctrl *pinctrl;
127 struct pinctrl_state *pins_default;
128 struct pinctrl_state *pins_sleep;
129
130 struct v4l2_subdev subdev;
131 struct media_pad pad;
132 struct v4l2_ctrl_handler ctrl_handler;
133 struct v4l2_ctrl *exposure;
134 struct v4l2_ctrl *anal_gain;
135 struct v4l2_ctrl *digi_gain;
136 struct v4l2_ctrl *hblank;
137 struct v4l2_ctrl *vblank;
138 struct v4l2_ctrl *pixel_rate;
139 struct v4l2_ctrl *link_freq;
140 struct v4l2_ctrl *h_flip;
141 struct v4l2_ctrl *v_flip;
142 struct mutex mutex;
143 bool streaming;
144 bool power_on;
145 const struct ov02b10_mode *cur_mode;
146 u32 cfg_num;
147 u32 module_index;
148 const char *module_facing;
149 const char *module_name;
150 const char *len_name;
151 bool has_init_exp;
152 struct preisp_hdrae_exp_s init_hdrae_exp;
153 u8 flip;
154 };
155
156 #define to_ov02b10(sd) container_of(sd, struct ov02b10, subdev)
157
158 /*
159 * Xclk 24Mhz
160 */
161 static const struct regval ov02b10_linear10bit_1600x1200_regs[] = {
162 {0xfc, 0x01},
163 {0xfd, 0x00},
164 {0xfd, 0x00},
165 {0x24, 0x02},
166 {0x25, 0x06},
167 {0x29, 0x03},
168 {0x2a, 0x34},
169 {0x1e, 0x17},
170 {0x33, 0x07},
171 {0x35, 0x07},
172 {0x4a, 0x0c},
173 {0x3a, 0x05},
174 {0x3b, 0x02},
175 {0x3e, 0x00},
176 {0x46, 0x01},
177 {0x6d, 0x03},
178 {0xfd, 0x01},
179 {0x0e, 0x02},
180 {0x0f, 0x1a},
181 {0x18, 0x00},
182 {0x22, 0xff},
183 {0x23, 0x02},
184 {0x17, 0x2c},
185 {0x19, 0x20},
186 {0x1b, 0x06},
187 {0x1c, 0x04},
188 {0x20, 0x03},
189 {0x30, 0x01},
190 {0x33, 0x01},
191 {0x31, 0x0a},
192 {0x32, 0x09},
193 {0x38, 0x01},
194 {0x39, 0x01},
195 {0x3a, 0x01},
196 {0x3b, 0x01},
197 {0x4f, 0x04},
198 {0x4e, 0x05},
199 {0x50, 0x01},
200 {0x35, 0x0c},
201 {0x45, 0x2a},
202 {0x46, 0x2a},
203 {0x47, 0x2a},
204 {0x48, 0x2a},
205 {0x4a, 0x2c},
206 {0x4b, 0x2c},
207 {0x4c, 0x2c},
208 {0x4d, 0x2c},
209 {0x56, 0x3a},
210 {0x57, 0x0a},
211 {0x58, 0x24},
212 {0x59, 0x20},
213 {0x5a, 0x0a},
214 {0x5b, 0xff},
215 {0x37, 0x0a},
216 {0x42, 0x0e},
217 {0x68, 0x90},
218 {0x69, 0xcd},
219 {0x6a, 0x8f},
220 {0x7c, 0x0a},
221 {0x7d, 0x0a},
222 {0x7e, 0x0a},
223 {0x7f, 0x08},
224 {0x83, 0x14},
225 {0x84, 0x14},
226 {0x86, 0x14},
227 {0x87, 0x07},
228 {0x88, 0x0f},
229 {0x94, 0x02},
230 {0x98, 0xd1},
231 {0xfe, 0x02},
232 {0xfd, 0x03},
233 {0x97, 0x6c},
234 {0x98, 0x60},
235 {0x99, 0x60},
236 {0x9a, 0x6c},
237 {0xa1, 0x40},
238 {0xaf, 0x04},
239 {0xb1, 0x40},
240 {0xae, 0x0d},
241 {0x88, 0x5b},
242 {0x89, 0x7c},
243 {0xb4, 0x05},
244 {0x8c, 0x40},
245 {0x8e, 0x40},
246 {0x90, 0x40},
247 {0x92, 0x40},
248 {0x9b, 0x46},
249 {0xac, 0x40},
250 {0xfd, 0x00},
251 {0x5a, 0x15},
252 {0x74, 0x01},
253 {0xfd, 0x00},
254 {0x50, 0x40},
255 {0x52, 0xb0},
256 {0xfd, 0x01},
257 {0x03, 0x70},
258 {0x05, 0x10},
259 {0x07, 0x20},
260 {0x09, 0xb0},
261 {0xfd, 0x03},
262 {0xc2, 0x01},
263 {0xfb, 0x01},
264 {REG_NULL, 0x00},
265 };
266
267 /*
268 * The width and height must be configured to be
269 * the same as the current output resolution of the sensor.
270 * The input width of the isp needs to be 16 aligned.
271 * The input height of the isp needs to be 8 aligned.
272 * If the width or height does not meet the alignment rules,
273 * you can configure the cropping parameters with the following function to
274 * crop out the appropriate resolution.
275 * struct v4l2_subdev_pad_ops {
276 * .get_selection
277 * }
278 */
279 static const struct ov02b10_mode supported_modes[] = {
280 {
281 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
282 .width = 1600,
283 .height = 1200,
284 .max_fps = {
285 .numerator = 10000,
286 .denominator = 300000,
287 },
288 .exp_def = 0x02ea,
289 .hts_def = 0x06ac,
290 .vts_def = 0x04c4,
291 .reg_list = ov02b10_linear10bit_1600x1200_regs,
292 .hdr_mode = NO_HDR,
293 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
294 },
295 };
296
297 static const s64 link_freq_menu_items[] = {
298 MIPI_FREQ_360M,
299 };
300
301 static int __ov02b10_power_on(struct ov02b10 *ov02b10);
302
303 static int ov02b10_check_sensor_id(struct ov02b10 *ov02b10,
304 struct i2c_client *client);
305
306 /* sensor register write */
ov02b10_write_reg(struct i2c_client * client,u8 reg,u8 val)307 static int ov02b10_write_reg(struct i2c_client *client, u8 reg, u8 val)
308 {
309 struct i2c_msg msg;
310 u8 buf[2];
311 int ret;
312
313 buf[0] = reg & 0xFF;
314 buf[1] = val;
315
316 msg.addr = client->addr;
317 msg.flags = client->flags;
318 msg.buf = buf;
319 msg.len = sizeof(buf);
320
321 ret = i2c_transfer(client->adapter, &msg, 1);
322 if (ret >= 0)
323 return 0;
324
325 dev_err(&client->dev,
326 "ov02b10 write reg(0x%x val:0x%x) failed !\n", reg, val);
327
328 return ret;
329 }
330
ov02b10_write_array(struct i2c_client * client,const struct regval * regs)331 static int ov02b10_write_array(struct i2c_client *client,
332 const struct regval *regs)
333 {
334 int i, ret = 0;
335
336 i = 0;
337 while (regs[i].addr != REG_NULL) {
338 ret = ov02b10_write_reg(client, regs[i].addr, regs[i].val);
339 if (ret) {
340 dev_err(&client->dev, "%s failed !\n", __func__);
341 break;
342 }
343 i++;
344 }
345
346 return ret;
347 }
348
349 /* sensor register read */
ov02b10_read_reg(struct i2c_client * client,u8 reg,u8 * val)350 static int ov02b10_read_reg(struct i2c_client *client, u8 reg, u8 *val)
351 {
352 struct i2c_msg msg[2];
353 u8 buf[1];
354 int ret;
355
356 buf[0] = reg & 0xFF;
357
358 msg[0].addr = client->addr;
359 msg[0].flags = client->flags;
360 msg[0].buf = buf;
361 msg[0].len = sizeof(buf);
362
363 msg[1].addr = client->addr;
364 msg[1].flags = client->flags | I2C_M_RD;
365 msg[1].buf = buf;
366 msg[1].len = 1;
367
368 ret = i2c_transfer(client->adapter, msg, 2);
369 if (ret >= 0) {
370 *val = buf[0];
371 return 0;
372 }
373
374 dev_err(&client->dev,
375 "ov02b10 read reg(0x%x val:0x%x) failed !\n", reg, *val);
376
377 return ret;
378 }
379
ov02b10_get_reso_dist(const struct ov02b10_mode * mode,struct v4l2_mbus_framefmt * framefmt)380 static int ov02b10_get_reso_dist(const struct ov02b10_mode *mode,
381 struct v4l2_mbus_framefmt *framefmt)
382 {
383 return abs(mode->width - framefmt->width) +
384 abs(mode->height - framefmt->height);
385 }
386
387 static const struct ov02b10_mode *
ov02b10_find_best_fit(struct ov02b10 * ov02b10,struct v4l2_subdev_format * fmt)388 ov02b10_find_best_fit(struct ov02b10 *ov02b10, struct v4l2_subdev_format *fmt)
389 {
390 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
391 int dist;
392 int cur_best_fit = 0;
393 int cur_best_fit_dist = -1;
394 unsigned int i;
395
396 for (i = 0; i < ov02b10->cfg_num; i++) {
397 dist = ov02b10_get_reso_dist(&supported_modes[i], framefmt);
398 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
399 (supported_modes[i].bus_fmt == framefmt->code)) {
400 cur_best_fit_dist = dist;
401 cur_best_fit = i;
402 }
403 }
404
405 return &supported_modes[cur_best_fit];
406 }
407
ov02b10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)408 static int ov02b10_set_fmt(struct v4l2_subdev *sd,
409 struct v4l2_subdev_pad_config *cfg,
410 struct v4l2_subdev_format *fmt)
411 {
412 struct ov02b10 *ov02b10 = to_ov02b10(sd);
413 const struct ov02b10_mode *mode;
414 s64 h_blank, vblank_def;
415 u64 dst_link_freq = 0;
416 u64 dst_pixel_rate = 0;
417
418 mutex_lock(&ov02b10->mutex);
419
420 mode = ov02b10_find_best_fit(ov02b10, fmt);
421 fmt->format.code = mode->bus_fmt;
422 fmt->format.width = mode->width;
423 fmt->format.height = mode->height;
424 fmt->format.field = V4L2_FIELD_NONE;
425 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
426 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
427 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
428 #else
429 mutex_unlock(&ov02b10->mutex);
430 return -ENOTTY;
431 #endif
432 } else {
433 ov02b10->cur_mode = mode;
434 h_blank = mode->hts_def - mode->width;
435 __v4l2_ctrl_modify_range(ov02b10->hblank, h_blank,
436 h_blank, 1, h_blank);
437
438 /* From spec: vstart is 0xc by default */
439 vblank_def = mode->vts_def - mode->height - 0xc;
440 __v4l2_ctrl_modify_range(ov02b10->vblank, vblank_def,
441 OV02B10_VTS_MAX - mode->height,
442 1, vblank_def);
443 if (mode->hdr_mode == NO_HDR) {
444 if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
445 dst_link_freq = 0;
446 dst_pixel_rate = PIXEL_RATE_WITH_360M;
447 }
448 }
449 __v4l2_ctrl_s_ctrl_int64(ov02b10->pixel_rate,
450 dst_pixel_rate);
451 __v4l2_ctrl_s_ctrl(ov02b10->link_freq,
452 dst_link_freq);
453 }
454
455 mutex_unlock(&ov02b10->mutex);
456
457 return 0;
458 }
459
ov02b10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)460 static int ov02b10_get_fmt(struct v4l2_subdev *sd,
461 struct v4l2_subdev_pad_config *cfg,
462 struct v4l2_subdev_format *fmt)
463 {
464 struct ov02b10 *ov02b10 = to_ov02b10(sd);
465 const struct ov02b10_mode *mode = ov02b10->cur_mode;
466
467 mutex_lock(&ov02b10->mutex);
468 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
469 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
470 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
471 #else
472 mutex_unlock(&ov02b10->mutex);
473 return -ENOTTY;
474 #endif
475 } else {
476 fmt->format.width = mode->width;
477 fmt->format.height = mode->height;
478 fmt->format.code = mode->bus_fmt;
479 fmt->format.field = V4L2_FIELD_NONE;
480 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
481 fmt->reserved[0] = mode->vc[fmt->pad];
482 else
483 fmt->reserved[0] = mode->vc[PAD0];
484 }
485 mutex_unlock(&ov02b10->mutex);
486
487 return 0;
488 }
489
ov02b10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)490 static int ov02b10_enum_mbus_code(struct v4l2_subdev *sd,
491 struct v4l2_subdev_pad_config *cfg,
492 struct v4l2_subdev_mbus_code_enum *code)
493 {
494 struct ov02b10 *ov02b10 = to_ov02b10(sd);
495
496 if (code->index != 0)
497 return -EINVAL;
498 code->code = ov02b10->cur_mode->bus_fmt;
499
500 return 0;
501 }
502
ov02b10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)503 static int ov02b10_enum_frame_sizes(struct v4l2_subdev *sd,
504 struct v4l2_subdev_pad_config *cfg,
505 struct v4l2_subdev_frame_size_enum *fse)
506 {
507 struct ov02b10 *ov02b10 = to_ov02b10(sd);
508
509 if (fse->index >= ov02b10->cfg_num)
510 return -EINVAL;
511
512 if (fse->code != supported_modes[fse->index].bus_fmt)
513 return -EINVAL;
514
515 fse->min_width = supported_modes[fse->index].width;
516 fse->max_width = supported_modes[fse->index].width;
517 fse->max_height = supported_modes[fse->index].height;
518 fse->min_height = supported_modes[fse->index].height;
519
520 return 0;
521 }
522
ov02b10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)523 static int ov02b10_g_frame_interval(struct v4l2_subdev *sd,
524 struct v4l2_subdev_frame_interval *fi)
525 {
526 struct ov02b10 *ov02b10 = to_ov02b10(sd);
527 const struct ov02b10_mode *mode = ov02b10->cur_mode;
528
529 fi->interval = mode->max_fps;
530
531 return 0;
532 }
533
ov02b10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)534 static int ov02b10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
535 struct v4l2_mbus_config *config)
536 {
537 struct ov02b10 *ov02b10 = to_ov02b10(sd);
538 const struct ov02b10_mode *mode = ov02b10->cur_mode;
539 u32 val = 0;
540
541 if (mode->hdr_mode == NO_HDR)
542 val = 1 << (OV02B10_LANES - 1) |
543 V4L2_MBUS_CSI2_CHANNEL_0 |
544 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
545 if (mode->hdr_mode == HDR_X2)
546 val = 1 << (OV02B10_LANES - 1) |
547 V4L2_MBUS_CSI2_CHANNEL_0 |
548 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
549 V4L2_MBUS_CSI2_CHANNEL_1;
550
551 config->type = V4L2_MBUS_CSI2_DPHY;
552 config->flags = val;
553
554 return 0;
555 }
556
ov02b10_get_module_inf(struct ov02b10 * ov02b10,struct rkmodule_inf * inf)557 static void ov02b10_get_module_inf(struct ov02b10 *ov02b10,
558 struct rkmodule_inf *inf)
559 {
560 memset(inf, 0, sizeof(*inf));
561 strlcpy(inf->base.sensor, OV02B10_NAME, sizeof(inf->base.sensor));
562 strlcpy(inf->base.module, ov02b10->module_name,
563 sizeof(inf->base.module));
564 strlcpy(inf->base.lens, ov02b10->len_name, sizeof(inf->base.lens));
565 }
566
ov02b10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)567 static long ov02b10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
568 {
569 struct ov02b10 *ov02b10 = to_ov02b10(sd);
570 struct rkmodule_hdr_cfg *hdr_cfg;
571 long ret = 0;
572 u32 stream = 0;
573
574 switch (cmd) {
575 case PREISP_CMD_SET_HDRAE_EXP:
576 ret = -1;
577 break;
578 case RKMODULE_SET_HDR_CFG:
579 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
580 if (hdr_cfg->hdr_mode != 0)
581 ret = -1;
582 break;
583 case RKMODULE_GET_MODULE_INFO:
584 ov02b10_get_module_inf(ov02b10, (struct rkmodule_inf *)arg);
585 break;
586 case RKMODULE_GET_HDR_CFG:
587 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
588 hdr_cfg->esp.mode = HDR_NORMAL_VC;
589 hdr_cfg->hdr_mode = ov02b10->cur_mode->hdr_mode;
590 break;
591 case RKMODULE_SET_CONVERSION_GAIN:
592 break;
593 case RKMODULE_SET_QUICK_STREAM:
594 stream = *((u32 *)arg);
595 if (stream)
596 ret = ov02b10_write_reg(ov02b10->client, OV02B10_REG_CTRL_MODE,
597 OV02B10_MODE_STREAMING);
598 else
599 ret = ov02b10_write_reg(ov02b10->client, OV02B10_REG_CTRL_MODE,
600 OV02B10_MODE_SW_STANDBY);
601 break;
602 default:
603 ret = -ENOIOCTLCMD;
604 break;
605 }
606
607 return ret;
608 }
609
610 #ifdef CONFIG_COMPAT
ov02b10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)611 static long ov02b10_compat_ioctl32(struct v4l2_subdev *sd,
612 unsigned int cmd, unsigned long arg)
613 {
614 void __user *up = compat_ptr(arg);
615 struct rkmodule_inf *inf;
616 struct rkmodule_awb_cfg *cfg;
617 struct rkmodule_hdr_cfg *hdr;
618 struct preisp_hdrae_exp_s *hdrae;
619 long ret;
620 u32 cg = 0;
621 u32 stream = 0;
622
623 switch (cmd) {
624 case RKMODULE_GET_MODULE_INFO:
625 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
626 if (!inf) {
627 ret = -ENOMEM;
628 return ret;
629 }
630
631 ret = ov02b10_ioctl(sd, cmd, inf);
632 if (!ret) {
633 ret = copy_to_user(up, inf, sizeof(*inf));
634 if (ret)
635 ret = -EFAULT;
636 }
637 kfree(inf);
638 break;
639 case RKMODULE_AWB_CFG:
640 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
641 if (!cfg) {
642 ret = -ENOMEM;
643 return ret;
644 }
645
646 ret = copy_from_user(cfg, up, sizeof(*cfg));
647 if (!ret)
648 ret = ov02b10_ioctl(sd, cmd, cfg);
649 else
650 ret = -EFAULT;
651 kfree(cfg);
652 break;
653 case RKMODULE_GET_HDR_CFG:
654 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
655 if (!hdr) {
656 ret = -ENOMEM;
657 return ret;
658 }
659
660 ret = ov02b10_ioctl(sd, cmd, hdr);
661 if (!ret) {
662 ret = copy_to_user(up, hdr, sizeof(*hdr));
663 if (ret)
664 ret = -EFAULT;
665 }
666 kfree(hdr);
667 break;
668 case RKMODULE_SET_HDR_CFG:
669 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
670 if (!hdr) {
671 ret = -ENOMEM;
672 return ret;
673 }
674
675 ret = copy_from_user(hdr, up, sizeof(*hdr));
676 if (!ret)
677 ret = ov02b10_ioctl(sd, cmd, hdr);
678 else
679 ret = -EFAULT;
680 kfree(hdr);
681 break;
682 case PREISP_CMD_SET_HDRAE_EXP:
683 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
684 if (!hdrae) {
685 ret = -ENOMEM;
686 return ret;
687 }
688
689 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
690 if (!ret)
691 ret = ov02b10_ioctl(sd, cmd, hdrae);
692 else
693 ret = -EFAULT;
694 kfree(hdrae);
695 break;
696 case RKMODULE_SET_CONVERSION_GAIN:
697 ret = copy_from_user(&cg, up, sizeof(cg));
698 if (!ret)
699 ret = ov02b10_ioctl(sd, cmd, &cg);
700 else
701 ret = -EFAULT;
702 break;
703 case RKMODULE_SET_QUICK_STREAM:
704 ret = copy_from_user(&stream, up, sizeof(u32));
705 if (!ret)
706 ret = ov02b10_ioctl(sd, cmd, &stream);
707 else
708 ret = -EFAULT;
709 break;
710 default:
711 ret = -ENOIOCTLCMD;
712 break;
713 }
714
715 return ret;
716 }
717 #endif
718
__ov02b10_start_stream(struct ov02b10 * ov02b10)719 static int __ov02b10_start_stream(struct ov02b10 *ov02b10)
720 {
721 int ret;
722
723 ret = ov02b10_write_array(ov02b10->client, ov02b10->cur_mode->reg_list);
724 if (ret)
725 return ret;
726
727 /* In case these controls are set before streaming */
728 ret = __v4l2_ctrl_handler_setup(&ov02b10->ctrl_handler);
729 if (ret)
730 return ret;
731 if (ov02b10->has_init_exp && ov02b10->cur_mode->hdr_mode != NO_HDR) {
732 ret = ov02b10_ioctl(&ov02b10->subdev, PREISP_CMD_SET_HDRAE_EXP,
733 &ov02b10->init_hdrae_exp);
734 if (ret) {
735 dev_err(&ov02b10->client->dev,
736 "init exp fail in hdr mode\n");
737 return ret;
738 }
739 }
740 return ov02b10_write_reg(ov02b10->client, OV02B10_REG_CTRL_MODE, OV02B10_MODE_STREAMING);
741 }
742
__ov02b10_stop_stream(struct ov02b10 * ov02b10)743 static int __ov02b10_stop_stream(struct ov02b10 *ov02b10)
744 {
745 ov02b10->has_init_exp = false;
746 return ov02b10_write_reg(ov02b10->client, OV02B10_REG_CTRL_MODE, OV02B10_MODE_SW_STANDBY);
747 }
748
ov02b10_s_stream(struct v4l2_subdev * sd,int on)749 static int ov02b10_s_stream(struct v4l2_subdev *sd, int on)
750 {
751 struct ov02b10 *ov02b10 = to_ov02b10(sd);
752 struct i2c_client *client = ov02b10->client;
753 int ret = 0;
754
755 mutex_lock(&ov02b10->mutex);
756 on = !!on;
757 if (on == ov02b10->streaming)
758 goto unlock_and_return;
759
760 if (on) {
761 ret = pm_runtime_get_sync(&client->dev);
762 if (ret < 0) {
763 pm_runtime_put_noidle(&client->dev);
764 goto unlock_and_return;
765 }
766
767 ret = __ov02b10_start_stream(ov02b10);
768 if (ret) {
769 v4l2_err(sd, "start stream failed while write regs\n");
770 pm_runtime_put(&client->dev);
771 goto unlock_and_return;
772 }
773 } else {
774 __ov02b10_stop_stream(ov02b10);
775 pm_runtime_put(&client->dev);
776 }
777
778 ov02b10->streaming = on;
779
780 unlock_and_return:
781 mutex_unlock(&ov02b10->mutex);
782
783 return ret;
784 }
785
ov02b10_s_power(struct v4l2_subdev * sd,int on)786 static int ov02b10_s_power(struct v4l2_subdev *sd, int on)
787 {
788 struct ov02b10 *ov02b10 = to_ov02b10(sd);
789 struct i2c_client *client = ov02b10->client;
790 int ret = 0;
791
792 mutex_lock(&ov02b10->mutex);
793
794 /* If the power state is not modified - no work to do. */
795 if (ov02b10->power_on == !!on)
796 goto unlock_and_return;
797
798 if (on) {
799 ret = pm_runtime_get_sync(&client->dev);
800 if (ret < 0) {
801 pm_runtime_put_noidle(&client->dev);
802 goto unlock_and_return;
803 }
804
805 ret |= ov02b10_write_reg(ov02b10->client,
806 OV02B10_REG_SOFTWARE_RESET,
807 OV02B10_SOFTWARE_RESET_VAL);
808 usleep_range(100, 200);
809
810 ov02b10->power_on = true;
811 } else {
812 pm_runtime_put(&client->dev);
813 ov02b10->power_on = false;
814 }
815
816 unlock_and_return:
817 mutex_unlock(&ov02b10->mutex);
818
819 return ret;
820 }
821
ov02b10_enable_regulators(struct ov02b10 * ov02b10,struct regulator_bulk_data * consumers)822 static int ov02b10_enable_regulators(struct ov02b10 *ov02b10,
823 struct regulator_bulk_data *consumers)
824 {
825 int i, j;
826 int ret = 0;
827 struct device *dev = &ov02b10->client->dev;
828 int num_consumers = OV02B10_NUM_SUPPLIES;
829
830 for (i = 0; i < num_consumers; i++) {
831
832 ret = regulator_enable(consumers[i].consumer);
833 if (ret < 0) {
834 dev_err(dev, "Failed to enable regulator: %s\n",
835 consumers[i].supply);
836 goto err;
837 }
838 }
839 return 0;
840 err:
841 for (j = 0; j < i; j++)
842 regulator_disable(consumers[j].consumer);
843
844 return ret;
845 }
846
__ov02b10_power_on(struct ov02b10 * ov02b10)847 static int __ov02b10_power_on(struct ov02b10 *ov02b10)
848 {
849 int ret;
850 struct device *dev = &ov02b10->client->dev;
851
852 if (!IS_ERR_OR_NULL(ov02b10->pins_default)) {
853 ret = pinctrl_select_state(ov02b10->pinctrl,
854 ov02b10->pins_default);
855 if (ret < 0)
856 dev_err(dev, "could not set pins\n");
857 }
858 ret = clk_set_rate(ov02b10->xvclk, OV02B10_XVCLK_FREQ);
859 if (ret < 0)
860 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
861 if (clk_get_rate(ov02b10->xvclk) != OV02B10_XVCLK_FREQ)
862 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
863
864 if (!IS_ERR(ov02b10->pwdn_gpio))
865 gpiod_direction_output(ov02b10->pwdn_gpio, 1);
866
867 if (!IS_ERR(ov02b10->reset_gpio))
868 gpiod_direction_output(ov02b10->reset_gpio, 1);
869
870 ret = ov02b10_enable_regulators(ov02b10, ov02b10->supplies);
871 if (ret < 0) {
872 dev_err(dev, "Failed to enable regulators\n");
873 goto disable_clk;
874 }
875 usleep_range(100, 110);
876 ret = clk_prepare_enable(ov02b10->xvclk);
877 if (ret < 0) {
878 dev_err(dev, "Failed to enable xvclk\n");
879 return ret;
880 }
881
882 /* From spec: delay from power stable to pwdn off: 5ms */
883 usleep_range(5000, 6000);
884 if (!IS_ERR(ov02b10->pwdn_gpio))
885 gpiod_direction_output(ov02b10->pwdn_gpio, 0);
886
887 /* From spec: delay from pwdn off to reset off */
888 usleep_range(4000, 5000);
889 if (!IS_ERR(ov02b10->reset_gpio))
890 gpiod_direction_output(ov02b10->reset_gpio, 0);
891
892 /* From spec: 5ms for SCCB initialization */
893 usleep_range(5000, 6000);
894 return 0;
895
896 disable_clk:
897 clk_disable_unprepare(ov02b10->xvclk);
898
899 return ret;
900 }
901
__ov02b10_power_off(struct ov02b10 * ov02b10)902 static void __ov02b10_power_off(struct ov02b10 *ov02b10)
903 {
904 int ret;
905 struct device *dev = &ov02b10->client->dev;
906
907 if (!IS_ERR(ov02b10->reset_gpio))
908 gpiod_direction_output(ov02b10->reset_gpio, 1);
909
910 clk_disable_unprepare(ov02b10->xvclk);
911
912 if (!IS_ERR(ov02b10->pwdn_gpio))
913 gpiod_direction_output(ov02b10->pwdn_gpio, 1);
914
915 if (!IS_ERR_OR_NULL(ov02b10->pins_sleep)) {
916 ret = pinctrl_select_state(ov02b10->pinctrl,
917 ov02b10->pins_sleep);
918 if (ret < 0)
919 dev_dbg(dev, "could not set pins\n");
920 }
921 regulator_bulk_disable(OV02B10_NUM_SUPPLIES, ov02b10->supplies);
922 }
923
ov02b10_runtime_resume(struct device * dev)924 static int __maybe_unused ov02b10_runtime_resume(struct device *dev)
925 {
926 struct i2c_client *client = to_i2c_client(dev);
927 struct v4l2_subdev *sd = i2c_get_clientdata(client);
928 struct ov02b10 *ov02b10 = to_ov02b10(sd);
929
930 return __ov02b10_power_on(ov02b10);
931 }
932
ov02b10_runtime_suspend(struct device * dev)933 static int __maybe_unused ov02b10_runtime_suspend(struct device *dev)
934 {
935 struct i2c_client *client = to_i2c_client(dev);
936 struct v4l2_subdev *sd = i2c_get_clientdata(client);
937 struct ov02b10 *ov02b10 = to_ov02b10(sd);
938
939 __ov02b10_power_off(ov02b10);
940
941 return 0;
942 }
943
944 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov02b10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)945 static int ov02b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
946 {
947 struct ov02b10 *ov02b10 = to_ov02b10(sd);
948 struct v4l2_mbus_framefmt *try_fmt =
949 v4l2_subdev_get_try_format(sd, fh->pad, 0);
950 const struct ov02b10_mode *def_mode = &supported_modes[0];
951
952 mutex_lock(&ov02b10->mutex);
953 /* Initialize try_fmt */
954 try_fmt->width = def_mode->width;
955 try_fmt->height = def_mode->height;
956 try_fmt->code = def_mode->bus_fmt;
957 try_fmt->field = V4L2_FIELD_NONE;
958
959 mutex_unlock(&ov02b10->mutex);
960 /* No crop or compose */
961
962 return 0;
963 }
964 #endif
965
ov02b10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)966 static int ov02b10_enum_frame_interval(struct v4l2_subdev *sd,
967 struct v4l2_subdev_pad_config *cfg,
968 struct v4l2_subdev_frame_interval_enum *fie)
969 {
970 struct ov02b10 *ov02b10 = to_ov02b10(sd);
971
972 if (fie->index >= ov02b10->cfg_num)
973 return -EINVAL;
974
975 fie->code = supported_modes[fie->index].bus_fmt;
976 fie->width = supported_modes[fie->index].width;
977 fie->height = supported_modes[fie->index].height;
978 fie->interval = supported_modes[fie->index].max_fps;
979 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
980 return 0;
981 }
982
983 static const struct dev_pm_ops ov02b10_pm_ops = {
984 SET_RUNTIME_PM_OPS(ov02b10_runtime_suspend,
985 ov02b10_runtime_resume, NULL)
986 };
987
988 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
989 static const struct v4l2_subdev_internal_ops ov02b10_internal_ops = {
990 .open = ov02b10_open,
991 };
992 #endif
993
994 static const struct v4l2_subdev_core_ops ov02b10_core_ops = {
995 .s_power = ov02b10_s_power,
996 .ioctl = ov02b10_ioctl,
997 #ifdef CONFIG_COMPAT
998 .compat_ioctl32 = ov02b10_compat_ioctl32,
999 #endif
1000 };
1001
1002 static const struct v4l2_subdev_video_ops ov02b10_video_ops = {
1003 .s_stream = ov02b10_s_stream,
1004 .g_frame_interval = ov02b10_g_frame_interval,
1005 };
1006
1007 static const struct v4l2_subdev_pad_ops ov02b10_pad_ops = {
1008 .enum_mbus_code = ov02b10_enum_mbus_code,
1009 .enum_frame_size = ov02b10_enum_frame_sizes,
1010 .enum_frame_interval = ov02b10_enum_frame_interval,
1011 .get_fmt = ov02b10_get_fmt,
1012 .set_fmt = ov02b10_set_fmt,
1013 .get_mbus_config = ov02b10_g_mbus_config,
1014 };
1015
1016 static const struct v4l2_subdev_ops ov02b10_subdev_ops = {
1017 .core = &ov02b10_core_ops,
1018 .video = &ov02b10_video_ops,
1019 .pad = &ov02b10_pad_ops,
1020 };
1021
ov02b10_set_ctrl(struct v4l2_ctrl * ctrl)1022 static int ov02b10_set_ctrl(struct v4l2_ctrl *ctrl)
1023 {
1024 struct ov02b10 *ov02b10 = container_of(ctrl->handler,
1025 struct ov02b10, ctrl_handler);
1026 struct i2c_client *client = ov02b10->client;
1027 s64 max;
1028 int ret = 0;
1029 u8 again = 0, dgain = 0;
1030
1031 /* Propagate change of current control to all related controls */
1032 switch (ctrl->id) {
1033 case V4L2_CID_VBLANK:
1034 /* Update max exposure while meeting expected vblanking */
1035 max = ov02b10->cur_mode->height + ctrl->val - 7;
1036 __v4l2_ctrl_modify_range(ov02b10->exposure,
1037 ov02b10->exposure->minimum, max,
1038 ov02b10->exposure->step,
1039 ov02b10->exposure->default_value);
1040 break;
1041 }
1042
1043 if (!pm_runtime_get_if_in_use(&client->dev))
1044 return 0;
1045
1046 switch (ctrl->id) {
1047 case V4L2_CID_EXPOSURE:
1048 ret = ov02b10_write_reg(ov02b10->client,
1049 OV02B10_REG_PAGE_SELECT, 0x1);
1050 ret |= ov02b10_write_reg(ov02b10->client,
1051 OV02B10_REG_EXP_H, (ctrl->val >> 8) & 0xFF);
1052 ret |= ov02b10_write_reg(ov02b10->client,
1053 OV02B10_REG_EXP_L, ctrl->val & 0xFF);
1054 ret |= ov02b10_write_reg(ov02b10->client,
1055 OV02B10_REG_RESTART, 0x02);
1056 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1057 break;
1058 case V4L2_CID_ANALOGUE_GAIN:
1059 if (ctrl->val > 248) {
1060 again = 248;
1061 dgain = (ctrl->val * 64 / 248 > 0xff) ? 0xff : ctrl->val * 64 / 248;
1062 } else {
1063 dgain = 64;
1064 again = ctrl->val;
1065 }
1066 ret = ov02b10_write_reg(ov02b10->client,
1067 OV02B10_REG_PAGE_SELECT, 0x01);
1068 ret |= ov02b10_write_reg(ov02b10->client,
1069 OV02B10_REG_AGAIN, again);
1070 ret |= ov02b10_write_reg(ov02b10->client,
1071 OV02B10_REG_PAGE_SELECT, 0x03);
1072 ret |= ov02b10_write_reg(ov02b10->client,
1073 OV02B10_REG_DGAIN, dgain);
1074 ret |= ov02b10_write_reg(ov02b10->client,
1075 OV02B10_REG_RESTART, 0x02);
1076
1077 dev_dbg(&client->dev, "set gain 0x%x, again = %#x(%u), dgain = %#x(%u)\n",
1078 ctrl->val, again, again, dgain, dgain);
1079 break;
1080 case V4L2_CID_VBLANK:
1081 ret = ov02b10_write_reg(ov02b10->client,
1082 OV02B10_REG_PAGE_SELECT, 0x01);
1083 ret |= ov02b10_write_reg(ov02b10->client,
1084 OV02B10_REG_VBLANK_H, (ctrl->val >> 8) & 0xFF);
1085 ret |= ov02b10_write_reg(ov02b10->client,
1086 OV02B10_REG_VBLANK_L, ctrl->val & 0xFF);
1087 ret |= ov02b10_write_reg(ov02b10->client,
1088 OV02B10_REG_RESTART, 0x02);
1089 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1090 break;
1091 case V4L2_CID_TEST_PATTERN:
1092 break;
1093 case V4L2_CID_HFLIP:
1094 if (ctrl->val)
1095 ov02b10->flip |= MIRROR_BIT_MASK;
1096 else
1097 ov02b10->flip &= ~MIRROR_BIT_MASK;
1098
1099 ret = ov02b10_write_reg(ov02b10->client,
1100 OV02B10_REG_PAGE_SELECT, 0x01);
1101 ret |= ov02b10_write_reg(ov02b10->client,
1102 OV02B10_FLIP_REG, ov02b10->flip);
1103 ret |= ov02b10_write_reg(ov02b10->client,
1104 OV02B10_REG_RESTART, 0x02);
1105 dev_dbg(&client->dev, "set hflip 0x%x\n", ov02b10->flip);
1106 break;
1107 case V4L2_CID_VFLIP:
1108 if (ctrl->val)
1109 ov02b10->flip |= FLIP_BIT_MASK;
1110 else
1111 ov02b10->flip &= ~FLIP_BIT_MASK;
1112
1113 ret = ov02b10_write_reg(ov02b10->client,
1114 OV02B10_REG_PAGE_SELECT, 0x01);
1115 ret |= ov02b10_write_reg(ov02b10->client,
1116 OV02B10_FLIP_REG, ov02b10->flip);
1117 ret |= ov02b10_write_reg(ov02b10->client,
1118 OV02B10_REG_RESTART, 0x02);
1119 dev_dbg(&client->dev, "set vflip 0x%x\n", ov02b10->flip);
1120 break;
1121 default:
1122 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1123 __func__, ctrl->id, ctrl->val);
1124 break;
1125 }
1126 pm_runtime_put(&client->dev);
1127
1128 return ret;
1129 }
1130
1131 static const struct v4l2_ctrl_ops ov02b10_ctrl_ops = {
1132 .s_ctrl = ov02b10_set_ctrl,
1133 };
1134
ov02b10_initialize_controls(struct ov02b10 * ov02b10)1135 static int ov02b10_initialize_controls(struct ov02b10 *ov02b10)
1136 {
1137 const struct ov02b10_mode *mode;
1138 struct v4l2_ctrl_handler *handler;
1139 s64 exposure_max, vblank_def;
1140 u32 h_blank;
1141 int ret;
1142 u64 dst_link_freq = 0;
1143 u64 dst_pixel_rate = 0;
1144
1145 handler = &ov02b10->ctrl_handler;
1146 mode = ov02b10->cur_mode;
1147 ret = v4l2_ctrl_handler_init(handler, 9);
1148 if (ret)
1149 return ret;
1150 handler->lock = &ov02b10->mutex;
1151
1152 ov02b10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1153 V4L2_CID_LINK_FREQ,
1154 1, 0, link_freq_menu_items);
1155
1156 if (ov02b10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
1157 dst_link_freq = 0;
1158 dst_pixel_rate = PIXEL_RATE_WITH_360M;
1159 }
1160 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1161 ov02b10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1162 V4L2_CID_PIXEL_RATE,
1163 0, PIXEL_RATE_WITH_360M,
1164 1, dst_pixel_rate);
1165
1166 __v4l2_ctrl_s_ctrl(ov02b10->link_freq,
1167 dst_link_freq);
1168
1169 h_blank = mode->hts_def - mode->width;
1170 ov02b10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1171 h_blank, h_blank, 1, h_blank);
1172 if (ov02b10->hblank)
1173 ov02b10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1174
1175 /* From spec: vstart is 0xc by default */
1176 vblank_def = mode->vts_def - mode->height - 0xc;
1177 ov02b10->vblank = v4l2_ctrl_new_std(handler, &ov02b10_ctrl_ops,
1178 V4L2_CID_VBLANK, vblank_def,
1179 OV02B10_VTS_MAX - mode->height,
1180 1, vblank_def);
1181
1182 exposure_max = mode->vts_def - 7;
1183 ov02b10->exposure = v4l2_ctrl_new_std(handler, &ov02b10_ctrl_ops,
1184 V4L2_CID_EXPOSURE, OV02B10_EXPOSURE_MIN,
1185 exposure_max, OV02B10_EXPOSURE_STEP,
1186 mode->exp_def);
1187
1188 ov02b10->anal_gain = v4l2_ctrl_new_std(handler, &ov02b10_ctrl_ops,
1189 V4L2_CID_ANALOGUE_GAIN, OV02B10_GAIN_MIN,
1190 OV02B10_GAIN_MAX, OV02B10_GAIN_STEP,
1191 OV02B10_GAIN_DEFAULT);
1192
1193 ov02b10->h_flip = v4l2_ctrl_new_std(handler, &ov02b10_ctrl_ops,
1194 V4L2_CID_HFLIP, 0, 1, 1, 0);
1195
1196 ov02b10->v_flip = v4l2_ctrl_new_std(handler, &ov02b10_ctrl_ops,
1197 V4L2_CID_VFLIP, 0, 1, 1, 0);
1198 ov02b10->flip = 0;
1199 if (handler->error) {
1200 ret = handler->error;
1201 dev_err(&ov02b10->client->dev,
1202 "Failed to init controls(%d)\n", ret);
1203 goto err_free_handler;
1204 }
1205
1206 ov02b10->subdev.ctrl_handler = handler;
1207 ov02b10->has_init_exp = false;
1208
1209 return 0;
1210
1211 err_free_handler:
1212 v4l2_ctrl_handler_free(handler);
1213
1214 return ret;
1215 }
1216
ov02b10_check_sensor_id(struct ov02b10 * ov02b10,struct i2c_client * client)1217 static int ov02b10_check_sensor_id(struct ov02b10 *ov02b10,
1218 struct i2c_client *client)
1219 {
1220 struct device *dev = &ov02b10->client->dev;
1221 u8 id_h = 0, id_l = 0, id = 0;
1222 int ret;
1223
1224 ret = ov02b10_read_reg(client, OV02B10_REG_CHIP_ID_H, &id_h);
1225 ret |= ov02b10_read_reg(client, OV02B10_REG_CHIP_ID_L, &id_l);
1226
1227 id = SENSOR_ID(id_h, id_l);
1228 if (id != OV02B10_CHIP_ID) {
1229 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1230 return -ENODEV;
1231 }
1232 dev_info(dev, "Detected OV%06x sensor\n", OV02B10_CHIP_ID);
1233 return 0;
1234 }
1235
ov02b10_configure_regulators(struct ov02b10 * ov02b10)1236 static int ov02b10_configure_regulators(struct ov02b10 *ov02b10)
1237 {
1238 unsigned int i;
1239
1240 for (i = 0; i < OV02B10_NUM_SUPPLIES; i++)
1241 ov02b10->supplies[i].supply = OV02B10_supply_names[i];
1242
1243 return devm_regulator_bulk_get(&ov02b10->client->dev,
1244 OV02B10_NUM_SUPPLIES,
1245 ov02b10->supplies);
1246 }
1247
ov02b10_probe(struct i2c_client * client,const struct i2c_device_id * id)1248 static int ov02b10_probe(struct i2c_client *client,
1249 const struct i2c_device_id *id)
1250 {
1251 struct device *dev = &client->dev;
1252 struct device_node *node = dev->of_node;
1253 struct ov02b10 *ov02b10;
1254 struct v4l2_subdev *sd;
1255 char facing[2];
1256 int ret;
1257 u32 i, hdr_mode = 0;
1258
1259 dev_info(dev, "driver version: %02x.%02x.%02x",
1260 DRIVER_VERSION >> 16,
1261 (DRIVER_VERSION & 0xff00) >> 8,
1262 DRIVER_VERSION & 0x00ff);
1263
1264 ov02b10 = devm_kzalloc(dev, sizeof(*ov02b10), GFP_KERNEL);
1265 if (!ov02b10)
1266 return -ENOMEM;
1267
1268 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1269 &ov02b10->module_index);
1270 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1271 &ov02b10->module_facing);
1272 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1273 &ov02b10->module_name);
1274 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1275 &ov02b10->len_name);
1276 if (ret) {
1277 dev_err(dev, "could not get module information!\n");
1278 return -EINVAL;
1279 }
1280
1281 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
1282 &hdr_mode);
1283 if (ret) {
1284 hdr_mode = NO_HDR;
1285 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1286 }
1287 ov02b10->cfg_num = ARRAY_SIZE(supported_modes);
1288 for (i = 0; i < ov02b10->cfg_num; i++) {
1289 if (hdr_mode == supported_modes[i].hdr_mode) {
1290 ov02b10->cur_mode = &supported_modes[i];
1291 break;
1292 }
1293 }
1294 ov02b10->client = client;
1295
1296 ov02b10->xvclk = devm_clk_get(dev, "xvclk");
1297 if (IS_ERR(ov02b10->xvclk)) {
1298 dev_err(dev, "Failed to get xvclk\n");
1299 return -EINVAL;
1300 }
1301
1302 ov02b10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1303 if (IS_ERR(ov02b10->reset_gpio))
1304 dev_warn(dev, "Failed to get reset-gpios\n");
1305
1306 ov02b10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1307 if (IS_ERR(ov02b10->pwdn_gpio))
1308 dev_warn(dev, "Failed to get pwdn-gpios\n");
1309
1310 ov02b10->pinctrl = devm_pinctrl_get(dev);
1311 if (!IS_ERR(ov02b10->pinctrl)) {
1312 ov02b10->pins_default =
1313 pinctrl_lookup_state(ov02b10->pinctrl,
1314 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1315 if (IS_ERR(ov02b10->pins_default))
1316 dev_err(dev, "could not get default pinstate\n");
1317
1318 ov02b10->pins_sleep =
1319 pinctrl_lookup_state(ov02b10->pinctrl,
1320 OF_CAMERA_PINCTRL_STATE_SLEEP);
1321 if (IS_ERR(ov02b10->pins_sleep))
1322 dev_err(dev, "could not get sleep pinstate\n");
1323 } else {
1324 dev_err(dev, "no pinctrl\n");
1325 }
1326
1327 ret = ov02b10_configure_regulators(ov02b10);
1328 if (ret) {
1329 dev_err(dev, "Failed to get power regulators\n");
1330 return ret;
1331 }
1332
1333 mutex_init(&ov02b10->mutex);
1334
1335 sd = &ov02b10->subdev;
1336 v4l2_i2c_subdev_init(sd, client, &ov02b10_subdev_ops);
1337 ret = ov02b10_initialize_controls(ov02b10);
1338 if (ret)
1339 goto err_destroy_mutex;
1340
1341 ret = __ov02b10_power_on(ov02b10);
1342 if (ret)
1343 goto err_free_handler;
1344
1345 ret = ov02b10_check_sensor_id(ov02b10, client);
1346 if (ret)
1347 goto err_power_off;
1348
1349 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1350 sd->internal_ops = &ov02b10_internal_ops;
1351 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1352 #endif
1353 #if defined(CONFIG_MEDIA_CONTROLLER)
1354 ov02b10->pad.flags = MEDIA_PAD_FL_SOURCE;
1355 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1356 ret = media_entity_pads_init(&sd->entity, 1, &ov02b10->pad);
1357 if (ret < 0)
1358 goto err_power_off;
1359 #endif
1360
1361 memset(facing, 0, sizeof(facing));
1362 if (strcmp(ov02b10->module_facing, "back") == 0)
1363 facing[0] = 'b';
1364 else
1365 facing[0] = 'f';
1366
1367 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1368 ov02b10->module_index, facing,
1369 OV02B10_NAME, dev_name(sd->dev));
1370 ret = v4l2_async_register_subdev_sensor_common(sd);
1371 if (ret) {
1372 dev_err(dev, "v4l2 async register subdev failed\n");
1373 goto err_clean_entity;
1374 }
1375
1376 pm_runtime_set_active(dev);
1377 pm_runtime_enable(dev);
1378 pm_runtime_idle(dev);
1379
1380 return 0;
1381
1382 err_clean_entity:
1383 #if defined(CONFIG_MEDIA_CONTROLLER)
1384 media_entity_cleanup(&sd->entity);
1385 #endif
1386 err_power_off:
1387 __ov02b10_power_off(ov02b10);
1388 err_free_handler:
1389 v4l2_ctrl_handler_free(&ov02b10->ctrl_handler);
1390 err_destroy_mutex:
1391 mutex_destroy(&ov02b10->mutex);
1392
1393 return ret;
1394 }
1395
ov02b10_remove(struct i2c_client * client)1396 static int ov02b10_remove(struct i2c_client *client)
1397 {
1398 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1399 struct ov02b10 *ov02b10 = to_ov02b10(sd);
1400
1401 v4l2_async_unregister_subdev(sd);
1402 #if defined(CONFIG_MEDIA_CONTROLLER)
1403 media_entity_cleanup(&sd->entity);
1404 #endif
1405 v4l2_ctrl_handler_free(&ov02b10->ctrl_handler);
1406 mutex_destroy(&ov02b10->mutex);
1407
1408 pm_runtime_disable(&client->dev);
1409 if (!pm_runtime_status_suspended(&client->dev))
1410 __ov02b10_power_off(ov02b10);
1411 pm_runtime_set_suspended(&client->dev);
1412
1413 return 0;
1414 }
1415
1416 #if IS_ENABLED(CONFIG_OF)
1417 static const struct of_device_id ov02b10_of_match[] = {
1418 { .compatible = "ovti,ov02b10" },
1419 {},
1420 };
1421 MODULE_DEVICE_TABLE(of, ov02b10_of_match);
1422 #endif
1423
1424 static const struct i2c_device_id ov02b10_match_id[] = {
1425 { "ovti,ov02b10", 0 },
1426 { },
1427 };
1428
1429 static struct i2c_driver ov02b10_i2c_driver = {
1430 .driver = {
1431 .name = OV02B10_NAME,
1432 .pm = &ov02b10_pm_ops,
1433 .of_match_table = of_match_ptr(ov02b10_of_match),
1434 },
1435 .probe = &ov02b10_probe,
1436 .remove = &ov02b10_remove,
1437 .id_table = ov02b10_match_id,
1438 };
1439
1440 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
1441 module_i2c_driver(ov02b10_i2c_driver);
1442 #else
sensor_mod_init(void)1443 static int __init sensor_mod_init(void)
1444 {
1445 return i2c_add_driver(&ov02b10_i2c_driver);
1446 }
1447
sensor_mod_exit(void)1448 static void __exit sensor_mod_exit(void)
1449 {
1450 i2c_del_driver(&ov02b10_i2c_driver);
1451 }
1452
1453 device_initcall_sync(sensor_mod_init);
1454 module_exit(sensor_mod_exit);
1455 #endif
1456
1457 MODULE_DESCRIPTION("OmniVision ov02b10 sensor driver");
1458 MODULE_LICENSE("GPL v2");
1459