1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * os08a20 driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 init version.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/of.h>
18 #include <linux/of_graph.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/version.h>
23 #include <media/v4l2-async.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-image-sizes.h>
31 #include <media/v4l2-mediabus.h>
32 #include <media/v4l2-subdev.h>
33
34 #include <linux/rk-camera-module.h>
35
36 /* verify default register values */
37 //#define CHECK_REG_VALUE
38
39 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
40
41 #ifndef V4L2_CID_DIGITAL_GAIN
42 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
43 #endif
44
45 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
46 #define MIPI_FREQ 480000000U
47 #define OS08A20_PIXEL_RATE (MIPI_FREQ * 2LL * 4LL / 10)
48 #define OS08A20_XVCLK_FREQ 24000000
49
50 #define CHIP_ID 0x530841
51 #define OS08A20_REG_CHIP_ID 0x300a
52
53 #define OS08A20_REG_CTRL_MODE 0x0100
54 #define OS08A20_MODE_SW_STANDBY 0x00
55 #define OS08A20_MODE_STREAMING 0x01
56
57 #define OS08A20_REG_EXPOSURE 0x3501
58 #define OS08A20_EXPOSURE_MIN 4
59 #define OS08A20_EXPOSURE_STEP 1
60 #define OS08A20_VTS_MAX 0x7fff
61
62 #define OS08A20_REG_GAIN_H 0x3508
63 #define OS08A20_REG_GAIN_L 0x3509
64 #define OS08A20_GAIN_L_MASK 0xff
65 #define OS08A20_GAIN_H_MASK 0x3f
66 #define OS08A20_GAIN_H_SHIFT 8
67 #define ANALOG_GAIN_MIN 0x80
68 #define ANALOG_GAIN_MAX 0x7C0
69 #define ANALOG_GAIN_STEP 1
70 #define ANALOG_GAIN_DEFAULT 1024
71
72 #define OS08A20_REG_GROUP 0x3208
73 #define OS08A20_REG_FLIP 0x3820
74 #define OS08A20_REG_MIRROR 0x3821
75 #define MIRROR_BIT_MASK BIT(2)
76 #define FLIP_BIT_MASK BIT(2)
77
78 #define OS08A20_REG_TEST_PATTERN 0x5081
79 #define OS08A20_TEST_PATTERN_ENABLE 0x08
80 #define OS08A20_TEST_PATTERN_DISABLE 0x0
81
82 #define OS08A20_REG_VTS 0x380e
83
84 #define REG_NULL 0xFFFF
85 #define DELAY_MS 0xEEEE /* Array delay token */
86
87 #define OS08A20_REG_VALUE_08BIT 1
88 #define OS08A20_REG_VALUE_16BIT 2
89 #define OS08A20_REG_VALUE_24BIT 3
90
91 #define OS08A20_LANES 4
92 #define OS08A20_BITS_PER_SAMPLE 10
93
94 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
95 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
96
97 #define OS08A20_NAME "os08a20"
98 #define OS08A20_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
99
100 struct os08a20_otp_info {
101 int flag; // bit[7]: info, bit[6]:wb
102 int module_id;
103 int lens_id;
104 int year;
105 int month;
106 int day;
107 int rg_ratio;
108 int bg_ratio;
109 };
110
111 static const char * const os08a20_supply_names[] = {
112 "avdd", /* Analog power */
113 "dovdd", /* Digital I/O power */
114 "dvdd", /* Digital core power */
115 };
116
117 #define OS08A20_NUM_SUPPLIES ARRAY_SIZE(os08a20_supply_names)
118
119 struct regval {
120 u16 addr;
121 u8 val;
122 };
123
124 struct os08a20_mode {
125 u32 width;
126 u32 height;
127 struct v4l2_fract max_fps;
128 u32 hts_def;
129 u32 vts_def;
130 u32 exp_def;
131 const struct regval *reg_list;
132 u8 hdr_mode;
133 };
134
135 struct os08a20 {
136 struct i2c_client *client;
137 struct clk *xvclk;
138 struct gpio_desc *power_gpio;
139 struct gpio_desc *reset_gpio;
140 struct gpio_desc *pwdn_gpio;
141 struct regulator_bulk_data supplies[OS08A20_NUM_SUPPLIES];
142
143 struct pinctrl *pinctrl;
144 struct pinctrl_state *pins_default;
145 struct pinctrl_state *pins_sleep;
146
147 struct v4l2_subdev subdev;
148 struct media_pad pad;
149 struct v4l2_ctrl_handler ctrl_handler;
150 struct v4l2_ctrl *exposure;
151 struct v4l2_ctrl *anal_gain;
152 struct v4l2_ctrl *digi_gain;
153 struct v4l2_ctrl *hblank;
154 struct v4l2_ctrl *vblank;
155 struct v4l2_ctrl *test_pattern;
156 struct mutex mutex;
157 bool streaming;
158 bool power_on;
159 const struct os08a20_mode *cur_mode;
160 unsigned int lane_num;
161 unsigned int cfg_num;
162 unsigned int pixel_rate;
163 u32 module_index;
164 struct os08a20_otp_info *otp;
165 const char *module_facing;
166 const char *module_name;
167 const char *len_name;
168 struct rkmodule_awb_cfg awb_cfg;
169 };
170
171 #define to_os08a20(sd) container_of(sd, struct os08a20, subdev)
172
173 struct os08a20_id_name {
174 int id;
175 char name[RKMODULE_NAME_LEN];
176 };
177
178 /*
179 * Xclk 24Mhz
180 * grabwindow_width 3840
181 * grabwindow_height 2160
182 * max_framerate 30fps
183 * mipi_datarate per lane 960Mbps
184 */
185 static const struct regval os08a20_global_regs[] = {
186 {0x0100, 0x00},
187 {0x0103, 0x01},
188 {0x0303, 0x01},
189 {0x0305, 0x5a},
190 {0x0306, 0x00},
191 {0x0308, 0x03},
192 {0x0309, 0x04},
193 {0x032a, 0x00},
194 {0x300f, 0x11},
195 {0x3010, 0x01},
196 {0x3011, 0x04},
197 {0x3012, 0x41},
198 {0x3016, 0xf0},
199 {0x301e, 0x98},
200 {0x3031, 0xa9},
201 {0x3103, 0x92},
202 {0x3104, 0x01},
203 {0x3106, 0x10},
204 {0x340c, 0xff},
205 {0x340d, 0xff},
206 {0x031e, 0x09},
207 {0x3505, 0x83},
208 {0x3508, 0x00},
209 {0x3509, 0x80},
210 {0x350a, 0x04},
211 {0x350b, 0x00},
212 {0x350c, 0x00},
213 {0x350d, 0x80},
214 {0x350e, 0x04},
215 {0x350f, 0x00},
216 {0x3600, 0x00},
217 {0x3603, 0x2c},
218 {0x3605, 0x50},
219 {0x3609, 0xb5},
220 {0x3610, 0x39},
221 {0x3762, 0x11},
222 {0x360c, 0x01},
223 {0x3628, 0xa4},
224 {0x362d, 0x10},
225 {0x3660, 0x43},
226 {0x3661, 0x06},
227 {0x3662, 0x00},
228 {0x3663, 0x28},
229 {0x3664, 0x0d},
230 {0x366a, 0x38},
231 {0x366b, 0xa0},
232 {0x366d, 0x00},
233 {0x366e, 0x00},
234 {0x3680, 0x00},
235 {0x36c0, 0x00},
236 {0x3701, 0x02},
237 {0x373b, 0x02},
238 {0x373c, 0x02},
239 {0x3736, 0x02},
240 {0x3737, 0x02},
241 {0x3705, 0x00},
242 {0x3706, 0x39},
243 {0x370a, 0x00},
244 {0x370b, 0x98},
245 {0x3709, 0x49},
246 {0x3714, 0x21},
247 {0x371c, 0x00},
248 {0x371d, 0x08},
249 {0x3740, 0x1b},
250 {0x3741, 0x04},
251 {0x375e, 0x0b},
252 {0x3760, 0x10},
253 {0x3776, 0x10},
254 {0x3781, 0x02},
255 {0x3782, 0x04},
256 {0x3783, 0x02},
257 {0x3784, 0x08},
258 {0x3785, 0x08},
259 {0x3788, 0x01},
260 {0x3789, 0x01},
261 {0x3797, 0x04},
262 {0x3800, 0x00},
263 {0x3801, 0x00},
264 {0x3802, 0x00},
265 {0x3803, 0x0c},
266 {0x3804, 0x0e},
267 {0x3805, 0xff},
268 {0x3806, 0x08},
269 {0x3807, 0x6f},
270 {0x3808, 0x0f},
271 {0x3809, 0x00},
272 {0x380a, 0x08},
273 {0x380b, 0x70},
274 {0x380c, 0x04},
275 {0x380d, 0x0c},
276 {0x380e, 0x09},
277 {0x380f, 0x0a},
278 {0x3813, 0x10},
279 {0x3814, 0x01},
280 {0x3815, 0x01},
281 {0x3816, 0x01},
282 {0x3817, 0x01},
283 {0x381c, 0x00},
284 {0x3820, 0x00},
285 {0x3821, 0x04},
286 {0x3823, 0x08},
287 {0x3826, 0x00},
288 {0x3827, 0x08},
289 {0x382d, 0x08},
290 {0x3832, 0x02},
291 {0x3833, 0x00},
292 {0x383c, 0x48},
293 {0x383d, 0xff},
294 {0x3d85, 0x0b},
295 {0x3d84, 0x40},
296 {0x3d8c, 0x63},
297 {0x3d8d, 0xd7},
298 {0x4000, 0xf8},
299 {0x4001, 0x2b},
300 {0x4004, 0x00},
301 {0x4005, 0x40},
302 {0x400a, 0x01},
303 {0x400f, 0xa0},
304 {0x4010, 0x12},
305 {0x4018, 0x00},
306 {0x4008, 0x02},
307 {0x4009, 0x0d},
308 {0x401a, 0x58},
309 {0x4050, 0x00},
310 {0x4051, 0x01},
311 {0x4028, 0x2f},
312 {0x4052, 0x00},
313 {0x4053, 0x80},
314 {0x4054, 0x00},
315 {0x4055, 0x80},
316 {0x4056, 0x00},
317 {0x4057, 0x80},
318 {0x4058, 0x00},
319 {0x4059, 0x80},
320 {0x430b, 0xff},
321 {0x430c, 0xff},
322 {0x430d, 0x00},
323 {0x430e, 0x00},
324 {0x4501, 0x18},
325 {0x4502, 0x00},
326 {0x4643, 0x00},
327 {0x4640, 0x01},
328 {0x4641, 0x04},
329 {0x4800, 0x64},
330 {0x4809, 0x2b},
331 {0x4813, 0x90},
332 {0x4817, 0x04},
333 {0x4833, 0x18},
334 {0x483b, 0x00},
335 {0x484b, 0x03},
336 {0x4850, 0x7c},
337 {0x4852, 0x06},
338 {0x4856, 0x58},
339 {0x4857, 0xaa},
340 {0x4862, 0x0a},
341 {0x4869, 0x18},
342 {0x486a, 0xaa},
343 {0x486e, 0x03},
344 {0x486f, 0x55},
345 {0x4875, 0xf0},
346 {0x5000, 0x89},
347 {0x5001, 0x42},
348 {0x5004, 0x40},
349 {0x5005, 0x00},
350 {0x5180, 0x00},
351 {0x5181, 0x10},
352 {0x580b, 0x03},
353 {0x4d00, 0x03},
354 {0x4d01, 0xc9},
355 {0x4d02, 0xbc},
356 {0x4d03, 0xc6},
357 {0x4d04, 0x4a},
358 {0x4d05, 0x25},
359 {REG_NULL, 0x00},
360 };
361
362 /*
363 * Xclk 24Mhz
364 * Pclk 210Mhz
365 * linelength 2200(0x898)
366 * framelength 2250(0x7f6)
367 * grabwindow_width 3840
368 * grabwindow_height 2160
369 * max_framerate 30fps
370 * mipi_datarate per lane 960Mbps
371 */
372 static const struct regval os08a20_3840x2160_regs_4lane[] = {
373 // Sysclk 148Mhz, MIPI4_960Mbps/Lane, 30Fps.
374 //Line_length =2200, Frame_length =2250
375 {0x4700, 0x2b},
376 {0x4e00, 0x2b},
377 {0x0305, 0x3c},
378 {0x0323, 0x07},
379 {0x0324, 0x01},
380 {0x0325, 0x29},
381 {0x380c, 0x08},
382 {0x380d, 0x98},
383 {0x380e, 0x08},
384 {0x380f, 0xca},
385 {0x3501, 0x06},
386 {0x3502, 0xca},
387 {0x4837, 0x10},
388 {REG_NULL, 0x00},
389 };
390
391
392 static const struct os08a20_mode supported_modes_4lane[] = {
393 {
394 .width = 3840,
395 .height = 2160,
396 .max_fps = {
397 .numerator = 10000,
398 .denominator = 300000,
399 },
400 .exp_def = 0x08b0,
401 .hts_def = 0x898 * 2,
402 .vts_def = 0x08c6,
403 .reg_list = os08a20_3840x2160_regs_4lane,
404 .hdr_mode = NO_HDR,
405 },
406 };
407
408 static const struct os08a20_mode *supported_modes;
409
410 static const s64 link_freq_menu_items[] = {
411 MIPI_FREQ
412 };
413
414 static const char * const os08a20_test_pattern_menu[] = {
415 "Disabled",
416 "Vertical Color Bar Type 1",
417 "Vertical Color Bar Type 2",
418 "Vertical Color Bar Type 3",
419 "Vertical Color Bar Type 4",
420 "Square_BW Color Bar Type 1",
421 "Square_BW Color Bar Type 2",
422 "Square_BW Color Bar Type 3",
423 "Square_BW Color Bar Type 4",
424 "Transparent Color Bar Type 1",
425 "Transparent Color Bar Type 2",
426 "Transparent Color Bar Type 3",
427 "Transparent Color Bar Type 4",
428 "Rolling Color Bar Type 1",
429 "Rolling Color Bar Type 2",
430 "Rolling Color Bar Type 3",
431 "Rolling Color Bar Type 4",
432 };
433
434 /* Write registers up to 4 at a time */
os08a20_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)435 static int os08a20_write_reg(struct i2c_client *client, u16 reg,
436 u32 len, u32 val)
437 {
438 u32 buf_i, val_i;
439 u8 buf[6];
440 u8 *val_p;
441 __be32 val_be;
442
443 dev_dbg(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
444 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
445
446 if (len > 4)
447 return -EINVAL;
448
449 buf[0] = reg >> 8;
450 buf[1] = reg & 0xff;
451
452 val_be = cpu_to_be32(val);
453 val_p = (u8 *)&val_be;
454 buf_i = 2;
455 val_i = 4 - len;
456
457 while (val_i < 4)
458 buf[buf_i++] = val_p[val_i++];
459
460 if (i2c_master_send(client, buf, len + 2) != len + 2) {
461 dev_err(&client->dev,
462 "write reg(0x%x val:0x%x)failed !\n", reg, val);
463 return -EIO;
464 }
465 return 0;
466 }
467
os08a20_write_array(struct i2c_client * client,const struct regval * regs)468 static int os08a20_write_array(struct i2c_client *client,
469 const struct regval *regs)
470 {
471 int i, delay_ms, ret = 0;
472
473 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
474 if (regs[i].addr == DELAY_MS) {
475 delay_ms = regs[i].val;
476 dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
477 usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
478 continue;
479 }
480 ret = os08a20_write_reg(client, regs[i].addr,
481 OS08A20_REG_VALUE_08BIT, regs[i].val);
482 if (ret)
483 dev_err(&client->dev, "%s failed !\n", __func__);
484 }
485 return ret;
486 }
487
488 /* Read registers up to 4 at a time */
os08a20_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)489 static int os08a20_read_reg(struct i2c_client *client, u16 reg,
490 unsigned int len, u32 *val)
491 {
492 struct i2c_msg msgs[2];
493 u8 *data_be_p;
494 __be32 data_be = 0;
495 __be16 reg_addr_be = cpu_to_be16(reg);
496 int ret;
497
498 if (len > 4 || !len)
499 return -EINVAL;
500
501 data_be_p = (u8 *)&data_be;
502 /* Write register address */
503 msgs[0].addr = client->addr;
504 msgs[0].flags = 0;
505 msgs[0].len = 2;
506 msgs[0].buf = (u8 *)®_addr_be;
507
508 /* Read data from register */
509 msgs[1].addr = client->addr;
510 msgs[1].flags = I2C_M_RD;
511 msgs[1].len = len;
512 msgs[1].buf = &data_be_p[4 - len];
513
514 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
515 if (ret != ARRAY_SIZE(msgs))
516 return -EIO;
517
518 *val = be32_to_cpu(data_be);
519
520 return 0;
521 }
522
523 /* Check Register value */
524 #ifdef CHECK_REG_VALUE
os08a20_reg_verify(struct i2c_client * client,const struct regval * regs)525 static int os08a20_reg_verify(struct i2c_client *client,
526 const struct regval *regs)
527 {
528 u32 i;
529 int ret = 0;
530 u32 value;
531
532 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
533 ret = os08a20_read_reg(client, regs[i].addr,
534 OS08A20_REG_VALUE_08BIT, &value);
535 if (value != regs[i].val) {
536 dev_info(&client->dev, "%s: 0x%04x is 0x%x instead of 0x%x\n",
537 __func__, regs[i].addr, value, regs[i].val);
538 }
539 }
540 return ret;
541 }
542 #endif
543
os08a20_get_reso_dist(const struct os08a20_mode * mode,struct v4l2_mbus_framefmt * framefmt)544 static int os08a20_get_reso_dist(const struct os08a20_mode *mode,
545 struct v4l2_mbus_framefmt *framefmt)
546 {
547 return abs(mode->width - framefmt->width) +
548 abs(mode->height - framefmt->height);
549 }
550
551 static const struct os08a20_mode *
os08a20_find_best_fit(struct os08a20 * os08a20,struct v4l2_subdev_format * fmt)552 os08a20_find_best_fit(struct os08a20 *os08a20,
553 struct v4l2_subdev_format *fmt)
554 {
555 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
556 int dist;
557 int cur_best_fit = 0;
558 int cur_best_fit_dist = -1;
559 unsigned int i;
560
561 for (i = 0; i < os08a20->cfg_num; i++) {
562 dist = os08a20_get_reso_dist(&supported_modes[i], framefmt);
563 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
564 cur_best_fit_dist = dist;
565 cur_best_fit = i;
566 }
567 }
568
569 return &supported_modes[cur_best_fit];
570 }
571
os08a20_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)572 static int os08a20_set_fmt(struct v4l2_subdev *sd,
573 struct v4l2_subdev_pad_config *cfg,
574 struct v4l2_subdev_format *fmt)
575 {
576 struct os08a20 *os08a20 = to_os08a20(sd);
577 const struct os08a20_mode *mode;
578 s64 h_blank, vblank_def;
579
580 mutex_lock(&os08a20->mutex);
581
582 mode = os08a20_find_best_fit(os08a20, fmt);
583 fmt->format.code = OS08A20_MEDIA_BUS_FMT;
584 fmt->format.width = mode->width;
585 fmt->format.height = mode->height;
586 fmt->format.field = V4L2_FIELD_NONE;
587 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
588 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
589 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
590 #else
591 mutex_unlock(&os08a20->mutex);
592 return -ENOTTY;
593 #endif
594 } else {
595 os08a20->cur_mode = mode;
596 h_blank = mode->hts_def - mode->width;
597 __v4l2_ctrl_modify_range(os08a20->hblank, h_blank,
598 h_blank, 1, h_blank);
599 vblank_def = mode->vts_def - mode->height;
600 __v4l2_ctrl_modify_range(os08a20->vblank, vblank_def,
601 OS08A20_VTS_MAX - mode->height,
602 1, vblank_def);
603 }
604
605 mutex_unlock(&os08a20->mutex);
606
607 return 0;
608 }
609
os08a20_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)610 static int os08a20_get_fmt(struct v4l2_subdev *sd,
611 struct v4l2_subdev_pad_config *cfg,
612 struct v4l2_subdev_format *fmt)
613 {
614 struct os08a20 *os08a20 = to_os08a20(sd);
615 const struct os08a20_mode *mode = os08a20->cur_mode;
616
617 mutex_lock(&os08a20->mutex);
618 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
619 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
620 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
621 #else
622 mutex_unlock(&os08a20->mutex);
623 return -ENOTTY;
624 #endif
625 } else {
626 fmt->format.width = mode->width;
627 fmt->format.height = mode->height;
628 fmt->format.code = OS08A20_MEDIA_BUS_FMT;
629 fmt->format.field = V4L2_FIELD_NONE;
630 }
631 mutex_unlock(&os08a20->mutex);
632
633 return 0;
634 }
635
os08a20_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)636 static int os08a20_enum_mbus_code(struct v4l2_subdev *sd,
637 struct v4l2_subdev_pad_config *cfg,
638 struct v4l2_subdev_mbus_code_enum *code)
639 {
640 if (code->index != 0)
641 return -EINVAL;
642 code->code = OS08A20_MEDIA_BUS_FMT;
643
644 return 0;
645 }
646
os08a20_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)647 static int os08a20_enum_frame_sizes(struct v4l2_subdev *sd,
648 struct v4l2_subdev_pad_config *cfg,
649 struct v4l2_subdev_frame_size_enum *fse)
650 {
651 struct os08a20 *os08a20 = to_os08a20(sd);
652
653 if (fse->index >= os08a20->cfg_num)
654 return -EINVAL;
655
656 if (fse->code != OS08A20_MEDIA_BUS_FMT)
657 return -EINVAL;
658
659 fse->min_width = supported_modes[fse->index].width;
660 fse->max_width = supported_modes[fse->index].width;
661 fse->max_height = supported_modes[fse->index].height;
662 fse->min_height = supported_modes[fse->index].height;
663
664 return 0;
665 }
666
os08a20_enable_test_pattern(struct os08a20 * os08a20,u32 pattern)667 static int os08a20_enable_test_pattern(struct os08a20 *os08a20, u32 pattern)
668 {
669 u32 val;
670
671 if (pattern)
672 val = (pattern - 1) | OS08A20_TEST_PATTERN_ENABLE;
673 else
674 val = OS08A20_TEST_PATTERN_DISABLE;
675
676 /* test pattern select*/
677 return os08a20_write_reg(os08a20->client, OS08A20_REG_TEST_PATTERN,
678 OS08A20_REG_VALUE_08BIT, val);
679 }
680
os08a20_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)681 static int os08a20_g_frame_interval(struct v4l2_subdev *sd,
682 struct v4l2_subdev_frame_interval *fi)
683 {
684 struct os08a20 *os08a20 = to_os08a20(sd);
685 const struct os08a20_mode *mode = os08a20->cur_mode;
686
687 fi->interval = mode->max_fps;
688
689 return 0;
690 }
691
os08a20_get_module_inf(struct os08a20 * os08a20,struct rkmodule_inf * inf)692 static void os08a20_get_module_inf(struct os08a20 *os08a20,
693 struct rkmodule_inf *inf)
694 {
695 memset(inf, 0, sizeof(*inf));
696 strscpy(inf->base.sensor, OS08A20_NAME, sizeof(inf->base.sensor));
697 strscpy(inf->base.module, os08a20->module_name,
698 sizeof(inf->base.module));
699 strscpy(inf->base.lens, os08a20->len_name, sizeof(inf->base.lens));
700 }
701
os08a20_set_awb_cfg(struct os08a20 * os08a20,struct rkmodule_awb_cfg * cfg)702 static void os08a20_set_awb_cfg(struct os08a20 *os08a20,
703 struct rkmodule_awb_cfg *cfg)
704 {
705 mutex_lock(&os08a20->mutex);
706 memcpy(&os08a20->awb_cfg, cfg, sizeof(*cfg));
707 mutex_unlock(&os08a20->mutex);
708 }
709
os08a20_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)710 static long os08a20_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
711 {
712 struct os08a20 *os08a20 = to_os08a20(sd);
713 struct rkmodule_hdr_cfg *hdr;
714 long ret = 0;
715 u32 stream = 0;
716
717 switch (cmd) {
718 case RKMODULE_GET_MODULE_INFO:
719 os08a20_get_module_inf(os08a20, (struct rkmodule_inf *)arg);
720 break;
721 case RKMODULE_GET_HDR_CFG:
722 hdr = (struct rkmodule_hdr_cfg *)arg;
723 hdr->esp.mode = HDR_NORMAL_VC;
724 hdr->hdr_mode = os08a20->cur_mode->hdr_mode;
725 break;
726 case RKMODULE_SET_HDR_CFG:
727 hdr = (struct rkmodule_hdr_cfg *)arg;
728 if (hdr->hdr_mode != 0)
729 ret = -1;
730 break;
731 case RKMODULE_AWB_CFG:
732 os08a20_set_awb_cfg(os08a20, (struct rkmodule_awb_cfg *)arg);
733 break;
734 case RKMODULE_SET_QUICK_STREAM:
735
736 stream = *((u32 *)arg);
737
738 if (stream)
739 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_CTRL_MODE,
740 OS08A20_REG_VALUE_08BIT, OS08A20_MODE_STREAMING);
741 else
742 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_CTRL_MODE,
743 OS08A20_REG_VALUE_08BIT, OS08A20_MODE_SW_STANDBY);
744 break;
745 default:
746 ret = -ENOIOCTLCMD;
747 break;
748 }
749
750 return ret;
751 }
752
753 #ifdef CONFIG_COMPAT
os08a20_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)754 static long os08a20_compat_ioctl32(struct v4l2_subdev *sd,
755 unsigned int cmd, unsigned long arg)
756 {
757 void __user *up = compat_ptr(arg);
758 struct rkmodule_inf *inf;
759 struct rkmodule_awb_cfg *awb_cfg;
760 struct rkmodule_hdr_cfg *hdr;
761 long ret;
762 u32 stream = 0;
763
764 switch (cmd) {
765 case RKMODULE_GET_MODULE_INFO:
766 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
767 if (!inf) {
768 ret = -ENOMEM;
769 return ret;
770 }
771
772 ret = os08a20_ioctl(sd, cmd, inf);
773 if (!ret) {
774 ret = copy_to_user(up, inf, sizeof(*inf));
775 if (ret)
776 ret = -EFAULT;
777 }
778 kfree(inf);
779 break;
780 case RKMODULE_GET_HDR_CFG:
781 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
782 if (!hdr) {
783 ret = -ENOMEM;
784 return ret;
785 }
786
787 ret = os08a20_ioctl(sd, cmd, hdr);
788 if (!ret) {
789 ret = copy_to_user(up, hdr, sizeof(*hdr));
790 if (ret)
791 ret = -EFAULT;
792 }
793 kfree(hdr);
794 break;
795 case RKMODULE_SET_HDR_CFG:
796 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
797 if (!hdr) {
798 ret = -ENOMEM;
799 return ret;
800 }
801
802 if (copy_from_user(hdr, up, sizeof(*hdr))) {
803 kfree(hdr);
804 return -EFAULT;
805 }
806
807 ret = os08a20_ioctl(sd, cmd, hdr);
808 kfree(hdr);
809 break;
810 case RKMODULE_AWB_CFG:
811 awb_cfg = kzalloc(sizeof(*awb_cfg), GFP_KERNEL);
812 if (!awb_cfg) {
813 ret = -ENOMEM;
814 return ret;
815 }
816
817 if (copy_from_user(awb_cfg, up, sizeof(*awb_cfg))) {
818 kfree(awb_cfg);
819 return -EFAULT;
820 }
821
822 ret = os08a20_ioctl(sd, cmd, awb_cfg);
823 kfree(awb_cfg);
824 break;
825 case RKMODULE_SET_QUICK_STREAM:
826 if (copy_from_user(&stream, up, sizeof(u32)))
827 return -EFAULT;
828
829 ret = os08a20_ioctl(sd, cmd, &stream);
830 break;
831 default:
832 ret = -ENOIOCTLCMD;
833 break;
834 }
835
836 return ret;
837 }
838 #endif
839
__os08a20_start_stream(struct os08a20 * os08a20)840 static int __os08a20_start_stream(struct os08a20 *os08a20)
841 {
842 int ret;
843
844 ret = os08a20_write_array(os08a20->client, os08a20->cur_mode->reg_list);
845 if (ret)
846 return ret;
847
848 #ifdef CHECK_REG_VALUE
849 usleep_range(10000, 20000);
850 /* verify default values to make sure everything has */
851 /* been written correctly as expected */
852 dev_info(&os08a20->client->dev, "%s:Check register value!\n",
853 __func__);
854 ret = os08a20_reg_verify(os08a20->client, os08a20_global_regs);
855 if (ret)
856 return ret;
857
858 ret = os08a20_reg_verify(os08a20->client, os08a20->cur_mode->reg_list);
859 if (ret)
860 return ret;
861 #endif
862
863 /* In case these controls are set before streaming */
864 mutex_unlock(&os08a20->mutex);
865 ret = v4l2_ctrl_handler_setup(&os08a20->ctrl_handler);
866 mutex_lock(&os08a20->mutex);
867 if (ret)
868 return ret;
869
870 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_CTRL_MODE,
871 OS08A20_REG_VALUE_08BIT, OS08A20_MODE_STREAMING);
872 return ret;
873 }
874
__os08a20_stop_stream(struct os08a20 * os08a20)875 static int __os08a20_stop_stream(struct os08a20 *os08a20)
876 {
877 return os08a20_write_reg(os08a20->client, OS08A20_REG_CTRL_MODE,
878 OS08A20_REG_VALUE_08BIT, OS08A20_MODE_SW_STANDBY);
879 }
880
os08a20_s_stream(struct v4l2_subdev * sd,int on)881 static int os08a20_s_stream(struct v4l2_subdev *sd, int on)
882 {
883 struct os08a20 *os08a20 = to_os08a20(sd);
884 struct i2c_client *client = os08a20->client;
885 int ret = 0;
886
887 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
888 os08a20->cur_mode->width,
889 os08a20->cur_mode->height,
890 DIV_ROUND_CLOSEST(os08a20->cur_mode->max_fps.denominator,
891 os08a20->cur_mode->max_fps.numerator));
892
893 mutex_lock(&os08a20->mutex);
894 on = !!on;
895 if (on == os08a20->streaming)
896 goto unlock_and_return;
897
898 if (on) {
899 dev_info(&client->dev, "stream on!!!\n");
900 ret = pm_runtime_get_sync(&client->dev);
901 if (ret < 0) {
902 pm_runtime_put_noidle(&client->dev);
903 goto unlock_and_return;
904 }
905
906 ret = __os08a20_start_stream(os08a20);
907 if (ret) {
908 v4l2_err(sd, "start stream failed while write regs\n");
909 pm_runtime_put(&client->dev);
910 goto unlock_and_return;
911 }
912 } else {
913 dev_info(&client->dev, "stream off!!!\n");
914 __os08a20_stop_stream(os08a20);
915 pm_runtime_put(&client->dev);
916 }
917
918 os08a20->streaming = on;
919
920 unlock_and_return:
921 mutex_unlock(&os08a20->mutex);
922
923 return ret;
924 }
925
os08a20_s_power(struct v4l2_subdev * sd,int on)926 static int os08a20_s_power(struct v4l2_subdev *sd, int on)
927 {
928 struct os08a20 *os08a20 = to_os08a20(sd);
929 struct i2c_client *client = os08a20->client;
930 int ret = 0;
931
932 dev_dbg(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
933
934 mutex_lock(&os08a20->mutex);
935
936 /* If the power state is not modified - no work to do. */
937 if (os08a20->power_on == !!on)
938 goto unlock_and_return;
939
940 if (on) {
941 ret = pm_runtime_get_sync(&client->dev);
942 if (ret < 0) {
943 pm_runtime_put_noidle(&client->dev);
944 goto unlock_and_return;
945 }
946
947 ret = os08a20_write_array(os08a20->client, os08a20_global_regs);
948 if (ret) {
949 v4l2_err(sd, "could not set init registers\n");
950 pm_runtime_put_noidle(&client->dev);
951 goto unlock_and_return;
952 }
953
954 os08a20->power_on = true;
955 /* export gpio */
956 if (!IS_ERR(os08a20->reset_gpio))
957 gpiod_export(os08a20->reset_gpio, false);
958 if (!IS_ERR(os08a20->pwdn_gpio))
959 gpiod_export(os08a20->pwdn_gpio, false);
960 } else {
961 pm_runtime_put(&client->dev);
962 os08a20->power_on = false;
963 }
964
965 unlock_and_return:
966 mutex_unlock(&os08a20->mutex);
967
968 return ret;
969 }
970
971 /* Calculate the delay in us by clock rate and clock cycles */
os08a20_cal_delay(u32 cycles)972 static inline u32 os08a20_cal_delay(u32 cycles)
973 {
974 return DIV_ROUND_UP(cycles, OS08A20_XVCLK_FREQ / 1000 / 1000);
975 }
976
__os08a20_power_on(struct os08a20 * os08a20)977 static int __os08a20_power_on(struct os08a20 *os08a20)
978 {
979 int ret;
980 u32 delay_us;
981 struct device *dev = &os08a20->client->dev;
982
983 if (!IS_ERR(os08a20->power_gpio))
984 gpiod_set_value_cansleep(os08a20->power_gpio, 1);
985
986 usleep_range(1000, 2000);
987
988 if (!IS_ERR_OR_NULL(os08a20->pins_default)) {
989 ret = pinctrl_select_state(os08a20->pinctrl,
990 os08a20->pins_default);
991 if (ret < 0)
992 dev_err(dev, "could not set pins\n");
993 }
994 ret = clk_set_rate(os08a20->xvclk, OS08A20_XVCLK_FREQ);
995 if (ret < 0)
996 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
997 if (clk_get_rate(os08a20->xvclk) != OS08A20_XVCLK_FREQ)
998 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
999 ret = clk_prepare_enable(os08a20->xvclk);
1000 if (ret < 0) {
1001 dev_err(dev, "Failed to enable xvclk\n");
1002 return ret;
1003 }
1004
1005 ret = regulator_bulk_enable(OS08A20_NUM_SUPPLIES, os08a20->supplies);
1006 if (ret < 0) {
1007 dev_err(dev, "Failed to enable regulators\n");
1008 goto disable_clk;
1009 }
1010
1011 if (!IS_ERR(os08a20->reset_gpio))
1012 gpiod_set_value_cansleep(os08a20->reset_gpio, 1);
1013
1014 if (!IS_ERR(os08a20->pwdn_gpio))
1015 gpiod_set_value_cansleep(os08a20->pwdn_gpio, 1);
1016
1017 /* export gpio */
1018 if (!IS_ERR(os08a20->reset_gpio))
1019 gpiod_export(os08a20->reset_gpio, false);
1020 if (!IS_ERR(os08a20->pwdn_gpio))
1021 gpiod_export(os08a20->pwdn_gpio, false);
1022
1023 /* 8192 cycles prior to first SCCB transaction */
1024 delay_us = os08a20_cal_delay(8192);
1025 usleep_range(delay_us, delay_us * 2);
1026 usleep_range(10000, 20000);
1027 return 0;
1028
1029 disable_clk:
1030 clk_disable_unprepare(os08a20->xvclk);
1031
1032 return ret;
1033 }
1034
__os08a20_power_off(struct os08a20 * os08a20)1035 static void __os08a20_power_off(struct os08a20 *os08a20)
1036 {
1037 int ret;
1038 struct device *dev = &os08a20->client->dev;
1039
1040 if (!IS_ERR(os08a20->pwdn_gpio))
1041 gpiod_set_value_cansleep(os08a20->pwdn_gpio, 0);
1042 clk_disable_unprepare(os08a20->xvclk);
1043 if (!IS_ERR(os08a20->reset_gpio))
1044 gpiod_set_value_cansleep(os08a20->reset_gpio, 0);
1045 if (!IS_ERR_OR_NULL(os08a20->pins_sleep)) {
1046 ret = pinctrl_select_state(os08a20->pinctrl,
1047 os08a20->pins_sleep);
1048 if (ret < 0)
1049 dev_dbg(dev, "could not set pins\n");
1050 }
1051 if (!IS_ERR(os08a20->power_gpio))
1052 gpiod_set_value_cansleep(os08a20->power_gpio, 0);
1053
1054 regulator_bulk_disable(OS08A20_NUM_SUPPLIES, os08a20->supplies);
1055 }
1056
os08a20_runtime_resume(struct device * dev)1057 static int os08a20_runtime_resume(struct device *dev)
1058 {
1059 struct i2c_client *client = to_i2c_client(dev);
1060 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1061 struct os08a20 *os08a20 = to_os08a20(sd);
1062
1063 return __os08a20_power_on(os08a20);
1064 }
1065
os08a20_runtime_suspend(struct device * dev)1066 static int os08a20_runtime_suspend(struct device *dev)
1067 {
1068 struct i2c_client *client = to_i2c_client(dev);
1069 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1070 struct os08a20 *os08a20 = to_os08a20(sd);
1071
1072 __os08a20_power_off(os08a20);
1073
1074 return 0;
1075 }
1076
1077 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
os08a20_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1078 static int os08a20_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1079 {
1080 struct os08a20 *os08a20 = to_os08a20(sd);
1081 struct v4l2_mbus_framefmt *try_fmt =
1082 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1083 const struct os08a20_mode *def_mode = &supported_modes[0];
1084
1085 mutex_lock(&os08a20->mutex);
1086 /* Initialize try_fmt */
1087 try_fmt->width = def_mode->width;
1088 try_fmt->height = def_mode->height;
1089 try_fmt->code = OS08A20_MEDIA_BUS_FMT;
1090 try_fmt->field = V4L2_FIELD_NONE;
1091
1092 mutex_unlock(&os08a20->mutex);
1093 /* No crop or compose */
1094
1095 return 0;
1096 }
1097 #endif
1098
os08a20_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1099 static int os08a20_enum_frame_interval(struct v4l2_subdev *sd,
1100 struct v4l2_subdev_pad_config *cfg,
1101 struct v4l2_subdev_frame_interval_enum *fie)
1102 {
1103 struct os08a20 *os08a20 = to_os08a20(sd);
1104
1105 if (fie->index >= os08a20->cfg_num)
1106 return -EINVAL;
1107
1108 fie->code = OS08A20_MEDIA_BUS_FMT;
1109 fie->width = supported_modes[fie->index].width;
1110 fie->height = supported_modes[fie->index].height;
1111 fie->interval = supported_modes[fie->index].max_fps;
1112 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1113 return 0;
1114 }
1115
os08a20_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1116 static int os08a20_g_mbus_config(struct v4l2_subdev *sd,
1117 unsigned int pad_id,
1118 struct v4l2_mbus_config *config)
1119 {
1120 u32 val = 0;
1121
1122 val = 1 << (OS08A20_LANES - 1) |
1123 V4L2_MBUS_CSI2_CHANNEL_0 |
1124 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1125 config->type = V4L2_MBUS_CSI2_DPHY;
1126 config->flags = val;
1127
1128 return 0;
1129 }
1130
1131 static const struct dev_pm_ops os08a20_pm_ops = {
1132 SET_RUNTIME_PM_OPS(os08a20_runtime_suspend,
1133 os08a20_runtime_resume, NULL)
1134 };
1135
1136 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1137 static const struct v4l2_subdev_internal_ops os08a20_internal_ops = {
1138 .open = os08a20_open,
1139 };
1140 #endif
1141
1142 static const struct v4l2_subdev_core_ops os08a20_core_ops = {
1143 .s_power = os08a20_s_power,
1144 .ioctl = os08a20_ioctl,
1145 #ifdef CONFIG_COMPAT
1146 .compat_ioctl32 = os08a20_compat_ioctl32,
1147 #endif
1148 };
1149
1150 static const struct v4l2_subdev_video_ops os08a20_video_ops = {
1151 .s_stream = os08a20_s_stream,
1152 .g_frame_interval = os08a20_g_frame_interval,
1153 };
1154
1155 static const struct v4l2_subdev_pad_ops os08a20_pad_ops = {
1156 .enum_mbus_code = os08a20_enum_mbus_code,
1157 .enum_frame_size = os08a20_enum_frame_sizes,
1158 .enum_frame_interval = os08a20_enum_frame_interval,
1159 .get_fmt = os08a20_get_fmt,
1160 .set_fmt = os08a20_set_fmt,
1161 .get_mbus_config = os08a20_g_mbus_config,
1162 };
1163
1164 static const struct v4l2_subdev_ops os08a20_subdev_ops = {
1165 .core = &os08a20_core_ops,
1166 .video = &os08a20_video_ops,
1167 .pad = &os08a20_pad_ops,
1168 };
1169
os08a20_set_ctrl(struct v4l2_ctrl * ctrl)1170 static int os08a20_set_ctrl(struct v4l2_ctrl *ctrl)
1171 {
1172 struct os08a20 *os08a20 = container_of(ctrl->handler,
1173 struct os08a20, ctrl_handler);
1174 struct i2c_client *client = os08a20->client;
1175 s64 max;
1176 u32 val = 0;
1177 int ret = 0;
1178
1179 /* Propagate change of current control to all related controls */
1180 switch (ctrl->id) {
1181 case V4L2_CID_VBLANK:
1182 /* Update max exposure while meeting expected vblanking */
1183 max = os08a20->cur_mode->height + ctrl->val - 4;
1184 __v4l2_ctrl_modify_range(os08a20->exposure,
1185 os08a20->exposure->minimum, max,
1186 os08a20->exposure->step,
1187 os08a20->exposure->default_value);
1188 break;
1189 }
1190
1191 if (!pm_runtime_get_if_in_use(&client->dev))
1192 return 0;
1193
1194 switch (ctrl->id) {
1195 case V4L2_CID_EXPOSURE:
1196 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_EXPOSURE,
1197 OS08A20_REG_VALUE_16BIT, ctrl->val);
1198 break;
1199 case V4L2_CID_ANALOGUE_GAIN:
1200 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_GAIN_L,
1201 OS08A20_REG_VALUE_08BIT,
1202 ctrl->val & OS08A20_GAIN_L_MASK);
1203 ret |= os08a20_write_reg(os08a20->client, OS08A20_REG_GAIN_H,
1204 OS08A20_REG_VALUE_08BIT,
1205 (ctrl->val >> OS08A20_GAIN_H_SHIFT) &
1206 OS08A20_GAIN_H_MASK);
1207 break;
1208 case V4L2_CID_VBLANK:
1209 ret = os08a20_write_reg(os08a20->client, OS08A20_REG_VTS,
1210 OS08A20_REG_VALUE_16BIT,
1211 ctrl->val + os08a20->cur_mode->height);
1212 break;
1213 case V4L2_CID_TEST_PATTERN:
1214 ret = os08a20_enable_test_pattern(os08a20, ctrl->val);
1215 break;
1216 case V4L2_CID_HFLIP:
1217 ret = os08a20_read_reg(os08a20->client, OS08A20_REG_MIRROR,
1218 OS08A20_REG_VALUE_08BIT,
1219 &val);
1220 if (ctrl->val)
1221 val |= MIRROR_BIT_MASK;
1222 else
1223 val &= ~MIRROR_BIT_MASK;
1224 ret |= os08a20_write_reg(os08a20->client, OS08A20_REG_MIRROR,
1225 OS08A20_REG_VALUE_08BIT,
1226 val);
1227 break;
1228 case V4L2_CID_VFLIP:
1229 ret = os08a20_read_reg(os08a20->client, OS08A20_REG_FLIP,
1230 OS08A20_REG_VALUE_08BIT,
1231 &val);
1232 if (ctrl->val)
1233 val |= FLIP_BIT_MASK;
1234 else
1235 val &= ~FLIP_BIT_MASK;
1236 ret |= os08a20_write_reg(os08a20->client, OS08A20_REG_FLIP,
1237 OS08A20_REG_VALUE_08BIT,
1238 val);
1239 break;
1240 default:
1241 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1242 __func__, ctrl->id, ctrl->val);
1243 break;
1244 }
1245
1246 pm_runtime_put(&client->dev);
1247
1248 return ret;
1249 }
1250
1251 static const struct v4l2_ctrl_ops os08a20_ctrl_ops = {
1252 .s_ctrl = os08a20_set_ctrl,
1253 };
1254
os08a20_initialize_controls(struct os08a20 * os08a20)1255 static int os08a20_initialize_controls(struct os08a20 *os08a20)
1256 {
1257 const struct os08a20_mode *mode;
1258 struct v4l2_ctrl_handler *handler;
1259 struct v4l2_ctrl *ctrl;
1260 s64 exposure_max, vblank_def;
1261 u32 h_blank;
1262 int ret;
1263
1264 handler = &os08a20->ctrl_handler;
1265 mode = os08a20->cur_mode;
1266 ret = v4l2_ctrl_handler_init(handler, 9);
1267 if (ret)
1268 return ret;
1269 handler->lock = &os08a20->mutex;
1270
1271 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1272 0, 0, link_freq_menu_items);
1273 if (ctrl)
1274 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1275
1276 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1277 0, os08a20->pixel_rate, 1, os08a20->pixel_rate);
1278
1279 h_blank = mode->hts_def - mode->width;
1280 os08a20->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1281 h_blank, h_blank, 1, h_blank);
1282 if (os08a20->hblank)
1283 os08a20->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1284
1285 vblank_def = mode->vts_def - mode->height;
1286 os08a20->vblank = v4l2_ctrl_new_std(handler, &os08a20_ctrl_ops,
1287 V4L2_CID_VBLANK, vblank_def,
1288 OS08A20_VTS_MAX - mode->height,
1289 1, vblank_def);
1290
1291 exposure_max = mode->vts_def - 4;
1292 os08a20->exposure = v4l2_ctrl_new_std(handler, &os08a20_ctrl_ops,
1293 V4L2_CID_EXPOSURE, OS08A20_EXPOSURE_MIN,
1294 exposure_max, OS08A20_EXPOSURE_STEP,
1295 mode->exp_def);
1296
1297 os08a20->anal_gain = v4l2_ctrl_new_std(handler, &os08a20_ctrl_ops,
1298 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1299 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1300 ANALOG_GAIN_DEFAULT);
1301
1302 os08a20->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1303 &os08a20_ctrl_ops, V4L2_CID_TEST_PATTERN,
1304 ARRAY_SIZE(os08a20_test_pattern_menu) - 1,
1305 0, 0, os08a20_test_pattern_menu);
1306
1307 v4l2_ctrl_new_std(handler, &os08a20_ctrl_ops,
1308 V4L2_CID_HFLIP, 0, 1, 1, 0);
1309
1310 v4l2_ctrl_new_std(handler, &os08a20_ctrl_ops,
1311 V4L2_CID_VFLIP, 0, 1, 1, 0);
1312
1313 if (handler->error) {
1314 ret = handler->error;
1315 dev_err(&os08a20->client->dev,
1316 "Failed to init controls(%d)\n", ret);
1317 goto err_free_handler;
1318 }
1319
1320 os08a20->subdev.ctrl_handler = handler;
1321
1322 return 0;
1323
1324 err_free_handler:
1325 v4l2_ctrl_handler_free(handler);
1326
1327 return ret;
1328 }
1329
os08a20_check_sensor_id(struct os08a20 * os08a20,struct i2c_client * client)1330 static int os08a20_check_sensor_id(struct os08a20 *os08a20,
1331 struct i2c_client *client)
1332 {
1333 struct device *dev = &os08a20->client->dev;
1334 u32 id = 0;
1335 int ret;
1336
1337 ret = os08a20_read_reg(client, OS08A20_REG_CHIP_ID,
1338 OS08A20_REG_VALUE_24BIT, &id);
1339 if (id != CHIP_ID) {
1340 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1341 return -ENODEV;
1342 }
1343
1344 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1345
1346 return 0;
1347 }
1348
os08a20_configure_regulators(struct os08a20 * os08a20)1349 static int os08a20_configure_regulators(struct os08a20 *os08a20)
1350 {
1351 unsigned int i;
1352
1353 for (i = 0; i < OS08A20_NUM_SUPPLIES; i++)
1354 os08a20->supplies[i].supply = os08a20_supply_names[i];
1355
1356 return devm_regulator_bulk_get(&os08a20->client->dev,
1357 OS08A20_NUM_SUPPLIES,
1358 os08a20->supplies);
1359 }
1360
os08a20_parse_of(struct os08a20 * os08a20)1361 static int os08a20_parse_of(struct os08a20 *os08a20)
1362 {
1363 struct device *dev = &os08a20->client->dev;
1364 struct device_node *endpoint;
1365 struct fwnode_handle *fwnode;
1366 int rval;
1367
1368 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1369 if (!endpoint) {
1370 dev_err(dev, "Failed to get endpoint\n");
1371 return -EINVAL;
1372 }
1373 fwnode = of_fwnode_handle(endpoint);
1374 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
1375 if (rval <= 0) {
1376 dev_warn(dev, " Get mipi lane num failed!\n");
1377 return -1;
1378 }
1379
1380 os08a20->lane_num = rval;
1381 if (os08a20->lane_num == 4) {
1382 os08a20->cur_mode = &supported_modes_4lane[0];
1383 supported_modes = supported_modes_4lane;
1384 os08a20->cfg_num = ARRAY_SIZE(supported_modes_4lane);
1385
1386 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1387 os08a20->pixel_rate = MIPI_FREQ * 2U * os08a20->lane_num / 8U;
1388 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
1389 os08a20->lane_num, os08a20->pixel_rate);
1390 } else {
1391 dev_err(dev, "unsupported lane_num(%d)\n", os08a20->lane_num);
1392 return -1;
1393 }
1394
1395 return 0;
1396 }
1397
os08a20_probe(struct i2c_client * client,const struct i2c_device_id * id)1398 static int os08a20_probe(struct i2c_client *client,
1399 const struct i2c_device_id *id)
1400 {
1401 struct device *dev = &client->dev;
1402 struct device_node *node = dev->of_node;
1403 struct os08a20 *os08a20;
1404 struct v4l2_subdev *sd;
1405 char facing[2] = "b";
1406 int ret;
1407
1408 dev_info(dev, "driver version: %02x.%02x.%02x",
1409 DRIVER_VERSION >> 16,
1410 (DRIVER_VERSION & 0xff00) >> 8,
1411 DRIVER_VERSION & 0x00ff);
1412
1413 os08a20 = devm_kzalloc(dev, sizeof(*os08a20), GFP_KERNEL);
1414 if (!os08a20)
1415 return -ENOMEM;
1416
1417 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1418 &os08a20->module_index);
1419 if (ret) {
1420 dev_warn(dev, "could not get module index!\n");
1421 os08a20->module_index = 0;
1422 }
1423 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1424 &os08a20->module_facing);
1425 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1426 &os08a20->module_name);
1427 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1428 &os08a20->len_name);
1429 if (ret) {
1430 dev_err(dev, "could not get module information!\n");
1431 return -EINVAL;
1432 }
1433
1434 os08a20->client = client;
1435
1436 os08a20->xvclk = devm_clk_get(dev, "xvclk");
1437 if (IS_ERR(os08a20->xvclk)) {
1438 dev_err(dev, "Failed to get xvclk\n");
1439 return -EINVAL;
1440 }
1441
1442 os08a20->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1443 if (IS_ERR(os08a20->power_gpio))
1444 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1445
1446 os08a20->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1447 if (IS_ERR(os08a20->reset_gpio))
1448 dev_warn(dev, "Failed to get reset-gpios, maybe no use\n");
1449
1450 os08a20->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1451 if (IS_ERR(os08a20->pwdn_gpio))
1452 dev_warn(dev, "Failed to get pwdn-gpios\n");
1453
1454 ret = os08a20_configure_regulators(os08a20);
1455 if (ret) {
1456 dev_err(dev, "Failed to get power regulators\n");
1457 return ret;
1458 }
1459 ret = os08a20_parse_of(os08a20);
1460 if (ret != 0)
1461 return -EINVAL;
1462
1463 os08a20->pinctrl = devm_pinctrl_get(dev);
1464 if (!IS_ERR(os08a20->pinctrl)) {
1465 os08a20->pins_default =
1466 pinctrl_lookup_state(os08a20->pinctrl,
1467 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1468 if (IS_ERR(os08a20->pins_default))
1469 dev_err(dev, "could not get default pinstate\n");
1470
1471 os08a20->pins_sleep =
1472 pinctrl_lookup_state(os08a20->pinctrl,
1473 OF_CAMERA_PINCTRL_STATE_SLEEP);
1474 if (IS_ERR(os08a20->pins_sleep))
1475 dev_err(dev, "could not get sleep pinstate\n");
1476 }
1477
1478 mutex_init(&os08a20->mutex);
1479
1480 sd = &os08a20->subdev;
1481 v4l2_i2c_subdev_init(sd, client, &os08a20_subdev_ops);
1482 ret = os08a20_initialize_controls(os08a20);
1483 if (ret)
1484 goto err_destroy_mutex;
1485
1486 ret = __os08a20_power_on(os08a20);
1487 if (ret)
1488 goto err_free_handler;
1489
1490 ret = os08a20_check_sensor_id(os08a20, client);
1491 if (ret < 0) {
1492 dev_err(&client->dev, "%s(%d) Check id failed,\n"
1493 "check following information:\n"
1494 "Power/PowerDown/Reset/Mclk/I2cBus !!\n",
1495 __func__, __LINE__);
1496 goto err_power_off;
1497 }
1498
1499 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1500 sd->internal_ops = &os08a20_internal_ops;
1501 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1502 V4L2_SUBDEV_FL_HAS_EVENTS;
1503 #endif
1504 #if defined(CONFIG_MEDIA_CONTROLLER)
1505 os08a20->pad.flags = MEDIA_PAD_FL_SOURCE;
1506 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1507 ret = media_entity_pads_init(&sd->entity, 1, &os08a20->pad);
1508 if (ret < 0)
1509 goto err_power_off;
1510 #endif
1511
1512 memset(facing, 0, sizeof(facing));
1513 if (strcmp(os08a20->module_facing, "back") == 0)
1514 facing[0] = 'b';
1515 else
1516 facing[0] = 'f';
1517
1518 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1519 os08a20->module_index, facing,
1520 OS08A20_NAME, dev_name(sd->dev));
1521
1522 ret = v4l2_async_register_subdev_sensor_common(sd);
1523 if (ret) {
1524 dev_err(dev, "v4l2 async register subdev failed\n");
1525 goto err_clean_entity;
1526 }
1527
1528 pm_runtime_set_active(dev);
1529 pm_runtime_enable(dev);
1530 pm_runtime_idle(dev);
1531
1532 return 0;
1533
1534 err_clean_entity:
1535 #if defined(CONFIG_MEDIA_CONTROLLER)
1536 media_entity_cleanup(&sd->entity);
1537 #endif
1538 err_power_off:
1539 __os08a20_power_off(os08a20);
1540 err_free_handler:
1541 v4l2_ctrl_handler_free(&os08a20->ctrl_handler);
1542 err_destroy_mutex:
1543 mutex_destroy(&os08a20->mutex);
1544
1545 return ret;
1546 }
1547
os08a20_remove(struct i2c_client * client)1548 static int os08a20_remove(struct i2c_client *client)
1549 {
1550 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1551 struct os08a20 *os08a20 = to_os08a20(sd);
1552
1553 v4l2_async_unregister_subdev(sd);
1554 #if defined(CONFIG_MEDIA_CONTROLLER)
1555 media_entity_cleanup(&sd->entity);
1556 #endif
1557 v4l2_ctrl_handler_free(&os08a20->ctrl_handler);
1558 mutex_destroy(&os08a20->mutex);
1559
1560 pm_runtime_disable(&client->dev);
1561 if (!pm_runtime_status_suspended(&client->dev))
1562 __os08a20_power_off(os08a20);
1563 pm_runtime_set_suspended(&client->dev);
1564
1565 return 0;
1566 }
1567
1568 #if IS_ENABLED(CONFIG_OF)
1569 static const struct of_device_id os08a20_of_match[] = {
1570 { .compatible = "ovti,os08a20" },
1571 {},
1572 };
1573 MODULE_DEVICE_TABLE(of, os08a20_of_match);
1574 #endif
1575
1576 static const struct i2c_device_id os08a20_match_id[] = {
1577 { "ovti,os08a20", 0 },
1578 { },
1579 };
1580
1581 static struct i2c_driver os08a20_i2c_driver = {
1582 .driver = {
1583 .name = OS08A20_NAME,
1584 .pm = &os08a20_pm_ops,
1585 .of_match_table = of_match_ptr(os08a20_of_match),
1586 },
1587 .probe = &os08a20_probe,
1588 .remove = &os08a20_remove,
1589 .id_table = os08a20_match_id,
1590 };
1591
sensor_mod_init(void)1592 static int __init sensor_mod_init(void)
1593 {
1594 return i2c_add_driver(&os08a20_i2c_driver);
1595 }
1596
sensor_mod_exit(void)1597 static void __exit sensor_mod_exit(void)
1598 {
1599 i2c_del_driver(&os08a20_i2c_driver);
1600 }
1601
1602 device_initcall_sync(sensor_mod_init);
1603 module_exit(sensor_mod_exit);
1604
1605 MODULE_DESCRIPTION("OmniVision os08a20 sensor driver");
1606 MODULE_LICENSE("GPL");
1607