1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * os04a10 driver
4 *
5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 support conversion gain switch.
9 * V0.0X01.0X02 add debug interface for conversion gain switch.
10 * V0.0X01.0X03 support enum sensor fmt
11 * V0.0X01.0X04 add quick stream on/off
12 * V0.0X01.0X05 support get dcg ratio from sensor
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/version.h>
26 #include <linux/rk-camera-module.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-async.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-subdev.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/rk-preisp.h>
33 #include <media/v4l2-fwnode.h>
34 #include <linux/of_graph.h>
35 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
36
37 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
38
39 #ifndef V4L2_CID_DIGITAL_GAIN
40 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
41 #endif
42
43 #define MIPI_FREQ_360M 360000000
44 #define MIPI_FREQ_648M 648000000
45 #define MIPI_FREQ_720M 720000000
46
47 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4)
48 #define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 10 * 4)
49 #define PIXEL_RATE_WITH_720M (MIPI_FREQ_720M * 2 / 10 * 4)
50
51 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
52
53 #define OS04A10_XVCLK_FREQ 24000000
54
55 #define CHIP_ID 0x530441
56 #define OS04A10_REG_CHIP_ID 0x300a
57
58 #define OS04A10_REG_CTRL_MODE 0x0100
59 #define OS04A10_MODE_SW_STANDBY 0x0
60 #define OS04A10_MODE_STREAMING BIT(0)
61
62 #define OS04A10_EXPOSURE_MIN 2
63 #define OS04A10_EXPOSURE_STEP 1
64 #define OS04A10_VTS_MAX 0xffff
65
66 #define OS04A10_REG_EXP_LONG_H 0x3501
67 #define OS04A10_REG_EXP_MID_H 0x3541
68 #define OS04A10_REG_EXP_VS_H 0x3581
69
70 #define OS04A10_REG_HCG_SWITCH 0x376C
71 #define OS04A10_REG_AGAIN_LONG_H 0x3508
72 #define OS04A10_REG_AGAIN_MID_H 0x3548
73 #define OS04A10_REG_AGAIN_VS_H 0x3588
74 #define OS04A10_REG_DGAIN_LONG_H 0x350A
75 #define OS04A10_REG_DGAIN_MID_H 0x354A
76 #define OS04A10_REG_DGAIN_VS_H 0x358A
77 #define OS04A10_GAIN_MIN 0x10
78 #define OS04A10_GAIN_MAX 0xF7C
79 #define OS04A10_GAIN_STEP 1
80 #define OS04A10_GAIN_DEFAULT 0x10
81
82 #define OS04A10_GROUP_UPDATE_ADDRESS 0x3208
83 #define OS04A10_GROUP_UPDATE_START_DATA 0x00
84 #define OS04A10_GROUP_UPDATE_END_DATA 0x10
85 #define OS04A10_GROUP_UPDATE_END_LAUNCH 0xA0
86
87 #define OS04A10_SOFTWARE_RESET_REG 0x0103
88
89 #define OS04A10_FETCH_MSB_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */
90 #define OS04A10_FETCH_LSB_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
91
92 #define OS04A10_FETCH_LSB_GAIN(VAL) (((VAL) << 4) & 0xf0)
93 #define OS04A10_FETCH_MSB_GAIN(VAL) (((VAL) >> 4) & 0x1f)
94
95 #define OS04A10_REG_TEST_PATTERN 0x5080
96 #define OS04A10_TEST_PATTERN_ENABLE 0x80
97 #define OS04A10_TEST_PATTERN_DISABLE 0x0
98
99 #define OS04A10_REG_VTS 0x380e
100
101 #define REG_NULL 0xFFFF
102
103 #define OS04A10_REG_VALUE_08BIT 1
104 #define OS04A10_REG_VALUE_16BIT 2
105 #define OS04A10_REG_VALUE_24BIT 3
106
107 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
108 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
109
110 #define OS04A10_NAME "os04a10"
111
112 #define USED_SYS_DEBUG
113
114 static const char * const os04a10_supply_names[] = {
115 "avdd", /* Analog power */
116 "dovdd", /* Digital I/O power */
117 "dvdd", /* Digital core power */
118 };
119
120 #define OS04A10_NUM_SUPPLIES ARRAY_SIZE(os04a10_supply_names)
121
122 #define OS04A10_FLIP_REG 0x3820
123 #define MIRROR_BIT_MASK BIT(1)
124 #define FLIP_BIT_MASK BIT(2)
125
126 struct regval {
127 u16 addr;
128 u8 val;
129 };
130
131 struct os04a10_mode {
132 u32 bus_fmt;
133 u32 width;
134 u32 height;
135 struct v4l2_fract max_fps;
136 u32 hts_def;
137 u32 vts_def;
138 u32 exp_def;
139 const struct regval *global_reg_list;
140 const struct regval *reg_list;
141 u32 hdr_mode;
142 u32 link_freq_idx;
143 u32 bpp;
144 u32 vc[PAD_MAX];
145 };
146
147 struct os04a10 {
148 struct i2c_client *client;
149 struct clk *xvclk;
150 struct gpio_desc *reset_gpio;
151 struct gpio_desc *pwdn_gpio;
152 struct regulator_bulk_data supplies[OS04A10_NUM_SUPPLIES];
153
154 struct pinctrl *pinctrl;
155 struct pinctrl_state *pins_default;
156 struct pinctrl_state *pins_sleep;
157
158 struct v4l2_subdev subdev;
159 struct media_pad pad;
160 struct v4l2_ctrl_handler ctrl_handler;
161 struct v4l2_ctrl *exposure;
162 struct v4l2_ctrl *anal_gain;
163 struct v4l2_ctrl *digi_gain;
164 struct v4l2_ctrl *hblank;
165 struct v4l2_ctrl *vblank;
166 struct v4l2_ctrl *test_pattern;
167 struct v4l2_ctrl *pixel_rate;
168 struct v4l2_ctrl *link_freq;
169 struct v4l2_ctrl *h_flip;
170 struct v4l2_ctrl *v_flip;
171 struct mutex mutex;
172 bool streaming;
173 bool power_on;
174 const struct os04a10_mode *supported_modes;
175 const struct os04a10_mode *cur_mode;
176 u32 cfg_num;
177 u32 module_index;
178 const char *module_facing;
179 const char *module_name;
180 const char *len_name;
181 bool has_init_exp;
182 struct preisp_hdrae_exp_s init_hdrae_exp;
183 bool long_hcg;
184 bool middle_hcg;
185 bool short_hcg;
186 bool is_thunderboot;
187 bool is_thunderboot_ng;
188 bool is_first_streamoff;
189 u8 flip;
190 u32 dcg_ratio;
191 struct v4l2_fwnode_endpoint bus_cfg;
192 };
193
194 #define to_os04a10(sd) container_of(sd, struct os04a10, subdev)
195
196 /*
197 * Xclk 24Mhz
198 */
199 static const struct regval os04a10_global_regs[] = {
200 {0x0109, 0x01},
201 {0x0104, 0x02},
202 {0x0102, 0x00},
203 {0x0306, 0x00},
204 {0x0307, 0x00},
205 {0x030a, 0x01},
206 {0x0322, 0x01},
207 {0x0323, 0x02},
208 {0x0324, 0x00},
209 {0x0327, 0x05},
210 {0x0329, 0x02},
211 {0x032c, 0x02},
212 {0x032d, 0x02},
213 {0x300f, 0x11},
214 {0x3012, 0x41},
215 {0x3026, 0x10},
216 {0x3027, 0x08},
217 {0x302d, 0x24},
218 {0x3104, 0x01},
219 {0x3106, 0x11},
220 {0x3400, 0x00},
221 {0x3408, 0x05},
222 {0x340c, 0x0c},
223 {0x340d, 0xb0},
224 {0x3425, 0x51},
225 {0x3426, 0x50},
226 {0x3427, 0x15},
227 {0x3428, 0x50},
228 {0x3429, 0x10},
229 {0x342a, 0x10},
230 {0x342b, 0x04},
231 {0x3501, 0x02},
232 {0x3504, 0x08},
233 {0x3508, 0x01},
234 {0x3509, 0x00},
235 {0x350a, 0x01},
236 {0x3544, 0x08},
237 {0x3548, 0x01},
238 {0x3549, 0x00},
239 {0x3584, 0x08},
240 {0x3588, 0x01},
241 {0x3589, 0x00},
242 {0x3601, 0x70},
243 {0x3604, 0xe3},
244 {0x3608, 0xa8},
245 {0x360a, 0xd0},
246 {0x360b, 0x08},
247 {0x360e, 0xc8},
248 {0x360f, 0x66},
249 {0x3610, 0x89},
250 {0x3611, 0x8a},
251 {0x3612, 0x4e},
252 {0x3613, 0xbd},
253 {0x3614, 0x9b},
254 {0x362a, 0x0e},
255 {0x362b, 0x0e},
256 {0x362c, 0x0e},
257 {0x362e, 0x1a},
258 {0x362f, 0x34},
259 {0x3630, 0x67},
260 {0x3631, 0x7f},
261 {0x3638, 0x00},
262 {0x3643, 0x00},
263 {0x3644, 0x00},
264 {0x3645, 0x00},
265 {0x3646, 0x00},
266 {0x3647, 0x00},
267 {0x3648, 0x00},
268 {0x3649, 0x00},
269 {0x364a, 0x04},
270 {0x364c, 0x0e},
271 {0x364d, 0x0e},
272 {0x364e, 0x0e},
273 {0x364f, 0x0e},
274 {0x3650, 0xff},
275 {0x3651, 0xff},
276 {0x365a, 0x00},
277 {0x365b, 0x00},
278 {0x365c, 0x00},
279 {0x365d, 0x00},
280 {0x3661, 0x07},
281 {0x3663, 0x20},
282 {0x3665, 0x12},
283 {0x3668, 0x80},
284 {0x366c, 0x00},
285 {0x366d, 0x00},
286 {0x366e, 0x00},
287 {0x366f, 0x00},
288 {0x3673, 0x2a},
289 {0x3681, 0x80},
290 {0x3700, 0x2d},
291 {0x3701, 0x22},
292 {0x3702, 0x25},
293 {0x3705, 0x00},
294 {0x3707, 0x0a},
295 {0x3708, 0x36},
296 {0x3709, 0x57},
297 {0x3714, 0x01},
298 {0x371c, 0x00},
299 {0x371d, 0x08},
300 {0x373f, 0x63},
301 {0x3740, 0x63},
302 {0x3741, 0x63},
303 {0x3742, 0x63},
304 {0x3762, 0x1c},
305 {0x3776, 0x05},
306 {0x3777, 0x22},
307 {0x3779, 0x60},
308 {0x377c, 0x48},
309 {0x3784, 0x06},
310 {0x3785, 0x0a},
311 {0x3790, 0x10},
312 {0x3793, 0x04},
313 {0x3794, 0x07},
314 {0x3796, 0x00},
315 {0x3797, 0x02},
316 {0x379c, 0x4d},
317 {0x37a1, 0x80},
318 {0x37bb, 0x88},
319 {0x37be, 0x48},
320 {0x37bf, 0x01},
321 {0x37c0, 0x01},
322 {0x37c4, 0x72},
323 {0x37c5, 0x72},
324 {0x37c6, 0x72},
325 {0x37ca, 0x21},
326 {0x37cd, 0x90},
327 {0x37cf, 0x02},
328 {0x37d0, 0x00},
329 {0x37d8, 0x01},
330 {0x37dc, 0x00},
331 {0x37dd, 0x00},
332 {0x37da, 0x00},
333 {0x37db, 0x00},
334 {0x3800, 0x00},
335 {0x3802, 0x00},
336 {0x3804, 0x0a},
337 {0x3806, 0x05},
338 {0x3808, 0x0a},
339 {0x380a, 0x05},
340 {0x3811, 0x08},
341 {0x3813, 0x08},
342 {0x3814, 0x01},
343 {0x3815, 0x01},
344 {0x3816, 0x01},
345 {0x3817, 0x01},
346 {0x3821, 0x00},
347 {0x3822, 0x14},
348 {0x3823, 0x18},
349 {0x3826, 0x00},
350 {0x3827, 0x00},
351 {0x3858, 0x3c},
352 {0x3865, 0x02},
353 {0x3866, 0x00},
354 {0x3867, 0x00},
355 {0x3868, 0x02},
356 {0x3900, 0x13},
357 {0x3940, 0x13},
358 {0x3980, 0x13},
359 {0x3c01, 0x11},
360 {0x3c05, 0x00},
361 {0x3c0f, 0x1c},
362 {0x3c12, 0x0d},
363 {0x3c19, 0x00},
364 {0x3c21, 0x00},
365 {0x3c3a, 0x10},
366 {0x3c3b, 0x18},
367 {0x3c3d, 0xc6},
368 {0x3c55, 0xcb},
369 {0x3c5d, 0xcf},
370 {0x3c5e, 0xcf},
371 {0x3d8c, 0x70},
372 {0x3d8d, 0x10},
373 {0x4000, 0xf9},
374 {0x4008, 0x02},
375 {0x4009, 0x11},
376 {0x400e, 0x40},
377 {0x4030, 0x00},
378 {0x4033, 0x80},
379 {0x4050, 0x00},
380 {0x4051, 0x07},
381 {0x4011, 0xbb},
382 {0x410f, 0x01},
383 {0x4289, 0x00},
384 {0x428a, 0x46},
385 {0x430d, 0x00},
386 {0x430e, 0x00},
387 {0x4314, 0x04},
388 {0x4500, 0x18},
389 {0x4501, 0x18},
390 {0x4503, 0x10},
391 {0x4504, 0x00},
392 {0x4506, 0x32},
393 {0x4601, 0x30},
394 {0x4603, 0x00},
395 {0x460a, 0x50},
396 {0x460c, 0x60},
397 {0x4640, 0x62},
398 {0x4646, 0xaa},
399 {0x4647, 0x55},
400 {0x4648, 0x99},
401 {0x4649, 0x66},
402 {0x464d, 0x00},
403 {0x4654, 0x11},
404 {0x4655, 0x22},
405 {0x4800, 0x44},
406 {0x4810, 0xff},
407 {0x4811, 0xff},
408 {0x481f, 0x30},
409 {0x4d00, 0x4d},
410 {0x4d01, 0x9d},
411 {0x4d02, 0xb9},
412 {0x4d03, 0x2e},
413 {0x4d04, 0x4a},
414 {0x4d05, 0x3d},
415 {0x4d09, 0x4f},
416 {0x5080, 0x00},
417 {0x50c0, 0x00},
418 {0x5100, 0x00},
419 {0x5200, 0x00},
420 {0x5201, 0x00},
421 {0x5202, 0x03},
422 {0x5203, 0xff},
423 {0x5780, 0x53},
424 {0x5786, 0x01},
425 {0x5792, 0x11},
426 {0x5793, 0x33},
427 {0x5857, 0xff},
428 {0x5858, 0xff},
429 {0x5859, 0xff},
430 {0x58d7, 0xff},
431 {0x58d8, 0xff},
432 {0x58d9, 0xff},
433 {REG_NULL, 0x00},
434 };
435
436 static const struct regval os04a10_linear10bit_2688x1520_regs[] = {
437 {0x0305, 0x3c},
438 {0x0308, 0x04},
439 {0x0317, 0x09},
440 {0x0325, 0x90},
441 {0x032e, 0x02},
442 {0x3605, 0x7f},
443 {0x3606, 0x80},
444 {0x362d, 0x0e},
445 {0x3662, 0x02},
446 {0x3667, 0xd4},
447 {0x3671, 0x08},
448 {0x3703, 0x20},
449 {0x3706, 0x72},
450 {0x370a, 0x01},
451 {0x370b, 0x14},
452 {0x3719, 0x1f},
453 {0x371b, 0x16},
454 {0x3756, 0x9d},
455 {0x3757, 0x9d},
456 {0x376c, 0x04},
457 {0x37cc, 0x13},
458 {0x37d1, 0x72},
459 {0x37d2, 0x01},
460 {0x37d3, 0x14},
461 {0x37d4, 0x00},
462 {0x37d5, 0x6c},
463 {0x37d6, 0x00},
464 {0x37d7, 0xf7},
465 {0x3801, 0x00},
466 {0x3803, 0x00},
467 {0x3805, 0x8f},
468 {0x3807, 0xff},
469 {0x3809, 0x80},
470 {0x380b, 0xf0},
471 {0x380c, 0x02},
472 {0x380d, 0xdc},
473 {0x380e, 0x0c},
474 {0x380f, 0xb0},
475 {0x381c, 0x00},
476 {0x3820, 0x00},
477 {0x3833, 0x40},
478 {0x384c, 0x02},
479 {0x384d, 0xdc},
480 {0x3c5a, 0x55},
481 {0x4004, 0x00},
482 {0x4001, 0x2f},
483 {0x4005, 0x40},
484 {0x400a, 0x06},
485 {0x400b, 0x40},
486 {0x402e, 0x00},
487 {0x402f, 0x40},
488 {0x4031, 0x40},
489 {0x4032, 0x0f},
490 {0x4288, 0xcf},
491 {0x430b, 0x0f},
492 {0x430c, 0xfc},
493 {0x4507, 0x02},
494 {0x480e, 0x00},
495 {0x4813, 0x00},
496 {0x4837, 0x0e},
497 {0x484b, 0x27},
498 {0x5000, 0x1f},
499 {0x5001, 0x0d},
500 {0x5782, 0x18},
501 {0x5783, 0x3c},
502 {0x5788, 0x18},
503 {0x5789, 0x3c},
504 {REG_NULL, 0x00},
505 };
506
507 static const struct regval os04a10_linear12bit_2688x1520_regs[] = {
508 {0x0305, 0x6c},
509 {0x0308, 0x05},
510 {0x0317, 0x0a},
511 {0x0325, 0xd8},
512 {0x032e, 0x02},
513 {0x3605, 0xff},
514 {0x3606, 0x01},
515 {0x362d, 0x09},
516 {0x3662, 0x00},
517 {0x3667, 0xd4},
518 {0x3671, 0x08},
519 {0x3703, 0x28},
520 {0x3706, 0xf0},
521 {0x370a, 0x03},
522 {0x370b, 0x15},
523 {0x3719, 0x24},
524 {0x371b, 0x1f},
525 {0x3756, 0xe7},
526 {0x3757, 0xe7},
527 {0x376c, 0x00},
528 {0x37cc, 0x15},
529 {0x37d1, 0xf0},
530 {0x37d2, 0x03},
531 {0x37d3, 0x15},
532 {0x37d4, 0x01},
533 {0x37d5, 0x00},
534 {0x37d6, 0x03},
535 {0x37d7, 0x15},
536 {0x3801, 0x00},
537 {0x3803, 0x00},
538 {0x3805, 0x8f},
539 {0x3807, 0xff},
540 {0x3809, 0x80},
541 {0x380b, 0xf0},
542 {0x380c, 0x05},
543 {0x380d, 0xc4},
544 {0x380e, 0x09},
545 {0x380f, 0x84},
546 {0x381c, 0x00},
547 {0x3820, 0x00},
548 {0x3833, 0x40},
549 {0x384c, 0x05},
550 {0x384d, 0xc4},
551 {0x3c5a, 0xe5},
552 {0x4001, 0x2f},
553 {0x4004, 0x01},
554 {0x4005, 0x00},
555 {0x400a, 0x03},
556 {0x400b, 0x27},
557 {0x402e, 0x01},
558 {0x402f, 0x00},
559 {0x4031, 0x80},
560 {0x4032, 0x9f},
561 {0x4288, 0xcf},
562 {0x430b, 0xff},
563 {0x430c, 0xff},
564 {0x4507, 0x02},
565 {0x480e, 0x00},
566 {0x4813, 0x00},
567 {0x4837, 0x0c},
568 {0x484b, 0x27},
569 {0x5000, 0x1f},
570 {0x5001, 0x0d},
571 {0x5782, 0x60},
572 {0x5783, 0xf0},
573 {0x5788, 0x60},
574 {0x5789, 0xf0},
575 {REG_NULL, 0x00},
576 };
577
578 static const struct regval os04a10_hdr10bit_2688x1520_regs[] = {
579 {0x0305, 0x3c},
580 {0x0308, 0x04},
581 {0x0317, 0x09},
582 {0x0325, 0x90},
583 {0x032e, 0x02},
584 {0x3605, 0x7f},
585 {0x3606, 0x80},
586 {0x362d, 0x0e},
587 {0x3662, 0x02},
588 {0x3667, 0x54},
589 {0x3671, 0x09},
590 {0x3703, 0x20},
591 {0x3706, 0x72},
592 {0x370a, 0x01},
593 {0x370b, 0x14},
594 {0x3719, 0x1f},
595 {0x371b, 0x16},
596 {0x3756, 0x9d},
597 {0x3757, 0x9d},
598 {0x376c, 0x04},
599 {0x37cc, 0x13},
600 {0x37d1, 0x72},
601 {0x37d2, 0x01},
602 {0x37d3, 0x14},
603 {0x37d4, 0x00},
604 {0x37d5, 0x6c},
605 {0x37d6, 0x00},
606 {0x37d7, 0xf7},
607 {0x3801, 0x00},
608 {0x3803, 0x00},
609 {0x3805, 0x8f},
610 {0x3807, 0xff},
611 {0x3809, 0x80},
612 {0x380b, 0xf0},
613 {0x380c, 0x02},
614 {0x380d, 0xdc},
615 {0x380e, 0x06},
616 {0x380f, 0x58},
617 //{0x380e, 0x0c},
618 //{0x380f, 0xb0},
619 {0x381c, 0x08},
620 {0x3820, 0x01},
621 {0x3833, 0x41},
622 {0x384c, 0x02},
623 {0x384d, 0xdc},
624 {0x3c5a, 0x55},
625 {0x4001, 0xef},
626 {0x4004, 0x00},
627 {0x4005, 0x40},
628 {0x400a, 0x06},
629 {0x400b, 0x40},
630 {0x402e, 0x00},
631 {0x402f, 0x40},
632 {0x4031, 0x40},
633 {0x4032, 0x0f},
634 {0x4288, 0xce},
635 {0x430b, 0x0f},
636 {0x430c, 0xfc},
637 {0x4507, 0x03},
638 {0x480e, 0x04},
639 {0x4813, 0x84},
640 {0x4837, 0x0e},
641 {0x484b, 0x67},
642 {0x5000, 0x1f},
643 {0x5001, 0x0c},
644 {0x5782, 0x18},
645 {0x5783, 0x3c},
646 {0x5788, 0x18},
647 {0x5789, 0x3c},
648 {REG_NULL, 0x00},
649 };
650
651 static const struct regval os04a10_hdr12bit_2688x1520_regs[] = {
652 {0x0305, 0x6c},
653 {0x0308, 0x05},
654 {0x0317, 0x0a},
655 {0x0325, 0xd8},
656 {0x032e, 0x05},
657 {0x3605, 0xff},
658 {0x3606, 0x01},
659 {0x362d, 0x09},
660 {0x3662, 0x00},
661 {0x3667, 0x54},
662 {0x3671, 0x09},
663 {0x3703, 0x28},
664 {0x3706, 0xf0},
665 {0x370a, 0x03},
666 {0x370b, 0x15},
667 {0x3719, 0x24},
668 {0x371b, 0x1f},
669 {0x3756, 0xe7},
670 {0x3757, 0xe7},
671 {0x376c, 0x00},
672 {0x37cc, 0x15},
673 {0x37d1, 0xf0},
674 {0x37d2, 0x03},
675 {0x37d3, 0x15},
676 {0x37d4, 0x01},
677 {0x37d5, 0x00},
678 {0x37d6, 0x03},
679 {0x37d7, 0x15},
680 {0x3801, 0x00},
681 {0x3803, 0x00},
682 {0x3805, 0x8f},
683 {0x3807, 0xff},
684 {0x3809, 0x80},
685 {0x380b, 0xf0},
686 {0x380c, 0x05},
687 {0x380d, 0xc4},
688 {0x380e, 0x06},
689 {0x380f, 0x58},
690 {0x381c, 0x08},
691 {0x3820, 0x01},
692 {0x3833, 0x41},
693 {0x384c, 0x05},
694 {0x384d, 0xc4},
695 {0x3c5a, 0xe5},
696 {0x4001, 0xef},
697 {0x4004, 0x01},
698 {0x4005, 0x00},
699 {0x400a, 0x03},
700 {0x400b, 0x27},
701 {0x402e, 0x01},
702 {0x402f, 0x00},
703 {0x4031, 0x80},
704 {0x4032, 0x9f},
705 {0x4288, 0xce},
706 {0x430b, 0xff},
707 {0x430c, 0xff},
708 {0x4507, 0x03},
709 {0x480e, 0x04},
710 {0x4813, 0x84},
711 {0x4837, 0x0c},
712 {0x484b, 0x67},
713 {0x5000, 0x7f},
714 {0x5001, 0x0c},
715 {0x5782, 0x60},
716 {0x5783, 0xf0},
717 {0x5788, 0x60},
718 {0x5789, 0xf0},
719 {REG_NULL, 0x00},
720 };
721
722 static const struct regval os04a10_hdr12bit_2560x1440_regs[] = {
723 {0x0305, 0x6c},
724 {0x0308, 0x05},
725 {0x0317, 0x0a},
726 {0x0325, 0xd8},
727 {0x032e, 0x05},
728 {0x3605, 0xff},
729 {0x3606, 0x01},
730 {0x362d, 0x09},
731 {0x3662, 0x00},
732 {0x3667, 0x54},
733 {0x3671, 0x09},
734 {0x3703, 0x28},
735 {0x3706, 0xf0},
736 {0x370a, 0x03},
737 {0x370b, 0x15},
738 {0x3719, 0x24},
739 {0x371b, 0x1f},
740 {0x3756, 0xe7},
741 {0x3757, 0xe7},
742 {0x376c, 0x00},
743 {0x37cc, 0x15},
744 {0x37d1, 0xf0},
745 {0x37d2, 0x03},
746 {0x37d3, 0x15},
747 {0x37d4, 0x01},
748 {0x37d5, 0x00},
749 {0x37d6, 0x03},
750 {0x37d7, 0x15},
751 {0x3801, 0x40},
752 {0x3803, 0x28},
753 {0x3805, 0x4f},
754 {0x3807, 0xd7},
755 {0x3809, 0x00},
756 {0x380b, 0xa0},
757 {0x380c, 0x05},
758 {0x380d, 0xa0},
759 {0x380e, 0x05},
760 {0x380f, 0xdc},
761 {0x381c, 0x08},
762 {0x3820, 0x01},
763 {0x3833, 0x41},
764 {0x384c, 0x05},
765 {0x384d, 0xa0},
766 {0x3c5a, 0xe5},
767 {0x4001, 0xef},
768 {0x4004, 0x00},
769 {0x4005, 0x80},
770 {0x400a, 0x03},
771 {0x400b, 0x27},
772 {0x402e, 0x00},
773 {0x402f, 0x80},
774 {0x4031, 0x80},
775 {0x4032, 0x9f},
776 {0x4288, 0xce},
777 {0x430b, 0xff},
778 {0x430c, 0xff},
779 {0x4507, 0x03},
780 {0x480e, 0x04},
781 {0x4813, 0x84},
782 {0x4837, 0x0c},
783 {0x484b, 0x67},
784 {0x5000, 0x7f},
785 {0x5001, 0x0c},
786 {0x5782, 0x60},
787 {0x5783, 0xf0},
788 {0x5788, 0x60},
789 {0x5789, 0xf0},
790 {REG_NULL, 0x00},
791 };
792
793 static const struct regval os04a10_global_regs_2lane[] = {
794 {0x0109, 0x01},
795 {0x0104, 0x02},
796 {0x0102, 0x00},
797 {0x0306, 0x00},
798 {0x0307, 0x00},
799 {0x0308, 0x04},
800 {0x030a, 0x01},
801 {0x0317, 0x09},
802 {0x0322, 0x01},
803 {0x0323, 0x02},
804 {0x0324, 0x00},
805 {0x0327, 0x05},
806 {0x0329, 0x02},
807 {0x032c, 0x02},
808 {0x032d, 0x02},
809 {0x032e, 0x02},
810 {0x300f, 0x11},
811 {0x3012, 0x21},
812 {0x3026, 0x10},
813 {0x3027, 0x08},
814 {0x302d, 0x24},
815 {0x3104, 0x01},
816 {0x3106, 0x11},
817 {0x3400, 0x00},
818 {0x3408, 0x05},
819 {0x340c, 0x0c},
820 {0x340d, 0xb0},
821 {0x3425, 0x51},
822 {0x3426, 0x10},
823 {0x3427, 0x14},
824 {0x3428, 0x10},
825 {0x3429, 0x10},
826 {0x342a, 0x10},
827 {0x342b, 0x04},
828 {0x3501, 0x02},
829 {0x3504, 0x08},
830 {0x3508, 0x01},
831 {0x3509, 0x00},
832 {0x350a, 0x01},
833 {0x3544, 0x08},
834 {0x3548, 0x01},
835 {0x3549, 0x00},
836 {0x3584, 0x08},
837 {0x3588, 0x01},
838 {0x3589, 0x00},
839 {0x3601, 0x70},
840 {0x3604, 0xe3},
841 {0x3605, 0x7f},
842 {0x3606, 0x80},
843 {0x3608, 0xa8},
844 {0x360a, 0xd0},
845 {0x360b, 0x08},
846 {0x360e, 0xc8},
847 {0x360f, 0x66},
848 {0x3610, 0x89},
849 {0x3611, 0x8a},
850 {0x3612, 0x4e},
851 {0x3613, 0xbd},
852 {0x3614, 0x9b},
853 {0x362a, 0x0e},
854 {0x362b, 0x0e},
855 {0x362c, 0x0e},
856 {0x362d, 0x0e},
857 {0x362e, 0x1a},
858 {0x362f, 0x34},
859 {0x3630, 0x67},
860 {0x3631, 0x7f},
861 {0x3638, 0x00},
862 {0x3643, 0x00},
863 {0x3644, 0x00},
864 {0x3645, 0x00},
865 {0x3646, 0x00},
866 {0x3647, 0x00},
867 {0x3648, 0x00},
868 {0x3649, 0x00},
869 {0x364a, 0x04},
870 {0x364c, 0x0e},
871 {0x364d, 0x0e},
872 {0x364e, 0x0e},
873 {0x364f, 0x0e},
874 {0x3650, 0xff},
875 {0x3651, 0xff},
876 {0x365a, 0x00},
877 {0x365b, 0x00},
878 {0x365c, 0x00},
879 {0x365d, 0x00},
880 {0x3661, 0x07},
881 {0x3662, 0x02},
882 {0x3663, 0x20},
883 {0x3665, 0x12},
884 {0x3668, 0x80},
885 {0x366c, 0x00},
886 {0x366d, 0x00},
887 {0x366e, 0x00},
888 {0x366f, 0x00},
889 {0x3673, 0x2a},
890 {0x3681, 0x80},
891 {0x3700, 0x2d},
892 {0x3701, 0x22},
893 {0x3702, 0x25},
894 {0x3703, 0x20},
895 {0x3705, 0x00},
896 {0x3706, 0x72},
897 {0x3707, 0x0a},
898 {0x3708, 0x36},
899 {0x3709, 0x57},
900 {0x370a, 0x01},
901 {0x370b, 0x14},
902 {0x3714, 0x01},
903 {0x3719, 0x1f},
904 {0x371b, 0x16},
905 {0x371c, 0x00},
906 {0x371d, 0x08},
907 {0x373f, 0x63},
908 {0x3740, 0x63},
909 {0x3741, 0x63},
910 {0x3742, 0x63},
911 {0x3743, 0x01},
912 {0x3756, 0x9d},
913 {0x3757, 0x9d},
914 {0x3762, 0x1c},
915 {0x3673, 0x2a},
916 {0x3681, 0x80},
917 {0x3700, 0x2d},
918 {0x3701, 0x22},
919 {0x3702, 0x25},
920 {0x3703, 0x20},
921 {0x3705, 0x00},
922 {0x3706, 0x72},
923 {0x3707, 0x0a},
924 {0x3708, 0x36},
925 {0x3709, 0x57},
926 {0x370a, 0x01},
927 {0x370b, 0x14},
928 {0x3714, 0x01},
929 {0x3719, 0x1f},
930 {0x371b, 0x16},
931 {0x371c, 0x00},
932 {0x371d, 0x08},
933 {0x373f, 0x63},
934 {0x3740, 0x63},
935 {0x3741, 0x63},
936 {0x3742, 0x63},
937 {0x3743, 0x01},
938 {0x3756, 0x9d},
939 {0x3757, 0x9d},
940 {0x3762, 0x1c},
941 {0x3776, 0x05},
942 {0x3777, 0x22},
943 {0x3779, 0x60},
944 {0x377c, 0x48},
945 {0x3784, 0x06},
946 {0x3785, 0x0a},
947 {0x3790, 0x10},
948 {0x3793, 0x04},
949 {0x3794, 0x07},
950 {0x3796, 0x00},
951 {0x3797, 0x02},
952 {0x379c, 0x4d},
953 {0x37a1, 0x80},
954 {0x37bb, 0x88},
955 {0x37be, 0x48},
956 {0x37bf, 0x01},
957 {0x37c0, 0x01},
958 {0x37c4, 0x72},
959 {0x37c5, 0x72},
960 {0x37c6, 0x72},
961 {0x37ca, 0x21},
962 {0x37cc, 0x13},
963 {0x37cd, 0x90},
964 {0x37cf, 0x02},
965 {0x37d0, 0x00},
966 {0x37d1, 0x72},
967 {0x37d2, 0x01},
968 {0x37d3, 0x14},
969 {0x37d4, 0x00},
970 {0x37d5, 0x6c},
971 {0x37d6, 0x00},
972 {0x37d7, 0xf7},
973 {0x37d8, 0x01},
974 {0x37dc, 0x00},
975 {0x37dd, 0x00},
976 {0x37da, 0x00},
977 {0x37db, 0x00},
978 {0x3800, 0x00},
979 {0x3801, 0x00},
980 {0x3802, 0x00},
981 {0x3803, 0x00},
982 {0x3804, 0x0a},
983 {0x3805, 0x8f},
984 {0x3806, 0x05},
985 {0x3807, 0xff},
986 {0x3808, 0x0a},
987 {0x3809, 0x80},
988 {0x380a, 0x05},
989 {0x380b, 0xf0},
990 {0x380e, 0x06},
991 {0x380f, 0x58},
992 {0x3811, 0x08},
993 {0x3813, 0x08},
994 {0x3814, 0x01},
995 {0x3815, 0x01},
996 {0x3816, 0x01},
997 {0x3817, 0x01},
998 {0x3821, 0x00},
999 {0x3822, 0x14},
1000 {0x3823, 0x18},
1001 {0x3826, 0x00},
1002 {0x3827, 0x00},
1003 {0x384c, 0x02},
1004 {0x384d, 0xdc},
1005 {0x3858, 0x3c},
1006 {0x3865, 0x02},
1007 {0x3866, 0x00},
1008 {0x3867, 0x00},
1009 {0x3868, 0x02},
1010 {0x3900, 0x13},
1011 {0x3940, 0x13},
1012 {0x3980, 0x13},
1013 {0x3c01, 0x11},
1014 {0x3c05, 0x00},
1015 {0x3c0f, 0x1c},
1016 {0x3c12, 0x0d},
1017 {0x3c19, 0x00},
1018 {0x3c21, 0x00},
1019 {0x3c3a, 0x10},
1020 {0x3c3b, 0x18},
1021 {0x3c3d, 0xc6},
1022 {0x3c5a, 0x55},
1023 {0x3c5d, 0xcf},
1024 {0x3c5e, 0xcf},
1025 {0x3d8c, 0x70},
1026 {0x3d8d, 0x10},
1027 {0x4000, 0xf9},
1028 {0x4004, 0x00},
1029 {0x4005, 0x40},
1030 {0x4008, 0x02},
1031 {0x4009, 0x11},
1032 {0x400a, 0x06},
1033 {0x400b, 0x40},
1034 {0x400e, 0x40},
1035 {0x402e, 0x00},
1036 {0x402f, 0x40},
1037 {0x4030, 0x00},
1038 {0x4031, 0x40},
1039 {0x4032, 0x0f},
1040 {0x4033, 0x80},
1041 {0x4050, 0x00},
1042 {0x4051, 0x07},
1043 {0x4011, 0xbb},
1044 {0x410f, 0x01},
1045 {0x4289, 0x00},
1046 {0x428a, 0x46},
1047 {0x430b, 0x0f},
1048 {0x430c, 0xfc},
1049 {0x430d, 0x00},
1050 {0x430e, 0x00},
1051 {0x4314, 0x04},
1052 {0x4500, 0x18},
1053 {0x4501, 0x18},
1054 {0x4503, 0x10},
1055 {0x4504, 0x00},
1056 {0x4506, 0x32},
1057 {0x4601, 0x30},
1058 {0x4603, 0x00},
1059 {0x460a, 0x50},
1060 {0x460c, 0x60},
1061 {0x4640, 0x62},
1062 {0x4646, 0xaa},
1063 {0x4647, 0x55},
1064 {0x4648, 0x99},
1065 {0x4649, 0x66},
1066 {0x464d, 0x00},
1067 {0x4654, 0x11},
1068 {0x4655, 0x22},
1069 {0x4800, 0x44},
1070 {0x4810, 0xff},
1071 {0x4811, 0xff},
1072 {0x481f, 0x30},
1073 {0x4d00, 0x4d},
1074 {0x4d01, 0x9d},
1075 {0x4d02, 0xb9},
1076 {0x4d03, 0x2e},
1077 {0x4d04, 0x4a},
1078 {0x4d05, 0x3d},
1079 {0x4d09, 0x4f},
1080 {0x5000, 0x1f},
1081 {0x5080, 0x00},
1082 {0x50c0, 0x00},
1083 {0x5100, 0x00},
1084 {0x5200, 0x00},
1085 {0x5201, 0x00},
1086 {0x5202, 0x03},
1087 {0x5203, 0xff},
1088 {0x5780, 0x53},
1089 {0x5782, 0x18},
1090 {0x5783, 0x3c},
1091 {0x5786, 0x01},
1092 {0x5788, 0x18},
1093 {0x5789, 0x3c},
1094 {0x5792, 0x11},
1095 {0x5793, 0x33},
1096 {0x5857, 0xff},
1097 {0x5858, 0xff},
1098 {0x5859, 0xff},
1099 {0x58d7, 0xff},
1100 {0x58d8, 0xff},
1101 {0x58d9, 0xff},
1102 {REG_NULL, 0x00},
1103 };
1104
1105 static const struct regval os04a10_linear10bit_2688x1520_regs_2lane[] = {
1106 {0x0305, 0x5c},
1107 {0x0325, 0xd8},
1108 {0x3667, 0xd4},
1109 {0x3671, 0x08},
1110 {0x376c, 0x14},
1111 {0x380c, 0x08},
1112 {0x380d, 0x94},
1113 {0x381c, 0x00},
1114 {0x3820, 0x02},
1115 {0x3833, 0x40},
1116 {0x3c55, 0x08},
1117 {0x4001, 0x2f},
1118 {0x4288, 0xcf},
1119 {0x4507, 0x02},
1120 {0x480e, 0x00},
1121 {0x4813, 0x00},
1122 {0x4837, 0x0e},
1123 {0x484b, 0x27},
1124 {0x5001, 0x0d},
1125 {REG_NULL, 0x00},
1126 };
1127
1128 static const struct regval os04a10_hdr10bit_2688x1520_regs_2lane[] = {
1129 {0x0305, 0x78},
1130 {0x0325, 0x90},
1131 {0x3667, 0x54},
1132 {0x3671, 0x09},
1133 {0x376c, 0x04},
1134 {0x380c, 0x02},
1135 {0x380d, 0xdc},
1136 {0x381c, 0x08},
1137 {0x3820, 0x03},
1138 {0x3833, 0x41},
1139 {0x3c55, 0xcb},
1140 {0x4001, 0xef},
1141 {0x4288, 0xce},
1142 {0x4507, 0x03},
1143 {0x480e, 0x04},
1144 {0x4813, 0x84},
1145 {0x4837, 0x07},
1146 {0x484b, 0x67},
1147 {0x4883, 0x05},
1148 {0x4884, 0x08},
1149 {0x4885, 0x03},
1150 {0x5001, 0x0c},
1151 {REG_NULL, 0x00},
1152 };
1153
1154 /*
1155 * The width and height must be configured to be
1156 * the same as the current output resolution of the sensor.
1157 * The input width of the isp needs to be 16 aligned.
1158 * The input height of the isp needs to be 8 aligned.
1159 * If the width or height does not meet the alignment rules,
1160 * you can configure the cropping parameters with the following function to
1161 * crop out the appropriate resolution.
1162 * struct v4l2_subdev_pad_ops {
1163 * .get_selection
1164 * }
1165 */
1166 static const struct os04a10_mode supported_modes[] = {
1167 {
1168 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1169 .width = 2688,
1170 .height = 1520,
1171 .max_fps = {
1172 .numerator = 10000,
1173 .denominator = 302834,
1174 },
1175 .exp_def = 0x0240,
1176 .hts_def = 0x02dc * 4,
1177 .vts_def = 0x0cb0,
1178 .global_reg_list = os04a10_global_regs,
1179 .reg_list = os04a10_linear10bit_2688x1520_regs,
1180 .hdr_mode = NO_HDR,
1181 .link_freq_idx = 0,
1182 .bpp = 10,
1183 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1184 },
1185 {
1186 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1187 .width = 2688,
1188 .height = 1520,
1189 .max_fps = {
1190 .numerator = 10000,
1191 .denominator = 302834,
1192 /*.denominator = 151417,*/
1193 },
1194 .exp_def = 0x0240,
1195 .hts_def = 0x02dc * 4,
1196 .vts_def = 0x0658,
1197 /*.vts_def = 0x0cb0,*/
1198 .global_reg_list = os04a10_global_regs,
1199 .reg_list = os04a10_hdr10bit_2688x1520_regs,
1200 .hdr_mode = HDR_X2,
1201 .link_freq_idx = 0,
1202 .bpp = 10,
1203 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
1204 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
1205 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
1206 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
1207 },
1208 {
1209 .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
1210 .width = 2688,
1211 .height = 1520,
1212 .max_fps = {
1213 .numerator = 10000,
1214 .denominator = 300372,
1215 },
1216 .exp_def = 0x0240,
1217 .hts_def = 0x05c4 * 2,
1218 .vts_def = 0x0984,
1219 .global_reg_list = os04a10_global_regs,
1220 .reg_list = os04a10_linear12bit_2688x1520_regs,
1221 .hdr_mode = NO_HDR,
1222 .link_freq_idx = 1,
1223 .bpp = 12,
1224 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1225 },
1226 {
1227 .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
1228 .width = 2688,
1229 .height = 1520,
1230 .max_fps = {
1231 .numerator = 10000,
1232 .denominator = 225000,
1233 },
1234 .exp_def = 0x0240,
1235 .hts_def = 0x05c4 * 2,
1236 .vts_def = 0x0658,
1237 .global_reg_list = os04a10_global_regs,
1238 .reg_list = os04a10_hdr12bit_2688x1520_regs,
1239 .hdr_mode = HDR_X2,
1240 .link_freq_idx = 1,
1241 .bpp = 12,
1242 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
1243 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
1244 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
1245 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
1246 },
1247 {
1248 .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
1249 .width = 2560,
1250 .height = 1440,
1251 .max_fps = {
1252 .numerator = 10000,
1253 .denominator = 250000,
1254 },
1255 .exp_def = 0x0200,
1256 .hts_def = 0x05a0 * 2,
1257 .vts_def = 0x05dc,
1258 .global_reg_list = os04a10_global_regs,
1259 .reg_list = os04a10_hdr12bit_2560x1440_regs,
1260 .hdr_mode = HDR_X2,
1261 .link_freq_idx = 1,
1262 .bpp = 12,
1263 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
1264 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
1265 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
1266 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
1267 },
1268 };
1269
1270 static const struct os04a10_mode supported_modes_2lane[] = {
1271 {
1272 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1273 .width = 2688,
1274 .height = 1520,
1275 .max_fps = {
1276 .numerator = 10000,
1277 .denominator = 302834,
1278 },
1279 .exp_def = 0x0640,
1280 .hts_def = 0x0894,
1281 .vts_def = 0x0658,
1282 .global_reg_list = os04a10_global_regs_2lane,
1283 .reg_list = os04a10_linear10bit_2688x1520_regs_2lane,
1284 .hdr_mode = NO_HDR,
1285 .link_freq_idx = 0,
1286 .bpp = 10,
1287 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1288 },
1289 {
1290 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1291 .width = 2688,
1292 .height = 1520,
1293 .max_fps = {
1294 .numerator = 10000,
1295 .denominator = 302834,
1296 /*.denominator = 151417,*/
1297 },
1298 .exp_def = 0x0640,
1299 .hts_def = 0x02dc * 4,
1300 .vts_def = 0x0658,
1301 /*.vts_def = 0x0cb0,*/
1302 .global_reg_list = os04a10_global_regs_2lane,
1303 .reg_list = os04a10_hdr10bit_2688x1520_regs_2lane,
1304 .hdr_mode = HDR_X2,
1305 .link_freq_idx = 2,
1306 .bpp = 10,
1307 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
1308 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
1309 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
1310 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
1311 },
1312 };
1313
1314 static const s64 link_freq_menu_items[] = {
1315 MIPI_FREQ_360M,
1316 MIPI_FREQ_648M,
1317 MIPI_FREQ_720M,
1318 };
1319
1320 static const char * const os04a10_test_pattern_menu[] = {
1321 "Disabled",
1322 "Vertical Color Bar Type 1",
1323 "Vertical Color Bar Type 2",
1324 "Vertical Color Bar Type 3",
1325 "Vertical Color Bar Type 4"
1326 };
1327
1328 static int __os04a10_power_on(struct os04a10 *os04a10);
1329
1330 /* Write registers up to 4 at a time */
os04a10_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)1331 static int os04a10_write_reg(struct i2c_client *client, u16 reg,
1332 u32 len, u32 val)
1333 {
1334 u32 buf_i, val_i;
1335 u8 buf[6];
1336 u8 *val_p;
1337 __be32 val_be;
1338
1339 if (len > 4)
1340 return -EINVAL;
1341
1342 buf[0] = reg >> 8;
1343 buf[1] = reg & 0xff;
1344
1345 val_be = cpu_to_be32(val);
1346 val_p = (u8 *)&val_be;
1347 buf_i = 2;
1348 val_i = 4 - len;
1349
1350 while (val_i < 4)
1351 buf[buf_i++] = val_p[val_i++];
1352
1353 if (i2c_master_send(client, buf, len + 2) != len + 2)
1354 return -EIO;
1355
1356 return 0;
1357 }
1358
os04a10_write_array(struct i2c_client * client,const struct regval * regs)1359 static int os04a10_write_array(struct i2c_client *client,
1360 const struct regval *regs)
1361 {
1362 u32 i;
1363 int ret = 0;
1364
1365 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
1366 ret |= os04a10_write_reg(client, regs[i].addr,
1367 OS04A10_REG_VALUE_08BIT, regs[i].val);
1368 }
1369 return ret;
1370 }
1371
1372 /* Read registers up to 4 at a time */
os04a10_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)1373 static int os04a10_read_reg(struct i2c_client *client,
1374 u16 reg,
1375 unsigned int len,
1376 u32 *val)
1377 {
1378 struct i2c_msg msgs[2];
1379 u8 *data_be_p;
1380 __be32 data_be = 0;
1381 __be16 reg_addr_be = cpu_to_be16(reg);
1382 int ret;
1383
1384 if (len > 4 || !len)
1385 return -EINVAL;
1386
1387 data_be_p = (u8 *)&data_be;
1388 /* Write register address */
1389 msgs[0].addr = client->addr;
1390 msgs[0].flags = 0;
1391 msgs[0].len = 2;
1392 msgs[0].buf = (u8 *)®_addr_be;
1393
1394 /* Read data from register */
1395 msgs[1].addr = client->addr;
1396 msgs[1].flags = I2C_M_RD;
1397 msgs[1].len = len;
1398 msgs[1].buf = &data_be_p[4 - len];
1399
1400 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1401 if (ret != ARRAY_SIZE(msgs))
1402 return -EIO;
1403
1404 *val = be32_to_cpu(data_be);
1405
1406 return 0;
1407 }
1408
os04a10_get_reso_dist(const struct os04a10_mode * mode,struct v4l2_mbus_framefmt * framefmt)1409 static int os04a10_get_reso_dist(const struct os04a10_mode *mode,
1410 struct v4l2_mbus_framefmt *framefmt)
1411 {
1412 return abs(mode->width - framefmt->width) +
1413 abs(mode->height - framefmt->height);
1414 }
1415
1416 static const struct os04a10_mode *
os04a10_find_best_fit(struct os04a10 * os04a10,struct v4l2_subdev_format * fmt)1417 os04a10_find_best_fit(struct os04a10 *os04a10, struct v4l2_subdev_format *fmt)
1418 {
1419 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1420 int dist;
1421 int cur_best_fit = 0;
1422 int cur_best_fit_dist = -1;
1423 unsigned int i;
1424
1425 for (i = 0; i < os04a10->cfg_num; i++) {
1426 dist = os04a10_get_reso_dist(&os04a10->supported_modes[i], framefmt);
1427 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
1428 (os04a10->supported_modes[i].bus_fmt == framefmt->code)) {
1429 cur_best_fit_dist = dist;
1430 cur_best_fit = i;
1431 }
1432 }
1433
1434 return &os04a10->supported_modes[cur_best_fit];
1435 }
1436
os04a10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1437 static int os04a10_set_fmt(struct v4l2_subdev *sd,
1438 struct v4l2_subdev_pad_config *cfg,
1439 struct v4l2_subdev_format *fmt)
1440 {
1441 struct os04a10 *os04a10 = to_os04a10(sd);
1442 const struct os04a10_mode *mode;
1443 s64 h_blank, vblank_def;
1444 u64 dst_link_freq = 0;
1445 u64 dst_pixel_rate = 0;
1446 u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
1447
1448 mutex_lock(&os04a10->mutex);
1449
1450 mode = os04a10_find_best_fit(os04a10, fmt);
1451 fmt->format.code = mode->bus_fmt;
1452 fmt->format.width = mode->width;
1453 fmt->format.height = mode->height;
1454 fmt->format.field = V4L2_FIELD_NONE;
1455 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1456 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1457 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1458 #else
1459 mutex_unlock(&os04a10->mutex);
1460 return -ENOTTY;
1461 #endif
1462 } else {
1463 os04a10->cur_mode = mode;
1464 h_blank = mode->hts_def - mode->width;
1465 __v4l2_ctrl_modify_range(os04a10->hblank, h_blank,
1466 h_blank, 1, h_blank);
1467 vblank_def = mode->vts_def - mode->height;
1468 __v4l2_ctrl_modify_range(os04a10->vblank, vblank_def,
1469 OS04A10_VTS_MAX - mode->height,
1470 1, vblank_def);
1471 dst_link_freq = mode->link_freq_idx;
1472 dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1473 mode->bpp * 2 * lanes;
1474 __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
1475 dst_pixel_rate);
1476 __v4l2_ctrl_s_ctrl(os04a10->link_freq,
1477 dst_link_freq);
1478 }
1479
1480 mutex_unlock(&os04a10->mutex);
1481
1482 return 0;
1483 }
1484
os04a10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1485 static int os04a10_get_fmt(struct v4l2_subdev *sd,
1486 struct v4l2_subdev_pad_config *cfg,
1487 struct v4l2_subdev_format *fmt)
1488 {
1489 struct os04a10 *os04a10 = to_os04a10(sd);
1490 const struct os04a10_mode *mode = os04a10->cur_mode;
1491
1492 mutex_lock(&os04a10->mutex);
1493 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1494 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1495 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1496 #else
1497 mutex_unlock(&os04a10->mutex);
1498 return -ENOTTY;
1499 #endif
1500 } else {
1501 fmt->format.width = mode->width;
1502 fmt->format.height = mode->height;
1503 fmt->format.code = mode->bus_fmt;
1504 fmt->format.field = V4L2_FIELD_NONE;
1505 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
1506 fmt->reserved[0] = mode->vc[fmt->pad];
1507 else
1508 fmt->reserved[0] = mode->vc[PAD0];
1509 }
1510 mutex_unlock(&os04a10->mutex);
1511
1512 return 0;
1513 }
1514
os04a10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1515 static int os04a10_enum_mbus_code(struct v4l2_subdev *sd,
1516 struct v4l2_subdev_pad_config *cfg,
1517 struct v4l2_subdev_mbus_code_enum *code)
1518 {
1519 struct os04a10 *os04a10 = to_os04a10(sd);
1520
1521 if (code->index != 0)
1522 return -EINVAL;
1523 code->code = os04a10->cur_mode->bus_fmt;
1524
1525 return 0;
1526 }
1527
os04a10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1528 static int os04a10_enum_frame_sizes(struct v4l2_subdev *sd,
1529 struct v4l2_subdev_pad_config *cfg,
1530 struct v4l2_subdev_frame_size_enum *fse)
1531 {
1532 struct os04a10 *os04a10 = to_os04a10(sd);
1533
1534 if (fse->index >= os04a10->cfg_num)
1535 return -EINVAL;
1536
1537 if (fse->code != os04a10->supported_modes[fse->index].bus_fmt)
1538 return -EINVAL;
1539
1540 fse->min_width = os04a10->supported_modes[fse->index].width;
1541 fse->max_width = os04a10->supported_modes[fse->index].width;
1542 fse->max_height = os04a10->supported_modes[fse->index].height;
1543 fse->min_height = os04a10->supported_modes[fse->index].height;
1544
1545 return 0;
1546 }
1547
os04a10_enable_test_pattern(struct os04a10 * os04a10,u32 pattern)1548 static int os04a10_enable_test_pattern(struct os04a10 *os04a10, u32 pattern)
1549 {
1550 u32 val;
1551 int ret = 0;
1552
1553 if (pattern)
1554 val = ((pattern - 1) << 2) | OS04A10_TEST_PATTERN_ENABLE;
1555 else
1556 val = OS04A10_TEST_PATTERN_DISABLE;
1557 ret = os04a10_write_reg(os04a10->client, OS04A10_REG_TEST_PATTERN,
1558 OS04A10_REG_VALUE_08BIT, val);
1559 ret |= os04a10_write_reg(os04a10->client, OS04A10_REG_TEST_PATTERN + 0x40,
1560 OS04A10_REG_VALUE_08BIT, val);
1561 return ret;
1562 }
1563
os04a10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1564 static int os04a10_g_frame_interval(struct v4l2_subdev *sd,
1565 struct v4l2_subdev_frame_interval *fi)
1566 {
1567 struct os04a10 *os04a10 = to_os04a10(sd);
1568 const struct os04a10_mode *mode = os04a10->cur_mode;
1569
1570 fi->interval = mode->max_fps;
1571
1572 return 0;
1573 }
1574
os04a10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1575 static int os04a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1576 struct v4l2_mbus_config *config)
1577 {
1578 struct os04a10 *os04a10 = to_os04a10(sd);
1579 const struct os04a10_mode *mode = os04a10->cur_mode;
1580 u32 val = 0;
1581 u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
1582
1583 if (mode->hdr_mode == NO_HDR)
1584 val = 1 << (lanes - 1) |
1585 V4L2_MBUS_CSI2_CHANNEL_0 |
1586 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1587 if (mode->hdr_mode == HDR_X2)
1588 val = 1 << (lanes - 1) |
1589 V4L2_MBUS_CSI2_CHANNEL_0 |
1590 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
1591 V4L2_MBUS_CSI2_CHANNEL_1;
1592
1593 config->type = V4L2_MBUS_CSI2_DPHY;
1594 config->flags = val;
1595
1596 return 0;
1597 }
1598
os04a10_get_module_inf(struct os04a10 * os04a10,struct rkmodule_inf * inf)1599 static void os04a10_get_module_inf(struct os04a10 *os04a10,
1600 struct rkmodule_inf *inf)
1601 {
1602 memset(inf, 0, sizeof(*inf));
1603 strscpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor));
1604 strscpy(inf->base.module, os04a10->module_name,
1605 sizeof(inf->base.module));
1606 strscpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens));
1607 }
1608
os04a10_set_hdrae(struct os04a10 * os04a10,struct preisp_hdrae_exp_s * ae)1609 static int os04a10_set_hdrae(struct os04a10 *os04a10,
1610 struct preisp_hdrae_exp_s *ae)
1611 {
1612 u32 l_exp_time, m_exp_time, s_exp_time;
1613 u32 l_a_gain, m_a_gain, s_a_gain;
1614 u32 l_d_gain = 1024;
1615 u32 m_d_gain = 1024;
1616 u32 s_d_gain = 1024;
1617 int ret = 0;
1618 u8 l_cg_mode = 0;
1619 u8 m_cg_mode = 0;
1620 u8 s_cg_mode = 0;
1621 u32 gain_switch = 0;
1622 u8 is_need_switch = 0;
1623
1624 if (!os04a10->has_init_exp && !os04a10->streaming) {
1625 os04a10->init_hdrae_exp = *ae;
1626 os04a10->has_init_exp = true;
1627 if (os04a10->init_hdrae_exp.short_exp_reg >= 0x90) {
1628 dev_err(&os04a10->client->dev, "short exposure must less than 0x90 before start stream!\n");
1629 return -EINVAL;
1630 }
1631 dev_dbg(&os04a10->client->dev, "os04a10 don't stream, record exp for hdr!\n");
1632 return ret;
1633 }
1634 l_exp_time = ae->long_exp_reg;
1635 m_exp_time = ae->middle_exp_reg;
1636 s_exp_time = ae->short_exp_reg;
1637 l_a_gain = ae->long_gain_reg;
1638 m_a_gain = ae->middle_gain_reg;
1639 s_a_gain = ae->short_gain_reg;
1640 l_cg_mode = ae->long_cg_mode;
1641 m_cg_mode = ae->middle_cg_mode;
1642 s_cg_mode = ae->short_cg_mode;
1643 dev_dbg(&os04a10->client->dev,
1644 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
1645 l_exp_time, l_a_gain,
1646 m_exp_time, m_a_gain,
1647 s_exp_time, s_a_gain);
1648
1649 if (os04a10->cur_mode->hdr_mode == HDR_X2) {
1650 //2 stagger
1651 l_a_gain = m_a_gain;
1652 l_exp_time = m_exp_time;
1653 l_cg_mode = m_cg_mode;
1654 m_a_gain = s_a_gain;
1655 m_exp_time = s_exp_time;
1656 m_cg_mode = s_cg_mode;
1657 }
1658 ret = os04a10_read_reg(os04a10->client, OS04A10_REG_HCG_SWITCH,
1659 OS04A10_REG_VALUE_08BIT, &gain_switch);
1660
1661 if (os04a10->long_hcg && l_cg_mode == GAIN_MODE_LCG) {
1662 gain_switch |= 0x10;
1663 os04a10->long_hcg = false;
1664 is_need_switch++;
1665 } else if (!os04a10->long_hcg && l_cg_mode == GAIN_MODE_HCG) {
1666 gain_switch &= 0xef;
1667 os04a10->long_hcg = true;
1668 is_need_switch++;
1669 }
1670 if (os04a10->middle_hcg && m_cg_mode == GAIN_MODE_LCG) {
1671 gain_switch |= 0x20;
1672 os04a10->middle_hcg = false;
1673 is_need_switch++;
1674 } else if (!os04a10->middle_hcg && m_cg_mode == GAIN_MODE_HCG) {
1675 gain_switch &= 0xdf;
1676 os04a10->middle_hcg = true;
1677 is_need_switch++;
1678 }
1679 if (l_a_gain > 248) {
1680 l_d_gain = l_a_gain * 1024 / 248;
1681 l_a_gain = 248;
1682 }
1683 if (m_a_gain > 248) {
1684 m_d_gain = m_a_gain * 1024 / 248;
1685 m_a_gain = 248;
1686 }
1687 if (os04a10->cur_mode->hdr_mode == HDR_X3 && s_a_gain > 248) {
1688 s_d_gain = s_a_gain * 1024 / 248;
1689 s_a_gain = 248;
1690 }
1691
1692 ret |= os04a10_write_reg(os04a10->client,
1693 OS04A10_GROUP_UPDATE_ADDRESS,
1694 OS04A10_REG_VALUE_08BIT,
1695 OS04A10_GROUP_UPDATE_START_DATA);
1696 ret |= os04a10_write_reg(os04a10->client,
1697 OS04A10_REG_AGAIN_LONG_H,
1698 OS04A10_REG_VALUE_16BIT,
1699 (l_a_gain << 4) & 0x1ff0);
1700 ret |= os04a10_write_reg(os04a10->client,
1701 OS04A10_REG_DGAIN_LONG_H,
1702 OS04A10_REG_VALUE_24BIT,
1703 (l_d_gain << 6) & 0xfffc0);
1704 ret |= os04a10_write_reg(os04a10->client,
1705 OS04A10_REG_EXP_LONG_H,
1706 OS04A10_REG_VALUE_16BIT,
1707 l_exp_time);
1708 ret |= os04a10_write_reg(os04a10->client,
1709 OS04A10_REG_AGAIN_MID_H,
1710 OS04A10_REG_VALUE_16BIT,
1711 (m_a_gain << 4) & 0x1ff0);
1712 ret |= os04a10_write_reg(os04a10->client,
1713 OS04A10_REG_DGAIN_MID_H,
1714 OS04A10_REG_VALUE_24BIT,
1715 (m_d_gain << 6) & 0xfffc0);
1716 ret |= os04a10_write_reg(os04a10->client,
1717 OS04A10_REG_EXP_MID_H,
1718 OS04A10_REG_VALUE_16BIT,
1719 m_exp_time);
1720 if (os04a10->cur_mode->hdr_mode == HDR_X3) {
1721 //3 stagger
1722 ret |= os04a10_write_reg(os04a10->client,
1723 OS04A10_REG_AGAIN_VS_H,
1724 OS04A10_REG_VALUE_16BIT,
1725 (s_a_gain << 4) & 0x1ff0);
1726 ret |= os04a10_write_reg(os04a10->client,
1727 OS04A10_REG_EXP_VS_H,
1728 OS04A10_REG_VALUE_16BIT,
1729 s_exp_time);
1730 ret |= os04a10_write_reg(os04a10->client,
1731 OS04A10_REG_DGAIN_VS_H,
1732 OS04A10_REG_VALUE_24BIT,
1733 (s_d_gain << 6) & 0xfffc0);
1734 if (os04a10->short_hcg && s_cg_mode == GAIN_MODE_LCG) {
1735 gain_switch |= 0x40;
1736 os04a10->short_hcg = false;
1737 is_need_switch++;
1738 } else if (!os04a10->short_hcg && s_cg_mode == GAIN_MODE_HCG) {
1739 gain_switch &= 0xbf;
1740 os04a10->short_hcg = true;
1741 is_need_switch++;
1742 }
1743 }
1744 if (is_need_switch)
1745 ret |= os04a10_write_reg(os04a10->client,
1746 OS04A10_REG_HCG_SWITCH,
1747 OS04A10_REG_VALUE_08BIT,
1748 gain_switch);
1749 ret |= os04a10_write_reg(os04a10->client,
1750 OS04A10_GROUP_UPDATE_ADDRESS,
1751 OS04A10_REG_VALUE_08BIT,
1752 OS04A10_GROUP_UPDATE_END_DATA);
1753 ret |= os04a10_write_reg(os04a10->client,
1754 OS04A10_GROUP_UPDATE_ADDRESS,
1755 OS04A10_REG_VALUE_08BIT,
1756 OS04A10_GROUP_UPDATE_END_LAUNCH);
1757 return ret;
1758 }
1759
os04a10_set_conversion_gain(struct os04a10 * os04a10,u32 * cg)1760 static int os04a10_set_conversion_gain(struct os04a10 *os04a10, u32 *cg)
1761 {
1762 int ret = 0;
1763 struct i2c_client *client = os04a10->client;
1764 u32 cur_cg = *cg;
1765 u32 val = 0;
1766 s32 is_need_change = 0;
1767
1768 dev_dbg(&os04a10->client->dev, "set conversion gain %d\n", cur_cg);
1769 if (os04a10->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1770 os04a10->is_thunderboot = false;
1771 os04a10->is_thunderboot_ng = true;
1772 __os04a10_power_on(os04a10);
1773 }
1774
1775 ret = os04a10_read_reg(client,
1776 OS04A10_REG_HCG_SWITCH,
1777 OS04A10_REG_VALUE_08BIT,
1778 &val);
1779 if (os04a10->long_hcg && cur_cg == GAIN_MODE_LCG) {
1780 val |= 0x10;
1781 is_need_change++;
1782 os04a10->long_hcg = false;
1783 } else if (!os04a10->long_hcg && cur_cg == GAIN_MODE_HCG) {
1784 val &= 0xef;
1785 is_need_change++;
1786 os04a10->long_hcg = true;
1787 }
1788 ret |= os04a10_write_reg(client,
1789 OS04A10_GROUP_UPDATE_ADDRESS,
1790 OS04A10_REG_VALUE_08BIT,
1791 OS04A10_GROUP_UPDATE_START_DATA);
1792 if (is_need_change)
1793 ret |= os04a10_write_reg(client,
1794 OS04A10_REG_HCG_SWITCH,
1795 OS04A10_REG_VALUE_08BIT,
1796 val);
1797 ret |= os04a10_write_reg(client,
1798 OS04A10_GROUP_UPDATE_ADDRESS,
1799 OS04A10_REG_VALUE_08BIT,
1800 OS04A10_GROUP_UPDATE_END_DATA);
1801 ret |= os04a10_write_reg(client,
1802 OS04A10_GROUP_UPDATE_ADDRESS,
1803 OS04A10_REG_VALUE_08BIT,
1804 OS04A10_GROUP_UPDATE_END_LAUNCH);
1805 return ret;
1806 }
1807
1808 #ifdef USED_SYS_DEBUG
1809 //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg
set_conversion_gain_status(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1810 static ssize_t set_conversion_gain_status(struct device *dev,
1811 struct device_attribute *attr,
1812 const char *buf,
1813 size_t count)
1814 {
1815 struct i2c_client *client = to_i2c_client(dev);
1816 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1817 struct os04a10 *os04a10 = to_os04a10(sd);
1818 int status = 0;
1819 int ret = 0;
1820
1821 ret = kstrtoint(buf, 0, &status);
1822 if (!ret && status >= 0 && status < 2)
1823 os04a10_set_conversion_gain(os04a10, &status);
1824 else
1825 dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
1826 return count;
1827 }
1828
1829 static struct device_attribute attributes[] = {
1830 __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
1831 };
1832
add_sysfs_interfaces(struct device * dev)1833 static int add_sysfs_interfaces(struct device *dev)
1834 {
1835 int i;
1836
1837 for (i = 0; i < ARRAY_SIZE(attributes); i++)
1838 if (device_create_file(dev, attributes + i))
1839 goto undo;
1840 return 0;
1841 undo:
1842 for (i--; i >= 0 ; i--)
1843 device_remove_file(dev, attributes + i);
1844 dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
1845 return -ENODEV;
1846 }
1847 #endif
1848
os04a10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1849 static long os04a10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1850 {
1851 struct os04a10 *os04a10 = to_os04a10(sd);
1852 struct rkmodule_hdr_cfg *hdr_cfg;
1853 struct rkmodule_dcg_ratio *dcg;
1854 long ret = 0;
1855 u32 i, h, w;
1856 u32 stream = 0;
1857 u64 dst_link_freq = 0;
1858 u64 dst_pixel_rate = 0;
1859 u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
1860 const struct os04a10_mode *mode;
1861
1862 switch (cmd) {
1863 case PREISP_CMD_SET_HDRAE_EXP:
1864 return os04a10_set_hdrae(os04a10, arg);
1865 case RKMODULE_SET_HDR_CFG:
1866 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1867 w = os04a10->cur_mode->width;
1868 h = os04a10->cur_mode->height;
1869 for (i = 0; i < os04a10->cfg_num; i++) {
1870 if (w == os04a10->supported_modes[i].width &&
1871 h == os04a10->supported_modes[i].height &&
1872 os04a10->supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1873 os04a10->cur_mode = &os04a10->supported_modes[i];
1874 break;
1875 }
1876 }
1877 if (i == os04a10->cfg_num) {
1878 dev_err(&os04a10->client->dev,
1879 "not find hdr mode:%d %dx%d config\n",
1880 hdr_cfg->hdr_mode, w, h);
1881 ret = -EINVAL;
1882 } else {
1883 mode = os04a10->cur_mode;
1884 w = mode->hts_def - mode->width;
1885 h = mode->vts_def - mode->height;
1886 __v4l2_ctrl_modify_range(os04a10->hblank, w, w, 1, w);
1887 __v4l2_ctrl_modify_range(os04a10->vblank, h,
1888 OS04A10_VTS_MAX - os04a10->cur_mode->height,
1889 1, h);
1890 dst_link_freq = mode->link_freq_idx;
1891 dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1892 mode->bpp * 2 * lanes;
1893 __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
1894 dst_pixel_rate);
1895 __v4l2_ctrl_s_ctrl(os04a10->link_freq,
1896 dst_link_freq);
1897 dev_info(&os04a10->client->dev,
1898 "sensor mode: %d\n",
1899 os04a10->cur_mode->hdr_mode);
1900 }
1901 break;
1902 case RKMODULE_GET_MODULE_INFO:
1903 os04a10_get_module_inf(os04a10, (struct rkmodule_inf *)arg);
1904 break;
1905 case RKMODULE_GET_HDR_CFG:
1906 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
1907 hdr_cfg->esp.mode = HDR_NORMAL_VC;
1908 hdr_cfg->hdr_mode = os04a10->cur_mode->hdr_mode;
1909 break;
1910 case RKMODULE_SET_CONVERSION_GAIN:
1911 ret = os04a10_set_conversion_gain(os04a10, (u32 *)arg);
1912 break;
1913 case RKMODULE_SET_QUICK_STREAM:
1914
1915 stream = *((u32 *)arg);
1916
1917 if (stream)
1918 ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
1919 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
1920 else
1921 ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
1922 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
1923 break;
1924 case RKMODULE_GET_DCG_RATIO:
1925 if (os04a10->dcg_ratio == 0)
1926 return -EINVAL;
1927 dcg = (struct rkmodule_dcg_ratio *)arg;
1928 dcg->integer = (os04a10->dcg_ratio >> 8) & 0xff;
1929 dcg->decimal = os04a10->dcg_ratio & 0xff;
1930 dcg->div_coeff = 256;
1931 dev_info(&os04a10->client->dev,
1932 "get dcg ratio integer %d, decimal %d div_coeff %d\n",
1933 dcg->integer, dcg->decimal, dcg->div_coeff);
1934 break;
1935 default:
1936 ret = -ENOIOCTLCMD;
1937 break;
1938 }
1939
1940 return ret;
1941 }
1942
1943 #ifdef CONFIG_COMPAT
os04a10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1944 static long os04a10_compat_ioctl32(struct v4l2_subdev *sd,
1945 unsigned int cmd, unsigned long arg)
1946 {
1947 void __user *up = compat_ptr(arg);
1948 struct rkmodule_inf *inf;
1949 struct rkmodule_hdr_cfg *hdr;
1950 struct preisp_hdrae_exp_s *hdrae;
1951 struct rkmodule_dcg_ratio *dcg;
1952 long ret;
1953 u32 cg = 0;
1954 u32 stream = 0;
1955
1956 switch (cmd) {
1957 case RKMODULE_GET_MODULE_INFO:
1958 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1959 if (!inf) {
1960 ret = -ENOMEM;
1961 return ret;
1962 }
1963
1964 ret = os04a10_ioctl(sd, cmd, inf);
1965 if (!ret) {
1966 ret = copy_to_user(up, inf, sizeof(*inf));
1967 if (ret)
1968 ret = -EFAULT;
1969 }
1970 kfree(inf);
1971 break;
1972 case RKMODULE_GET_HDR_CFG:
1973 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1974 if (!hdr) {
1975 ret = -ENOMEM;
1976 return ret;
1977 }
1978
1979 ret = os04a10_ioctl(sd, cmd, hdr);
1980 if (!ret) {
1981 ret = copy_to_user(up, hdr, sizeof(*hdr));
1982 if (ret)
1983 ret = -EFAULT;
1984 }
1985 kfree(hdr);
1986 break;
1987 case RKMODULE_SET_HDR_CFG:
1988 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1989 if (!hdr) {
1990 ret = -ENOMEM;
1991 return ret;
1992 }
1993
1994 if (copy_from_user(hdr, up, sizeof(*hdr)))
1995 return -EFAULT;
1996
1997 ret = os04a10_ioctl(sd, cmd, hdr);
1998 kfree(hdr);
1999 break;
2000 case PREISP_CMD_SET_HDRAE_EXP:
2001 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
2002 if (!hdrae) {
2003 ret = -ENOMEM;
2004 return ret;
2005 }
2006
2007 if (copy_from_user(hdrae, up, sizeof(*hdrae)))
2008 return -EFAULT;
2009
2010 ret = os04a10_ioctl(sd, cmd, hdrae);
2011 kfree(hdrae);
2012 break;
2013 case RKMODULE_SET_CONVERSION_GAIN:
2014 if (copy_from_user(&cg, up, sizeof(cg)))
2015 return -EFAULT;
2016
2017 ret = os04a10_ioctl(sd, cmd, &cg);
2018 break;
2019 case RKMODULE_SET_QUICK_STREAM:
2020 if (copy_from_user(&stream, up, sizeof(u32)))
2021 return -EFAULT;
2022
2023 ret = os04a10_ioctl(sd, cmd, &stream);
2024 break;
2025 case RKMODULE_GET_DCG_RATIO:
2026 dcg = kzalloc(sizeof(*dcg), GFP_KERNEL);
2027 if (!dcg) {
2028 ret = -ENOMEM;
2029 return ret;
2030 }
2031
2032 ret = os04a10_ioctl(sd, cmd, dcg);
2033 if (!ret) {
2034 ret = copy_to_user(up, dcg, sizeof(*dcg));
2035 if (ret)
2036 return -EFAULT;
2037 }
2038 kfree(dcg);
2039 break;
2040 default:
2041 ret = -ENOIOCTLCMD;
2042 break;
2043 }
2044
2045 return ret;
2046 }
2047 #endif
2048
os04a10_init_conversion_gain(struct os04a10 * os04a10)2049 static int os04a10_init_conversion_gain(struct os04a10 *os04a10)
2050 {
2051 int ret = 0;
2052 struct i2c_client *client = os04a10->client;
2053 u32 val = 0;
2054
2055 ret = os04a10_read_reg(client,
2056 OS04A10_REG_HCG_SWITCH,
2057 OS04A10_REG_VALUE_08BIT,
2058 &val);
2059 val &= ~0x70;
2060 if (!os04a10->long_hcg)
2061 val |= 0x10;
2062 if (!os04a10->middle_hcg)
2063 val |= 0x20;
2064 if (!os04a10->short_hcg)
2065 val |= 0x40;
2066 ret |= os04a10_write_reg(client,
2067 OS04A10_REG_HCG_SWITCH,
2068 OS04A10_REG_VALUE_08BIT,
2069 val);
2070 return ret;
2071 }
2072
__os04a10_start_stream(struct os04a10 * os04a10)2073 static int __os04a10_start_stream(struct os04a10 *os04a10)
2074 {
2075 int ret;
2076
2077 if (!os04a10->is_thunderboot) {
2078 ret = os04a10_write_array(os04a10->client, os04a10->cur_mode->reg_list);
2079 if (ret)
2080 return ret;
2081 }
2082
2083 ret = os04a10_init_conversion_gain(os04a10);
2084 if (ret)
2085 return ret;
2086
2087 /* In case these controls are set before streaming */
2088 ret = __v4l2_ctrl_handler_setup(&os04a10->ctrl_handler);
2089 if (ret)
2090 return ret;
2091 if (os04a10->has_init_exp && os04a10->cur_mode->hdr_mode != NO_HDR) {
2092 ret = os04a10_ioctl(&os04a10->subdev, PREISP_CMD_SET_HDRAE_EXP, &os04a10->init_hdrae_exp);
2093 if (ret) {
2094 dev_err(&os04a10->client->dev,
2095 "init exp fail in hdr mode\n");
2096 return ret;
2097 }
2098 }
2099 return os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
2100 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
2101 }
2102
__os04a10_stop_stream(struct os04a10 * os04a10)2103 static int __os04a10_stop_stream(struct os04a10 *os04a10)
2104 {
2105 os04a10->has_init_exp = false;
2106 if (os04a10->is_thunderboot)
2107 os04a10->is_first_streamoff = true;
2108 return os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
2109 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
2110 }
2111
os04a10_s_stream(struct v4l2_subdev * sd,int on)2112 static int os04a10_s_stream(struct v4l2_subdev *sd, int on)
2113 {
2114 struct os04a10 *os04a10 = to_os04a10(sd);
2115 struct i2c_client *client = os04a10->client;
2116 int ret = 0;
2117
2118 mutex_lock(&os04a10->mutex);
2119 on = !!on;
2120 if (on == os04a10->streaming)
2121 goto unlock_and_return;
2122
2123 if (on) {
2124 if (os04a10->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
2125 os04a10->is_thunderboot = false;
2126 __os04a10_power_on(os04a10);
2127 }
2128 ret = pm_runtime_get_sync(&client->dev);
2129 if (ret < 0) {
2130 pm_runtime_put_noidle(&client->dev);
2131 goto unlock_and_return;
2132 }
2133
2134 ret = __os04a10_start_stream(os04a10);
2135 if (ret) {
2136 v4l2_err(sd, "start stream failed while write regs\n");
2137 pm_runtime_put(&client->dev);
2138 goto unlock_and_return;
2139 }
2140 } else {
2141 __os04a10_stop_stream(os04a10);
2142 pm_runtime_put(&client->dev);
2143 }
2144
2145 os04a10->streaming = on;
2146
2147 unlock_and_return:
2148 mutex_unlock(&os04a10->mutex);
2149
2150 return ret;
2151 }
2152
os04a10_s_power(struct v4l2_subdev * sd,int on)2153 static int os04a10_s_power(struct v4l2_subdev *sd, int on)
2154 {
2155 struct os04a10 *os04a10 = to_os04a10(sd);
2156 struct i2c_client *client = os04a10->client;
2157 int ret = 0;
2158
2159 mutex_lock(&os04a10->mutex);
2160
2161 /* If the power state is not modified - no work to do. */
2162 if (os04a10->power_on == !!on)
2163 goto unlock_and_return;
2164
2165 if (on) {
2166 ret = pm_runtime_get_sync(&client->dev);
2167 if (ret < 0) {
2168 pm_runtime_put_noidle(&client->dev);
2169 goto unlock_and_return;
2170 }
2171
2172 if (!os04a10->is_thunderboot) {
2173 ret |= os04a10_write_reg(os04a10->client,
2174 OS04A10_SOFTWARE_RESET_REG,
2175 OS04A10_REG_VALUE_08BIT,
2176 0x01);
2177 usleep_range(100, 200);
2178 ret |= os04a10_write_array(os04a10->client,
2179 os04a10->cur_mode->global_reg_list);
2180 if (ret) {
2181 dev_err(&os04a10->client->dev,
2182 "could not set init registers\n");
2183 goto unlock_and_return;
2184 }
2185 }
2186
2187 os04a10->power_on = true;
2188 } else {
2189 pm_runtime_put(&client->dev);
2190 os04a10->power_on = false;
2191 }
2192
2193 unlock_and_return:
2194 mutex_unlock(&os04a10->mutex);
2195
2196 return ret;
2197 }
2198
2199 /* Calculate the delay in us by clock rate and clock cycles */
os04a10_cal_delay(u32 cycles)2200 static inline u32 os04a10_cal_delay(u32 cycles)
2201 {
2202 return DIV_ROUND_UP(cycles, OS04A10_XVCLK_FREQ / 1000 / 1000);
2203 }
2204
__os04a10_power_on(struct os04a10 * os04a10)2205 static int __os04a10_power_on(struct os04a10 *os04a10)
2206 {
2207 int ret;
2208 u32 delay_us;
2209 struct device *dev = &os04a10->client->dev;
2210
2211 if (os04a10->is_thunderboot)
2212 return 0;
2213
2214 if (!IS_ERR_OR_NULL(os04a10->pins_default)) {
2215 ret = pinctrl_select_state(os04a10->pinctrl,
2216 os04a10->pins_default);
2217 if (ret < 0)
2218 dev_err(dev, "could not set pins\n");
2219 }
2220 ret = clk_set_rate(os04a10->xvclk, OS04A10_XVCLK_FREQ);
2221 if (ret < 0)
2222 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
2223 if (clk_get_rate(os04a10->xvclk) != OS04A10_XVCLK_FREQ)
2224 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
2225 ret = clk_prepare_enable(os04a10->xvclk);
2226 if (ret < 0) {
2227 dev_err(dev, "Failed to enable xvclk\n");
2228 return ret;
2229 }
2230 if (!IS_ERR(os04a10->reset_gpio))
2231 gpiod_direction_output(os04a10->reset_gpio, 1);
2232
2233 ret = regulator_bulk_enable(OS04A10_NUM_SUPPLIES, os04a10->supplies);
2234 if (ret < 0) {
2235 dev_err(dev, "Failed to enable regulators\n");
2236 goto disable_clk;
2237 }
2238 usleep_range(25000, 30000);
2239 if (!IS_ERR(os04a10->reset_gpio))
2240 gpiod_direction_output(os04a10->reset_gpio, 0);
2241
2242 usleep_range(500, 1000);
2243 if (!IS_ERR(os04a10->pwdn_gpio))
2244 gpiod_direction_output(os04a10->pwdn_gpio, 1);
2245 /*
2246 * There is no need to wait for the delay of RC circuit
2247 * if the reset signal is directly controlled by GPIO.
2248 */
2249 if (!IS_ERR(os04a10->reset_gpio))
2250 usleep_range(6000, 8000);
2251 else
2252 usleep_range(12000, 16000);
2253
2254 /* 8192 cycles prior to first SCCB transaction */
2255 delay_us = os04a10_cal_delay(8192);
2256 usleep_range(delay_us, delay_us * 2);
2257
2258 return 0;
2259
2260 disable_clk:
2261 clk_disable_unprepare(os04a10->xvclk);
2262
2263 return ret;
2264 }
2265
__os04a10_power_off(struct os04a10 * os04a10)2266 static void __os04a10_power_off(struct os04a10 *os04a10)
2267 {
2268 int ret;
2269 struct device *dev = &os04a10->client->dev;
2270
2271 if (os04a10->is_thunderboot) {
2272 if (os04a10->is_first_streamoff) {
2273 os04a10->is_thunderboot = false;
2274 os04a10->is_first_streamoff = false;
2275 } else {
2276 return;
2277 }
2278 }
2279
2280 if (!IS_ERR(os04a10->pwdn_gpio))
2281 gpiod_direction_output(os04a10->pwdn_gpio, 0);
2282
2283 clk_disable_unprepare(os04a10->xvclk);
2284
2285 if (!IS_ERR(os04a10->reset_gpio))
2286 gpiod_direction_output(os04a10->reset_gpio, 0);
2287 if (!IS_ERR_OR_NULL(os04a10->pins_sleep)) {
2288 ret = pinctrl_select_state(os04a10->pinctrl,
2289 os04a10->pins_sleep);
2290 if (ret < 0)
2291 dev_dbg(dev, "could not set pins\n");
2292 }
2293
2294 if (os04a10->is_thunderboot_ng) {
2295 os04a10->is_thunderboot_ng = false;
2296 regulator_bulk_disable(OS04A10_NUM_SUPPLIES, os04a10->supplies);
2297 }
2298 usleep_range(30000, 31000);
2299 }
2300
os04a10_runtime_resume(struct device * dev)2301 static int __maybe_unused os04a10_runtime_resume(struct device *dev)
2302 {
2303 struct i2c_client *client = to_i2c_client(dev);
2304 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2305 struct os04a10 *os04a10 = to_os04a10(sd);
2306
2307 return __os04a10_power_on(os04a10);
2308 }
2309
os04a10_runtime_suspend(struct device * dev)2310 static int __maybe_unused os04a10_runtime_suspend(struct device *dev)
2311 {
2312 struct i2c_client *client = to_i2c_client(dev);
2313 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2314 struct os04a10 *os04a10 = to_os04a10(sd);
2315
2316 __os04a10_power_off(os04a10);
2317
2318 return 0;
2319 }
2320
2321 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
os04a10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)2322 static int os04a10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2323 {
2324 struct os04a10 *os04a10 = to_os04a10(sd);
2325 struct v4l2_mbus_framefmt *try_fmt =
2326 v4l2_subdev_get_try_format(sd, fh->pad, 0);
2327 const struct os04a10_mode *def_mode = &os04a10->supported_modes[0];
2328
2329 mutex_lock(&os04a10->mutex);
2330 /* Initialize try_fmt */
2331 try_fmt->width = def_mode->width;
2332 try_fmt->height = def_mode->height;
2333 try_fmt->code = def_mode->bus_fmt;
2334 try_fmt->field = V4L2_FIELD_NONE;
2335
2336 mutex_unlock(&os04a10->mutex);
2337 /* No crop or compose */
2338
2339 return 0;
2340 }
2341 #endif
2342
os04a10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2343 static int os04a10_enum_frame_interval(struct v4l2_subdev *sd,
2344 struct v4l2_subdev_pad_config *cfg,
2345 struct v4l2_subdev_frame_interval_enum *fie)
2346 {
2347 struct os04a10 *os04a10 = to_os04a10(sd);
2348
2349 if (fie->index >= os04a10->cfg_num)
2350 return -EINVAL;
2351
2352 fie->code = os04a10->supported_modes[fie->index].bus_fmt;
2353 fie->width = os04a10->supported_modes[fie->index].width;
2354 fie->height = os04a10->supported_modes[fie->index].height;
2355 fie->interval = os04a10->supported_modes[fie->index].max_fps;
2356 fie->reserved[0] = os04a10->supported_modes[fie->index].hdr_mode;
2357 return 0;
2358 }
2359
2360 static const struct dev_pm_ops os04a10_pm_ops = {
2361 SET_RUNTIME_PM_OPS(os04a10_runtime_suspend,
2362 os04a10_runtime_resume, NULL)
2363 };
2364
2365 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2366 static const struct v4l2_subdev_internal_ops os04a10_internal_ops = {
2367 .open = os04a10_open,
2368 };
2369 #endif
2370
2371 static const struct v4l2_subdev_core_ops os04a10_core_ops = {
2372 .s_power = os04a10_s_power,
2373 .ioctl = os04a10_ioctl,
2374 #ifdef CONFIG_COMPAT
2375 .compat_ioctl32 = os04a10_compat_ioctl32,
2376 #endif
2377 };
2378
2379 static const struct v4l2_subdev_video_ops os04a10_video_ops = {
2380 .s_stream = os04a10_s_stream,
2381 .g_frame_interval = os04a10_g_frame_interval,
2382 };
2383
2384 static const struct v4l2_subdev_pad_ops os04a10_pad_ops = {
2385 .enum_mbus_code = os04a10_enum_mbus_code,
2386 .enum_frame_size = os04a10_enum_frame_sizes,
2387 .enum_frame_interval = os04a10_enum_frame_interval,
2388 .get_fmt = os04a10_get_fmt,
2389 .set_fmt = os04a10_set_fmt,
2390 .get_mbus_config = os04a10_g_mbus_config,
2391 };
2392
2393 static const struct v4l2_subdev_ops os04a10_subdev_ops = {
2394 .core = &os04a10_core_ops,
2395 .video = &os04a10_video_ops,
2396 .pad = &os04a10_pad_ops,
2397 };
2398
os04a10_set_ctrl(struct v4l2_ctrl * ctrl)2399 static int os04a10_set_ctrl(struct v4l2_ctrl *ctrl)
2400 {
2401 struct os04a10 *os04a10 = container_of(ctrl->handler,
2402 struct os04a10, ctrl_handler);
2403 struct i2c_client *client = os04a10->client;
2404 s64 max;
2405 int ret = 0;
2406 u32 again, dgain;
2407 u32 val = 0;
2408
2409 /* Propagate change of current control to all related controls */
2410 switch (ctrl->id) {
2411 case V4L2_CID_VBLANK:
2412 /* Update max exposure while meeting expected vblanking */
2413 max = os04a10->cur_mode->height + ctrl->val - 4;
2414 __v4l2_ctrl_modify_range(os04a10->exposure,
2415 os04a10->exposure->minimum, max,
2416 os04a10->exposure->step,
2417 os04a10->exposure->default_value);
2418 break;
2419 }
2420
2421 if (!pm_runtime_get_if_in_use(&client->dev))
2422 return 0;
2423
2424 switch (ctrl->id) {
2425 case V4L2_CID_EXPOSURE:
2426 ret = os04a10_write_reg(os04a10->client,
2427 OS04A10_REG_EXP_LONG_H,
2428 OS04A10_REG_VALUE_16BIT,
2429 ctrl->val);
2430 dev_dbg(&client->dev, "set exposure 0x%x\n",
2431 ctrl->val);
2432 break;
2433 case V4L2_CID_ANALOGUE_GAIN:
2434 if (ctrl->val > 248) {
2435 dgain = ctrl->val * 1024 / 248;
2436 again = 248;
2437 } else {
2438 dgain = 1024;
2439 again = ctrl->val;
2440 }
2441 ret = os04a10_write_reg(os04a10->client,
2442 OS04A10_REG_AGAIN_LONG_H,
2443 OS04A10_REG_VALUE_16BIT,
2444 (again << 4) & 0x1ff0);
2445 ret |= os04a10_write_reg(os04a10->client,
2446 OS04A10_REG_DGAIN_LONG_H,
2447 OS04A10_REG_VALUE_24BIT,
2448 (dgain << 6) & 0xfffc0);
2449 dev_dbg(&client->dev, "set analog gain 0x%x\n",
2450 ctrl->val);
2451 break;
2452 case V4L2_CID_VBLANK:
2453 ret = os04a10_write_reg(os04a10->client, OS04A10_REG_VTS,
2454 OS04A10_REG_VALUE_16BIT,
2455 ctrl->val + os04a10->cur_mode->height);
2456 dev_dbg(&client->dev, "set vblank 0x%x\n",
2457 ctrl->val);
2458 break;
2459 case V4L2_CID_TEST_PATTERN:
2460 ret = os04a10_enable_test_pattern(os04a10, ctrl->val);
2461 break;
2462 case V4L2_CID_HFLIP:
2463 ret = os04a10_read_reg(os04a10->client, OS04A10_FLIP_REG,
2464 OS04A10_REG_VALUE_08BIT,
2465 &val);
2466 if (ctrl->val)
2467 val |= MIRROR_BIT_MASK;
2468 else
2469 val &= ~MIRROR_BIT_MASK;
2470 ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
2471 OS04A10_REG_VALUE_08BIT,
2472 val);
2473 if (ret == 0)
2474 os04a10->flip = val;
2475 break;
2476 case V4L2_CID_VFLIP:
2477 ret = os04a10_read_reg(os04a10->client, OS04A10_FLIP_REG,
2478 OS04A10_REG_VALUE_08BIT,
2479 &val);
2480 if (ctrl->val)
2481 val |= FLIP_BIT_MASK;
2482 else
2483 val &= ~FLIP_BIT_MASK;
2484 ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
2485 OS04A10_REG_VALUE_08BIT,
2486 val);
2487 if (ret == 0)
2488 os04a10->flip = val;
2489 break;
2490 default:
2491 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2492 __func__, ctrl->id, ctrl->val);
2493 break;
2494 }
2495
2496 pm_runtime_put(&client->dev);
2497
2498 return ret;
2499 }
2500
2501 static const struct v4l2_ctrl_ops os04a10_ctrl_ops = {
2502 .s_ctrl = os04a10_set_ctrl,
2503 };
2504
os04a10_initialize_controls(struct os04a10 * os04a10)2505 static int os04a10_initialize_controls(struct os04a10 *os04a10)
2506 {
2507 const struct os04a10_mode *mode;
2508 struct v4l2_ctrl_handler *handler;
2509 s64 exposure_max, vblank_def;
2510 u32 h_blank;
2511 int ret;
2512 u64 dst_link_freq = 0;
2513 u64 dst_pixel_rate = 0;
2514 u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
2515
2516 handler = &os04a10->ctrl_handler;
2517 mode = os04a10->cur_mode;
2518 ret = v4l2_ctrl_handler_init(handler, 9);
2519 if (ret)
2520 return ret;
2521 handler->lock = &os04a10->mutex;
2522
2523 os04a10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2524 V4L2_CID_LINK_FREQ,
2525 ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
2526
2527 dst_link_freq = mode->link_freq_idx;
2528 dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
2529 mode->bpp * 2 * lanes;
2530 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2531 os04a10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
2532 V4L2_CID_PIXEL_RATE,
2533 0, PIXEL_RATE_WITH_648M,
2534 1, dst_pixel_rate);
2535
2536 __v4l2_ctrl_s_ctrl(os04a10->link_freq, dst_link_freq);
2537
2538 h_blank = mode->hts_def - mode->width;
2539 os04a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2540 h_blank, h_blank, 1, h_blank);
2541 if (os04a10->hblank)
2542 os04a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2543
2544 vblank_def = mode->vts_def - mode->height;
2545 os04a10->vblank = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
2546 V4L2_CID_VBLANK, vblank_def,
2547 OS04A10_VTS_MAX - mode->height,
2548 1, vblank_def);
2549
2550 exposure_max = mode->vts_def - 4;
2551 os04a10->exposure = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
2552 V4L2_CID_EXPOSURE, OS04A10_EXPOSURE_MIN,
2553 exposure_max, OS04A10_EXPOSURE_STEP,
2554 mode->exp_def);
2555
2556 os04a10->anal_gain = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
2557 V4L2_CID_ANALOGUE_GAIN, OS04A10_GAIN_MIN,
2558 OS04A10_GAIN_MAX, OS04A10_GAIN_STEP,
2559 OS04A10_GAIN_DEFAULT);
2560
2561 os04a10->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
2562 &os04a10_ctrl_ops, V4L2_CID_TEST_PATTERN,
2563 ARRAY_SIZE(os04a10_test_pattern_menu) - 1,
2564 0, 0, os04a10_test_pattern_menu);
2565
2566 os04a10->h_flip = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
2567 V4L2_CID_HFLIP, 0, 1, 1, 0);
2568
2569 os04a10->v_flip = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
2570 V4L2_CID_VFLIP, 0, 1, 1, 0);
2571 os04a10->flip = 0;
2572 if (handler->error) {
2573 ret = handler->error;
2574 dev_err(&os04a10->client->dev,
2575 "Failed to init controls(%d)\n", ret);
2576 goto err_free_handler;
2577 }
2578
2579 os04a10->subdev.ctrl_handler = handler;
2580 os04a10->has_init_exp = false;
2581 os04a10->long_hcg = false;
2582 os04a10->middle_hcg = false;
2583 os04a10->short_hcg = false;
2584 if (!os04a10->is_thunderboot)
2585 os04a10->is_thunderboot_ng = true;
2586
2587 return 0;
2588
2589 err_free_handler:
2590 v4l2_ctrl_handler_free(handler);
2591
2592 return ret;
2593 }
2594
os04a10_check_sensor_id(struct os04a10 * os04a10,struct i2c_client * client)2595 static int os04a10_check_sensor_id(struct os04a10 *os04a10,
2596 struct i2c_client *client)
2597 {
2598 struct device *dev = &os04a10->client->dev;
2599 u32 id = 0;
2600 int ret;
2601
2602 if (os04a10->is_thunderboot) {
2603 dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
2604 return 0;
2605 }
2606
2607 ret = os04a10_read_reg(client, OS04A10_REG_CHIP_ID,
2608 OS04A10_REG_VALUE_24BIT, &id);
2609 if (id != CHIP_ID) {
2610 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2611 return -ENODEV;
2612 }
2613
2614 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
2615
2616 return 0;
2617 }
2618
os04a10_configure_regulators(struct os04a10 * os04a10)2619 static int os04a10_configure_regulators(struct os04a10 *os04a10)
2620 {
2621 unsigned int i;
2622
2623 for (i = 0; i < OS04A10_NUM_SUPPLIES; i++)
2624 os04a10->supplies[i].supply = os04a10_supply_names[i];
2625
2626 return devm_regulator_bulk_get(&os04a10->client->dev,
2627 OS04A10_NUM_SUPPLIES,
2628 os04a10->supplies);
2629 }
2630
os04a10_get_dcg_ratio(struct os04a10 * os04a10)2631 static int os04a10_get_dcg_ratio(struct os04a10 *os04a10)
2632 {
2633 struct device *dev = &os04a10->client->dev;
2634 u32 val = 0;
2635 int ret = 0;
2636
2637 if (os04a10->is_thunderboot) {
2638 ret = os04a10_read_reg(os04a10->client, 0x77fe,
2639 OS04A10_REG_VALUE_16BIT, &val);
2640 } else {
2641 ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
2642 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
2643 usleep_range(5000, 6000);
2644 ret |= os04a10_read_reg(os04a10->client, 0x77fe,
2645 OS04A10_REG_VALUE_16BIT, &val);
2646 ret |= os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
2647 OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
2648 }
2649
2650 if (ret != 0 || val == 0) {
2651 os04a10->dcg_ratio = 0;
2652 dev_err(dev, "get dcg ratio fail, ret %d, dcg ratio %d\n", ret, val);
2653 } else {
2654 os04a10->dcg_ratio = val;
2655 dev_info(dev, "get dcg ratio reg val 0x%04x\n", val);
2656 }
2657
2658 return ret;
2659 }
2660
os04a10_probe(struct i2c_client * client,const struct i2c_device_id * id)2661 static int os04a10_probe(struct i2c_client *client,
2662 const struct i2c_device_id *id)
2663 {
2664 struct device *dev = &client->dev;
2665 struct device_node *node = dev->of_node;
2666 struct os04a10 *os04a10;
2667 struct v4l2_subdev *sd;
2668 struct device_node *endpoint;
2669 char facing[2];
2670 int ret;
2671 u32 i, hdr_mode = 0;
2672
2673 dev_info(dev, "driver version: %02x.%02x.%02x",
2674 DRIVER_VERSION >> 16,
2675 (DRIVER_VERSION & 0xff00) >> 8,
2676 DRIVER_VERSION & 0x00ff);
2677
2678 os04a10 = devm_kzalloc(dev, sizeof(*os04a10), GFP_KERNEL);
2679 if (!os04a10)
2680 return -ENOMEM;
2681
2682 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2683 &os04a10->module_index);
2684 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2685 &os04a10->module_facing);
2686 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2687 &os04a10->module_name);
2688 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2689 &os04a10->len_name);
2690 if (ret) {
2691 dev_err(dev, "could not get module information!\n");
2692 return -EINVAL;
2693 }
2694
2695 os04a10->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
2696 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
2697 &hdr_mode);
2698 if (ret) {
2699 hdr_mode = NO_HDR;
2700 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2701 }
2702 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2703 if (!endpoint) {
2704 dev_err(dev, "Failed to get endpoint\n");
2705 return -EINVAL;
2706 }
2707
2708 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
2709 &os04a10->bus_cfg);
2710 if (ret) {
2711 dev_err(dev, "Failed to get bus config\n");
2712 return -EINVAL;
2713 }
2714 if (os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
2715 os04a10->supported_modes = supported_modes;
2716 os04a10->cfg_num = ARRAY_SIZE(supported_modes);
2717 dev_info(dev, "detect os04a10 lane %d\n",
2718 os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
2719 } else {
2720 os04a10->supported_modes = supported_modes_2lane;
2721 os04a10->cfg_num = ARRAY_SIZE(supported_modes_2lane);
2722 dev_info(dev, "detect os04a10 lane %d\n",
2723 os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
2724 }
2725
2726 for (i = 0; i < os04a10->cfg_num; i++) {
2727 if (hdr_mode == supported_modes[i].hdr_mode) {
2728 os04a10->cur_mode = &os04a10->supported_modes[i];
2729 break;
2730 }
2731 }
2732 os04a10->client = client;
2733
2734 os04a10->xvclk = devm_clk_get(dev, "xvclk");
2735 if (IS_ERR(os04a10->xvclk)) {
2736 dev_err(dev, "Failed to get xvclk\n");
2737 return -EINVAL;
2738 }
2739
2740 os04a10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
2741 if (IS_ERR(os04a10->reset_gpio))
2742 dev_warn(dev, "Failed to get reset-gpios\n");
2743
2744 os04a10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
2745 if (IS_ERR(os04a10->pwdn_gpio))
2746 dev_warn(dev, "Failed to get pwdn-gpios\n");
2747
2748 os04a10->pinctrl = devm_pinctrl_get(dev);
2749 if (!IS_ERR(os04a10->pinctrl)) {
2750 os04a10->pins_default =
2751 pinctrl_lookup_state(os04a10->pinctrl,
2752 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2753 if (IS_ERR(os04a10->pins_default))
2754 dev_err(dev, "could not get default pinstate\n");
2755
2756 os04a10->pins_sleep =
2757 pinctrl_lookup_state(os04a10->pinctrl,
2758 OF_CAMERA_PINCTRL_STATE_SLEEP);
2759 if (IS_ERR(os04a10->pins_sleep))
2760 dev_err(dev, "could not get sleep pinstate\n");
2761 } else {
2762 dev_err(dev, "no pinctrl\n");
2763 }
2764
2765 ret = os04a10_configure_regulators(os04a10);
2766 if (ret) {
2767 dev_err(dev, "Failed to get power regulators\n");
2768 return ret;
2769 }
2770
2771 mutex_init(&os04a10->mutex);
2772
2773 sd = &os04a10->subdev;
2774 v4l2_i2c_subdev_init(sd, client, &os04a10_subdev_ops);
2775 ret = os04a10_initialize_controls(os04a10);
2776 if (ret)
2777 goto err_destroy_mutex;
2778
2779 ret = __os04a10_power_on(os04a10);
2780 if (ret)
2781 goto err_free_handler;
2782
2783 ret = os04a10_check_sensor_id(os04a10, client);
2784 if (ret)
2785 goto err_power_off;
2786
2787 ret = os04a10_get_dcg_ratio(os04a10);
2788 if (ret)
2789 dev_warn(dev, "get dcg ratio failed\n");
2790
2791 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2792 sd->internal_ops = &os04a10_internal_ops;
2793 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2794 #endif
2795 #if defined(CONFIG_MEDIA_CONTROLLER)
2796 os04a10->pad.flags = MEDIA_PAD_FL_SOURCE;
2797 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2798 ret = media_entity_pads_init(&sd->entity, 1, &os04a10->pad);
2799 if (ret < 0)
2800 goto err_power_off;
2801 #endif
2802
2803 memset(facing, 0, sizeof(facing));
2804 if (strcmp(os04a10->module_facing, "back") == 0)
2805 facing[0] = 'b';
2806 else
2807 facing[0] = 'f';
2808
2809 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2810 os04a10->module_index, facing,
2811 OS04A10_NAME, dev_name(sd->dev));
2812 ret = v4l2_async_register_subdev_sensor_common(sd);
2813 if (ret) {
2814 dev_err(dev, "v4l2 async register subdev failed\n");
2815 goto err_clean_entity;
2816 }
2817
2818 pm_runtime_set_active(dev);
2819 pm_runtime_enable(dev);
2820 pm_runtime_idle(dev);
2821 #ifdef USED_SYS_DEBUG
2822 add_sysfs_interfaces(dev);
2823 #endif
2824 return 0;
2825
2826 err_clean_entity:
2827 #if defined(CONFIG_MEDIA_CONTROLLER)
2828 media_entity_cleanup(&sd->entity);
2829 #endif
2830 err_power_off:
2831 __os04a10_power_off(os04a10);
2832 err_free_handler:
2833 v4l2_ctrl_handler_free(&os04a10->ctrl_handler);
2834 err_destroy_mutex:
2835 mutex_destroy(&os04a10->mutex);
2836
2837 return ret;
2838 }
2839
os04a10_remove(struct i2c_client * client)2840 static int os04a10_remove(struct i2c_client *client)
2841 {
2842 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2843 struct os04a10 *os04a10 = to_os04a10(sd);
2844
2845 v4l2_async_unregister_subdev(sd);
2846 #if defined(CONFIG_MEDIA_CONTROLLER)
2847 media_entity_cleanup(&sd->entity);
2848 #endif
2849 v4l2_ctrl_handler_free(&os04a10->ctrl_handler);
2850 mutex_destroy(&os04a10->mutex);
2851
2852 pm_runtime_disable(&client->dev);
2853 if (!pm_runtime_status_suspended(&client->dev))
2854 __os04a10_power_off(os04a10);
2855 pm_runtime_set_suspended(&client->dev);
2856
2857 return 0;
2858 }
2859
2860 #if IS_ENABLED(CONFIG_OF)
2861 static const struct of_device_id os04a10_of_match[] = {
2862 { .compatible = "ovti,os04a10" },
2863 {},
2864 };
2865 MODULE_DEVICE_TABLE(of, os04a10_of_match);
2866 #endif
2867
2868 static const struct i2c_device_id os04a10_match_id[] = {
2869 { "ovti,os04a10", 0 },
2870 { },
2871 };
2872
2873 static struct i2c_driver os04a10_i2c_driver = {
2874 .driver = {
2875 .name = OS04A10_NAME,
2876 .pm = &os04a10_pm_ops,
2877 .of_match_table = of_match_ptr(os04a10_of_match),
2878 },
2879 .probe = &os04a10_probe,
2880 .remove = &os04a10_remove,
2881 .id_table = os04a10_match_id,
2882 };
2883
2884 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
2885 module_i2c_driver(os04a10_i2c_driver);
2886 #else
sensor_mod_init(void)2887 static int __init sensor_mod_init(void)
2888 {
2889 return i2c_add_driver(&os04a10_i2c_driver);
2890 }
2891
sensor_mod_exit(void)2892 static void __exit sensor_mod_exit(void)
2893 {
2894 i2c_del_driver(&os04a10_i2c_driver);
2895 }
2896
2897 device_initcall_sync(sensor_mod_init);
2898 module_exit(sensor_mod_exit);
2899 #endif
2900
2901 MODULE_DESCRIPTION("OmniVision os04a10 sensor driver");
2902 MODULE_LICENSE("GPL v2");
2903