xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/nvp6158_drv/nvp6158_common.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /********************************************************************************
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
5*4882a593Smuzhiyun *  Module		: Common header file
6*4882a593Smuzhiyun *  Description	: This file is common header file
7*4882a593Smuzhiyun *  Author		:
8*4882a593Smuzhiyun *  Date         :
9*4882a593Smuzhiyun *  Version		: Version 2.0
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun ********************************************************************************
12*4882a593Smuzhiyun *  History      :
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun ********************************************************************************/
16*4882a593Smuzhiyun #ifndef __COMMON_H__
17*4882a593Smuzhiyun #define __COMMON_H__
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun unsigned char nvp6158_I2CReadByte8(unsigned char devaddress, unsigned char address);
20*4882a593Smuzhiyun void nvp6158_I2CWriteByte8(unsigned char devaddress, unsigned char address, unsigned char data);
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define  gpio_i2c_read   nvp6158_I2CReadByte8
23*4882a593Smuzhiyun #define  gpio_i2c_write  nvp6158_I2CWriteByte8
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun //#define STREAM_ON_DEFLAULT
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define I2C_0       (0)
28*4882a593Smuzhiyun #define I2C_1       (1)
29*4882a593Smuzhiyun #define I2C_2       (2)
30*4882a593Smuzhiyun #define I2C_3       (3)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun // device address define
33*4882a593Smuzhiyun #define NVP6158_R0_ID 	0xA1
34*4882a593Smuzhiyun #define NVP6158C_R0_ID 	0xA0   //6158B AND 6158C USES THE SAME CHIPID,DIFF IN REV_ID
35*4882a593Smuzhiyun #define NVP6158_REV_ID 	0x00
36*4882a593Smuzhiyun #define NVP6168_R0_ID 	0xC1
37*4882a593Smuzhiyun #define NVP6168C_R0_ID 	0xC0
38*4882a593Smuzhiyun //#define NVP6158C_REV_ID 	0x01
39*4882a593Smuzhiyun #define CH_PER_CHIP		4
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define NTSC		0x00
42*4882a593Smuzhiyun #define PAL			0x01
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define AHD_PELCO_16BIT
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun enum {
47*4882a593Smuzhiyun     NC_AD_SAMPLE_RATE_8000 = 8000,
48*4882a593Smuzhiyun     NC_AD_SAMPLE_RATE_16000 = 16000,
49*4882a593Smuzhiyun     NC_AD_SAMPLE_RATE_32000 = 32000,
50*4882a593Smuzhiyun     NC_AD_SAMPLE_RATE_44100 = 44100,
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun     NC_AD_SAMPLE_RATE_MAX,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun enum {
56*4882a593Smuzhiyun 	NC_AD_AI = 0,
57*4882a593Smuzhiyun 	NC_AD_AOC,
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	NC_AD_MAX
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun enum {
63*4882a593Smuzhiyun 	NC_AD_BIT_WIDTH_8 = 0,
64*4882a593Smuzhiyun 	NC_AD_BIT_WIDTH_16,
65*4882a593Smuzhiyun 	NC_AD_BIT_WIDTH_24,
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	NC_AD_BIT_WIDTH_MAX
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun //FIXME HI3520 Register
71*4882a593Smuzhiyun #define VIU_CH_CTRL					0x08
72*4882a593Smuzhiyun #define VIU_ANC0_START				0x9c
73*4882a593Smuzhiyun #define VIU_ANC0_SIZE				0xa0
74*4882a593Smuzhiyun #define VIU_ANC1_START				0xa4
75*4882a593Smuzhiyun #define VIU_ANC1_SIZE				0xa8
76*4882a593Smuzhiyun #define VIU_BLANK_DATA_ADDR			0xac
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define IOC_VDEC_GET_EQ_DIST			0x07
79*4882a593Smuzhiyun #define IOC_VDEC_GET_INPUT_VIDEO_FMT	0x08
80*4882a593Smuzhiyun #define IOC_VDEC_GET_VIDEO_LOSS     	0x09
81*4882a593Smuzhiyun #define IOC_VDEC_SET_SYNC		     	0x0A
82*4882a593Smuzhiyun #define IOC_VDEC_SET_EQUALIZER			0x0B
83*4882a593Smuzhiyun #define IOC_VDEC_GET_DRIVERVER			0x0C
84*4882a593Smuzhiyun #define IOC_VDEC_PTZ_ACP_READ			0x0D
85*4882a593Smuzhiyun #define IOC_VDEC_SET_BRIGHTNESS	    	0x0E
86*4882a593Smuzhiyun #define IOC_VDEC_SET_CONTRAST   		0x0F
87*4882a593Smuzhiyun #define IOC_VDEC_SET_HUE    			0x10
88*4882a593Smuzhiyun #define IOC_VDEC_SET_SATURATION  		0x11
89*4882a593Smuzhiyun #define IOC_VDEC_SET_SHARPNESS  		0x12
90*4882a593Smuzhiyun #define IOC_VDEC_SET_CHNMODE    		0x13
91*4882a593Smuzhiyun #define IOC_VDEC_SET_OUTPORTMODE  		0x14
92*4882a593Smuzhiyun #define IOC_VDEC_SET_CHDETMODE  		0x15
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define IOC_VDEC_ACP_WRITE              0x2f
95*4882a593Smuzhiyun #define IOC_VDEC_ACP_WRITE_EXTENTION    0x30
96*4882a593Smuzhiyun #define IOC_VDEC_PTZ_ACP_READ_EACH_CH	0x31
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define IOC_VDEC_INIT_MOTION			0x40
99*4882a593Smuzhiyun #define IOC_VDEC_ENABLE_MOTION			0x41
100*4882a593Smuzhiyun #define IOC_VDEC_DISABLE_MOTION			0x42
101*4882a593Smuzhiyun #define IOC_VDEC_SET_MOTION_AREA		0x43
102*4882a593Smuzhiyun #define IOC_VDEC_GET_MOTION_INFO		0x44
103*4882a593Smuzhiyun #define IOC_VDEC_SET_MOTION_DISPLAY		0x45
104*4882a593Smuzhiyun #define IOC_VDEC_SET_MOTION_SENS		0x46
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define IOC_AUDIO_SET_CHNNUM            0x80
107*4882a593Smuzhiyun #define IOC_AUDIO_SET_SAMPLE_RATE       0x81
108*4882a593Smuzhiyun #define IOC_AUDIO_SET_BITWIDTH          0x82
109*4882a593Smuzhiyun #define IOC_VDEC_SET_I2C				0x83
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #define IOC_VDEC_ACP_POSSIBLE_FIRMUP	0xA0	// by Andy(2016-06-26)
112*4882a593Smuzhiyun #define IOC_VDEC_ACP_CHECK_ISPSTATUS    0xA1	// by Andy(2016-07-12)
113*4882a593Smuzhiyun #define IOC_VDEC_ACP_START_FIRMUP	    0xA2	// by Andy(2016-07-12)
114*4882a593Smuzhiyun #define IOC_VDEC_ACP_FIRMUP				0xA3	// by Andy(2016-06-26)
115*4882a593Smuzhiyun #define IOC_VDEC_ACP_FIRMUP_END			0xA4	// by Andy(2016-06-26)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define IOC_VDEC_GET_ADC_CLK			0xB1
118*4882a593Smuzhiyun #define IOC_VDEC_SET_ADC_CLK			0xB2
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /*----------------------- Coaxial protocol  ---------------------*/
121*4882a593Smuzhiyun // Coax UP Stream - 8bit
122*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_INIT			  0xA0
123*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_CMD_SEND	  0xA1
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun // Coax UP Stream - 16bit only ACP 720P Support
126*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_16BIT_INIT		  0xB4
127*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_16BIT_CMD_SEND	  0xB5
128*4882a593Smuzhiyun #define IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND 0xB6
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun // Coax Down Stream
131*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_INIT      0xA2
132*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_DATA_READ 0xA3
133*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_BUF_CLEAR 0xA4
134*4882a593Smuzhiyun #define IOC_VDEC_COAX_RX_DEINIT    0xA5
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun // Coax Test
137*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ  0xA6
138*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_DATA_SET           0xA7
139*4882a593Smuzhiyun #define IOC_VDEC_COAX_TEST_DATA_READ          0xA8
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun // Coax FW Update
142*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_ACP_HEADER_GET     0xA9
143*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_READY_CMD_SET  0xAA
144*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_READY_ACK_GET  0xAB
145*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_START_CMD_SET  0xAC
146*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_START_ACK_GET  0xAD
147*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_SEND_DATA_SET  0xAE
148*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_SEND_ACK_GET   0xAF
149*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_END_CMD_SET    0xB0
150*4882a593Smuzhiyun #define IOC_VDEC_COAX_FW_END_ACK_GET    0xB1
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun // Bank Dump Test
153*4882a593Smuzhiyun #define IOC_VDEC_COAX_BANK_DUMP_GET    0xB2
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun // ACP Option
156*4882a593Smuzhiyun #define IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET 0xB3
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun /*----------------------- MOTION -----------------*/
159*4882a593Smuzhiyun #define IOC_VDEC_MOTION_SET			0x70
160*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PIXEL_SET     0x71
161*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PIXEL_GET     0x72
162*4882a593Smuzhiyun #define IOC_VDEC_MOTION_TSEN_SET      0x73
163*4882a593Smuzhiyun #define IOC_VDEC_MOTION_PSEN_SET      0x74
164*4882a593Smuzhiyun #define IOC_VDEC_MOTION_ALL_PIXEL_SET 0x75
165*4882a593Smuzhiyun #define IOC_VDEC_MOTION_DETECTION_GET 0x76
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun typedef struct _nvp6158_video_mode
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun     unsigned int chip;
170*4882a593Smuzhiyun     unsigned int mode;
171*4882a593Smuzhiyun 	unsigned char vformat[16];
172*4882a593Smuzhiyun 	unsigned char chmode[16];
173*4882a593Smuzhiyun }nvp6158_video_mode;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun typedef struct _nvp6158_chn_mode
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun     unsigned char ch;
178*4882a593Smuzhiyun 	unsigned char vformat;
179*4882a593Smuzhiyun 	unsigned char chmode;
180*4882a593Smuzhiyun }nvp6158_chn_mode;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun typedef struct _nvp6158_opt_mode
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	unsigned char chipsel;
185*4882a593Smuzhiyun     unsigned char portsel;
186*4882a593Smuzhiyun 	unsigned char portmode;
187*4882a593Smuzhiyun 	unsigned char chid;
188*4882a593Smuzhiyun }nvp6158_opt_mode;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun typedef struct _nvp6158_input_videofmt
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun     unsigned int inputvideofmt[16];
193*4882a593Smuzhiyun 	unsigned int getvideofmt[16];
194*4882a593Smuzhiyun 	unsigned int geteqstage[16];
195*4882a593Smuzhiyun 	unsigned int getacpdata[16][8];
196*4882a593Smuzhiyun }nvp6158_input_videofmt;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun typedef struct _nvp6158_input_videofmt_ch
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	unsigned char ch;
201*4882a593Smuzhiyun 	nvp6158_input_videofmt vfmt;
202*4882a593Smuzhiyun }nvp6158_input_videofmt_ch;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun typedef struct _nvp6124_i2c_mode
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	unsigned char flag;       // 0: read, 1 : write
207*4882a593Smuzhiyun 	unsigned char slaveaddr;
208*4882a593Smuzhiyun 	unsigned char bank;
209*4882a593Smuzhiyun 	unsigned char address;
210*4882a593Smuzhiyun 	unsigned char data;
211*4882a593Smuzhiyun }nvp6124_i2c_mode;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun typedef struct _nvp6158_video_adjust
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun  	unsigned char ch;
216*4882a593Smuzhiyun 	unsigned char value;
217*4882a593Smuzhiyun }nvp6158_video_adjust;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun typedef struct _nvp6158_motion_area
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun     unsigned char ch;
222*4882a593Smuzhiyun     int m_info[12];
223*4882a593Smuzhiyun }nvp6158_motion_area;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun typedef struct _nvp6158_audio_playback
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun     unsigned char chip;
228*4882a593Smuzhiyun     unsigned char ch;
229*4882a593Smuzhiyun }nvp6158_audio_playback;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun typedef struct _nvp6158_audio_da_mute
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun     unsigned char chip;
234*4882a593Smuzhiyun }nvp6158_audio_da_mute;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun typedef struct _nvp6158_audio_da_volume
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun     unsigned char chip;
239*4882a593Smuzhiyun     unsigned char volume;
240*4882a593Smuzhiyun }nvp6158_audio_da_volume;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun typedef struct _nvp6158_audio_format
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun 	unsigned char format;   /* 0:i2s; 1:dsp */
245*4882a593Smuzhiyun     unsigned char mode;   /* 0:slave 1:master*/
246*4882a593Smuzhiyun 	unsigned char dspformat; /*0:dsp;1:ssp*/
247*4882a593Smuzhiyun     unsigned char clkdir;  /*0:inverted;1:non-inverted*/
248*4882a593Smuzhiyun 	unsigned char chn_num; /*2,4,8,16*/
249*4882a593Smuzhiyun 	unsigned char bitrate; /*0:256fs 1:384fs invalid for nvp6114 2:320fs*/
250*4882a593Smuzhiyun 	unsigned char precision;/*0:16bit;1:8bit*/
251*4882a593Smuzhiyun 	unsigned char samplerate;/*0:8kHZ;1:16kHZ; 2:32kHZ*/
252*4882a593Smuzhiyun } nvp6158_audio_format;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun // by Andy(2016-06-26)
255*4882a593Smuzhiyun /*typedef struct __file_information
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	unsigned int	channel;
258*4882a593Smuzhiyun   	unsigned char 	filename[64];
259*4882a593Smuzhiyun   	unsigned char 	filePullname[64+32];
260*4882a593Smuzhiyun   	unsigned int	filesize;
261*4882a593Smuzhiyun   	unsigned int	filechecksum;			// (sum of file&0x0000FFFFF)
262*4882a593Smuzhiyun   	unsigned int	currentpacketnum;		// current packet sequnce number(0,1,2........)
263*4882a593Smuzhiyun   	unsigned int	filepacketnum;			// file packet number = (total size/128bytes), if remain exist, file packet number++
264*4882a593Smuzhiyun   	unsigned char 	onepacketbuf[128+32];
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun   	unsigned int	currentFileOffset;		// Current file offset
267*4882a593Smuzhiyun   	unsigned int	readsize;				// currnet read size
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun   	unsigned int	ispossiblefirmup[16]; 	// is it possible to update firmware?
270*4882a593Smuzhiyun   	int 			result;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun   	int				appstatus[16];			// Application status
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun } FIRMWARE_UP_FILE_INFO, *PFIRMWARE_UP_FILE_INFO;
275*4882a593Smuzhiyun */
276*4882a593Smuzhiyun enum __CABLE_TYPE_INFORMATION__
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun 	CABLE_TYPE_COAX=0,
279*4882a593Smuzhiyun 	CABLE_TYPE_UTP,
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	CABLE_TYPE_MAX
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun enum __DETECTION_TYPE_INFORMATION__
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	DETECTION_TYPE_AUTO=0,
287*4882a593Smuzhiyun 	DETECTION_TYPE_AHD,
288*4882a593Smuzhiyun 	DETECTION_TYPE_CHD,
289*4882a593Smuzhiyun 	DETECTION_TYPE_THD,
290*4882a593Smuzhiyun 	DETECTION_TYPE_CVBS,
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	DETECTION_TYPE_MAX
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun #define NVP6158_IOC_MAGIC            'n'
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #define NVP6158_SET_AUDIO_PLAYBACK   		_IOW(NVP6158_IOC_MAGIC, 0x21, nvp6158_audio_playback)
298*4882a593Smuzhiyun #define NVP6158_SET_AUDIO_DA_MUTE    		_IOW(NVP6158_IOC_MAGIC, 0x22, nvp6158_audio_da_mute)
299*4882a593Smuzhiyun #define NVP6158_SET_AUDIO_DA_VOLUME  		_IOW(NVP6158_IOC_MAGIC, 0x23, nvp6158_audio_da_volume)
300*4882a593Smuzhiyun /*set record format*/
301*4882a593Smuzhiyun #define NVP6158_SET_AUDIO_R_FORMAT     		_IOW(NVP6158_IOC_MAGIC, 0x24, nvp6158_audio_format)
302*4882a593Smuzhiyun /*set playback format*/
303*4882a593Smuzhiyun #define NVP6158_SET_AUDIO_PB_FORMAT     	_IOW(NVP6158_IOC_MAGIC, 0x25, nvp6158_audio_format)
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun #define _SET_BIT(data,bit) ((data)|=(1<<(bit)))
306*4882a593Smuzhiyun #define _CLE_BIT(data,bit) ((data)&=(~(1<<(bit))))
307*4882a593Smuzhiyun //////////////////////////////////////
308*4882a593Smuzhiyun typedef enum _NC_VIDEO_ONOFF
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	VIDEO_LOSS_ON = 0,
311*4882a593Smuzhiyun 	VIDEO_LOSS_OFF = 1,
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun } NC_VIDEO_ONOFF;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun typedef struct _decoder_dev_ch_info_s
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun 	unsigned char ch;
318*4882a593Smuzhiyun 	unsigned char devnum;
319*4882a593Smuzhiyun 	unsigned char fmt_def;
320*4882a593Smuzhiyun }decoder_dev_ch_info_s;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun typedef enum NC_VIVO_CH_FORMATDEF
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF_UNKNOWN = 0,
325*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF_AUTO,
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	AHD20_SD_H960_NT,   //960h*480i
328*4882a593Smuzhiyun 	AHD20_SD_H960_PAL,  //960h*576i
329*4882a593Smuzhiyun 	AHD20_SD_SH720_NT,  //720h*480i
330*4882a593Smuzhiyun 	AHD20_SD_SH720_PAL, //720h*576i
331*4882a593Smuzhiyun 	AHD20_SD_H1280_NT,
332*4882a593Smuzhiyun 	AHD20_SD_H1280_PAL,
333*4882a593Smuzhiyun 	AHD20_SD_H1440_NT,
334*4882a593Smuzhiyun 	AHD20_SD_H1440_PAL,
335*4882a593Smuzhiyun 	AHD20_SD_H960_EX_NT,  //1920h*480i
336*4882a593Smuzhiyun 	AHD20_SD_H960_EX_PAL, //1920h*576i
337*4882a593Smuzhiyun 	AHD20_SD_H960_2EX_NT,
338*4882a593Smuzhiyun 	AHD20_SD_H960_2EX_PAL,
339*4882a593Smuzhiyun 	AHD20_SD_H960_2EX_Btype_NT,	 //3840h*480i
340*4882a593Smuzhiyun 	AHD20_SD_H960_2EX_Btype_PAL, //3840h*576i
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	AHD30_4M_30P,
343*4882a593Smuzhiyun 	AHD30_4M_25P,
344*4882a593Smuzhiyun 	AHD30_4M_15P,
345*4882a593Smuzhiyun 	AHD30_3M_30P,
346*4882a593Smuzhiyun 	AHD30_3M_25P,
347*4882a593Smuzhiyun 	AHD30_3M_18P,	//2048 x 1536
348*4882a593Smuzhiyun 	AHD30_5M_12_5P,	//2592 x 1944
349*4882a593Smuzhiyun 	AHD30_5M_20P,	//2592 x 1944
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	AHD30_5_3M_20P,
352*4882a593Smuzhiyun 	AHD30_6M_18P,
353*4882a593Smuzhiyun 	AHD30_6M_20P,
354*4882a593Smuzhiyun 	AHD30_8M_X_30P,
355*4882a593Smuzhiyun 	AHD30_8M_X_25P,
356*4882a593Smuzhiyun 	AHD30_8M_7_5P,
357*4882a593Smuzhiyun 	AHD30_8M_12_5P,
358*4882a593Smuzhiyun 	AHD30_8M_15P,
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	TVI_FHD_30P,
361*4882a593Smuzhiyun 	TVI_FHD_25P,
362*4882a593Smuzhiyun 	TVI_HD_60P,
363*4882a593Smuzhiyun 	TVI_HD_50P,
364*4882a593Smuzhiyun 	TVI_HD_30P,
365*4882a593Smuzhiyun 	TVI_HD_25P,
366*4882a593Smuzhiyun 	TVI_HD_30P_EX,
367*4882a593Smuzhiyun 	TVI_HD_25P_EX,
368*4882a593Smuzhiyun 	TVI_HD_B_30P,
369*4882a593Smuzhiyun 	TVI_HD_B_25P,
370*4882a593Smuzhiyun 	TVI_HD_B_30P_EX,
371*4882a593Smuzhiyun 	TVI_HD_B_25P_EX,
372*4882a593Smuzhiyun 	TVI_3M_18P,	//1920 x 1536
373*4882a593Smuzhiyun 	TVI_5M_12_5P,
374*4882a593Smuzhiyun 	TVI_5M_20P,
375*4882a593Smuzhiyun 	TVI_4M_30P,
376*4882a593Smuzhiyun 	TVI_4M_25P,
377*4882a593Smuzhiyun 	TVI_4M_15P,
378*4882a593Smuzhiyun 	TVI_8M_15P,
379*4882a593Smuzhiyun 	TVI_8M_12_5P,
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	CVI_FHD_30P,
382*4882a593Smuzhiyun 	CVI_FHD_25P,
383*4882a593Smuzhiyun 	CVI_HD_60P,
384*4882a593Smuzhiyun 	CVI_HD_50P,
385*4882a593Smuzhiyun 	CVI_HD_30P,
386*4882a593Smuzhiyun 	CVI_HD_25P,
387*4882a593Smuzhiyun 	CVI_HD_30P_EX,
388*4882a593Smuzhiyun 	CVI_HD_25P_EX,
389*4882a593Smuzhiyun 	CVI_4M_30P,
390*4882a593Smuzhiyun 	CVI_4M_25P,
391*4882a593Smuzhiyun 	CVI_5M_20P,
392*4882a593Smuzhiyun 	CVI_8M_15P,
393*4882a593Smuzhiyun 	CVI_8M_12_5P,
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	AHD20_1080P_60P,
396*4882a593Smuzhiyun 	AHD20_1080P_50P,
397*4882a593Smuzhiyun 	AHD20_1080P_15P,
398*4882a593Smuzhiyun 	AHD20_1080P_12_5P,
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	TVI_FHD_60P,
401*4882a593Smuzhiyun 	TVI_FHD_50P,
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	AHD20_960P_30P,
404*4882a593Smuzhiyun 	AHD20_960P_25P,
405*4882a593Smuzhiyun 	AHD20_960P_60P,
406*4882a593Smuzhiyun 	AHD20_960P_50P,
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	AHD20_1080P_15P_EX, // Hidden For test
409*4882a593Smuzhiyun 	AHD20_1080P_12_5P_EX, // Hidden For test
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	AHD20_720P_15P_2EX_Btype, // Hidden For test
412*4882a593Smuzhiyun 	AHD20_720P_12_5P_2EX_Btype, // Hidden For test
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	AHD20_720P_15P_EX_Btype, // Hidden For test
415*4882a593Smuzhiyun 	AHD20_720P_12_5P_EX_Btype, // Hidden For test
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	AHD20_1080P_30P,
418*4882a593Smuzhiyun 	AHD20_1080P_25P,
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	AHD20_720P_60P,
421*4882a593Smuzhiyun 	AHD20_720P_50P,
422*4882a593Smuzhiyun 	AHD20_720P_30P,
423*4882a593Smuzhiyun 	AHD20_720P_25P,
424*4882a593Smuzhiyun 	AHD20_720P_30P_EX,
425*4882a593Smuzhiyun 	AHD20_720P_25P_EX,
426*4882a593Smuzhiyun 	AHD20_720P_30P_EX_Btype,
427*4882a593Smuzhiyun 	AHD20_720P_25P_EX_Btype,
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF_MAX,
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun } NC_VIVO_CH_FORMATDEF;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun typedef enum NC_FORMAT_FPS
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	FMT_FPS_UNKNOWN = 0,
436*4882a593Smuzhiyun 	FMT_NT = 1,
437*4882a593Smuzhiyun 	FMT_PAL,
438*4882a593Smuzhiyun 	FMT_12_5P,
439*4882a593Smuzhiyun 	FMT_7_5P,
440*4882a593Smuzhiyun 	FMT_30P,
441*4882a593Smuzhiyun 	FMT_25P,
442*4882a593Smuzhiyun 	FMT_50P,
443*4882a593Smuzhiyun 	FMT_60P,
444*4882a593Smuzhiyun 	FMT_15P,
445*4882a593Smuzhiyun 	FMT_18P,
446*4882a593Smuzhiyun 	FMT_18_75P,
447*4882a593Smuzhiyun 	FMT_20P,
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	FMT_FPS_MAX,
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun } NC_FORMAT_FPS;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun typedef enum NC_FORMAT_STANDARD
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	FMT_STD_UNKNOWN = 0,
456*4882a593Smuzhiyun 	FMT_SD,
457*4882a593Smuzhiyun 	FMT_AHD20,
458*4882a593Smuzhiyun 	FMT_AHD30,
459*4882a593Smuzhiyun 	FMT_TVI,
460*4882a593Smuzhiyun 	FMT_CVI,
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	FMT_AUTO,		// FIXME
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	FMT_STD_MAX,
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun } NC_FORMAT_STANDARD;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun typedef enum NC_FORMAT_RESOLUTION
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	FMT_RESOL_UNKNOWN = 0,
471*4882a593Smuzhiyun 	FMT_SH720,
472*4882a593Smuzhiyun 	FMT_H960,
473*4882a593Smuzhiyun 	FMT_H1280,
474*4882a593Smuzhiyun 	FMT_H1440,
475*4882a593Smuzhiyun 	FMT_H960_EX,
476*4882a593Smuzhiyun 	FMT_H960_2EX,
477*4882a593Smuzhiyun 	FMT_H960_Btype_2EX,
478*4882a593Smuzhiyun 	FMT_720P,
479*4882a593Smuzhiyun 	FMT_720P_EX,
480*4882a593Smuzhiyun 	FMT_720P_Btype,
481*4882a593Smuzhiyun 	FMT_720P_Btype_EX,
482*4882a593Smuzhiyun 	FMT_1080P,
483*4882a593Smuzhiyun 	FMT_1080P_EX,
484*4882a593Smuzhiyun 	FMT_3M,
485*4882a593Smuzhiyun 	FMT_4M,
486*4882a593Smuzhiyun 	FMT_5M,
487*4882a593Smuzhiyun 	FMT_5_3M,
488*4882a593Smuzhiyun 	FMT_6M,
489*4882a593Smuzhiyun 	FMT_8M_X,
490*4882a593Smuzhiyun 	FMT_8M,
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	FMT_H960_Btype_2EX_SP,
493*4882a593Smuzhiyun 	FMT_720P_Btype_EX_SP,
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	FMT_RESOL_MAX,
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun } NC_FORMAT_RESOLUTION;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun typedef enum _dvp_mode
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun 	BT601 = 0,
502*4882a593Smuzhiyun 	BT656_1MUX,
503*4882a593Smuzhiyun 	BT656_2MUX,
504*4882a593Smuzhiyun 	BT656_4MUX,
505*4882a593Smuzhiyun 	BT656I_TEST_MODES,
506*4882a593Smuzhiyun 	BT1120_1MUX,
507*4882a593Smuzhiyun 	BT1120_2MUX,
508*4882a593Smuzhiyun 	BT1120_4MUX,
509*4882a593Smuzhiyun 	NVP6158_DVP_MODES_END
510*4882a593Smuzhiyun } NVP6158_DVP_MODE;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun typedef struct VDEC_DEV_INFORM_S{
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	unsigned char nvp6158_chip_id[4];
515*4882a593Smuzhiyun 	unsigned char chip_rev[4];
516*4882a593Smuzhiyun 	unsigned char chip_addr[4];
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	unsigned char Total_Port_Num;
519*4882a593Smuzhiyun 	unsigned char Total_Chip_Cnt;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun }VDEC_DEV_INFORM_S;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun typedef struct _NVP6158_INFORMATION_S
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun 	unsigned char			ch;
526*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF 	curvideofmt[ 16 ];
527*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF 	prevideofmt[ 16 ];
528*4882a593Smuzhiyun 	unsigned char 		 	curvideoloss[ 16 ];
529*4882a593Smuzhiyun 	unsigned char			vfc[16];
530*4882a593Smuzhiyun 	unsigned char			debounce[16][5];
531*4882a593Smuzhiyun 	unsigned char			debounceidx[16];
532*4882a593Smuzhiyun 	VDEC_DEV_INFORM_S 		chipinform;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun } NVP6158_INFORMATION_S;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun #endif
537*4882a593Smuzhiyun 
538