1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************** 3 * 4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved. 5 * Module : Common header file 6 * Description : This file is common header file 7 * Author : 8 * Date : 9 * Version : Version 2.0 10 * 11 ******************************************************************************** 12 * History : 13 * 14 * 15 ********************************************************************************/ 16 #ifndef __COMMON_H__ 17 #define __COMMON_H__ 18 19 unsigned char nvp6158_I2CReadByte8(unsigned char devaddress, unsigned char address); 20 void nvp6158_I2CWriteByte8(unsigned char devaddress, unsigned char address, unsigned char data); 21 22 #define gpio_i2c_read nvp6158_I2CReadByte8 23 #define gpio_i2c_write nvp6158_I2CWriteByte8 24 25 //#define STREAM_ON_DEFLAULT 26 27 #define I2C_0 (0) 28 #define I2C_1 (1) 29 #define I2C_2 (2) 30 #define I2C_3 (3) 31 32 // device address define 33 #define NVP6158_R0_ID 0xA1 34 #define NVP6158C_R0_ID 0xA0 //6158B AND 6158C USES THE SAME CHIPID,DIFF IN REV_ID 35 #define NVP6158_REV_ID 0x00 36 #define NVP6168_R0_ID 0xC1 37 #define NVP6168C_R0_ID 0xC0 38 //#define NVP6158C_REV_ID 0x01 39 #define CH_PER_CHIP 4 40 41 #define NTSC 0x00 42 #define PAL 0x01 43 44 #define AHD_PELCO_16BIT 45 46 enum { 47 NC_AD_SAMPLE_RATE_8000 = 8000, 48 NC_AD_SAMPLE_RATE_16000 = 16000, 49 NC_AD_SAMPLE_RATE_32000 = 32000, 50 NC_AD_SAMPLE_RATE_44100 = 44100, 51 52 NC_AD_SAMPLE_RATE_MAX, 53 }; 54 55 enum { 56 NC_AD_AI = 0, 57 NC_AD_AOC, 58 59 NC_AD_MAX 60 }; 61 62 enum { 63 NC_AD_BIT_WIDTH_8 = 0, 64 NC_AD_BIT_WIDTH_16, 65 NC_AD_BIT_WIDTH_24, 66 67 NC_AD_BIT_WIDTH_MAX 68 }; 69 70 //FIXME HI3520 Register 71 #define VIU_CH_CTRL 0x08 72 #define VIU_ANC0_START 0x9c 73 #define VIU_ANC0_SIZE 0xa0 74 #define VIU_ANC1_START 0xa4 75 #define VIU_ANC1_SIZE 0xa8 76 #define VIU_BLANK_DATA_ADDR 0xac 77 78 #define IOC_VDEC_GET_EQ_DIST 0x07 79 #define IOC_VDEC_GET_INPUT_VIDEO_FMT 0x08 80 #define IOC_VDEC_GET_VIDEO_LOSS 0x09 81 #define IOC_VDEC_SET_SYNC 0x0A 82 #define IOC_VDEC_SET_EQUALIZER 0x0B 83 #define IOC_VDEC_GET_DRIVERVER 0x0C 84 #define IOC_VDEC_PTZ_ACP_READ 0x0D 85 #define IOC_VDEC_SET_BRIGHTNESS 0x0E 86 #define IOC_VDEC_SET_CONTRAST 0x0F 87 #define IOC_VDEC_SET_HUE 0x10 88 #define IOC_VDEC_SET_SATURATION 0x11 89 #define IOC_VDEC_SET_SHARPNESS 0x12 90 #define IOC_VDEC_SET_CHNMODE 0x13 91 #define IOC_VDEC_SET_OUTPORTMODE 0x14 92 #define IOC_VDEC_SET_CHDETMODE 0x15 93 94 #define IOC_VDEC_ACP_WRITE 0x2f 95 #define IOC_VDEC_ACP_WRITE_EXTENTION 0x30 96 #define IOC_VDEC_PTZ_ACP_READ_EACH_CH 0x31 97 98 #define IOC_VDEC_INIT_MOTION 0x40 99 #define IOC_VDEC_ENABLE_MOTION 0x41 100 #define IOC_VDEC_DISABLE_MOTION 0x42 101 #define IOC_VDEC_SET_MOTION_AREA 0x43 102 #define IOC_VDEC_GET_MOTION_INFO 0x44 103 #define IOC_VDEC_SET_MOTION_DISPLAY 0x45 104 #define IOC_VDEC_SET_MOTION_SENS 0x46 105 106 #define IOC_AUDIO_SET_CHNNUM 0x80 107 #define IOC_AUDIO_SET_SAMPLE_RATE 0x81 108 #define IOC_AUDIO_SET_BITWIDTH 0x82 109 #define IOC_VDEC_SET_I2C 0x83 110 111 #define IOC_VDEC_ACP_POSSIBLE_FIRMUP 0xA0 // by Andy(2016-06-26) 112 #define IOC_VDEC_ACP_CHECK_ISPSTATUS 0xA1 // by Andy(2016-07-12) 113 #define IOC_VDEC_ACP_START_FIRMUP 0xA2 // by Andy(2016-07-12) 114 #define IOC_VDEC_ACP_FIRMUP 0xA3 // by Andy(2016-06-26) 115 #define IOC_VDEC_ACP_FIRMUP_END 0xA4 // by Andy(2016-06-26) 116 117 #define IOC_VDEC_GET_ADC_CLK 0xB1 118 #define IOC_VDEC_SET_ADC_CLK 0xB2 119 120 /*----------------------- Coaxial protocol ---------------------*/ 121 // Coax UP Stream - 8bit 122 #define IOC_VDEC_COAX_TX_INIT 0xA0 123 #define IOC_VDEC_COAX_TX_CMD_SEND 0xA1 124 125 // Coax UP Stream - 16bit only ACP 720P Support 126 #define IOC_VDEC_COAX_TX_16BIT_INIT 0xB4 127 #define IOC_VDEC_COAX_TX_16BIT_CMD_SEND 0xB5 128 #define IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND 0xB6 129 130 // Coax Down Stream 131 #define IOC_VDEC_COAX_RX_INIT 0xA2 132 #define IOC_VDEC_COAX_RX_DATA_READ 0xA3 133 #define IOC_VDEC_COAX_RX_BUF_CLEAR 0xA4 134 #define IOC_VDEC_COAX_RX_DEINIT 0xA5 135 136 // Coax Test 137 #define IOC_VDEC_COAX_TEST_TX_INIT_DATA_READ 0xA6 138 #define IOC_VDEC_COAX_TEST_DATA_SET 0xA7 139 #define IOC_VDEC_COAX_TEST_DATA_READ 0xA8 140 141 // Coax FW Update 142 #define IOC_VDEC_COAX_FW_ACP_HEADER_GET 0xA9 143 #define IOC_VDEC_COAX_FW_READY_CMD_SET 0xAA 144 #define IOC_VDEC_COAX_FW_READY_ACK_GET 0xAB 145 #define IOC_VDEC_COAX_FW_START_CMD_SET 0xAC 146 #define IOC_VDEC_COAX_FW_START_ACK_GET 0xAD 147 #define IOC_VDEC_COAX_FW_SEND_DATA_SET 0xAE 148 #define IOC_VDEC_COAX_FW_SEND_ACK_GET 0xAF 149 #define IOC_VDEC_COAX_FW_END_CMD_SET 0xB0 150 #define IOC_VDEC_COAX_FW_END_ACK_GET 0xB1 151 152 // Bank Dump Test 153 #define IOC_VDEC_COAX_BANK_DUMP_GET 0xB2 154 155 // ACP Option 156 #define IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET 0xB3 157 158 /*----------------------- MOTION -----------------*/ 159 #define IOC_VDEC_MOTION_SET 0x70 160 #define IOC_VDEC_MOTION_PIXEL_SET 0x71 161 #define IOC_VDEC_MOTION_PIXEL_GET 0x72 162 #define IOC_VDEC_MOTION_TSEN_SET 0x73 163 #define IOC_VDEC_MOTION_PSEN_SET 0x74 164 #define IOC_VDEC_MOTION_ALL_PIXEL_SET 0x75 165 #define IOC_VDEC_MOTION_DETECTION_GET 0x76 166 167 typedef struct _nvp6158_video_mode 168 { 169 unsigned int chip; 170 unsigned int mode; 171 unsigned char vformat[16]; 172 unsigned char chmode[16]; 173 }nvp6158_video_mode; 174 175 typedef struct _nvp6158_chn_mode 176 { 177 unsigned char ch; 178 unsigned char vformat; 179 unsigned char chmode; 180 }nvp6158_chn_mode; 181 182 typedef struct _nvp6158_opt_mode 183 { 184 unsigned char chipsel; 185 unsigned char portsel; 186 unsigned char portmode; 187 unsigned char chid; 188 }nvp6158_opt_mode; 189 190 typedef struct _nvp6158_input_videofmt 191 { 192 unsigned int inputvideofmt[16]; 193 unsigned int getvideofmt[16]; 194 unsigned int geteqstage[16]; 195 unsigned int getacpdata[16][8]; 196 }nvp6158_input_videofmt; 197 198 typedef struct _nvp6158_input_videofmt_ch 199 { 200 unsigned char ch; 201 nvp6158_input_videofmt vfmt; 202 }nvp6158_input_videofmt_ch; 203 204 typedef struct _nvp6124_i2c_mode 205 { 206 unsigned char flag; // 0: read, 1 : write 207 unsigned char slaveaddr; 208 unsigned char bank; 209 unsigned char address; 210 unsigned char data; 211 }nvp6124_i2c_mode; 212 213 typedef struct _nvp6158_video_adjust 214 { 215 unsigned char ch; 216 unsigned char value; 217 }nvp6158_video_adjust; 218 219 typedef struct _nvp6158_motion_area 220 { 221 unsigned char ch; 222 int m_info[12]; 223 }nvp6158_motion_area; 224 225 typedef struct _nvp6158_audio_playback 226 { 227 unsigned char chip; 228 unsigned char ch; 229 }nvp6158_audio_playback; 230 231 typedef struct _nvp6158_audio_da_mute 232 { 233 unsigned char chip; 234 }nvp6158_audio_da_mute; 235 236 typedef struct _nvp6158_audio_da_volume 237 { 238 unsigned char chip; 239 unsigned char volume; 240 }nvp6158_audio_da_volume; 241 242 typedef struct _nvp6158_audio_format 243 { 244 unsigned char format; /* 0:i2s; 1:dsp */ 245 unsigned char mode; /* 0:slave 1:master*/ 246 unsigned char dspformat; /*0:dsp;1:ssp*/ 247 unsigned char clkdir; /*0:inverted;1:non-inverted*/ 248 unsigned char chn_num; /*2,4,8,16*/ 249 unsigned char bitrate; /*0:256fs 1:384fs invalid for nvp6114 2:320fs*/ 250 unsigned char precision;/*0:16bit;1:8bit*/ 251 unsigned char samplerate;/*0:8kHZ;1:16kHZ; 2:32kHZ*/ 252 } nvp6158_audio_format; 253 254 // by Andy(2016-06-26) 255 /*typedef struct __file_information 256 { 257 unsigned int channel; 258 unsigned char filename[64]; 259 unsigned char filePullname[64+32]; 260 unsigned int filesize; 261 unsigned int filechecksum; // (sum of file&0x0000FFFFF) 262 unsigned int currentpacketnum; // current packet sequnce number(0,1,2........) 263 unsigned int filepacketnum; // file packet number = (total size/128bytes), if remain exist, file packet number++ 264 unsigned char onepacketbuf[128+32]; 265 266 unsigned int currentFileOffset; // Current file offset 267 unsigned int readsize; // currnet read size 268 269 unsigned int ispossiblefirmup[16]; // is it possible to update firmware? 270 int result; 271 272 int appstatus[16]; // Application status 273 274 } FIRMWARE_UP_FILE_INFO, *PFIRMWARE_UP_FILE_INFO; 275 */ 276 enum __CABLE_TYPE_INFORMATION__ 277 { 278 CABLE_TYPE_COAX=0, 279 CABLE_TYPE_UTP, 280 281 CABLE_TYPE_MAX 282 }; 283 284 enum __DETECTION_TYPE_INFORMATION__ 285 { 286 DETECTION_TYPE_AUTO=0, 287 DETECTION_TYPE_AHD, 288 DETECTION_TYPE_CHD, 289 DETECTION_TYPE_THD, 290 DETECTION_TYPE_CVBS, 291 292 DETECTION_TYPE_MAX 293 }; 294 295 #define NVP6158_IOC_MAGIC 'n' 296 297 #define NVP6158_SET_AUDIO_PLAYBACK _IOW(NVP6158_IOC_MAGIC, 0x21, nvp6158_audio_playback) 298 #define NVP6158_SET_AUDIO_DA_MUTE _IOW(NVP6158_IOC_MAGIC, 0x22, nvp6158_audio_da_mute) 299 #define NVP6158_SET_AUDIO_DA_VOLUME _IOW(NVP6158_IOC_MAGIC, 0x23, nvp6158_audio_da_volume) 300 /*set record format*/ 301 #define NVP6158_SET_AUDIO_R_FORMAT _IOW(NVP6158_IOC_MAGIC, 0x24, nvp6158_audio_format) 302 /*set playback format*/ 303 #define NVP6158_SET_AUDIO_PB_FORMAT _IOW(NVP6158_IOC_MAGIC, 0x25, nvp6158_audio_format) 304 305 #define _SET_BIT(data,bit) ((data)|=(1<<(bit))) 306 #define _CLE_BIT(data,bit) ((data)&=(~(1<<(bit)))) 307 ////////////////////////////////////// 308 typedef enum _NC_VIDEO_ONOFF 309 { 310 VIDEO_LOSS_ON = 0, 311 VIDEO_LOSS_OFF = 1, 312 313 } NC_VIDEO_ONOFF; 314 315 typedef struct _decoder_dev_ch_info_s 316 { 317 unsigned char ch; 318 unsigned char devnum; 319 unsigned char fmt_def; 320 }decoder_dev_ch_info_s; 321 322 typedef enum NC_VIVO_CH_FORMATDEF 323 { 324 NC_VIVO_CH_FORMATDEF_UNKNOWN = 0, 325 NC_VIVO_CH_FORMATDEF_AUTO, 326 327 AHD20_SD_H960_NT, //960h*480i 328 AHD20_SD_H960_PAL, //960h*576i 329 AHD20_SD_SH720_NT, //720h*480i 330 AHD20_SD_SH720_PAL, //720h*576i 331 AHD20_SD_H1280_NT, 332 AHD20_SD_H1280_PAL, 333 AHD20_SD_H1440_NT, 334 AHD20_SD_H1440_PAL, 335 AHD20_SD_H960_EX_NT, //1920h*480i 336 AHD20_SD_H960_EX_PAL, //1920h*576i 337 AHD20_SD_H960_2EX_NT, 338 AHD20_SD_H960_2EX_PAL, 339 AHD20_SD_H960_2EX_Btype_NT, //3840h*480i 340 AHD20_SD_H960_2EX_Btype_PAL, //3840h*576i 341 342 AHD30_4M_30P, 343 AHD30_4M_25P, 344 AHD30_4M_15P, 345 AHD30_3M_30P, 346 AHD30_3M_25P, 347 AHD30_3M_18P, //2048 x 1536 348 AHD30_5M_12_5P, //2592 x 1944 349 AHD30_5M_20P, //2592 x 1944 350 351 AHD30_5_3M_20P, 352 AHD30_6M_18P, 353 AHD30_6M_20P, 354 AHD30_8M_X_30P, 355 AHD30_8M_X_25P, 356 AHD30_8M_7_5P, 357 AHD30_8M_12_5P, 358 AHD30_8M_15P, 359 360 TVI_FHD_30P, 361 TVI_FHD_25P, 362 TVI_HD_60P, 363 TVI_HD_50P, 364 TVI_HD_30P, 365 TVI_HD_25P, 366 TVI_HD_30P_EX, 367 TVI_HD_25P_EX, 368 TVI_HD_B_30P, 369 TVI_HD_B_25P, 370 TVI_HD_B_30P_EX, 371 TVI_HD_B_25P_EX, 372 TVI_3M_18P, //1920 x 1536 373 TVI_5M_12_5P, 374 TVI_5M_20P, 375 TVI_4M_30P, 376 TVI_4M_25P, 377 TVI_4M_15P, 378 TVI_8M_15P, 379 TVI_8M_12_5P, 380 381 CVI_FHD_30P, 382 CVI_FHD_25P, 383 CVI_HD_60P, 384 CVI_HD_50P, 385 CVI_HD_30P, 386 CVI_HD_25P, 387 CVI_HD_30P_EX, 388 CVI_HD_25P_EX, 389 CVI_4M_30P, 390 CVI_4M_25P, 391 CVI_5M_20P, 392 CVI_8M_15P, 393 CVI_8M_12_5P, 394 395 AHD20_1080P_60P, 396 AHD20_1080P_50P, 397 AHD20_1080P_15P, 398 AHD20_1080P_12_5P, 399 400 TVI_FHD_60P, 401 TVI_FHD_50P, 402 403 AHD20_960P_30P, 404 AHD20_960P_25P, 405 AHD20_960P_60P, 406 AHD20_960P_50P, 407 408 AHD20_1080P_15P_EX, // Hidden For test 409 AHD20_1080P_12_5P_EX, // Hidden For test 410 411 AHD20_720P_15P_2EX_Btype, // Hidden For test 412 AHD20_720P_12_5P_2EX_Btype, // Hidden For test 413 414 AHD20_720P_15P_EX_Btype, // Hidden For test 415 AHD20_720P_12_5P_EX_Btype, // Hidden For test 416 417 AHD20_1080P_30P, 418 AHD20_1080P_25P, 419 420 AHD20_720P_60P, 421 AHD20_720P_50P, 422 AHD20_720P_30P, 423 AHD20_720P_25P, 424 AHD20_720P_30P_EX, 425 AHD20_720P_25P_EX, 426 AHD20_720P_30P_EX_Btype, 427 AHD20_720P_25P_EX_Btype, 428 429 NC_VIVO_CH_FORMATDEF_MAX, 430 431 } NC_VIVO_CH_FORMATDEF; 432 433 typedef enum NC_FORMAT_FPS 434 { 435 FMT_FPS_UNKNOWN = 0, 436 FMT_NT = 1, 437 FMT_PAL, 438 FMT_12_5P, 439 FMT_7_5P, 440 FMT_30P, 441 FMT_25P, 442 FMT_50P, 443 FMT_60P, 444 FMT_15P, 445 FMT_18P, 446 FMT_18_75P, 447 FMT_20P, 448 449 FMT_FPS_MAX, 450 451 } NC_FORMAT_FPS; 452 453 typedef enum NC_FORMAT_STANDARD 454 { 455 FMT_STD_UNKNOWN = 0, 456 FMT_SD, 457 FMT_AHD20, 458 FMT_AHD30, 459 FMT_TVI, 460 FMT_CVI, 461 462 FMT_AUTO, // FIXME 463 464 FMT_STD_MAX, 465 466 } NC_FORMAT_STANDARD; 467 468 typedef enum NC_FORMAT_RESOLUTION 469 { 470 FMT_RESOL_UNKNOWN = 0, 471 FMT_SH720, 472 FMT_H960, 473 FMT_H1280, 474 FMT_H1440, 475 FMT_H960_EX, 476 FMT_H960_2EX, 477 FMT_H960_Btype_2EX, 478 FMT_720P, 479 FMT_720P_EX, 480 FMT_720P_Btype, 481 FMT_720P_Btype_EX, 482 FMT_1080P, 483 FMT_1080P_EX, 484 FMT_3M, 485 FMT_4M, 486 FMT_5M, 487 FMT_5_3M, 488 FMT_6M, 489 FMT_8M_X, 490 FMT_8M, 491 492 FMT_H960_Btype_2EX_SP, 493 FMT_720P_Btype_EX_SP, 494 495 FMT_RESOL_MAX, 496 497 } NC_FORMAT_RESOLUTION; 498 499 typedef enum _dvp_mode 500 { 501 BT601 = 0, 502 BT656_1MUX, 503 BT656_2MUX, 504 BT656_4MUX, 505 BT656I_TEST_MODES, 506 BT1120_1MUX, 507 BT1120_2MUX, 508 BT1120_4MUX, 509 NVP6158_DVP_MODES_END 510 } NVP6158_DVP_MODE; 511 512 typedef struct VDEC_DEV_INFORM_S{ 513 514 unsigned char nvp6158_chip_id[4]; 515 unsigned char chip_rev[4]; 516 unsigned char chip_addr[4]; 517 518 unsigned char Total_Port_Num; 519 unsigned char Total_Chip_Cnt; 520 521 }VDEC_DEV_INFORM_S; 522 523 typedef struct _NVP6158_INFORMATION_S 524 { 525 unsigned char ch; 526 NC_VIVO_CH_FORMATDEF curvideofmt[ 16 ]; 527 NC_VIVO_CH_FORMATDEF prevideofmt[ 16 ]; 528 unsigned char curvideoloss[ 16 ]; 529 unsigned char vfc[16]; 530 unsigned char debounce[16][5]; 531 unsigned char debounceidx[16]; 532 VDEC_DEV_INFORM_S chipinform; 533 534 } NVP6158_INFORMATION_S; 535 536 #endif 537 538