1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * max96712 GMSL2/GMSL1 to CSI-2 Deserializer driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 * V1.0.00 first version.
8 * V1.1.00 support Frame synchronization, stream on speed optimization.
9 * V1.2.00 enable lock gpio for hotplug irq.
10 * add i2c regmap for debug.
11 * support modes enable select.
12 * auto initial deskew enable configure.
13 * frame sync period enable configure.
14 * V1.3.00 t_lpx timing adjust from 53.4ns to 106.7ns.
15 * mipi dpll predef rate set api.
16 * V1.4.00 i2c read/write api update.
17 * support for GMSL1 Link.
18 * V1.5.00 only check max96712 chipid when probe.
19 * enable stream out if not all link are locked.
20 * V1.6.00 serdes read /write api depend on i2c id index.
21 *
22 */
23
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/delay.h>
27 #include <linux/iopoll.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/i2c.h>
31 #include <linux/regmap.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/sysfs.h>
36 #include <linux/slab.h>
37 #include <linux/version.h>
38 #include <linux/compat.h>
39 #include <linux/rk-camera-module.h>
40 #include <linux/of_graph.h>
41 #include <media/media-entity.h>
42 #include <media/v4l2-async.h>
43 #include <media/v4l2-ctrls.h>
44 #include <media/v4l2-subdev.h>
45 #include <media/v4l2-ctrls.h>
46 #include <media/v4l2-fwnode.h>
47 #include <media/v4l2-subdev.h>
48
49 #define DRIVER_VERSION KERNEL_VERSION(1, 0x06, 0x00)
50
51 #ifndef V4L2_CID_DIGITAL_GAIN
52 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
53 #endif
54
55 #define MAX96712_LINK_FREQ_MHZ(x) ((x) * 1000000UL)
56 #define MAX96712_XVCLK_FREQ 25000000
57
58 #define MAX96712_CHIP_ID 0xA0
59 #define MAX96712_REG_CHIP_ID 0x0D
60
61 #define MAX96715_CHIP_ID 0x45
62 #define MAX96715_REG_CHIP_ID 0x1E
63
64 #define MAX96717_CHIP_ID 0xBF
65 #define MAX96717_REG_CHIP_ID 0x0D
66
67 /* max96712->link mask: link type = bit[7:4], link mask = bit[3:0] */
68 #define MAXIM_GMSL_TYPE_LINK_A BIT(4)
69 #define MAXIM_GMSL_TYPE_LINK_B BIT(5)
70 #define MAXIM_GMSL_TYPE_LINK_C BIT(6)
71 #define MAXIM_GMSL_TYPE_LINK_D BIT(7)
72 #define MAXIM_GMSL_TYPE_MASK 0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */
73
74 #define MAXIM_GMSL_LOCK_LINK_A BIT(0)
75 #define MAXIM_GMSL_LOCK_LINK_B BIT(1)
76 #define MAXIM_GMSL_LOCK_LINK_C BIT(2)
77 #define MAXIM_GMSL_LOCK_LINK_D BIT(3)
78 #define MAXIM_GMSL_LOCK_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */
79
80 #define MAXIM_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84
85 #define MAX96712_NAME "max96712"
86
87 #define REG_NULL 0xFFFF
88
89 /* register length: 8bit or 16bit */
90 #define DEV_REG_LENGTH_08BITS 1
91 #define DEV_REG_LENGTH_16BITS 2
92
93 /* register value: 8bit or 16bit or 24bit */
94 #define DEV_REG_VALUE_08BITS 1
95 #define DEV_REG_VALUE_16BITS 2
96 #define DEV_REG_VALUE_24BITS 3
97
98 /* i2c device default address */
99 #define SER_I2C_ADDR (0x40)
100 #define CAM_I2C_ADDR (0x30)
101
102 /* Maxim Serdes I2C Device ID */
103 enum {
104 I2C_DEV_DES = 0,
105 I2C_DEV_SER,
106 I2C_DEV_CAM,
107 I2C_DEV_MAX
108 };
109
110 enum max96712_rx_rate {
111 MAX96712_RX_RATE_3GBPS = 0,
112 MAX96712_RX_RATE_6GBPS,
113 };
114
115 static const char *const max96712_supply_names[] = {
116 "avdd", /* Analog power */
117 "dovdd", /* Digital I/O power */
118 "dvdd", /* Digital core power */
119 };
120
121 #define MAX96712_NUM_SUPPLIES ARRAY_SIZE(max96712_supply_names)
122
123 struct regval {
124 u16 i2c_id;
125 u16 reg_len;
126 u16 reg;
127 u8 val;
128 u8 mask;
129 u16 delay;
130 };
131
132 struct max96712_mode {
133 u32 width;
134 u32 height;
135 struct v4l2_fract max_fps;
136 u32 hts_def;
137 u32 vts_def;
138 u32 exp_def;
139 u32 link_freq_idx;
140 u32 bus_fmt;
141 u32 bpp;
142 const struct regval *reg_list;
143 u32 vc[PAD_MAX];
144 };
145
146 struct max96712 {
147 struct i2c_client *client;
148 u16 i2c_addr[I2C_DEV_MAX];
149 struct clk *xvclk;
150 struct gpio_desc *power_gpio;
151 struct gpio_desc *reset_gpio;
152 struct gpio_desc *pwdn_gpio;
153 struct gpio_desc *pocen_gpio;
154 struct gpio_desc *lock_gpio;
155 struct regulator_bulk_data supplies[MAX96712_NUM_SUPPLIES];
156
157 struct pinctrl *pinctrl;
158 struct pinctrl_state *pins_default;
159 struct pinctrl_state *pins_sleep;
160
161 struct v4l2_subdev subdev;
162 struct media_pad pad;
163 struct v4l2_ctrl_handler ctrl_handler;
164 struct v4l2_ctrl *exposure;
165 struct v4l2_ctrl *anal_gain;
166 struct v4l2_ctrl *digi_gain;
167 struct v4l2_ctrl *hblank;
168 struct v4l2_ctrl *vblank;
169 struct v4l2_ctrl *pixel_rate;
170 struct v4l2_ctrl *link_freq;
171 struct v4l2_ctrl *test_pattern;
172 struct v4l2_fwnode_endpoint bus_cfg;
173
174 struct mutex mutex;
175 bool streaming;
176 bool power_on;
177 bool hot_plug;
178 u8 is_reset;
179 int hot_plug_irq;
180 enum max96712_rx_rate rx_rate;
181 u32 link_mask;
182 const struct max96712_mode *supported_modes;
183 const struct max96712_mode *cur_mode;
184 u32 cfg_modes_num;
185 u32 module_index;
186 u32 auto_init_deskew_mask;
187 u32 frame_sync_period;
188 const char *module_facing;
189 const char *module_name;
190 const char *len_name;
191 struct regmap *regmap;
192 };
193
194 static const struct regmap_config max96712_regmap_config = {
195 .reg_bits = 16,
196 .val_bits = 8,
197 .max_register = 0x1F17,
198 };
199
200 static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
201 .vendor = PHY_VENDOR_SAMSUNG,
202 .lp_vol_ref = 3,
203 .lp_hys_sw = {3, 0, 0, 0},
204 .lp_escclk_pol_sel = {1, 0, 0, 0},
205 .skew_data_cal_clk = {0, 0, 0, 0},
206 .clk_hs_term_sel = 2,
207 .data_hs_term_sel = {2, 2, 2, 2},
208 .reserved = {0},
209 };
210
211 /* max96717 */
212 static const struct regval max96712_mipi_4lane_1920x1440_30fps[] = {
213 // Link A/B/C/D all use GMSL2, and disabled
214 { I2C_DEV_DES, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled
215 // Disable MIPI CSI output
216 { I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled
217 // Increase CMU voltage
218 { I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range
219 // VGAHiGain
220 { I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain
221 { I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain
222 { I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain
223 { I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain
224 // SSC Configuration
225 { I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC
226 { I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC
227 { I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC
228 { I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC
229 // GMSL2 Link Video Pipe Selection
230 { I2C_DEV_DES, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pipe 1
231 { I2C_DEV_DES, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pipe 3
232 { I2C_DEV_DES, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes
233 // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
234 { I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
235 { I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
236 // For the following MSB 2 bits = VC, LSB 6 bits = DT
237 { I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
238 { I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit
239 { I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
240 { I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start
241 { I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
242 { I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End
243 // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
244 { I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
245 { I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
246 // For the following MSB 2 bits = VC, LSB 6 bits = DT
247 { I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
248 { I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit
249 { I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
250 { I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start
251 { I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
252 { I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End
253 // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
254 { I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
255 { I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
256 // For the following MSB 2 bits = VC, LSB 6 bits = DT
257 { I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
258 { I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit
259 { I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
260 { I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start
261 { I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
262 { I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End
263 // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
264 { I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
265 { I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
266 // For the following MSB 2 bits = VC, LSB 6 bits = DT
267 { I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
268 { I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit
269 { I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
270 { I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start
271 { I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
272 { I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End
273 // MIPI PHY Setting
274 { I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode
275 // Set Lane Mapping for 4-lane port A
276 { I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0
277 // Set 4 lane D-PHY, 2bit VC
278 { I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
279 { I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
280 // Turn on MIPI PHYs
281 { I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
282 // YUV422 8bit software override for all pipes since connected GMSL1 is under parallel mode
283 { I2C_DEV_DES, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
284 { I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
285 { I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit
286 { I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
287 { I2C_DEV_DES, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
288 { I2C_DEV_DES, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
289 // Enable all links and pipes
290 { I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0
291 { I2C_DEV_DES, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes
292 // Serializer Setting
293 { I2C_DEV_SER, 2, 0x0302, 0x10, 0x00, 0x00 }, // improve CMU voltage performance to improve link robustness
294 { I2C_DEV_SER, 2, 0x1417, 0x00, 0x00, 0x00 }, // Errata
295 { I2C_DEV_SER, 2, 0x1432, 0x7f, 0x00, 0x00 },
296 // End register setting
297 { I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 },
298 };
299
300 static const struct max96712_mode supported_modes_4lane[] = {
301 {
302 .width = 1920,
303 .height = 1440,
304 .max_fps = {
305 .numerator = 10000,
306 .denominator = 300000,
307 },
308 .reg_list = max96712_mipi_4lane_1920x1440_30fps,
309 .link_freq_idx = 20,
310 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
311 .bpp = 16,
312 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
313 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
314 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
315 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
316 },
317 };
318
319 /* link freq = index * MAX96712_LINK_FREQ_MHZ(50) */
320 static const s64 link_freq_items[] = {
321 MAX96712_LINK_FREQ_MHZ(0),
322 MAX96712_LINK_FREQ_MHZ(50),
323 MAX96712_LINK_FREQ_MHZ(100),
324 MAX96712_LINK_FREQ_MHZ(150),
325 MAX96712_LINK_FREQ_MHZ(200),
326 MAX96712_LINK_FREQ_MHZ(250),
327 MAX96712_LINK_FREQ_MHZ(300),
328 MAX96712_LINK_FREQ_MHZ(350),
329 MAX96712_LINK_FREQ_MHZ(400),
330 MAX96712_LINK_FREQ_MHZ(450),
331 MAX96712_LINK_FREQ_MHZ(500),
332 MAX96712_LINK_FREQ_MHZ(550),
333 MAX96712_LINK_FREQ_MHZ(600),
334 MAX96712_LINK_FREQ_MHZ(650),
335 MAX96712_LINK_FREQ_MHZ(700),
336 MAX96712_LINK_FREQ_MHZ(750),
337 MAX96712_LINK_FREQ_MHZ(800),
338 MAX96712_LINK_FREQ_MHZ(850),
339 MAX96712_LINK_FREQ_MHZ(900),
340 MAX96712_LINK_FREQ_MHZ(950),
341 MAX96712_LINK_FREQ_MHZ(1000),
342 MAX96712_LINK_FREQ_MHZ(1050),
343 MAX96712_LINK_FREQ_MHZ(1100),
344 MAX96712_LINK_FREQ_MHZ(1150),
345 MAX96712_LINK_FREQ_MHZ(1200),
346 MAX96712_LINK_FREQ_MHZ(1250),
347 };
348
max96712_write_reg(struct max96712 * max96712,u8 i2c_id,u16 reg,u16 reg_len,u16 val_len,u32 val)349 static int max96712_write_reg(struct max96712 *max96712, u8 i2c_id,
350 u16 reg, u16 reg_len, u16 val_len, u32 val)
351 {
352 struct i2c_client *client = max96712->client;
353 u16 client_addr = max96712->i2c_addr[i2c_id];
354 u32 buf_i, val_i;
355 u8 buf[6];
356 u8 *val_p;
357 __be32 val_be;
358
359 dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n",
360 client_addr, reg, reg_len, val);
361
362 if (val_len > 4)
363 return -EINVAL;
364
365 if (reg_len == 2) {
366 buf[0] = reg >> 8;
367 buf[1] = reg & 0xff;
368
369 buf_i = 2;
370 } else {
371 buf[0] = reg & 0xff;
372
373 buf_i = 1;
374 }
375
376 val_be = cpu_to_be32(val);
377 val_p = (u8 *)&val_be;
378 val_i = 4 - val_len;
379
380 while (val_i < 4)
381 buf[buf_i++] = val_p[val_i++];
382
383 client->addr = client_addr;
384
385 if (i2c_master_send(client, buf, (val_len + reg_len)) != (val_len + reg_len)) {
386 dev_err(&client->dev,
387 "%s: writing register 0x%04x from 0x%02x failed\n",
388 __func__, reg, client->addr);
389 return -EIO;
390 }
391
392 return 0;
393 }
394
max96712_read_reg(struct max96712 * max96712,u8 i2c_id,u16 reg,u16 reg_len,u16 val_len,u8 * val)395 static int max96712_read_reg(struct max96712 *max96712, u8 i2c_id,
396 u16 reg, u16 reg_len, u16 val_len, u8 *val)
397 {
398 struct i2c_client *client = max96712->client;
399 u16 client_addr = max96712->i2c_addr[i2c_id];
400 struct i2c_msg msgs[2];
401 u8 *data_be_p;
402 __be32 data_be = 0;
403 __be16 reg_addr_be = cpu_to_be16(reg);
404 u8 *reg_be_p;
405 int ret;
406
407 if (val_len > 4 || !val_len)
408 return -EINVAL;
409
410 client->addr = client_addr;
411 data_be_p = (u8 *)&data_be;
412 reg_be_p = (u8 *)®_addr_be;
413
414 /* Write register address */
415 msgs[0].addr = client->addr;
416 msgs[0].flags = 0;
417 msgs[0].len = reg_len;
418 msgs[0].buf = ®_be_p[2 - reg_len];
419
420 /* Read data from register */
421 msgs[1].addr = client->addr;
422 msgs[1].flags = I2C_M_RD;
423 msgs[1].len = val_len;
424 msgs[1].buf = &data_be_p[4 - val_len];
425
426 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
427 if (ret != ARRAY_SIZE(msgs)) {
428 dev_err(&client->dev,
429 "%s: reading register 0x%x from 0x%x failed\n",
430 __func__, reg, client->addr);
431 return -EIO;
432 }
433
434 *val = be32_to_cpu(data_be);
435
436 #if 0
437 dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n",
438 client_addr, reg, reg_len, *val);
439 #endif
440
441 return 0;
442 }
443
max96712_update_reg_bits(struct max96712 * max96712,u8 i2c_id,u16 reg,u16 reg_len,u8 mask,u8 val)444 static int max96712_update_reg_bits(struct max96712 *max96712, u8 i2c_id,
445 u16 reg, u16 reg_len, u8 mask, u8 val)
446 {
447 u8 value;
448 u32 val_len = DEV_REG_VALUE_08BITS;
449 int ret;
450
451 ret = max96712_read_reg(max96712, i2c_id, reg, reg_len, val_len, &value);
452 if (ret)
453 return ret;
454
455 value &= ~mask;
456 value |= (val & mask);
457 ret = max96712_write_reg(max96712, i2c_id, reg, reg_len, val_len, value);
458 if (ret)
459 return ret;
460
461 return 0;
462 }
463
max96712_write_array(struct max96712 * max96712,const struct regval * regs)464 static int max96712_write_array(struct max96712 *max96712,
465 const struct regval *regs)
466 {
467 u32 i;
468 int ret = 0;
469
470 for (i = 0; ret == 0 && regs[i].reg != REG_NULL; i++) {
471 if (regs[i].mask != 0)
472 ret = max96712_update_reg_bits(max96712, regs[i].i2c_id,
473 regs[i].reg, regs[i].reg_len,
474 regs[i].mask, regs[i].val);
475 else
476 ret = max96712_write_reg(max96712, regs[i].i2c_id,
477 regs[i].reg, regs[i].reg_len,
478 DEV_REG_VALUE_08BITS, regs[i].val);
479
480 if (regs[i].delay != 0)
481 msleep(regs[i].delay);
482 }
483
484 return ret;
485 }
486
max96712_check_local_chipid(struct max96712 * max96712)487 static int max96712_check_local_chipid(struct max96712 *max96712)
488 {
489 struct device *dev = &max96712->client->dev;
490 int ret;
491 u8 id = 0;
492
493 ret = max96712_read_reg(max96712, I2C_DEV_DES,
494 MAX96712_REG_CHIP_ID, DEV_REG_LENGTH_16BITS,
495 DEV_REG_VALUE_08BITS, &id);
496 if ((ret != 0) || (id != MAX96712_CHIP_ID)) {
497 dev_err(dev, "Unexpected MAX96712 chip id(%02x), ret(%d)\n", id, ret);
498 return -ENODEV;
499 }
500
501 dev_info(dev, "Detected MAX96712 chipid: %02x\n", id);
502
503 return 0;
504 }
505
max96712_check_remote_chipid(struct max96712 * max96712)506 static int __maybe_unused max96712_check_remote_chipid(struct max96712 *max96712)
507 {
508 struct device *dev = &max96712->client->dev;
509 int ret = 0;
510 u8 id;
511
512 dev_info(dev, "Check remote chipid\n");
513
514 id = 0;
515 #if 0
516 // max96717
517 ret = max96712_read_reg(max96712, I2C_DEV_SER,
518 MAX96717_REG_CHIP_ID, DEV_REG_LENGTH_16BITS,
519 DEV_REG_VALUE_08BITS, &id);
520 if ((ret != 0) || (id != MAX96717_CHIP_ID)) {
521 dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret);
522 return -ENODEV;
523 }
524 dev_info(dev, "Detected MAX96717 chipid: 0x%02x\n", id);
525 #endif
526
527 #if 0
528 // max96715
529 ret = max96712_read_reg(max96712, I2C_DEV_SER,
530 MAX96715_REG_CHIP_ID, DEV_REG_LENGTH_08BITS,
531 DEV_REG_VALUE_08BITS, &id);
532 if ((ret != 0) || (id != MAX96715_CHIP_ID)) {
533 dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret);
534 return -ENODEV;
535 }
536 dev_info(dev, "Detected MAX96715 chipid: 0x%02x\n", id);
537 #endif
538
539 return ret;
540 }
541
max96712_get_link_lock_state(struct max96712 * max96712,u8 link_mask)542 static u8 max96712_get_link_lock_state(struct max96712 *max96712, u8 link_mask)
543 {
544 struct device *dev = &max96712->client->dev;
545 u8 lock = 0, lock_state = 0;
546 u8 link_type = 0;
547
548 link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK;
549
550 if (link_mask & MAXIM_GMSL_LOCK_LINK_A) {
551 if (link_type & MAXIM_GMSL_TYPE_LINK_A) {
552 // GMSL2 LinkA
553 max96712_read_reg(max96712, I2C_DEV_DES,
554 0x001a, DEV_REG_LENGTH_16BITS,
555 DEV_REG_VALUE_08BITS, &lock);
556 if (lock & BIT(3)) {
557 lock_state |= MAXIM_GMSL_LOCK_LINK_A;
558 dev_info(dev, "GMSL2 LinkA locked\n");
559 }
560 } else {
561 // GMSL1 LinkA
562 max96712_read_reg(max96712, I2C_DEV_DES,
563 0x0bcb, DEV_REG_LENGTH_16BITS,
564 DEV_REG_VALUE_08BITS, &lock);
565 if (lock & BIT(0)) {
566 lock_state |= MAXIM_GMSL_LOCK_LINK_A;
567 dev_info(dev, "GMSL1 LinkA locked\n");
568 }
569 }
570 }
571
572 if (link_mask & MAXIM_GMSL_LOCK_LINK_B) {
573 if (link_type & MAXIM_GMSL_TYPE_LINK_B) {
574 // GMSL2 LinkB
575 max96712_read_reg(max96712, I2C_DEV_DES,
576 0x000a, DEV_REG_LENGTH_16BITS,
577 DEV_REG_VALUE_08BITS, &lock);
578 if (lock & BIT(3)) {
579 lock_state |= MAXIM_GMSL_LOCK_LINK_B;
580 dev_info(dev, "GMSL2 LinkB locked\n");
581 }
582 } else {
583 // GMSL1 LinkB
584 max96712_read_reg(max96712, I2C_DEV_DES,
585 0x0ccb, DEV_REG_LENGTH_16BITS,
586 DEV_REG_VALUE_08BITS, &lock);
587 if (lock & BIT(0)) {
588 lock_state |= MAXIM_GMSL_LOCK_LINK_B;
589 dev_info(dev, "GMSL1 LinkB locked\n");
590 }
591 }
592 }
593
594 if (link_mask & MAXIM_GMSL_LOCK_LINK_C) {
595 if (link_type & MAXIM_GMSL_TYPE_LINK_C) {
596 // GMSL2 LinkC
597 max96712_read_reg(max96712, I2C_DEV_DES,
598 0x000b, DEV_REG_LENGTH_16BITS,
599 DEV_REG_VALUE_08BITS, &lock);
600 if (lock & BIT(3)) {
601 lock_state |= MAXIM_GMSL_LOCK_LINK_C;
602 dev_info(dev, "GMSL2 LinkC locked\n");
603 }
604 } else {
605 // GMSL1 LinkC
606 max96712_read_reg(max96712, I2C_DEV_DES,
607 0x0dcb, DEV_REG_LENGTH_16BITS,
608 DEV_REG_VALUE_08BITS, &lock);
609 if (lock & BIT(0)) {
610 lock_state |= MAXIM_GMSL_LOCK_LINK_C;
611 dev_info(dev, "GMSL1 LinkC locked\n");
612 }
613 }
614 }
615
616 if (link_mask & MAXIM_GMSL_LOCK_LINK_D) {
617 if (link_type & MAXIM_GMSL_TYPE_LINK_D) {
618 // GMSL2 LinkD
619 max96712_read_reg(max96712, I2C_DEV_DES,
620 0x000c, DEV_REG_LENGTH_16BITS,
621 DEV_REG_VALUE_08BITS, &lock);
622 if (lock & BIT(3)) {
623 lock_state |= MAXIM_GMSL_LOCK_LINK_D;
624 dev_info(dev, "GMSL2 LinkD locked\n");
625 }
626 } else {
627 // GMSL1 LinkD
628 max96712_read_reg(max96712, I2C_DEV_DES,
629 0x0ecb, DEV_REG_LENGTH_16BITS,
630 DEV_REG_VALUE_08BITS, &lock);
631 if (lock & BIT(0)) {
632 lock_state |= MAXIM_GMSL_LOCK_LINK_D;
633 dev_info(dev, "GMSL1 LinkD locked\n");
634 }
635 }
636 }
637
638 return lock_state;
639 }
640
max96712_check_link_lock_state(struct max96712 * max96712)641 static int max96712_check_link_lock_state(struct max96712 *max96712)
642 {
643 struct device *dev = &max96712->client->dev;
644 u8 lock_state = 0, link_mask = 0, link_type = 0;
645 int ret, i, time_ms;
646
647 ret = max96712_check_local_chipid(max96712);
648 if (ret)
649 return ret;
650
651 /* IF VDD = 1.2V: Enable REG_ENABLE and REG_MNL
652 * CTRL0: Enable REG_ENABLE
653 * CTRL2: Enable REG_MNL
654 */
655 max96712_update_reg_bits(max96712, I2C_DEV_DES,
656 0x0017, DEV_REG_LENGTH_16BITS, BIT(2), BIT(2));
657 max96712_update_reg_bits(max96712, I2C_DEV_DES,
658 0x0019, DEV_REG_LENGTH_16BITS, BIT(4), BIT(4));
659
660 // CSI output disabled
661 max96712_write_reg(max96712, I2C_DEV_DES,
662 0x040B, DEV_REG_LENGTH_16BITS,
663 DEV_REG_VALUE_08BITS, 0x00);
664
665 // All links select mode by link_type and disable at beginning.
666 link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK;
667 max96712_write_reg(max96712, I2C_DEV_DES,
668 0x0006, DEV_REG_LENGTH_16BITS,
669 DEV_REG_VALUE_08BITS, link_type);
670
671 // Link Rate
672 if (max96712->rx_rate == MAX96712_RX_RATE_3GBPS) {
673 // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 3Gbps
674 max96712_write_reg(max96712, I2C_DEV_DES,
675 0x0010, DEV_REG_LENGTH_16BITS,
676 DEV_REG_VALUE_08BITS, 0x11);
677 max96712_write_reg(max96712, I2C_DEV_DES,
678 0x0011, DEV_REG_LENGTH_16BITS,
679 DEV_REG_VALUE_08BITS, 0x11);
680 } else {
681 // Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 6Gbps
682 max96712_write_reg(max96712, I2C_DEV_DES,
683 0x0010, DEV_REG_LENGTH_16BITS,
684 DEV_REG_VALUE_08BITS, 0x22);
685 max96712_write_reg(max96712, I2C_DEV_DES,
686 0x0011, DEV_REG_LENGTH_16BITS,
687 DEV_REG_VALUE_08BITS, 0x22);
688 }
689
690 // GMSL1: Enable HIM on deserializer on Link A/B/C/D
691 if ((link_type & MAXIM_GMSL_TYPE_LINK_A) == 0) {
692 max96712_write_reg(max96712, I2C_DEV_DES,
693 0x0B06, DEV_REG_LENGTH_16BITS,
694 DEV_REG_VALUE_08BITS, 0xEF);
695 }
696 if ((link_type & MAXIM_GMSL_TYPE_LINK_B) == 0) {
697 max96712_write_reg(max96712, I2C_DEV_DES,
698 0x0C06, DEV_REG_LENGTH_16BITS,
699 DEV_REG_VALUE_08BITS, 0xEF);
700 }
701 if ((link_type & MAXIM_GMSL_TYPE_LINK_C) == 0) {
702 max96712_write_reg(max96712, I2C_DEV_DES,
703 0x0D06, DEV_REG_LENGTH_16BITS,
704 DEV_REG_VALUE_08BITS, 0xEF);
705 }
706 if ((link_type & MAXIM_GMSL_TYPE_LINK_D) == 0) {
707 max96712_write_reg(max96712, I2C_DEV_DES,
708 0x0E06, DEV_REG_LENGTH_16BITS,
709 DEV_REG_VALUE_08BITS, 0xEF);
710 }
711
712 // Link A ~ Link D One-Shot Reset depend on link_mask
713 link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK;
714 max96712_write_reg(max96712, I2C_DEV_DES,
715 0x0018, DEV_REG_LENGTH_16BITS,
716 DEV_REG_VALUE_08BITS, link_mask);
717
718 // Link A ~ Link D enable depend on link_type and link_mask
719 max96712_write_reg(max96712, I2C_DEV_DES,
720 0x0006, DEV_REG_LENGTH_16BITS,
721 DEV_REG_VALUE_08BITS, link_type | link_mask);
722
723 time_ms = 50;
724 msleep(time_ms);
725
726 for (i = 0; i < 20; i++) {
727 if ((lock_state & MAXIM_GMSL_LOCK_LINK_A) == 0)
728 if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_A)) {
729 lock_state |= MAXIM_GMSL_LOCK_LINK_A;
730 dev_info(dev, "LinkA locked time: %d ms\n", time_ms);
731 }
732
733 if ((lock_state & MAXIM_GMSL_LOCK_LINK_B) == 0)
734 if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_B)) {
735 lock_state |= MAXIM_GMSL_LOCK_LINK_B;
736 dev_info(dev, "LinkB locked time: %d ms\n", time_ms);
737 }
738
739 if ((lock_state & MAXIM_GMSL_LOCK_LINK_C) == 0)
740 if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_C)) {
741 lock_state |= MAXIM_GMSL_LOCK_LINK_C;
742 dev_info(dev, "LinkC locked time: %d ms\n", time_ms);
743 }
744
745 if ((lock_state & MAXIM_GMSL_LOCK_LINK_D) == 0)
746 if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_D)) {
747 lock_state |= MAXIM_GMSL_LOCK_LINK_D;
748 dev_info(dev, "LinkD locked time: %d ms\n", time_ms);
749 }
750
751 if ((lock_state & link_mask) == link_mask) {
752 dev_info(dev, "All Links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms);
753 #if 0
754 max96712_check_remote_chipid(max96712);
755 #endif
756 return 0;
757 }
758
759 msleep(10);
760 time_ms += 10;
761 }
762
763 if ((lock_state & link_mask) != 0) {
764 dev_info(dev, "Partial links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms);
765 return 0;
766 } else {
767 dev_err(dev, "Failed to detect camera link, time_ms = %d!\n", time_ms);
768 return -ENODEV;
769 }
770 }
771
max96712_hot_plug_detect_irq_handler(int irq,void * dev_id)772 static irqreturn_t max96712_hot_plug_detect_irq_handler(int irq, void *dev_id)
773 {
774 struct max96712 *max96712 = dev_id;
775 struct device *dev = &max96712->client->dev;
776 u8 lock_state = 0, link_mask = 0;
777
778 link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK;
779 if (max96712->streaming) {
780 lock_state = max96712_get_link_lock_state(max96712, link_mask);
781 if (lock_state == link_mask) {
782 dev_info(dev, "serializer plug in, lock_state = 0x%02x\n", lock_state);
783 } else {
784 dev_info(dev, "serializer plug out, lock_state = 0x%02x\n", lock_state);
785 }
786 }
787
788 return IRQ_HANDLED;
789 }
790
max96712_dphy_dpll_predef_set(struct max96712 * max96712,u32 link_freq_mhz)791 static int max96712_dphy_dpll_predef_set(struct max96712 *max96712, u32 link_freq_mhz)
792 {
793 struct device *dev = &max96712->client->dev;
794 int ret = 0;
795 u8 dpll_val = 0, dpll_lock = 0;
796 u8 mipi_tx_phy_enable = 0;
797
798 ret = max96712_read_reg(max96712, I2C_DEV_DES,
799 0x08A2, DEV_REG_LENGTH_16BITS,
800 DEV_REG_VALUE_08BITS, &mipi_tx_phy_enable);
801 if (ret)
802 return ret;
803 mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4;
804
805 dev_info(dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n",
806 mipi_tx_phy_enable, link_freq_mhz);
807
808 // dphy max data rate is 2500MHz
809 if (link_freq_mhz > (2500 >> 1))
810 link_freq_mhz = (2500 >> 1);
811
812 dpll_val = DIV_ROUND_UP(link_freq_mhz * 2, 100) & 0x1F;
813 // Disable software override for frequency fine tuning
814 dpll_val |= BIT(5);
815
816 // MIPI PHY0
817 if (mipi_tx_phy_enable & BIT(0)) {
818 // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
819 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
820 0x1C00, DEV_REG_LENGTH_16BITS,
821 DEV_REG_VALUE_08BITS, 0xf4);
822 // Set data rate and enable software override
823 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
824 0x0415, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
825 // Release reset to DPLL (config_soft_rst_n = 1)
826 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
827 0x1C00, DEV_REG_LENGTH_16BITS,
828 DEV_REG_VALUE_08BITS, 0xf5);
829 }
830
831 // MIPI PHY1
832 if (mipi_tx_phy_enable & BIT(1)) {
833 // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
834 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
835 0x1D00, DEV_REG_LENGTH_16BITS,
836 DEV_REG_VALUE_08BITS, 0xf4);
837 // Set data rate and enable software override
838 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
839 0x0418, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
840 // Release reset to DPLL (config_soft_rst_n = 1)
841 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
842 0x1D00, DEV_REG_LENGTH_16BITS,
843 DEV_REG_VALUE_08BITS, 0xf5);
844 }
845
846 // MIPI PHY2
847 if (mipi_tx_phy_enable & BIT(2)) {
848 // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
849 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
850 0x1E00, DEV_REG_LENGTH_16BITS,
851 DEV_REG_VALUE_08BITS, 0xf4);
852 // Set data rate and enable software override
853 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
854 0x041B, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
855 // Release reset to DPLL (config_soft_rst_n = 1)
856 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
857 0x1E00, DEV_REG_LENGTH_16BITS,
858 DEV_REG_VALUE_08BITS, 0xf5);
859 }
860
861 // MIPI PHY3
862 if (mipi_tx_phy_enable & BIT(3)) {
863 // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
864 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
865 0x1F00, DEV_REG_LENGTH_16BITS,
866 DEV_REG_VALUE_08BITS, 0xf4);
867 // Set data rate and enable software override
868 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
869 0x041E, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
870 // Release reset to DPLL (config_soft_rst_n = 1)
871 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
872 0x1F00, DEV_REG_LENGTH_16BITS,
873 DEV_REG_VALUE_08BITS, 0xf5);
874 }
875
876 if (ret) {
877 dev_err(dev, "DPLL predef set error!\n");
878 return ret;
879 }
880
881 ret = read_poll_timeout(max96712_read_reg, ret,
882 !(ret < 0) && (dpll_lock & 0xF0),
883 1000, 10000, false,
884 max96712, I2C_DEV_DES,
885 0x0400, DEV_REG_LENGTH_16BITS,
886 DEV_REG_VALUE_08BITS, &dpll_lock);
887 if (ret < 0) {
888 dev_err(dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock);
889 return ret;
890 } else {
891 dev_err(dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock);
892 return 0;
893 }
894 }
895
max96712_auto_init_deskew(struct max96712 * max96712,u32 deskew_mask)896 static int max96712_auto_init_deskew(struct max96712 *max96712, u32 deskew_mask)
897 {
898 struct device *dev = &max96712->client->dev;
899 int ret = 0;
900
901 dev_info(dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask);
902
903 // D-PHY Deskew Initial Calibration Control
904 if (deskew_mask & BIT(0)) // MIPI PHY0
905 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
906 0x0903, DEV_REG_LENGTH_16BITS,
907 DEV_REG_VALUE_08BITS, 0x80);
908
909 if (deskew_mask & BIT(1)) // MIPI PHY1
910 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
911 0x0943, DEV_REG_LENGTH_16BITS,
912 DEV_REG_VALUE_08BITS, 0x80);
913
914 if (deskew_mask & BIT(2)) // MIPI PHY2
915 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
916 0x0983, DEV_REG_LENGTH_16BITS,
917 DEV_REG_VALUE_08BITS, 0x80);
918
919 if (deskew_mask & BIT(3)) // MIPI PHY3
920 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
921 0x09C3, DEV_REG_LENGTH_16BITS,
922 DEV_REG_VALUE_08BITS, 0x80);
923
924 return ret;
925 }
926
max96712_frame_sync_period(struct max96712 * max96712,u32 period)927 static int max96712_frame_sync_period(struct max96712 *max96712, u32 period)
928 {
929 struct device *dev = &max96712->client->dev;
930 u32 pclk, fsync_peroid;
931 u8 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l;
932 int ret = 0;
933
934 if (period == 0)
935 return 0;
936
937 dev_info(dev, "Frame sync period = %d\n", period);
938
939 #if 1 // TODO: Sensor slave mode
940 // SC320AT slave mode enable
941 ret |= max96712_write_reg(max96712, I2C_DEV_CAM,
942 0x3222, DEV_REG_LENGTH_16BITS,
943 DEV_REG_VALUE_08BITS, 0x01);
944 // Increase the allowable error range of the trigger signal
945 ret |= max96712_write_reg(max96712, I2C_DEV_CAM,
946 0x32e2, DEV_REG_LENGTH_16BITS,
947 DEV_REG_VALUE_08BITS, 0x19);
948 #endif
949
950 // Master link Video 0 for frame sync generation
951 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
952 0x04A2, DEV_REG_LENGTH_16BITS,
953 DEV_REG_VALUE_08BITS, 0x00);
954 // Disable Vsync-Fsync overlap window
955 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
956 0x04AA, DEV_REG_LENGTH_16BITS,
957 DEV_REG_VALUE_08BITS, 0x00);
958 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
959 0x04AB, DEV_REG_LENGTH_16BITS,
960 DEV_REG_VALUE_08BITS, 0x00);
961
962 // Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
963 pclk = 25 * 1000 * 1000;
964 fsync_peroid = DIV_ROUND_UP(pclk, period) - 1;
965 fsync_peroid_l = (fsync_peroid >> 0) & 0xFF;
966 fsync_peroid_m = (fsync_peroid >> 8) & 0xFF;
967 fsync_peroid_h = (fsync_peroid >> 16) & 0xFF;
968 dev_info(dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n",
969 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l);
970 // FSYNC_PERIOD_H
971 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
972 0x04A7, DEV_REG_LENGTH_16BITS,
973 DEV_REG_VALUE_08BITS, fsync_peroid_h);
974 // FSYNC_PERIOD_M
975 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
976 0x04A6, DEV_REG_LENGTH_16BITS,
977 DEV_REG_VALUE_08BITS, fsync_peroid_m);
978 // FSYNC_PERIOD_L
979 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
980 0x04A5, DEV_REG_LENGTH_16BITS,
981 DEV_REG_VALUE_08BITS, fsync_peroid_l);
982
983 // FSYNC is GMSL2 type, use osc for fsync, include all links/pipes in fsync gen
984 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
985 0x04AF, DEV_REG_LENGTH_16BITS,
986 DEV_REG_VALUE_08BITS, 0xcf);
987
988 #if 1 // TODO: Desrializer MFP
989 // FSYNC_TX_ID: set 4 to match MFP4 on serializer side
990 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
991 0x04B1, DEV_REG_LENGTH_16BITS,
992 DEV_REG_VALUE_08BITS, 0x20);
993 #endif
994
995 #if 1 // TODO: Serializer MFP
996 // Enable GPIO_RX_EN on serializer MFP4
997 ret |= max96712_write_reg(max96712, I2C_DEV_SER,
998 0x02CA, DEV_REG_LENGTH_16BITS,
999 DEV_REG_VALUE_08BITS, 0x84);
1000 #endif
1001
1002 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
1003 ret |= max96712_write_reg(max96712, I2C_DEV_DES,
1004 0x04A0, DEV_REG_LENGTH_16BITS,
1005 DEV_REG_VALUE_08BITS, 0x04);
1006
1007 return ret;
1008 }
1009
max96712_mipi_enable(struct max96712 * max96712,bool enable)1010 static int max96712_mipi_enable(struct max96712 *max96712, bool enable)
1011 {
1012 int ret = 0;
1013
1014 if (enable) {
1015 #if MAXIM_FORCE_ALL_CLOCK_EN
1016 // Force all MIPI clocks running
1017 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1018 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), BIT(7));
1019 #endif
1020 // CSI output enabled
1021 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1022 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), BIT(1));
1023 } else {
1024 #if MAXIM_FORCE_ALL_CLOCK_EN
1025 // Normal mode
1026 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1027 0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), 0x00);
1028 #endif
1029 // CSI output disabled
1030 ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1031 0x040B, DEV_REG_LENGTH_16BITS, BIT(1), 0x00);
1032 }
1033
1034 return ret;
1035 }
1036
max96712_get_reso_dist(const struct max96712_mode * mode,struct v4l2_mbus_framefmt * framefmt)1037 static int max96712_get_reso_dist(const struct max96712_mode *mode,
1038 struct v4l2_mbus_framefmt *framefmt)
1039 {
1040 return abs(mode->width - framefmt->width) +
1041 abs(mode->height - framefmt->height);
1042 }
1043
1044 static const struct max96712_mode *
max96712_find_best_fit(struct max96712 * max96712,struct v4l2_subdev_format * fmt)1045 max96712_find_best_fit(struct max96712 *max96712, struct v4l2_subdev_format *fmt)
1046 {
1047 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1048 int dist;
1049 int cur_best_fit = 0;
1050 int cur_best_fit_dist = -1;
1051 unsigned int i;
1052
1053 for (i = 0; i < max96712->cfg_modes_num; i++) {
1054 dist = max96712_get_reso_dist(&max96712->supported_modes[i], framefmt);
1055 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist)
1056 && (max96712->supported_modes[i].bus_fmt == framefmt->code)) {
1057 cur_best_fit_dist = dist;
1058 cur_best_fit = i;
1059 }
1060 }
1061
1062 return &max96712->supported_modes[cur_best_fit];
1063 }
1064
max96712_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1065 static int max96712_set_fmt(struct v4l2_subdev *sd,
1066 struct v4l2_subdev_pad_config *cfg,
1067 struct v4l2_subdev_format *fmt)
1068 {
1069 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1070 const struct max96712_mode *mode;
1071 u64 pixel_rate = 0;
1072 u8 data_lanes;
1073
1074 mutex_lock(&max96712->mutex);
1075
1076 mode = max96712_find_best_fit(max96712, fmt);
1077
1078 fmt->format.code = mode->bus_fmt;
1079 fmt->format.width = mode->width;
1080 fmt->format.height = mode->height;
1081 fmt->format.field = V4L2_FIELD_NONE;
1082 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1083 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1084 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1085 #else
1086 mutex_unlock(&max96712->mutex);
1087 return -ENOTTY;
1088 #endif
1089 } else {
1090 if (max96712->streaming) {
1091 mutex_unlock(&max96712->mutex);
1092 return -EBUSY;
1093 }
1094
1095 max96712->cur_mode = mode;
1096
1097 __v4l2_ctrl_s_ctrl(max96712->link_freq, mode->link_freq_idx);
1098 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1099 data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1100 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * data_lanes;
1101 __v4l2_ctrl_s_ctrl_int64(max96712->pixel_rate, pixel_rate);
1102
1103 dev_info(&max96712->client->dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n",
1104 mode->link_freq_idx, link_freq_items[mode->link_freq_idx]);
1105 dev_info(&max96712->client->dev, "pixel_rate = %lld, bpp = %d\n",
1106 pixel_rate, mode->bpp);
1107 }
1108
1109 mutex_unlock(&max96712->mutex);
1110
1111 return 0;
1112 }
1113
max96712_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1114 static int max96712_get_fmt(struct v4l2_subdev *sd,
1115 struct v4l2_subdev_pad_config *cfg,
1116 struct v4l2_subdev_format *fmt)
1117 {
1118 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1119 const struct max96712_mode *mode = max96712->cur_mode;
1120
1121 mutex_lock(&max96712->mutex);
1122 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1123 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1124 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1125 #else
1126 mutex_unlock(&max96712->mutex);
1127 return -ENOTTY;
1128 #endif
1129 } else {
1130 fmt->format.width = mode->width;
1131 fmt->format.height = mode->height;
1132 fmt->format.code = mode->bus_fmt;
1133 fmt->format.field = V4L2_FIELD_NONE;
1134 if (fmt->pad < PAD_MAX && fmt->pad >= PAD0)
1135 fmt->reserved[0] = mode->vc[fmt->pad];
1136 else
1137 fmt->reserved[0] = mode->vc[PAD0];
1138 }
1139 mutex_unlock(&max96712->mutex);
1140
1141 return 0;
1142 }
1143
max96712_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1144 static int max96712_enum_mbus_code(struct v4l2_subdev *sd,
1145 struct v4l2_subdev_pad_config *cfg,
1146 struct v4l2_subdev_mbus_code_enum *code)
1147 {
1148 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1149 const struct max96712_mode *mode = max96712->cur_mode;
1150
1151 if (code->index != 0)
1152 return -EINVAL;
1153 code->code = mode->bus_fmt;
1154
1155 return 0;
1156 }
1157
max96712_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1158 static int max96712_enum_frame_sizes(struct v4l2_subdev *sd,
1159 struct v4l2_subdev_pad_config *cfg,
1160 struct v4l2_subdev_frame_size_enum *fse)
1161 {
1162 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1163
1164 if (fse->index >= max96712->cfg_modes_num)
1165 return -EINVAL;
1166
1167 if (fse->code != max96712->supported_modes[fse->index].bus_fmt)
1168 return -EINVAL;
1169
1170 fse->min_width = max96712->supported_modes[fse->index].width;
1171 fse->max_width = max96712->supported_modes[fse->index].width;
1172 fse->max_height = max96712->supported_modes[fse->index].height;
1173 fse->min_height = max96712->supported_modes[fse->index].height;
1174
1175 return 0;
1176 }
1177
max96712_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1178 static int max96712_g_frame_interval(struct v4l2_subdev *sd,
1179 struct v4l2_subdev_frame_interval *fi)
1180 {
1181 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1182 const struct max96712_mode *mode = max96712->cur_mode;
1183
1184 mutex_lock(&max96712->mutex);
1185 fi->interval = mode->max_fps;
1186 mutex_unlock(&max96712->mutex);
1187
1188 return 0;
1189 }
1190
max96712_get_module_inf(struct max96712 * max96712,struct rkmodule_inf * inf)1191 static void max96712_get_module_inf(struct max96712 *max96712,
1192 struct rkmodule_inf *inf)
1193 {
1194 memset(inf, 0, sizeof(*inf));
1195 strscpy(inf->base.sensor, MAX96712_NAME, sizeof(inf->base.sensor));
1196 strscpy(inf->base.module, max96712->module_name,
1197 sizeof(inf->base.module));
1198 strscpy(inf->base.lens, max96712->len_name, sizeof(inf->base.lens));
1199 }
1200
1201 static void
max96712_get_vicap_rst_inf(struct max96712 * max96712,struct rkmodule_vicap_reset_info * rst_info)1202 max96712_get_vicap_rst_inf(struct max96712 *max96712,
1203 struct rkmodule_vicap_reset_info *rst_info)
1204 {
1205 struct i2c_client *client = max96712->client;
1206
1207 rst_info->is_reset = max96712->hot_plug;
1208 max96712->hot_plug = false;
1209 rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
1210 dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__,
1211 rst_info->is_reset);
1212 }
1213
1214 static void
max96712_set_vicap_rst_inf(struct max96712 * max96712,struct rkmodule_vicap_reset_info rst_info)1215 max96712_set_vicap_rst_inf(struct max96712 *max96712,
1216 struct rkmodule_vicap_reset_info rst_info)
1217 {
1218 max96712->is_reset = rst_info.is_reset;
1219 }
1220
max96712_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1221 static long max96712_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1222 {
1223 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1224 struct rkmodule_csi_dphy_param *dphy_param;
1225 long ret = 0;
1226 u32 stream = 0;
1227
1228 switch (cmd) {
1229 case RKMODULE_GET_MODULE_INFO:
1230 max96712_get_module_inf(max96712, (struct rkmodule_inf *)arg);
1231 break;
1232 case RKMODULE_SET_QUICK_STREAM:
1233 stream = *((u32 *)arg);
1234
1235 if (stream)
1236 ret = max96712_mipi_enable(max96712, true);
1237 else
1238 ret = max96712_mipi_enable(max96712, false);
1239 break;
1240 case RKMODULE_GET_VICAP_RST_INFO:
1241 max96712_get_vicap_rst_inf(
1242 max96712, (struct rkmodule_vicap_reset_info *)arg);
1243 break;
1244 case RKMODULE_SET_VICAP_RST_INFO:
1245 max96712_set_vicap_rst_inf(
1246 max96712, *(struct rkmodule_vicap_reset_info *)arg);
1247 break;
1248 case RKMODULE_GET_START_STREAM_SEQ:
1249 break;
1250 case RKMODULE_SET_CSI_DPHY_PARAM:
1251 dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1252 if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1253 rk3588_dcphy_param = *dphy_param;
1254 dev_dbg(&max96712->client->dev, "sensor set dphy param\n");
1255 break;
1256 case RKMODULE_GET_CSI_DPHY_PARAM:
1257 dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1258 if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1259 *dphy_param = rk3588_dcphy_param;
1260 dev_dbg(&max96712->client->dev, "sensor get dphy param\n");
1261 break;
1262 default:
1263 ret = -ENOIOCTLCMD;
1264 break;
1265 }
1266
1267 return ret;
1268 }
1269
1270 #ifdef CONFIG_COMPAT
max96712_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1271 static long max96712_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd,
1272 unsigned long arg)
1273 {
1274 void __user *up = compat_ptr(arg);
1275 struct rkmodule_inf *inf;
1276 struct rkmodule_awb_cfg *cfg;
1277 struct rkmodule_vicap_reset_info *vicap_rst_inf;
1278 struct rkmodule_csi_dphy_param *dphy_param;
1279 long ret = 0;
1280 int *seq;
1281 u32 stream = 0;
1282
1283 switch (cmd) {
1284 case RKMODULE_GET_MODULE_INFO:
1285 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1286 if (!inf) {
1287 ret = -ENOMEM;
1288 return ret;
1289 }
1290
1291 ret = max96712_ioctl(sd, cmd, inf);
1292 if (!ret) {
1293 ret = copy_to_user(up, inf, sizeof(*inf));
1294 if (ret)
1295 ret = -EFAULT;
1296 }
1297 kfree(inf);
1298 break;
1299 case RKMODULE_AWB_CFG:
1300 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1301 if (!cfg) {
1302 ret = -ENOMEM;
1303 return ret;
1304 }
1305
1306 ret = copy_from_user(cfg, up, sizeof(*cfg));
1307 if (!ret)
1308 ret = max96712_ioctl(sd, cmd, cfg);
1309 else
1310 ret = -EFAULT;
1311 kfree(cfg);
1312 break;
1313 case RKMODULE_GET_VICAP_RST_INFO:
1314 vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
1315 if (!vicap_rst_inf) {
1316 ret = -ENOMEM;
1317 return ret;
1318 }
1319
1320 ret = max96712_ioctl(sd, cmd, vicap_rst_inf);
1321 if (!ret) {
1322 ret = copy_to_user(up, vicap_rst_inf,
1323 sizeof(*vicap_rst_inf));
1324 if (ret)
1325 ret = -EFAULT;
1326 }
1327 kfree(vicap_rst_inf);
1328 break;
1329 case RKMODULE_SET_VICAP_RST_INFO:
1330 vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
1331 if (!vicap_rst_inf) {
1332 ret = -ENOMEM;
1333 return ret;
1334 }
1335
1336 ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
1337 if (!ret)
1338 ret = max96712_ioctl(sd, cmd, vicap_rst_inf);
1339 else
1340 ret = -EFAULT;
1341 kfree(vicap_rst_inf);
1342 break;
1343 case RKMODULE_GET_START_STREAM_SEQ:
1344 seq = kzalloc(sizeof(*seq), GFP_KERNEL);
1345 if (!seq) {
1346 ret = -ENOMEM;
1347 return ret;
1348 }
1349
1350 ret = max96712_ioctl(sd, cmd, seq);
1351 if (!ret) {
1352 ret = copy_to_user(up, seq, sizeof(*seq));
1353 if (ret)
1354 ret = -EFAULT;
1355 }
1356 kfree(seq);
1357 break;
1358 case RKMODULE_SET_QUICK_STREAM:
1359 ret = copy_from_user(&stream, up, sizeof(u32));
1360 if (!ret)
1361 ret = max96712_ioctl(sd, cmd, &stream);
1362 else
1363 ret = -EFAULT;
1364 break;
1365 case RKMODULE_SET_CSI_DPHY_PARAM:
1366 dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1367 if (!dphy_param) {
1368 ret = -ENOMEM;
1369 return ret;
1370 }
1371
1372 ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
1373 if (!ret)
1374 ret = max96712_ioctl(sd, cmd, dphy_param);
1375 else
1376 ret = -EFAULT;
1377 kfree(dphy_param);
1378 break;
1379 case RKMODULE_GET_CSI_DPHY_PARAM:
1380 dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1381 if (!dphy_param) {
1382 ret = -ENOMEM;
1383 return ret;
1384 }
1385
1386 ret = max96712_ioctl(sd, cmd, dphy_param);
1387 if (!ret) {
1388 ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
1389 if (ret)
1390 ret = -EFAULT;
1391 }
1392 kfree(dphy_param);
1393 break;
1394 default:
1395 ret = -ENOIOCTLCMD;
1396 break;
1397 }
1398
1399 return ret;
1400 }
1401 #endif
1402
__max96712_start_stream(struct max96712 * max96712)1403 static int __max96712_start_stream(struct max96712 *max96712)
1404 {
1405 int ret;
1406 u32 link_freq_mhz, link_freq_idx;
1407
1408 ret = max96712_check_link_lock_state(max96712);
1409 if (ret)
1410 return ret;
1411
1412 if (max96712->hot_plug_irq > 0)
1413 enable_irq(max96712->hot_plug_irq);
1414
1415 ret = max96712_write_array(max96712,
1416 max96712->cur_mode->reg_list);
1417 if (ret)
1418 return ret;
1419
1420 link_freq_idx = max96712->cur_mode->link_freq_idx;
1421 link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L);
1422 ret = max96712_dphy_dpll_predef_set(max96712, link_freq_mhz);
1423 if (ret)
1424 return ret;
1425
1426 if (max96712->auto_init_deskew_mask != 0) {
1427 ret = max96712_auto_init_deskew(max96712,
1428 max96712->auto_init_deskew_mask);
1429 if (ret)
1430 return ret;
1431 }
1432
1433 if (max96712->frame_sync_period != 0) {
1434 ret = max96712_frame_sync_period(max96712,
1435 max96712->frame_sync_period);
1436 if (ret)
1437 return ret;
1438 }
1439
1440 /* In case these controls are set before streaming */
1441 mutex_unlock(&max96712->mutex);
1442 ret = v4l2_ctrl_handler_setup(&max96712->ctrl_handler);
1443 mutex_lock(&max96712->mutex);
1444 if (ret)
1445 return ret;
1446
1447 return max96712_mipi_enable(max96712, true);
1448
1449 }
1450
__max96712_stop_stream(struct max96712 * max96712)1451 static int __max96712_stop_stream(struct max96712 *max96712)
1452 {
1453 if (max96712->hot_plug_irq > 0)
1454 disable_irq(max96712->hot_plug_irq);
1455
1456 return max96712_mipi_enable(max96712, false);
1457 }
1458
max96712_s_stream(struct v4l2_subdev * sd,int on)1459 static int max96712_s_stream(struct v4l2_subdev *sd, int on)
1460 {
1461 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1462 struct i2c_client *client = max96712->client;
1463 int ret = 0;
1464
1465 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1466 max96712->cur_mode->width, max96712->cur_mode->height,
1467 DIV_ROUND_CLOSEST(max96712->cur_mode->max_fps.denominator,
1468 max96712->cur_mode->max_fps.numerator));
1469
1470 mutex_lock(&max96712->mutex);
1471 on = !!on;
1472 if (on == max96712->streaming)
1473 goto unlock_and_return;
1474
1475 if (on) {
1476 ret = pm_runtime_get_sync(&client->dev);
1477 if (ret < 0) {
1478 pm_runtime_put_noidle(&client->dev);
1479 goto unlock_and_return;
1480 }
1481
1482 ret = __max96712_start_stream(max96712);
1483 if (ret) {
1484 v4l2_err(sd, "start stream failed while write regs\n");
1485 pm_runtime_put(&client->dev);
1486 goto unlock_and_return;
1487 }
1488 } else {
1489 __max96712_stop_stream(max96712);
1490 pm_runtime_put(&client->dev);
1491 }
1492
1493 max96712->streaming = on;
1494
1495 unlock_and_return:
1496 mutex_unlock(&max96712->mutex);
1497
1498 return ret;
1499 }
1500
max96712_s_power(struct v4l2_subdev * sd,int on)1501 static int max96712_s_power(struct v4l2_subdev *sd, int on)
1502 {
1503 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1504 struct i2c_client *client = max96712->client;
1505 int ret = 0;
1506
1507 mutex_lock(&max96712->mutex);
1508
1509 /* If the power state is not modified - no work to do. */
1510 if (max96712->power_on == !!on)
1511 goto unlock_and_return;
1512
1513 if (on) {
1514 ret = pm_runtime_get_sync(&client->dev);
1515 if (ret < 0) {
1516 pm_runtime_put_noidle(&client->dev);
1517 goto unlock_and_return;
1518 }
1519
1520 max96712->power_on = true;
1521 } else {
1522 pm_runtime_put(&client->dev);
1523 max96712->power_on = false;
1524 }
1525
1526 unlock_and_return:
1527 mutex_unlock(&max96712->mutex);
1528
1529 return ret;
1530 }
1531
1532 /* Calculate the delay in us by clock rate and clock cycles */
max96712_cal_delay(u32 cycles)1533 static inline u32 max96712_cal_delay(u32 cycles)
1534 {
1535 return DIV_ROUND_UP(cycles, MAX96712_XVCLK_FREQ / 1000 / 1000);
1536 }
1537
__max96712_power_on(struct max96712 * max96712)1538 static int __max96712_power_on(struct max96712 *max96712)
1539 {
1540 int ret;
1541 u32 delay_us;
1542 struct device *dev = &max96712->client->dev;
1543
1544 if (!IS_ERR(max96712->power_gpio)) {
1545 gpiod_set_value_cansleep(max96712->power_gpio, 1);
1546 usleep_range(5000, 10000);
1547 }
1548
1549 if (!IS_ERR(max96712->pocen_gpio)) {
1550 gpiod_set_value_cansleep(max96712->pocen_gpio, 1);
1551 usleep_range(5000, 10000);
1552 }
1553
1554 if (!IS_ERR_OR_NULL(max96712->pins_default)) {
1555 ret = pinctrl_select_state(max96712->pinctrl,
1556 max96712->pins_default);
1557 if (ret < 0)
1558 dev_err(dev, "could not set pins\n");
1559 }
1560
1561 if (!IS_ERR(max96712->reset_gpio))
1562 gpiod_set_value_cansleep(max96712->reset_gpio, 0);
1563
1564 ret = regulator_bulk_enable(MAX96712_NUM_SUPPLIES, max96712->supplies);
1565 if (ret < 0) {
1566 dev_err(dev, "Failed to enable regulators\n");
1567 goto disable_clk;
1568 }
1569 if (!IS_ERR(max96712->reset_gpio)) {
1570 gpiod_set_value_cansleep(max96712->reset_gpio, 1);
1571 usleep_range(500, 1000);
1572 }
1573
1574 if (!IS_ERR(max96712->pwdn_gpio))
1575 gpiod_set_value_cansleep(max96712->pwdn_gpio, 1);
1576
1577 /* 8192 cycles prior to first SCCB transaction */
1578 delay_us = max96712_cal_delay(8192);
1579 usleep_range(delay_us, delay_us * 2);
1580
1581 return 0;
1582
1583 disable_clk:
1584 clk_disable_unprepare(max96712->xvclk);
1585
1586 return ret;
1587 }
1588
__max96712_power_off(struct max96712 * max96712)1589 static void __max96712_power_off(struct max96712 *max96712)
1590 {
1591 int ret;
1592 struct device *dev = &max96712->client->dev;
1593
1594 if (!IS_ERR(max96712->pwdn_gpio))
1595 gpiod_set_value_cansleep(max96712->pwdn_gpio, 0);
1596 clk_disable_unprepare(max96712->xvclk);
1597
1598 if (!IS_ERR(max96712->reset_gpio))
1599 gpiod_set_value_cansleep(max96712->reset_gpio, 0);
1600
1601 if (!IS_ERR_OR_NULL(max96712->pins_sleep)) {
1602 ret = pinctrl_select_state(max96712->pinctrl,
1603 max96712->pins_sleep);
1604 if (ret < 0)
1605 dev_dbg(dev, "could not set pins\n");
1606 }
1607
1608 regulator_bulk_disable(MAX96712_NUM_SUPPLIES, max96712->supplies);
1609
1610 if (!IS_ERR(max96712->pocen_gpio))
1611 gpiod_set_value_cansleep(max96712->pocen_gpio, 0);
1612
1613 if (!IS_ERR(max96712->power_gpio))
1614 gpiod_set_value_cansleep(max96712->power_gpio, 0);
1615 }
1616
max96712_runtime_resume(struct device * dev)1617 static int max96712_runtime_resume(struct device *dev)
1618 {
1619 struct i2c_client *client = to_i2c_client(dev);
1620 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1621 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1622
1623 return __max96712_power_on(max96712);
1624 }
1625
max96712_runtime_suspend(struct device * dev)1626 static int max96712_runtime_suspend(struct device *dev)
1627 {
1628 struct i2c_client *client = to_i2c_client(dev);
1629 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1630 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1631
1632 __max96712_power_off(max96712);
1633
1634 return 0;
1635 }
1636
1637 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
max96712_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1638 static int max96712_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1639 {
1640 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1641 struct v4l2_mbus_framefmt *try_fmt =
1642 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1643 const struct max96712_mode *def_mode = &max96712->supported_modes[0];
1644
1645 mutex_lock(&max96712->mutex);
1646 /* Initialize try_fmt */
1647 try_fmt->width = def_mode->width;
1648 try_fmt->height = def_mode->height;
1649 try_fmt->code = def_mode->bus_fmt;
1650 try_fmt->field = V4L2_FIELD_NONE;
1651
1652 mutex_unlock(&max96712->mutex);
1653 /* No crop or compose */
1654
1655 return 0;
1656 }
1657 #endif
1658
1659 static int
max96712_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1660 max96712_enum_frame_interval(struct v4l2_subdev *sd,
1661 struct v4l2_subdev_pad_config *cfg,
1662 struct v4l2_subdev_frame_interval_enum *fie)
1663 {
1664 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1665
1666 if (fie->index >= max96712->cfg_modes_num)
1667 return -EINVAL;
1668
1669 fie->code = max96712->supported_modes[fie->index].bus_fmt;
1670 fie->width = max96712->supported_modes[fie->index].width;
1671 fie->height = max96712->supported_modes[fie->index].height;
1672 fie->interval = max96712->supported_modes[fie->index].max_fps;
1673
1674 return 0;
1675 }
1676
max96712_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1677 static int max96712_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1678 struct v4l2_mbus_config *config)
1679 {
1680 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1681 u32 val = 0;
1682 u8 data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1683
1684 val |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1685 val |= (1 << (data_lanes - 1));
1686 switch (data_lanes) {
1687 case 4:
1688 val |= V4L2_MBUS_CSI2_CHANNEL_3;
1689 fallthrough;
1690 case 3:
1691 val |= V4L2_MBUS_CSI2_CHANNEL_2;
1692 fallthrough;
1693 case 2:
1694 val |= V4L2_MBUS_CSI2_CHANNEL_1;
1695 fallthrough;
1696 case 1:
1697 default:
1698 val |= V4L2_MBUS_CSI2_CHANNEL_0;
1699 break;
1700 }
1701
1702 config->type = V4L2_MBUS_CSI2_DPHY;
1703 config->flags = val;
1704
1705 return 0;
1706 }
1707
max96712_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1708 static int max96712_get_selection(struct v4l2_subdev *sd,
1709 struct v4l2_subdev_pad_config *cfg,
1710 struct v4l2_subdev_selection *sel)
1711 {
1712 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
1713
1714 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1715 sel->r.left = 0;
1716 sel->r.width = max96712->cur_mode->width;
1717 sel->r.top = 0;
1718 sel->r.height = max96712->cur_mode->height;
1719 return 0;
1720 }
1721
1722 return -EINVAL;
1723 }
1724
1725 static const struct dev_pm_ops max96712_pm_ops = { SET_RUNTIME_PM_OPS(
1726 max96712_runtime_suspend, max96712_runtime_resume, NULL) };
1727
1728 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1729 static const struct v4l2_subdev_internal_ops max96712_internal_ops = {
1730 .open = max96712_open,
1731 };
1732 #endif
1733
1734 static const struct v4l2_subdev_core_ops max96712_core_ops = {
1735 .s_power = max96712_s_power,
1736 .ioctl = max96712_ioctl,
1737 #ifdef CONFIG_COMPAT
1738 .compat_ioctl32 = max96712_compat_ioctl32,
1739 #endif
1740 };
1741
1742 static const struct v4l2_subdev_video_ops max96712_video_ops = {
1743 .s_stream = max96712_s_stream,
1744 .g_frame_interval = max96712_g_frame_interval,
1745 };
1746
1747 static const struct v4l2_subdev_pad_ops max96712_pad_ops = {
1748 .enum_mbus_code = max96712_enum_mbus_code,
1749 .enum_frame_size = max96712_enum_frame_sizes,
1750 .enum_frame_interval = max96712_enum_frame_interval,
1751 .get_fmt = max96712_get_fmt,
1752 .set_fmt = max96712_set_fmt,
1753 .get_selection = max96712_get_selection,
1754 .get_mbus_config = max96712_g_mbus_config,
1755 };
1756
1757 static const struct v4l2_subdev_ops max96712_subdev_ops = {
1758 .core = &max96712_core_ops,
1759 .video = &max96712_video_ops,
1760 .pad = &max96712_pad_ops,
1761 };
1762
max96712_initialize_controls(struct max96712 * max96712)1763 static int max96712_initialize_controls(struct max96712 *max96712)
1764 {
1765 const struct max96712_mode *mode;
1766 struct v4l2_ctrl_handler *handler;
1767 u64 pixel_rate;
1768 u8 data_lanes;
1769 int ret;
1770
1771 handler = &max96712->ctrl_handler;
1772
1773 mode = max96712->cur_mode;
1774 ret = v4l2_ctrl_handler_init(handler, 2);
1775 if (ret)
1776 return ret;
1777 handler->lock = &max96712->mutex;
1778
1779 max96712->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1780 V4L2_CID_LINK_FREQ,
1781 ARRAY_SIZE(link_freq_items) - 1, 0,
1782 link_freq_items);
1783 __v4l2_ctrl_s_ctrl(max96712->link_freq, mode->link_freq_idx);
1784 dev_info(&max96712->client->dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n",
1785 mode->link_freq_idx, link_freq_items[mode->link_freq_idx]);
1786
1787 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1788 data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1789 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * data_lanes;
1790 max96712->pixel_rate =
1791 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0,
1792 pixel_rate, 1, pixel_rate);
1793 dev_info(&max96712->client->dev, "pixel_rate = %lld, bpp = %d\n",
1794 pixel_rate, mode->bpp);
1795
1796 if (handler->error) {
1797 ret = handler->error;
1798 dev_err(&max96712->client->dev, "Failed to init controls(%d)\n",
1799 ret);
1800 goto err_free_handler;
1801 }
1802
1803 max96712->subdev.ctrl_handler = handler;
1804
1805 return 0;
1806
1807 err_free_handler:
1808 v4l2_ctrl_handler_free(handler);
1809
1810 return ret;
1811 }
1812
max96712_configure_regulators(struct max96712 * max96712)1813 static int max96712_configure_regulators(struct max96712 *max96712)
1814 {
1815 unsigned int i;
1816
1817 for (i = 0; i < MAX96712_NUM_SUPPLIES; i++)
1818 max96712->supplies[i].supply = max96712_supply_names[i];
1819
1820 return devm_regulator_bulk_get(&max96712->client->dev,
1821 MAX96712_NUM_SUPPLIES,
1822 max96712->supplies);
1823 }
1824
max96712_parse_dt(struct max96712 * max96712)1825 static int max96712_parse_dt(struct max96712 *max96712)
1826 {
1827 struct device *dev = &max96712->client->dev;
1828 struct device_node *node = dev->of_node;
1829 u8 mipi_data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1830 u32 value = 0;
1831 int ret = 0;
1832
1833 /* serializer i2c address */
1834 ret = of_property_read_u32(node, "ser-i2c-addr", &value);
1835 if (ret) {
1836 max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR;
1837 } else {
1838 dev_info(dev, "ser-i2c-addr property: %d\n", value);
1839 max96712->i2c_addr[I2C_DEV_SER] = value;
1840 }
1841 dev_info(dev, "serializer i2c address: 0x%02x\n", max96712->i2c_addr[I2C_DEV_SER]);
1842
1843 /* max96712 link Receiver Rate: 3G or 6G */
1844 ret = of_property_read_u32(node, "link-rx-rate",
1845 &max96712->rx_rate);
1846 if (ret)
1847 max96712->rx_rate = MAX96712_RX_RATE_6GBPS;
1848 else
1849 dev_info(dev, "link-rx-rate property: %d\n", max96712->rx_rate);
1850 dev_info(dev, "serdes link receiver rate: %d\n", max96712->rx_rate);
1851
1852 /* max96712 link mask:
1853 * bit[3:0] = link enable mask: 0 = disable, 1 = enable:
1854 * bit0 - LinkA, bit1 - LinkB, bit2 - LinkC, bit3 - LinkD
1855 * bit[7:4] = link type, 0 = GMSL1, 1 = GMSL2:
1856 * bit4 - LinkA, bit5 - LinkB, bit6 - LinkC, bit7 = LinkD
1857 */
1858 ret = of_property_read_u32(node, "link-mask",
1859 &max96712->link_mask);
1860 if (ret) {
1861 /* default link mask */
1862 if (mipi_data_lanes == 4)
1863 max96712->link_mask = 0xFF; /* Link A/B/C/D: GMSL2 and enable */
1864 else
1865 max96712->link_mask = 0x33; /* Link A/B: GMSL2 and enable */
1866 } else {
1867 dev_info(dev, "link-mask property: 0x%08x\n", max96712->link_mask);
1868 }
1869 dev_info(dev, "serdes link mask: 0x%02x\n", max96712->link_mask);
1870
1871 /* auto initial deskew mask */
1872 ret = of_property_read_u32(node, "auto-init-deskew-mask",
1873 &max96712->auto_init_deskew_mask);
1874 if (ret)
1875 max96712->auto_init_deskew_mask = 0x0F; // 0x0F: default enable all
1876 dev_info(dev, "auto init deskew mask: 0x%02x\n", max96712->auto_init_deskew_mask);
1877
1878 /* FSYNC period config */
1879 ret = of_property_read_u32(node, "frame-sync-period",
1880 &max96712->frame_sync_period);
1881 if (ret)
1882 max96712->frame_sync_period = 0; // 0: disable (default)
1883 dev_info(dev, "frame sync period: %d\n", max96712->frame_sync_period);
1884
1885 return 0;
1886 }
1887
max96712_probe(struct i2c_client * client,const struct i2c_device_id * id)1888 static int max96712_probe(struct i2c_client *client,
1889 const struct i2c_device_id *id)
1890 {
1891 struct device *dev = &client->dev;
1892 struct device_node *node = dev->of_node;
1893 struct max96712 *max96712;
1894 struct v4l2_subdev *sd;
1895 struct device_node *endpoint;
1896 char facing[2];
1897 u8 mipi_data_lanes;
1898 int ret;
1899
1900 dev_info(dev, "driver version: %02x.%02x.%02x", DRIVER_VERSION >> 16,
1901 (DRIVER_VERSION & 0xff00) >> 8, DRIVER_VERSION & 0x00ff);
1902
1903 max96712 = devm_kzalloc(dev, sizeof(*max96712), GFP_KERNEL);
1904 if (!max96712)
1905 return -ENOMEM;
1906
1907 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1908 &max96712->module_index);
1909 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1910 &max96712->module_facing);
1911 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1912 &max96712->module_name);
1913 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1914 &max96712->len_name);
1915 if (ret) {
1916 dev_err(dev, "could not get module information!\n");
1917 return -EINVAL;
1918 }
1919
1920 max96712->regmap = devm_regmap_init_i2c(client, &max96712_regmap_config);
1921 if (IS_ERR(max96712->regmap)) {
1922 dev_err(dev, "Failed to regmap initialize I2C\n");
1923 return PTR_ERR(max96712->regmap);
1924 }
1925
1926 max96712->client = client;
1927 i2c_set_clientdata(client, max96712);
1928
1929 /* i2c default address init */
1930 max96712->i2c_addr[I2C_DEV_DES] = client->addr;
1931 max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR;
1932 max96712->i2c_addr[I2C_DEV_CAM] = CAM_I2C_ADDR;
1933
1934 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1935 if (!endpoint) {
1936 dev_err(dev, "Failed to get endpoint\n");
1937 return -EINVAL;
1938 }
1939
1940 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1941 &max96712->bus_cfg);
1942 if (ret) {
1943 dev_err(dev, "Failed to get bus config\n");
1944 return -EINVAL;
1945 }
1946 mipi_data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1947 dev_info(dev, "mipi csi2 phy data lanes %d\n", mipi_data_lanes);
1948
1949 if (mipi_data_lanes == 4) {
1950 max96712->supported_modes = supported_modes_4lane;
1951 max96712->cfg_modes_num = ARRAY_SIZE(supported_modes_4lane);
1952 } else {
1953 dev_err(dev, "Not support mipi data lane: %d\n", mipi_data_lanes);
1954 return -EINVAL;
1955 }
1956 max96712->cur_mode = &max96712->supported_modes[0];
1957
1958 max96712->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1959 if (IS_ERR(max96712->power_gpio))
1960 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1961
1962 max96712->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1963 if (IS_ERR(max96712->reset_gpio))
1964 dev_warn(dev, "Failed to get reset-gpios\n");
1965
1966 max96712->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1967 if (IS_ERR(max96712->pwdn_gpio))
1968 dev_warn(dev, "Failed to get pwdn-gpios\n");
1969
1970 max96712->pocen_gpio = devm_gpiod_get(dev, "pocen", GPIOD_OUT_LOW);
1971 if (IS_ERR(max96712->pocen_gpio))
1972 dev_warn(dev, "Failed to get pocen-gpios\n");
1973
1974 max96712->lock_gpio = devm_gpiod_get(dev, "lock", GPIOD_IN);
1975 if (IS_ERR(max96712->lock_gpio))
1976 dev_warn(dev, "Failed to get lock-gpios\n");
1977
1978 ret = max96712_configure_regulators(max96712);
1979 if (ret) {
1980 dev_err(dev, "Failed to get power regulators\n");
1981 return ret;
1982 }
1983
1984 max96712->pinctrl = devm_pinctrl_get(dev);
1985 if (!IS_ERR(max96712->pinctrl)) {
1986 max96712->pins_default = pinctrl_lookup_state(
1987 max96712->pinctrl, OF_CAMERA_PINCTRL_STATE_DEFAULT);
1988 if (IS_ERR(max96712->pins_default))
1989 dev_err(dev, "could not get default pinstate\n");
1990
1991 max96712->pins_sleep = pinctrl_lookup_state(
1992 max96712->pinctrl, OF_CAMERA_PINCTRL_STATE_SLEEP);
1993 if (IS_ERR(max96712->pins_sleep))
1994 dev_err(dev, "could not get sleep pinstate\n");
1995 }
1996
1997 max96712_parse_dt(max96712);
1998
1999 mutex_init(&max96712->mutex);
2000
2001 sd = &max96712->subdev;
2002 v4l2_i2c_subdev_init(sd, client, &max96712_subdev_ops);
2003 ret = max96712_initialize_controls(max96712);
2004 if (ret)
2005 goto err_destroy_mutex;
2006
2007 ret = __max96712_power_on(max96712);
2008 if (ret)
2009 goto err_free_handler;
2010
2011 ret = max96712_check_local_chipid(max96712);
2012 if (ret)
2013 goto err_power_off;
2014
2015 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2016 sd->internal_ops = &max96712_internal_ops;
2017 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2018 #endif
2019 #if defined(CONFIG_MEDIA_CONTROLLER)
2020 max96712->pad.flags = MEDIA_PAD_FL_SOURCE;
2021 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2022 ret = media_entity_pads_init(&sd->entity, 1, &max96712->pad);
2023 if (ret < 0)
2024 goto err_power_off;
2025 #endif
2026
2027 memset(facing, 0, sizeof(facing));
2028 if (strcmp(max96712->module_facing, "back") == 0)
2029 facing[0] = 'b';
2030 else
2031 facing[0] = 'f';
2032
2033 v4l2_set_subdevdata(sd, max96712);
2034
2035 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2036 max96712->module_index, facing, MAX96712_NAME,
2037 dev_name(sd->dev));
2038 ret = v4l2_async_register_subdev_sensor_common(sd);
2039 if (ret) {
2040 dev_err(dev, "v4l2 async register subdev failed\n");
2041 goto err_clean_entity;
2042 }
2043
2044 if (!IS_ERR(max96712->lock_gpio)) {
2045 max96712->hot_plug_irq = gpiod_to_irq(max96712->lock_gpio);
2046 if (max96712->hot_plug_irq < 0) {
2047 dev_err(dev, "failed to get hot plug irq\n");
2048 } else {
2049 ret = devm_request_threaded_irq(dev,
2050 max96712->hot_plug_irq,
2051 NULL,
2052 max96712_hot_plug_detect_irq_handler,
2053 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
2054 "max96712_hot_plug",
2055 max96712);
2056 if (ret) {
2057 dev_err(dev, "failed to request hot plug irq (%d)\n", ret);
2058 max96712->hot_plug_irq = -1;
2059 } else {
2060 disable_irq(max96712->hot_plug_irq);
2061 }
2062 }
2063 }
2064
2065 pm_runtime_set_active(dev);
2066 pm_runtime_enable(dev);
2067 pm_runtime_idle(dev);
2068
2069 return 0;
2070
2071 err_clean_entity:
2072 #if defined(CONFIG_MEDIA_CONTROLLER)
2073 media_entity_cleanup(&sd->entity);
2074 #endif
2075 err_power_off:
2076 __max96712_power_off(max96712);
2077 err_free_handler:
2078 v4l2_ctrl_handler_free(&max96712->ctrl_handler);
2079 err_destroy_mutex:
2080 mutex_destroy(&max96712->mutex);
2081
2082 return ret;
2083 }
2084
max96712_remove(struct i2c_client * client)2085 static int max96712_remove(struct i2c_client *client)
2086 {
2087 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2088 struct max96712 *max96712 = v4l2_get_subdevdata(sd);
2089
2090 v4l2_async_unregister_subdev(sd);
2091 #if defined(CONFIG_MEDIA_CONTROLLER)
2092 media_entity_cleanup(&sd->entity);
2093 #endif
2094 v4l2_ctrl_handler_free(&max96712->ctrl_handler);
2095 mutex_destroy(&max96712->mutex);
2096
2097 pm_runtime_disable(&client->dev);
2098 if (!pm_runtime_status_suspended(&client->dev))
2099 __max96712_power_off(max96712);
2100 pm_runtime_set_suspended(&client->dev);
2101
2102 return 0;
2103 }
2104
2105 #if IS_ENABLED(CONFIG_OF)
2106 static const struct of_device_id max96712_of_match[] = {
2107 { .compatible = "maxim,max96712" },
2108 {},
2109 };
2110 MODULE_DEVICE_TABLE(of, max96712_of_match);
2111 #endif
2112
2113 static const struct i2c_device_id max96712_match_id[] = {
2114 { "maxim,max96712", 0 },
2115 {},
2116 };
2117
2118 static struct i2c_driver max96712_i2c_driver = {
2119 .driver = {
2120 .name = MAX96712_NAME,
2121 .pm = &max96712_pm_ops,
2122 .of_match_table = of_match_ptr(max96712_of_match),
2123 },
2124 .probe = &max96712_probe,
2125 .remove = &max96712_remove,
2126 .id_table = max96712_match_id,
2127 };
2128
sensor_mod_init(void)2129 static int __init sensor_mod_init(void)
2130 {
2131 return i2c_add_driver(&max96712_i2c_driver);
2132 }
2133
sensor_mod_exit(void)2134 static void __exit sensor_mod_exit(void)
2135 {
2136 i2c_del_driver(&max96712_i2c_driver);
2137 }
2138
2139 module_init(sensor_mod_init);
2140 module_exit(sensor_mod_exit);
2141
2142 MODULE_DESCRIPTION("Maxim max96712 deserializer driver");
2143 MODULE_LICENSE("GPL");
2144