xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/lt8619c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Dingxian Wen <shawn.wen@rock-chips.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun  * V0.0X01.0X01
9*4882a593Smuzhiyun  * 1. add BT656 mode support.
10*4882a593Smuzhiyun  * 2. add ddr mode support.
11*4882a593Smuzhiyun  * 3. fix 576i and 480i support mode.
12*4882a593Smuzhiyun  * V0.0X01.0X02 add 4K30 mode.
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/clk.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
22*4882a593Smuzhiyun #include <linux/interrupt.h>
23*4882a593Smuzhiyun #include <linux/of_graph.h>
24*4882a593Smuzhiyun #include <linux/videodev2.h>
25*4882a593Smuzhiyun #include <linux/workqueue.h>
26*4882a593Smuzhiyun #include <linux/platform_device.h>
27*4882a593Smuzhiyun #include <linux/v4l2-dv-timings.h>
28*4882a593Smuzhiyun #include <linux/hdmi.h>
29*4882a593Smuzhiyun #include <linux/version.h>
30*4882a593Smuzhiyun #include <linux/compat.h>
31*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
32*4882a593Smuzhiyun #include <media/v4l2-dv-timings.h>
33*4882a593Smuzhiyun #include <media/v4l2-device.h>
34*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
35*4882a593Smuzhiyun #include <media/v4l2-event.h>
36*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
37*4882a593Smuzhiyun #include <linux/regmap.h>
38*4882a593Smuzhiyun #include "lt8619c.h"
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x02)
41*4882a593Smuzhiyun #define LT8619C_NAME		"LT8619C"
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static int debug;
44*4882a593Smuzhiyun module_param(debug, int, 0644);
45*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug level (0-2)");
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define RK_CAMERA_MODULE_DUAL_EDGE		"rockchip,dual-edge"
48*4882a593Smuzhiyun #define LT8619C_DEFAULT_DUAL_EDGE		1U
49*4882a593Smuzhiyun #define RK_CAMERA_MODULE_DVP_MODE		"rockchip,dvp-mode"
50*4882a593Smuzhiyun #define LT8619C_DEFAULT_DVP_MODE		BT1120_OUTPUT
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct lt8619c_mode {
53*4882a593Smuzhiyun 	u32 width;
54*4882a593Smuzhiyun 	u32 height;
55*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
56*4882a593Smuzhiyun 	u32 hts_def;
57*4882a593Smuzhiyun 	u32 vts_def;
58*4882a593Smuzhiyun 	u32 exp_def;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun struct lt8619c {
62*4882a593Smuzhiyun 	struct device *dev;
63*4882a593Smuzhiyun 	struct v4l2_subdev sd;
64*4882a593Smuzhiyun 	struct media_pad pad;
65*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
66*4882a593Smuzhiyun 	struct i2c_client *i2c_client;
67*4882a593Smuzhiyun 	struct mutex confctl_mutex;
68*4882a593Smuzhiyun 	struct v4l2_ctrl *detect_tx_5v_ctrl;
69*4882a593Smuzhiyun 	struct delayed_work delayed_work_enable_hotplug;
70*4882a593Smuzhiyun 	struct delayed_work delayed_work_monitor_resolution;
71*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
72*4882a593Smuzhiyun 	struct regmap *reg_map;
73*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
74*4882a593Smuzhiyun 	struct gpio_desc *power_gpio;
75*4882a593Smuzhiyun 	struct gpio_desc *plugin_det_gpio;
76*4882a593Smuzhiyun 	struct clk *xvclk;
77*4882a593Smuzhiyun 	const struct lt8619c_mode *cur_mode;
78*4882a593Smuzhiyun 	const char *module_facing;
79*4882a593Smuzhiyun 	const char *module_name;
80*4882a593Smuzhiyun 	const char *len_name;
81*4882a593Smuzhiyun 	bool nosignal;
82*4882a593Smuzhiyun 	bool enable_hdcp;
83*4882a593Smuzhiyun 	u32 clk_ddrmode_en;
84*4882a593Smuzhiyun 	bool BT656_double_clk_en;
85*4882a593Smuzhiyun 	bool hpd_output_inverted;
86*4882a593Smuzhiyun 	int plugin_irq;
87*4882a593Smuzhiyun 	u32 edid_blocks_written;
88*4882a593Smuzhiyun 	u32 mbus_fmt_code;
89*4882a593Smuzhiyun 	u32 module_index;
90*4882a593Smuzhiyun 	u32 yuv_output_mode;
91*4882a593Smuzhiyun 	u32 cp_convert_mode;
92*4882a593Smuzhiyun 	u32 yc_swap;
93*4882a593Smuzhiyun 	u32 yuv_colordepth;
94*4882a593Smuzhiyun 	u32 bt_tx_sync_pol;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static const struct v4l2_dv_timings_cap lt8619c_timings_cap = {
98*4882a593Smuzhiyun 	.type = V4L2_DV_BT_656_1120,
99*4882a593Smuzhiyun 	/* keep this initialization for compatibility with GCC < 4.4.6 */
100*4882a593Smuzhiyun 	.reserved = { 0 },
101*4882a593Smuzhiyun 	V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 410000000,
102*4882a593Smuzhiyun 			V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
103*4882a593Smuzhiyun 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
104*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
105*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_REDUCED_BLANKING |
106*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_CUSTOM)
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun static u8 edid_init_data[] = {
110*4882a593Smuzhiyun 	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
111*4882a593Smuzhiyun 	0x49, 0x78, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
112*4882a593Smuzhiyun 	0x1C, 0x1F, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
113*4882a593Smuzhiyun 	0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
114*4882a593Smuzhiyun 	0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
115*4882a593Smuzhiyun 	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
116*4882a593Smuzhiyun 	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
117*4882a593Smuzhiyun 	0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
118*4882a593Smuzhiyun 	0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
119*4882a593Smuzhiyun 	0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
120*4882a593Smuzhiyun 	0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
121*4882a593Smuzhiyun 	0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
122*4882a593Smuzhiyun 	0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
123*4882a593Smuzhiyun 	0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
124*4882a593Smuzhiyun 	0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
125*4882a593Smuzhiyun 	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x64,
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	0x02, 0x03, 0x1C, 0x71, 0x49, 0x90, 0x04, 0x02,
128*4882a593Smuzhiyun 	0x5F, 0x11, 0x07, 0x05, 0x16, 0x22, 0x23, 0x09,
129*4882a593Smuzhiyun 	0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03,
130*4882a593Smuzhiyun 	0x0C, 0x00, 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A,
131*4882a593Smuzhiyun 	0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
132*4882a593Smuzhiyun 	0x13, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09,
133*4882a593Smuzhiyun 	0x80, 0xA0, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60,
134*4882a593Smuzhiyun 	0xA2, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18,
135*4882a593Smuzhiyun 	0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20,
136*4882a593Smuzhiyun 	0x0C, 0x40, 0x55, 0x00, 0x48, 0x39, 0x00, 0x00,
137*4882a593Smuzhiyun 	0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
138*4882a593Smuzhiyun 	0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C,
139*4882a593Smuzhiyun 	0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18,
140*4882a593Smuzhiyun 	0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00,
141*4882a593Smuzhiyun 	0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
142*4882a593Smuzhiyun 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB3,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static u8 phase_num[10] = {
146*4882a593Smuzhiyun 	0x20, 0x28, 0x21, 0x29, 0x22,
147*4882a593Smuzhiyun 	0x2a, 0x23, 0x2b, 0x24, 0x2c,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static const struct lt8619c_mode supported_modes[] = {
151*4882a593Smuzhiyun 	{
152*4882a593Smuzhiyun 		.width = 3840,
153*4882a593Smuzhiyun 		.height = 2160,
154*4882a593Smuzhiyun 		.max_fps = {
155*4882a593Smuzhiyun 			.numerator = 10000,
156*4882a593Smuzhiyun 			.denominator = 300000,
157*4882a593Smuzhiyun 		},
158*4882a593Smuzhiyun 		.hts_def = 4400,
159*4882a593Smuzhiyun 		.vts_def = 2250,
160*4882a593Smuzhiyun 	}, {
161*4882a593Smuzhiyun 		.width = 1920,
162*4882a593Smuzhiyun 		.height = 1080,
163*4882a593Smuzhiyun 		.max_fps = {
164*4882a593Smuzhiyun 			.numerator = 10000,
165*4882a593Smuzhiyun 			.denominator = 600000,
166*4882a593Smuzhiyun 		},
167*4882a593Smuzhiyun 		.hts_def = 2200,
168*4882a593Smuzhiyun 		.vts_def = 1125,
169*4882a593Smuzhiyun 	}, {
170*4882a593Smuzhiyun 		.width = 1920,
171*4882a593Smuzhiyun 		.height = 1080,
172*4882a593Smuzhiyun 		.max_fps = {
173*4882a593Smuzhiyun 			.numerator = 10000,
174*4882a593Smuzhiyun 			.denominator = 300000,
175*4882a593Smuzhiyun 		},
176*4882a593Smuzhiyun 		.hts_def = 2200,
177*4882a593Smuzhiyun 		.vts_def = 1125,
178*4882a593Smuzhiyun 	}, {
179*4882a593Smuzhiyun 		.width = 1920,
180*4882a593Smuzhiyun 		.height = 540,
181*4882a593Smuzhiyun 		.max_fps = {
182*4882a593Smuzhiyun 			.numerator = 10000,
183*4882a593Smuzhiyun 			.denominator = 600000,
184*4882a593Smuzhiyun 		},
185*4882a593Smuzhiyun 		.hts_def = 2200,
186*4882a593Smuzhiyun 		.vts_def = 562,
187*4882a593Smuzhiyun 	}, {
188*4882a593Smuzhiyun 		.width = 1280,
189*4882a593Smuzhiyun 		.height = 720,
190*4882a593Smuzhiyun 		.max_fps = {
191*4882a593Smuzhiyun 			.numerator = 10000,
192*4882a593Smuzhiyun 			.denominator = 600000,
193*4882a593Smuzhiyun 		},
194*4882a593Smuzhiyun 		.hts_def = 1650,
195*4882a593Smuzhiyun 		.vts_def = 750,
196*4882a593Smuzhiyun 	}, {
197*4882a593Smuzhiyun 		.width = 720,
198*4882a593Smuzhiyun 		.height = 576,
199*4882a593Smuzhiyun 		.max_fps = {
200*4882a593Smuzhiyun 			.numerator = 10000,
201*4882a593Smuzhiyun 			.denominator = 500000,
202*4882a593Smuzhiyun 		},
203*4882a593Smuzhiyun 		.hts_def = 864,
204*4882a593Smuzhiyun 		.vts_def = 625,
205*4882a593Smuzhiyun 	}, {
206*4882a593Smuzhiyun 		.width = 720,
207*4882a593Smuzhiyun 		.height = 480,
208*4882a593Smuzhiyun 		.max_fps = {
209*4882a593Smuzhiyun 			.numerator = 10000,
210*4882a593Smuzhiyun 			.denominator = 600000,
211*4882a593Smuzhiyun 		},
212*4882a593Smuzhiyun 		.hts_def = 858,
213*4882a593Smuzhiyun 		.vts_def = 525,
214*4882a593Smuzhiyun 	}, {
215*4882a593Smuzhiyun 		.width = 1440,
216*4882a593Smuzhiyun 		.height = 480,
217*4882a593Smuzhiyun 		.max_fps = {
218*4882a593Smuzhiyun 			.numerator = 10000,
219*4882a593Smuzhiyun 			.denominator = 600000,
220*4882a593Smuzhiyun 		},
221*4882a593Smuzhiyun 		.hts_def = 1716,
222*4882a593Smuzhiyun 		.vts_def = 525,
223*4882a593Smuzhiyun 	}, {
224*4882a593Smuzhiyun 		.width = 1440,
225*4882a593Smuzhiyun 		.height = 576,
226*4882a593Smuzhiyun 		.max_fps = {
227*4882a593Smuzhiyun 			.numerator = 10000,
228*4882a593Smuzhiyun 			.denominator = 500000,
229*4882a593Smuzhiyun 		},
230*4882a593Smuzhiyun 		.hts_def = 1728,
231*4882a593Smuzhiyun 		.vts_def = 625,
232*4882a593Smuzhiyun 	},
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en);
236*4882a593Smuzhiyun static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd);
237*4882a593Smuzhiyun static void lt8619c_yuv_config(struct v4l2_subdev *sd);
238*4882a593Smuzhiyun static void lt8619c_format_change(struct v4l2_subdev *sd);
239*4882a593Smuzhiyun static void enable_stream(struct v4l2_subdev *sd, bool enable);
240*4882a593Smuzhiyun static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
241*4882a593Smuzhiyun 			struct v4l2_dv_timings *timings);
242*4882a593Smuzhiyun static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd);
243*4882a593Smuzhiyun static void LT8619C_phase_config(struct v4l2_subdev *sd);
244*4882a593Smuzhiyun static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
245*4882a593Smuzhiyun 		struct v4l2_dv_timings *timings);
246*4882a593Smuzhiyun static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
247*4882a593Smuzhiyun 		struct v4l2_dv_timings *timings);
248*4882a593Smuzhiyun 
to_lt8619c(struct v4l2_subdev * sd)249*4882a593Smuzhiyun static inline struct lt8619c *to_lt8619c(struct v4l2_subdev *sd)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	return container_of(sd, struct lt8619c, sd);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
tx_5v_power_present(struct v4l2_subdev * sd)254*4882a593Smuzhiyun static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	int val;
257*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	val = gpiod_get_value(lt8619c->plugin_det_gpio);
260*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s 5v_present: %d!\n", __func__, val);
261*4882a593Smuzhiyun 	return  (val > 0);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
no_signal(struct v4l2_subdev * sd)264*4882a593Smuzhiyun static inline bool no_signal(struct v4l2_subdev *sd)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "no signal:%d\n", lt8619c->nosignal);
269*4882a593Smuzhiyun 	return lt8619c->nosignal;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
lt8619c_is_supported_interlaced_res(struct v4l2_subdev * sd,u32 hact,u32 vact)272*4882a593Smuzhiyun static bool lt8619c_is_supported_interlaced_res(struct v4l2_subdev *sd,
273*4882a593Smuzhiyun 		u32 hact, u32 vact)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	if ((hact == 1920 && vact == 540) ||
276*4882a593Smuzhiyun 	    (hact == 1440 && vact == 288) ||
277*4882a593Smuzhiyun 	    (hact == 1440 && vact == 240))
278*4882a593Smuzhiyun 		return true;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	return false;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
lt8619c_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)283*4882a593Smuzhiyun static int lt8619c_get_detected_timings(struct v4l2_subdev *sd,
284*4882a593Smuzhiyun 				     struct v4l2_dv_timings *timings)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
287*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
288*4882a593Smuzhiyun 	u32 hact, vact, htotal, vtotal, hbp, hfp, hs;
289*4882a593Smuzhiyun 	u32 fps, hdmi_clk_cnt;
290*4882a593Smuzhiyun 	u32 val, vbp, vfp, vs;
291*4882a593Smuzhiyun 	u32 pix_clk;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
294*4882a593Smuzhiyun 	timings->type = V4L2_DV_BT_656_1120;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
297*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x22, &val);
298*4882a593Smuzhiyun 	hact = val << 8;
299*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x23, &val);
300*4882a593Smuzhiyun 	hact |= val;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x20, &val);
303*4882a593Smuzhiyun 	vact = (val & 0xf) << 8;
304*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x21, &val);
305*4882a593Smuzhiyun 	vact |= val;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1e, &val);
308*4882a593Smuzhiyun 	htotal = val << 8;
309*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1f, &val);
310*4882a593Smuzhiyun 	htotal |= val;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1c, &val);
313*4882a593Smuzhiyun 	vtotal = (val & 0xf) << 8;
314*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1d, &val);
315*4882a593Smuzhiyun 	vtotal |= val;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1a, &val);
318*4882a593Smuzhiyun 	hfp = val << 8;
319*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x1b, &val);
320*4882a593Smuzhiyun 	hfp |= val;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x18, &val);
323*4882a593Smuzhiyun 	hbp = val << 8;
324*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x19, &val);
325*4882a593Smuzhiyun 	hbp |= val;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x14, &val);
328*4882a593Smuzhiyun 	hs = val << 8;
329*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x15, &val);
330*4882a593Smuzhiyun 	hs |= val;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x17, &vfp);
333*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x16, &vbp);
334*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x13, &vs);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
337*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x44, &val);
338*4882a593Smuzhiyun 	hdmi_clk_cnt = (val & 0x3) << 16;
339*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x45, &val);
340*4882a593Smuzhiyun 	hdmi_clk_cnt |= val << 8;
341*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x46, &val);
342*4882a593Smuzhiyun 	hdmi_clk_cnt |= val;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	bt->width = hact;
345*4882a593Smuzhiyun 	bt->height = vact;
346*4882a593Smuzhiyun 	bt->hfrontporch = hfp;
347*4882a593Smuzhiyun 	bt->hsync = hs;
348*4882a593Smuzhiyun 	bt->hbackporch = hbp;
349*4882a593Smuzhiyun 	bt->vfrontporch = vfp;
350*4882a593Smuzhiyun 	bt->vsync = vs;
351*4882a593Smuzhiyun 	bt->vbackporch = vbp;
352*4882a593Smuzhiyun 	pix_clk = hdmi_clk_cnt * 1000;
353*4882a593Smuzhiyun 	bt->pixelclock = pix_clk;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	fps = 0;
356*4882a593Smuzhiyun 	if (htotal * vtotal)
357*4882a593Smuzhiyun 		fps = (pix_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	/* for interlaced res 1080i 576i 480i */
360*4882a593Smuzhiyun 	if (lt8619c_is_supported_interlaced_res(sd, hact, vact)) {
361*4882a593Smuzhiyun 		bt->interlaced = V4L2_DV_INTERLACED;
362*4882a593Smuzhiyun 		bt->height *= 2;
363*4882a593Smuzhiyun 		bt->il_vsync = bt->vsync + 1;
364*4882a593Smuzhiyun 	} else {
365*4882a593Smuzhiyun 		bt->interlaced = V4L2_DV_PROGRESSIVE;
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd,
369*4882a593Smuzhiyun 		"%s: act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu, frame mode:%s\n",
370*4882a593Smuzhiyun 		__func__, hact, vact, htotal, vtotal, fps, bt->pixelclock,
371*4882a593Smuzhiyun 		(bt->interlaced == V4L2_DV_INTERLACED) ? "I" : "P");
372*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd,
373*4882a593Smuzhiyun 		"%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
374*4882a593Smuzhiyun 		__func__, bt->hfrontporch, bt->hsync, bt->hbackporch,
375*4882a593Smuzhiyun 		bt->vfrontporch, bt->vsync, bt->vbackporch);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	return 0;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun 
lt8619c_config_all(struct v4l2_subdev * sd)380*4882a593Smuzhiyun static void lt8619c_config_all(struct v4l2_subdev *sd)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	lt8619c_wait_for_signal_stable(sd);
383*4882a593Smuzhiyun 	LVDSPLL_Lock_Det(sd);
384*4882a593Smuzhiyun 	lt8619c_yuv_config(sd);
385*4882a593Smuzhiyun 	LT8619C_phase_config(sd);
386*4882a593Smuzhiyun 	lt8619c_format_change(sd);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun 
lt8619c_delayed_work_enable_hotplug(struct work_struct * work)389*4882a593Smuzhiyun static void lt8619c_delayed_work_enable_hotplug(struct work_struct *work)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
392*4882a593Smuzhiyun 	struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
393*4882a593Smuzhiyun 			delayed_work_enable_hotplug);
394*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt8619c->sd;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: in\n", __func__);
397*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
398*4882a593Smuzhiyun 	if (tx_5v_power_present(sd)) {
399*4882a593Smuzhiyun 		lt8619c_set_hpd(sd, 1);
400*4882a593Smuzhiyun 		lt8619c_config_all(sd);
401*4882a593Smuzhiyun 		lt8619c->nosignal = false;
402*4882a593Smuzhiyun 		/* monitor resolution after 100ms */
403*4882a593Smuzhiyun 		schedule_delayed_work(&lt8619c->delayed_work_monitor_resolution,
404*4882a593Smuzhiyun 				HZ / 10);
405*4882a593Smuzhiyun 	} else {
406*4882a593Smuzhiyun 		cancel_delayed_work(&lt8619c->delayed_work_monitor_resolution);
407*4882a593Smuzhiyun 		enable_stream(sd, false);
408*4882a593Smuzhiyun 		lt8619c_set_hpd(sd, 0);
409*4882a593Smuzhiyun 		lt8619c->nosignal = true;
410*4882a593Smuzhiyun 	}
411*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun 
lt8619c_delayed_work_monitor_resolution(struct work_struct * work)414*4882a593Smuzhiyun static void lt8619c_delayed_work_monitor_resolution(struct work_struct *work)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
417*4882a593Smuzhiyun 	struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
418*4882a593Smuzhiyun 			delayed_work_monitor_resolution);
419*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt8619c->sd;
420*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
421*4882a593Smuzhiyun 	bool is_supported_res, is_timing_changed;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: in\n", __func__);
424*4882a593Smuzhiyun 	if (!tx_5v_power_present(sd)) {
425*4882a593Smuzhiyun 		v4l2_dbg(2, debug, sd, "%s: HDMI pull out, return!\n", __func__);
426*4882a593Smuzhiyun 		lt8619c->nosignal = true;
427*4882a593Smuzhiyun 		return;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
431*4882a593Smuzhiyun 	lt8619c_get_detected_timings(sd, &timings);
432*4882a593Smuzhiyun 	is_supported_res = lt8619c_rcv_supported_res(sd, &timings);
433*4882a593Smuzhiyun 	is_timing_changed = lt8619c_timing_changed(sd, &timings);
434*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd,
435*4882a593Smuzhiyun 		"%s: is_supported_res: %d, is_timing_changed: %d\n",
436*4882a593Smuzhiyun 		__func__, is_supported_res, is_timing_changed);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	if (!is_supported_res) {
439*4882a593Smuzhiyun 		lt8619c->nosignal = true;
440*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: no supported res, cfg as nosignal!\n",
441*4882a593Smuzhiyun 				__func__);
442*4882a593Smuzhiyun 	}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	if (is_supported_res && is_timing_changed) {
445*4882a593Smuzhiyun 		lt8619c_config_all(sd);
446*4882a593Smuzhiyun 		lt8619c->nosignal = false;
447*4882a593Smuzhiyun 	}
448*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	schedule_delayed_work(&lt8619c->delayed_work_monitor_resolution, HZ);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
lt8619c_load_hdcpkey(struct v4l2_subdev * sd)453*4882a593Smuzhiyun static void lt8619c_load_hdcpkey(struct v4l2_subdev *sd)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
456*4882a593Smuzhiyun 	int wait_cnt = 5;
457*4882a593Smuzhiyun 	u32 val;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
460*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xb2, 0x50);
461*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xa3, 0x77);
462*4882a593Smuzhiyun 	while (wait_cnt) {
463*4882a593Smuzhiyun 		usleep_range(50*1000, 50*1000);
464*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0xc0, &val);
465*4882a593Smuzhiyun 		if (val & 0x8)
466*4882a593Smuzhiyun 			break;
467*4882a593Smuzhiyun 		wait_cnt--;
468*4882a593Smuzhiyun 	}
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xb2, 0xd0);
471*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xa3, 0x57);
472*4882a593Smuzhiyun 	if (val & 0x8)
473*4882a593Smuzhiyun 		v4l2_info(sd, "load hdcp key success!\n");
474*4882a593Smuzhiyun 	else
475*4882a593Smuzhiyun 		v4l2_err(sd, "load hdcp key failed!\n");
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun 
lt8619c_set_hdmi_hdcp(struct v4l2_subdev * sd,bool enable)478*4882a593Smuzhiyun static void lt8619c_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
479*4882a593Smuzhiyun {
480*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: %sable\n", __func__, enable ? "en" : "dis");
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	if (enable)
483*4882a593Smuzhiyun 		lt8619c_load_hdcpkey(sd);
484*4882a593Smuzhiyun 	else
485*4882a593Smuzhiyun 		v4l2_info(sd, "disable hdcp function!\n");
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun 
lt8619c_mode_config(struct v4l2_subdev * sd)488*4882a593Smuzhiyun static void lt8619c_mode_config(struct v4l2_subdev *sd)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
493*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x2c, BIT(5) | BIT(4), BIT(5) | BIT(4));
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
496*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x80, CLK_SRC);
497*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x89, REF_RESISTANCE);
498*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8b, 0x90);
499*4882a593Smuzhiyun 	/* Turn off BT output */
500*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xa8, 0x07);
501*4882a593Smuzhiyun 	/* enable PLL detect */
502*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x04, 0xf2);
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	if (lt8619c->BT656_double_clk_en) {
505*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x96, 0x71);
506*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa0, 0x51);
507*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa3, 0x44);
508*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa2, 0x20);
509*4882a593Smuzhiyun 	} else {
510*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x96, 0x71);
511*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa0, 0x50);
512*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa3, 0x44);
513*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa2, 0x20);
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x60, OUTPUT_MODE_MASK,
516*4882a593Smuzhiyun 			lt8619c->yuv_output_mode);
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	if (lt8619c->clk_ddrmode_en == 1)
519*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa4, 0x14);
520*4882a593Smuzhiyun 	else
521*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa4, 0x10);
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	/* Vblank change reference EAV flag. */
524*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6f, 0x04);
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: output mode:%s, clk ddrmode en:%d\n",
527*4882a593Smuzhiyun 		__func__, (lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" :
528*4882a593Smuzhiyun 		"BT1120", lt8619c->clk_ddrmode_en);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
lt8619c_set_hpd(struct v4l2_subdev * sd,int en)531*4882a593Smuzhiyun static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
534*4882a593Smuzhiyun 	int level;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: %d\n", __func__, en);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	level = lt8619c->hpd_output_inverted ? !en : en;
539*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
540*4882a593Smuzhiyun 	if (level)
541*4882a593Smuzhiyun 		regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), BIT(3));
542*4882a593Smuzhiyun 	else
543*4882a593Smuzhiyun 		regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), 0);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun 
lt8619c_write_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)546*4882a593Smuzhiyun static void lt8619c_write_edid(struct v4l2_subdev *sd,
547*4882a593Smuzhiyun 				struct v4l2_subdev_edid *edid)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun 	int i;
550*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
551*4882a593Smuzhiyun 	u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
554*4882a593Smuzhiyun 	/* Enable EDID shadow operation */
555*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8e, 0x07);
556*4882a593Smuzhiyun 	/* EDID data write start address */
557*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8f, 0x00);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	for (i = 0; i < edid_len; i++)
560*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x90, edid->edid[i]);
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8e, 0x02);
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun 
lt8619c_read_edid(struct v4l2_subdev * sd,u8 * edid,u32 len)565*4882a593Smuzhiyun static void lt8619c_read_edid(struct v4l2_subdev *sd, u8 *edid, u32 len)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
568*4882a593Smuzhiyun 	int i;
569*4882a593Smuzhiyun 	u32 val;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
572*4882a593Smuzhiyun 	/* Enable EDID shadow operation */
573*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8e, 0x07);
574*4882a593Smuzhiyun 	/* EDID data write start address */
575*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8f, 0x00);
576*4882a593Smuzhiyun 	for (i = 0; i < len; i++) {
577*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x90, &val);
578*4882a593Smuzhiyun 		edid[i] = val;
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x8e, 0x02);
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun 
lt8619c_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)583*4882a593Smuzhiyun static int lt8619c_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt8619c->detect_tx_5v_ctrl,
588*4882a593Smuzhiyun 			tx_5v_power_present(sd));
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun 
lt8619c_update_controls(struct v4l2_subdev * sd)591*4882a593Smuzhiyun static int lt8619c_update_controls(struct v4l2_subdev *sd)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun 	int ret = 0;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	ret = lt8619c_s_ctrl_detect_tx_5v(sd);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	return ret;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun 
enable_stream(struct v4l2_subdev * sd,bool enable)600*4882a593Smuzhiyun static void enable_stream(struct v4l2_subdev *sd, bool enable)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun 	if (enable)
603*4882a593Smuzhiyun 		v4l2_info(sd, "%s: stream on!\n", __func__);
604*4882a593Smuzhiyun 	else
605*4882a593Smuzhiyun 		v4l2_info(sd, "%s: stream off!\n", __func__);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
lt8619c_set_bt_tx_timing(struct v4l2_subdev * sd)608*4882a593Smuzhiyun static void lt8619c_set_bt_tx_timing(struct v4l2_subdev *sd)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
611*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
612*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings.bt;
613*4882a593Smuzhiyun 	u32 h_offset, v_offset, v_blank, htotal, vtotal;
614*4882a593Smuzhiyun 	u32 hact, hfp, hbp, hs, vact, vfp, vbp, vs;
615*4882a593Smuzhiyun 	u32 double_cnt = 1;
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	/* read timing from HDMI RX */
618*4882a593Smuzhiyun 	lt8619c_get_detected_timings(sd, &timings);
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	hact = bt->width;
621*4882a593Smuzhiyun 	vact = bt->height;
622*4882a593Smuzhiyun 	hfp = bt->hfrontporch;
623*4882a593Smuzhiyun 	hs = bt->hsync;
624*4882a593Smuzhiyun 	hbp = bt->hbackporch;
625*4882a593Smuzhiyun 	vfp = bt->vfrontporch;
626*4882a593Smuzhiyun 	vs = bt->vsync;
627*4882a593Smuzhiyun 	vbp = bt->vbackporch;
628*4882a593Smuzhiyun 	htotal = hs + hbp + hact + hfp;
629*4882a593Smuzhiyun 	vtotal = vs + vbp + vact + vfp;
630*4882a593Smuzhiyun 	h_offset = hbp + hs;
631*4882a593Smuzhiyun 	v_offset = vbp + vs;
632*4882a593Smuzhiyun 	v_blank = vtotal - vact;
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	if (bt->interlaced == V4L2_DV_INTERLACED) {
635*4882a593Smuzhiyun 		/* already *2 in lt8619c_get_detected_timings */
636*4882a593Smuzhiyun 		vact /= 2;
637*4882a593Smuzhiyun 		double_cnt = 2;
638*4882a593Smuzhiyun 		regmap_update_bits(lt8619c->reg_map, 0x60, IP_SEL_MASK,
639*4882a593Smuzhiyun 				INTERLACE_INDICATOR);
640*4882a593Smuzhiyun 	}
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	vact = vact * double_cnt;
643*4882a593Smuzhiyun 	vtotal = vtotal * double_cnt;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd,
646*4882a593Smuzhiyun 		"%s: act:%dx%d, total:%dx%d, h_offset:%d, v_offset:%d, v_blank:%d\n",
647*4882a593Smuzhiyun 		__func__, hact, vact, htotal, vtotal, h_offset, v_offset, v_blank);
648*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd,
649*4882a593Smuzhiyun 		"%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
650*4882a593Smuzhiyun 		__func__, hfp, hs, hbp, vfp, vs, vbp);
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	/* write timing to BT TX */
653*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
654*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x61, (h_offset >> 8) & 0xff);
655*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x62, h_offset & 0xff);
656*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x63, (hact >> 8) & 0xff);
657*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x64, hact & 0xff);
658*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x65, (htotal >> 8) & 0xff);
659*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x66, htotal & 0xff);
660*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x67, v_offset & 0xff);
661*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x68, v_blank & 0xff);
662*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x69, (vact >> 8) & 0xff);
663*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6a, vact & 0xff);
664*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6b, (vtotal >> 8) & 0xff);
665*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6c, vtotal & 0xff);
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun 
lt8619c_power_on(struct lt8619c * lt8619c)668*4882a593Smuzhiyun static void lt8619c_power_on(struct lt8619c *lt8619c)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun 	if (lt8619c->power_gpio) {
671*4882a593Smuzhiyun 		gpiod_set_value(lt8619c->power_gpio, 1);
672*4882a593Smuzhiyun 		usleep_range(1000, 1100);
673*4882a593Smuzhiyun 	}
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	if (lt8619c->reset_gpio) {
676*4882a593Smuzhiyun 		gpiod_set_value(lt8619c->reset_gpio, 1);
677*4882a593Smuzhiyun 		usleep_range(100*1000, 110*1000);
678*4882a593Smuzhiyun 		gpiod_set_value(lt8619c->reset_gpio, 0);
679*4882a593Smuzhiyun 		usleep_range(50*1000, 50*1000);
680*4882a593Smuzhiyun 	}
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun 
lt8619c_wait_for_signal_stable(struct v4l2_subdev * sd)683*4882a593Smuzhiyun static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
686*4882a593Smuzhiyun 	int i;
687*4882a593Smuzhiyun 	u32 val;
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
690*4882a593Smuzhiyun 	for (i = 0; i < WAIT_MAX_TIMES; i++) {
691*4882a593Smuzhiyun 		usleep_range(100*1000, 110*1000);
692*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x43, &val);
693*4882a593Smuzhiyun 		if (val & 0x80)
694*4882a593Smuzhiyun 			break;
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if (val & 0x80)
698*4882a593Smuzhiyun 		v4l2_info(sd, "tmds clk det success, wait cnt:%d!\n", i);
699*4882a593Smuzhiyun 	else
700*4882a593Smuzhiyun 		v4l2_err(sd, "tmds clk det failed!\n");
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	for (i = 0; i < WAIT_MAX_TIMES; i++) {
703*4882a593Smuzhiyun 		usleep_range(100*1000, 110*1000);
704*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x13, &val);
705*4882a593Smuzhiyun 		if (val & 0x01)
706*4882a593Smuzhiyun 			break;
707*4882a593Smuzhiyun 	}
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 	if (val & 0x01)
710*4882a593Smuzhiyun 		v4l2_info(sd, "Hsync stable, wait cnt:%d!\n", i);
711*4882a593Smuzhiyun 	else
712*4882a593Smuzhiyun 		v4l2_err(sd, "Hsync unstable!\n");
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	/* reset HDMI RX logic */
715*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
716*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x09, 0x7f);
717*4882a593Smuzhiyun 	usleep_range(10*1000, 11*1000);
718*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x09, 0xff);
719*4882a593Smuzhiyun 	usleep_range(100*1000, 110*1000);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	/* reset video check logic */
722*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x0c, 0xfb);
723*4882a593Smuzhiyun 	usleep_range(10*1000, 11*1000);
724*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x0c, 0xff);
725*4882a593Smuzhiyun 	usleep_range(100*1000, 110*1000);
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun 
LVDSPLL_Lock_Det(struct v4l2_subdev * sd)728*4882a593Smuzhiyun static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun 	int temp = 0;
731*4882a593Smuzhiyun 	u32 val;
732*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
735*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
736*4882a593Smuzhiyun 	usleep_range(5*1000, 5*1000);
737*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x0e, 0xff);
738*4882a593Smuzhiyun 	usleep_range(100*1000, 100*1000);
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
741*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x87, &val);
742*4882a593Smuzhiyun 	while ((val & 0x20) == 0x00) {
743*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
744*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
745*4882a593Smuzhiyun 		usleep_range(5*1000, 5*1000);
746*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0e, 0xff);
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
749*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x87, &val);
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 		temp++;
752*4882a593Smuzhiyun 		if (temp > 3) {
753*4882a593Smuzhiyun 			v4l2_err(sd, "lvds pll lock det failed!\n");
754*4882a593Smuzhiyun 			break;
755*4882a593Smuzhiyun 		}
756*4882a593Smuzhiyun 	}
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
LT8619C_phase_config(struct v4l2_subdev * sd)759*4882a593Smuzhiyun static void LT8619C_phase_config(struct v4l2_subdev *sd)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun 	u32 i, val;
762*4882a593Smuzhiyun 	int start = -1;
763*4882a593Smuzhiyun 	int end = -1;
764*4882a593Smuzhiyun 	u32 bt_clk_lag  = 0;
765*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
768*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x87, &val);
769*4882a593Smuzhiyun 	while ((val & 0x20) == 0x00) {
770*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
771*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
772*4882a593Smuzhiyun 		usleep_range(5*1000, 5*1000);
773*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0e, 0xff);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0a, 0x3f);
776*4882a593Smuzhiyun 		usleep_range(5*1000, 5*1000);
777*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x0a, 0x7f);
778*4882a593Smuzhiyun 		usleep_range(100*1000, 100*1000);
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
781*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x87, &val);
782*4882a593Smuzhiyun 	}
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(phase_num); i++) {
785*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
786*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
787*4882a593Smuzhiyun 		usleep_range(50*1000, 50*1000);
788*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x91, &val);
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun 		if (val == 0x05) {
791*4882a593Smuzhiyun 			bt_clk_lag = 1;
792*4882a593Smuzhiyun 			break;
793*4882a593Smuzhiyun 		} else if (val == 0x01) {
794*4882a593Smuzhiyun 			if (start == -1)
795*4882a593Smuzhiyun 				start = i;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 			end = i;
798*4882a593Smuzhiyun 		}
799*4882a593Smuzhiyun 	}
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	v4l2_info(sd, "%s: BT_clk_lag:%d, start:%d, end:%d!\n", __func__,
802*4882a593Smuzhiyun 			bt_clk_lag, start, end);
803*4882a593Smuzhiyun 	if (bt_clk_lag) {
804*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
805*4882a593Smuzhiyun 	} else {
806*4882a593Smuzhiyun 		if ((start != -1) && (end != -1) && (end >= start))
807*4882a593Smuzhiyun 			regmap_write(lt8619c->reg_map, 0xa2,
808*4882a593Smuzhiyun 					phase_num[start + (end - start) / 2]);
809*4882a593Smuzhiyun 		else
810*4882a593Smuzhiyun 			regmap_write(lt8619c->reg_map, 0xa2,
811*4882a593Smuzhiyun 					phase_num[ARRAY_SIZE(phase_num) - 1]);
812*4882a593Smuzhiyun 	}
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	/* Turn on BT output */
815*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0xa8, 0x0f);
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun 
sync_polarity_config(struct v4l2_subdev * sd)818*4882a593Smuzhiyun static void sync_polarity_config(struct v4l2_subdev *sd)
819*4882a593Smuzhiyun {
820*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
821*4882a593Smuzhiyun 	u32 val, adj;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	if (lt8619c->bt_tx_sync_pol == BT_TX_SYNC_POSITIVE) {
824*4882a593Smuzhiyun 		v4l2_info(sd, "%s: cfg h_vsync pol: POSITIVE\n", __func__);
825*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
826*4882a593Smuzhiyun 		regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
827*4882a593Smuzhiyun 				BT_TX_SYNC_POSITIVE);
828*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
829*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x17, &val);
830*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x05, &adj);
831*4882a593Smuzhiyun 		if ((val & RGOD_VID_VSPOL) != RGOD_VID_VSPOL) {
832*4882a593Smuzhiyun 			adj ^= RGD_VS_POL_ADJ_MASK;
833*4882a593Smuzhiyun 			regmap_update_bits(lt8619c->reg_map, 0x05,
834*4882a593Smuzhiyun 					RGD_VS_POL_ADJ_MASK, adj);
835*4882a593Smuzhiyun 		}
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 		if ((val & RGOD_VID_HSPOL) != RGOD_VID_HSPOL) {
838*4882a593Smuzhiyun 			adj ^= RGD_HS_POL_ADJ_MASK;
839*4882a593Smuzhiyun 			regmap_update_bits(lt8619c->reg_map, 0x05,
840*4882a593Smuzhiyun 					RGD_HS_POL_ADJ_MASK, adj);
841*4882a593Smuzhiyun 		}
842*4882a593Smuzhiyun 	} else {
843*4882a593Smuzhiyun 		v4l2_info(sd, "%s: cfg h_vsync pol: NEGATIVE\n", __func__);
844*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
845*4882a593Smuzhiyun 		regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
846*4882a593Smuzhiyun 				BT_TX_SYNC_NEGATIVE);
847*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
848*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x17, &val);
849*4882a593Smuzhiyun 		regmap_read(lt8619c->reg_map, 0x05, &adj);
850*4882a593Smuzhiyun 		if ((val & RGOD_VID_VSPOL) == RGOD_VID_VSPOL) {
851*4882a593Smuzhiyun 			adj ^= RGD_VS_POL_ADJ_MASK;
852*4882a593Smuzhiyun 			regmap_update_bits(lt8619c->reg_map, 0x05,
853*4882a593Smuzhiyun 					RGD_VS_POL_ADJ_MASK, adj);
854*4882a593Smuzhiyun 		}
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 		if ((val & RGOD_VID_HSPOL) == RGOD_VID_HSPOL) {
857*4882a593Smuzhiyun 			adj ^= RGD_HS_POL_ADJ_MASK;
858*4882a593Smuzhiyun 			regmap_update_bits(lt8619c->reg_map, 0x05,
859*4882a593Smuzhiyun 					RGD_HS_POL_ADJ_MASK, adj);
860*4882a593Smuzhiyun 		}
861*4882a593Smuzhiyun 	}
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun 
lt8619c_yuv_config(struct v4l2_subdev * sd)864*4882a593Smuzhiyun static void lt8619c_yuv_config(struct v4l2_subdev *sd)
865*4882a593Smuzhiyun {
866*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
867*4882a593Smuzhiyun 	u32 val, colorspace;
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	sync_polarity_config(sd);
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	/* softrest BT TX module */
872*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
873*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
874*4882a593Smuzhiyun 	usleep_range(10*1000, 10*1000);
875*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	/* ColorSpace convert */
878*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
879*4882a593Smuzhiyun 	regmap_read(lt8619c->reg_map, 0x71, &val);
880*4882a593Smuzhiyun 	colorspace = (val & 0x60) >> 5;
881*4882a593Smuzhiyun 	if (colorspace == 2) {
882*4882a593Smuzhiyun 		/* YCbCr444 convert YCbCr422 enable */
883*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
884*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x07, 0xf0);
885*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x52, 0x02 +
886*4882a593Smuzhiyun 				lt8619c->cp_convert_mode);
887*4882a593Smuzhiyun 		v4l2_info(sd, "%s: colorspace: yuv444\n", __func__);
888*4882a593Smuzhiyun 	} else if (colorspace == 1) {
889*4882a593Smuzhiyun 		/* yuv422 */
890*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
891*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x07, 0x80);
892*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x52, 0x00);
893*4882a593Smuzhiyun 		v4l2_info(sd, "%s: colorspace: yuv222\n", __func__);
894*4882a593Smuzhiyun 	} else {
895*4882a593Smuzhiyun 		/* RGB convert YCbCr422 enable */
896*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
897*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x07, 0xf0);
898*4882a593Smuzhiyun 		regmap_write(lt8619c->reg_map, 0x52, 0x0a +
899*4882a593Smuzhiyun 					lt8619c->cp_convert_mode);
900*4882a593Smuzhiyun 		v4l2_info(sd, "%s: colorspace: RGB\n", __func__);
901*4882a593Smuzhiyun 	}
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 	lt8619c_set_bt_tx_timing(sd);
904*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
905*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6d, lt8619c->yc_swap);
906*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, 0x6e, lt8619c->yuv_colordepth);
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	/* LVDS PLL soft reset */
909*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), 0);
910*4882a593Smuzhiyun 	usleep_range(50*1000, 50*1000);
911*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), BIT(1));
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun 	/* BT TX controller and afifo soft reset */
914*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
915*4882a593Smuzhiyun 	usleep_range(50*1000, 50*1000);
916*4882a593Smuzhiyun 	regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun 
lt8619c_initial_setup(struct v4l2_subdev * sd)919*4882a593Smuzhiyun static void lt8619c_initial_setup(struct v4l2_subdev *sd)
920*4882a593Smuzhiyun {
921*4882a593Smuzhiyun 	static struct v4l2_dv_timings default_timing =
922*4882a593Smuzhiyun 		V4L2_DV_BT_CEA_640X480P59_94;
923*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
924*4882a593Smuzhiyun 	struct v4l2_subdev_edid def_edid;
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	def_edid.pad = 0;
927*4882a593Smuzhiyun 	def_edid.start_block = 0;
928*4882a593Smuzhiyun 	def_edid.blocks = 2;
929*4882a593Smuzhiyun 	def_edid.edid = edid_init_data;
930*4882a593Smuzhiyun 	lt8619c->enable_hdcp = false;
931*4882a593Smuzhiyun 	lt8619c->cp_convert_mode = CP_CONVERT_MODE;
932*4882a593Smuzhiyun 	lt8619c->yuv_colordepth = YUV_COLORDEPTH;
933*4882a593Smuzhiyun 	lt8619c->bt_tx_sync_pol = BT_TX_SYNC_POL;
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun 	if (lt8619c->yuv_output_mode == BT656_OUTPUT) {
936*4882a593Smuzhiyun 		lt8619c->yc_swap = YC_SWAP_DIS;
937*4882a593Smuzhiyun 		lt8619c->BT656_double_clk_en = true;
938*4882a593Smuzhiyun 	} else {
939*4882a593Smuzhiyun 		lt8619c->yc_swap = YC_SWAP_EN;
940*4882a593Smuzhiyun 		lt8619c->BT656_double_clk_en = false;
941*4882a593Smuzhiyun 	}
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	lt8619c_set_hpd(sd, 0);
944*4882a593Smuzhiyun 	lt8619c_write_edid(sd, &def_edid);
945*4882a593Smuzhiyun 	lt8619c->edid_blocks_written = def_edid.blocks;
946*4882a593Smuzhiyun 	lt8619c_set_hdmi_hdcp(sd, lt8619c->enable_hdcp);
947*4882a593Smuzhiyun 	lt8619c_mode_config(sd);
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	if (tx_5v_power_present(sd)) {
950*4882a593Smuzhiyun 		lt8619c_set_hpd(sd, 1);
951*4882a593Smuzhiyun 		lt8619c_config_all(sd);
952*4882a593Smuzhiyun 		/* monitor resolution after 100ms */
953*4882a593Smuzhiyun 		schedule_delayed_work(&lt8619c->delayed_work_monitor_resolution,
954*4882a593Smuzhiyun 				HZ / 10);
955*4882a593Smuzhiyun 	} else {
956*4882a593Smuzhiyun 		lt8619c_s_dv_timings(sd, &default_timing);
957*4882a593Smuzhiyun 	}
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: init ok\n", __func__);
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun 
lt8619c_format_change(struct v4l2_subdev * sd)962*4882a593Smuzhiyun static void lt8619c_format_change(struct v4l2_subdev *sd)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
965*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
966*4882a593Smuzhiyun 	const struct v4l2_event lt8619c_ev_fmt = {
967*4882a593Smuzhiyun 		.type = V4L2_EVENT_SOURCE_CHANGE,
968*4882a593Smuzhiyun 		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
969*4882a593Smuzhiyun 	};
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	lt8619c_get_detected_timings(sd, &timings);
972*4882a593Smuzhiyun 	if (!v4l2_match_dv_timings(&lt8619c->timings, &timings, 0, false)) {
973*4882a593Smuzhiyun 		/* automatically set timing rather than set by userspace */
974*4882a593Smuzhiyun 		lt8619c_s_dv_timings(sd, &timings);
975*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name,
976*4882a593Smuzhiyun 			"lt8619c_format_change: New format: ", &timings, false);
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	}
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	if (sd->devnode)
981*4882a593Smuzhiyun 		v4l2_subdev_notify_event(sd, &lt8619c_ev_fmt);
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun 
lt8619c_timing_changed(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)984*4882a593Smuzhiyun static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
985*4882a593Smuzhiyun 		struct v4l2_dv_timings *timings)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
988*4882a593Smuzhiyun 	struct v4l2_bt_timings *new_bt = &timings->bt;
989*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &lt8619c->timings.bt;
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	if ((bt->width != new_bt->width) |
992*4882a593Smuzhiyun 	    (bt->height != new_bt->height) |
993*4882a593Smuzhiyun 	    (abs(bt->hfrontporch - new_bt->hfrontporch) > 1) |
994*4882a593Smuzhiyun 	    (abs(bt->hsync - new_bt->hsync) > 1) |
995*4882a593Smuzhiyun 	    (abs(bt->hbackporch - new_bt->hbackporch) > 1) |
996*4882a593Smuzhiyun 	    (abs(bt->vfrontporch - new_bt->vfrontporch) > 1) |
997*4882a593Smuzhiyun 	    (abs(bt->vsync - new_bt->vsync) > 1) |
998*4882a593Smuzhiyun 	    (abs(bt->vbackporch - new_bt->vbackporch) > 1) |
999*4882a593Smuzhiyun 	    (abs(bt->pixelclock - new_bt->pixelclock) > 5000)) {
1000*4882a593Smuzhiyun 		v4l2_info(sd, "%s: timing changed!\n", __func__);
1001*4882a593Smuzhiyun 		return true;
1002*4882a593Smuzhiyun 	}
1003*4882a593Smuzhiyun 
1004*4882a593Smuzhiyun 	return false;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun 
lt8619c_rcv_supported_res(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1007*4882a593Smuzhiyun static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
1008*4882a593Smuzhiyun 					struct v4l2_dv_timings *timings)
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun 	u32 i;
1011*4882a593Smuzhiyun 	u32 hact, vact, htotal, vtotal;
1012*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	hact = bt->width;
1015*4882a593Smuzhiyun 	vact = bt->height;
1016*4882a593Smuzhiyun 	htotal = bt->hsync + bt->hbackporch + hact + bt->hfrontporch;
1017*4882a593Smuzhiyun 	vtotal = bt->vsync + bt->vbackporch + vact + bt->vfrontporch;
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1020*4882a593Smuzhiyun 		if ((supported_modes[i].width == hact) &&
1021*4882a593Smuzhiyun 		    (supported_modes[i].height == vact)) {
1022*4882a593Smuzhiyun 			break;
1023*4882a593Smuzhiyun 		}
1024*4882a593Smuzhiyun 	}
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(supported_modes)) {
1027*4882a593Smuzhiyun 		v4l2_err(sd, "%s do not support res act: %dx%d, total: %dx%d\n",
1028*4882a593Smuzhiyun 				__func__, hact, vact, htotal, vtotal);
1029*4882a593Smuzhiyun 		return false;
1030*4882a593Smuzhiyun 	}
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	if (bt->pixelclock < 25000000) {
1033*4882a593Smuzhiyun 		v4l2_err(sd, "%s pixclk: %llu, err!\n", __func__, bt->pixelclock);
1034*4882a593Smuzhiyun 		return false;
1035*4882a593Smuzhiyun 	}
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	return true;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
lt8619c_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1040*4882a593Smuzhiyun static int lt8619c_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1041*4882a593Smuzhiyun 				    struct v4l2_event_subscription *sub)
1042*4882a593Smuzhiyun {
1043*4882a593Smuzhiyun 	switch (sub->type) {
1044*4882a593Smuzhiyun 	case V4L2_EVENT_SOURCE_CHANGE:
1045*4882a593Smuzhiyun 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1046*4882a593Smuzhiyun 	case V4L2_EVENT_CTRL:
1047*4882a593Smuzhiyun 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1048*4882a593Smuzhiyun 	default:
1049*4882a593Smuzhiyun 		return -EINVAL;
1050*4882a593Smuzhiyun 	}
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun 
lt8619c_g_input_status(struct v4l2_subdev * sd,u32 * status)1053*4882a593Smuzhiyun static int lt8619c_g_input_status(struct v4l2_subdev *sd, u32 *status)
1054*4882a593Smuzhiyun {
1055*4882a593Smuzhiyun 	*status = 0;
1056*4882a593Smuzhiyun 	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	return 0;
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun 
lt8619c_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1063*4882a593Smuzhiyun static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
1064*4882a593Smuzhiyun 				 struct v4l2_dv_timings *timings)
1065*4882a593Smuzhiyun {
1066*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	if (!timings)
1069*4882a593Smuzhiyun 		return -EINVAL;
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	if (debug)
1072*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name, "lt8619c_s_dv_timings: ",
1073*4882a593Smuzhiyun 				timings, false);
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	if (v4l2_match_dv_timings(&lt8619c->timings, timings, 0, false)) {
1076*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1077*4882a593Smuzhiyun 		return 0;
1078*4882a593Smuzhiyun 	}
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings, &lt8619c_timings_cap, NULL, NULL)) {
1081*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1082*4882a593Smuzhiyun 		return -ERANGE;
1083*4882a593Smuzhiyun 	}
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	lt8619c->timings = *timings;
1086*4882a593Smuzhiyun 	enable_stream(sd, false);
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	return 0;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun 
lt8619c_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1091*4882a593Smuzhiyun static int lt8619c_g_dv_timings(struct v4l2_subdev *sd,
1092*4882a593Smuzhiyun 				 struct v4l2_dv_timings *timings)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	*timings = lt8619c->timings;
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	return 0;
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun 
lt8619c_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1101*4882a593Smuzhiyun static int lt8619c_enum_dv_timings(struct v4l2_subdev *sd,
1102*4882a593Smuzhiyun 				    struct v4l2_enum_dv_timings *timings)
1103*4882a593Smuzhiyun {
1104*4882a593Smuzhiyun 	if (timings->pad != 0)
1105*4882a593Smuzhiyun 		return -EINVAL;
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	return v4l2_enum_dv_timings_cap(timings, &lt8619c_timings_cap, NULL, NULL);
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun 
lt8619c_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1110*4882a593Smuzhiyun static int lt8619c_query_dv_timings(struct v4l2_subdev *sd,
1111*4882a593Smuzhiyun 		struct v4l2_dv_timings *timings)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun 	int ret;
1114*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
1117*4882a593Smuzhiyun 	ret = lt8619c_get_detected_timings(sd, timings);
1118*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
1119*4882a593Smuzhiyun 	if (ret)
1120*4882a593Smuzhiyun 		return ret;
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	if (debug)
1123*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name, "lt8619c_query_dv_timings: ",
1124*4882a593Smuzhiyun 				timings, false);
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings, &lt8619c_timings_cap, NULL, NULL)) {
1127*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1128*4882a593Smuzhiyun 		return -ERANGE;
1129*4882a593Smuzhiyun 	}
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 	return 0;
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun 
lt8619c_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1134*4882a593Smuzhiyun static int lt8619c_dv_timings_cap(struct v4l2_subdev *sd,
1135*4882a593Smuzhiyun 		struct v4l2_dv_timings_cap *cap)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun 	if (cap->pad != 0)
1138*4882a593Smuzhiyun 		return -EINVAL;
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	*cap = lt8619c_timings_cap;
1141*4882a593Smuzhiyun 
1142*4882a593Smuzhiyun 	return 0;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun 
lt8619c_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1145*4882a593Smuzhiyun static int lt8619c_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1146*4882a593Smuzhiyun 			     struct v4l2_mbus_config *cfg)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	cfg->type = V4L2_MBUS_BT656;
1151*4882a593Smuzhiyun 	if (lt8619c->clk_ddrmode_en) {
1152*4882a593Smuzhiyun 		cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
1153*4882a593Smuzhiyun 			V4L2_MBUS_PCLK_SAMPLE_RISING |
1154*4882a593Smuzhiyun 			V4L2_MBUS_PCLK_SAMPLE_FALLING;
1155*4882a593Smuzhiyun 	} else {
1156*4882a593Smuzhiyun 		cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
1157*4882a593Smuzhiyun 			V4L2_MBUS_PCLK_SAMPLE_RISING;
1158*4882a593Smuzhiyun 	}
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	return 0;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun 
lt8619c_s_stream(struct v4l2_subdev * sd,int enable)1163*4882a593Smuzhiyun static int lt8619c_s_stream(struct v4l2_subdev *sd, int enable)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun 	enable_stream(sd, enable);
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun 	return 0;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun 
lt8619c_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1170*4882a593Smuzhiyun static int lt8619c_enum_mbus_code(struct v4l2_subdev *sd,
1171*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
1172*4882a593Smuzhiyun 		struct v4l2_subdev_mbus_code_enum *code)
1173*4882a593Smuzhiyun {
1174*4882a593Smuzhiyun 	switch (code->index) {
1175*4882a593Smuzhiyun 	case 0:
1176*4882a593Smuzhiyun 		code->code = MEDIA_BUS_FMT_UYVY8_2X8;
1177*4882a593Smuzhiyun 		break;
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	default:
1180*4882a593Smuzhiyun 		return -EINVAL;
1181*4882a593Smuzhiyun 	}
1182*4882a593Smuzhiyun 	return 0;
1183*4882a593Smuzhiyun }
1184*4882a593Smuzhiyun 
lt8619c_get_ctrl(struct v4l2_ctrl * ctrl)1185*4882a593Smuzhiyun static int lt8619c_get_ctrl(struct v4l2_ctrl *ctrl)
1186*4882a593Smuzhiyun {
1187*4882a593Smuzhiyun 	int ret = -1;
1188*4882a593Smuzhiyun 	struct lt8619c *lt8619c = container_of(ctrl->handler, struct lt8619c, hdl);
1189*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &(lt8619c->sd);
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
1192*4882a593Smuzhiyun 		ret = tx_5v_power_present(sd);
1193*4882a593Smuzhiyun 		*ctrl->p_new.p_s32 = ret;
1194*4882a593Smuzhiyun 	}
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	return ret;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun 
lt8619c_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1199*4882a593Smuzhiyun static int lt8619c_enum_frame_sizes(struct v4l2_subdev *sd,
1200*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
1201*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
1206*4882a593Smuzhiyun 		return -EINVAL;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
1209*4882a593Smuzhiyun 		return -EINVAL;
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	fse->min_width  = supported_modes[fse->index].width;
1212*4882a593Smuzhiyun 	fse->max_width  = supported_modes[fse->index].width;
1213*4882a593Smuzhiyun 	fse->max_height = supported_modes[fse->index].height;
1214*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun 	return 0;
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun 
lt8619c_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1219*4882a593Smuzhiyun static int lt8619c_enum_frame_interval(struct v4l2_subdev *sd,
1220*4882a593Smuzhiyun 				       struct v4l2_subdev_pad_config *cfg,
1221*4882a593Smuzhiyun 				       struct v4l2_subdev_frame_interval_enum *fie)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun 	if (fie->index >= ARRAY_SIZE(supported_modes))
1224*4882a593Smuzhiyun 		return -EINVAL;
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	fie->code = MEDIA_BUS_FMT_UYVY8_2X8;
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 	fie->width = supported_modes[fie->index].width;
1229*4882a593Smuzhiyun 	fie->height = supported_modes[fie->index].height;
1230*4882a593Smuzhiyun 	fie->interval = supported_modes[fie->index].max_fps;
1231*4882a593Smuzhiyun 	return 0;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun 
lt8619c_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1234*4882a593Smuzhiyun static int lt8619c_get_fmt(struct v4l2_subdev *sd,
1235*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
1236*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
1237*4882a593Smuzhiyun {
1238*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1239*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
1242*4882a593Smuzhiyun 	format->format.code = lt8619c->mbus_fmt_code;
1243*4882a593Smuzhiyun 	format->format.width = lt8619c->timings.bt.width;
1244*4882a593Smuzhiyun 	format->format.height = lt8619c->timings.bt.height;
1245*4882a593Smuzhiyun 	format->format.colorspace = V4L2_COLORSPACE_SRGB;
1246*4882a593Smuzhiyun 	if (bt->interlaced == V4L2_DV_INTERLACED)
1247*4882a593Smuzhiyun 		format->format.field = V4L2_FIELD_INTERLACED;
1248*4882a593Smuzhiyun 	else
1249*4882a593Smuzhiyun 		format->format.field = V4L2_FIELD_NONE;
1250*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
1251*4882a593Smuzhiyun 
1252*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "fmt code:%d, w:%d, h:%d, field:%s, cosp:%d\n",
1253*4882a593Smuzhiyun 			format->format.code,
1254*4882a593Smuzhiyun 			format->format.width,
1255*4882a593Smuzhiyun 			format->format.height,
1256*4882a593Smuzhiyun 			(format->format.field == V4L2_FIELD_INTERLACED) ?
1257*4882a593Smuzhiyun 				"I" : "P",
1258*4882a593Smuzhiyun 			format->format.colorspace);
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun 	return 0;
1261*4882a593Smuzhiyun }
1262*4882a593Smuzhiyun 
lt8619c_get_reso_dist(const struct lt8619c_mode * mode,struct v4l2_mbus_framefmt * framefmt)1263*4882a593Smuzhiyun static int lt8619c_get_reso_dist(const struct lt8619c_mode *mode,
1264*4882a593Smuzhiyun 				 struct v4l2_mbus_framefmt *framefmt)
1265*4882a593Smuzhiyun {
1266*4882a593Smuzhiyun 	return abs(mode->width - framefmt->width) +
1267*4882a593Smuzhiyun 	       abs(mode->height - framefmt->height);
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun static const struct lt8619c_mode *
lt8619c_find_best_fit(struct v4l2_subdev_format * fmt)1271*4882a593Smuzhiyun lt8619c_find_best_fit(struct v4l2_subdev_format *fmt)
1272*4882a593Smuzhiyun {
1273*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1274*4882a593Smuzhiyun 	int dist;
1275*4882a593Smuzhiyun 	int cur_best_fit = 0;
1276*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
1277*4882a593Smuzhiyun 	unsigned int i;
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1280*4882a593Smuzhiyun 		dist = lt8619c_get_reso_dist(&supported_modes[i], framefmt);
1281*4882a593Smuzhiyun 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1282*4882a593Smuzhiyun 			cur_best_fit_dist = dist;
1283*4882a593Smuzhiyun 			cur_best_fit = i;
1284*4882a593Smuzhiyun 		}
1285*4882a593Smuzhiyun 	}
1286*4882a593Smuzhiyun 
1287*4882a593Smuzhiyun 	return &supported_modes[cur_best_fit];
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun 
lt8619c_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1290*4882a593Smuzhiyun static int lt8619c_set_fmt(struct v4l2_subdev *sd,
1291*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
1292*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
1293*4882a593Smuzhiyun {
1294*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1295*4882a593Smuzhiyun 	const struct lt8619c_mode *mode;
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	/* is overwritten by get_fmt */
1298*4882a593Smuzhiyun 	u32 code = format->format.code;
1299*4882a593Smuzhiyun 	int ret = lt8619c_get_fmt(sd, cfg, format);
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	format->format.code = code;
1302*4882a593Smuzhiyun 
1303*4882a593Smuzhiyun 	if (ret)
1304*4882a593Smuzhiyun 		return ret;
1305*4882a593Smuzhiyun 
1306*4882a593Smuzhiyun 	switch (code) {
1307*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_UYVY8_2X8:
1308*4882a593Smuzhiyun 		break;
1309*4882a593Smuzhiyun 	default:
1310*4882a593Smuzhiyun 		return -EINVAL;
1311*4882a593Smuzhiyun 	}
1312*4882a593Smuzhiyun 
1313*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1314*4882a593Smuzhiyun 		return 0;
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	lt8619c->mbus_fmt_code = format->format.code;
1317*4882a593Smuzhiyun 	mode = lt8619c_find_best_fit(format);
1318*4882a593Smuzhiyun 	lt8619c->cur_mode = mode;
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	enable_stream(sd, false);
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	return 0;
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun 
lt8619c_g_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1325*4882a593Smuzhiyun static int lt8619c_g_edid(struct v4l2_subdev *sd,
1326*4882a593Smuzhiyun 		struct v4l2_subdev_edid *edid)
1327*4882a593Smuzhiyun {
1328*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1329*4882a593Smuzhiyun 
1330*4882a593Smuzhiyun 	memset(edid->reserved, 0, sizeof(edid->reserved));
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun 	if (edid->pad != 0)
1333*4882a593Smuzhiyun 		return -EINVAL;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	if (edid->start_block == 0 && edid->blocks == 0) {
1336*4882a593Smuzhiyun 		edid->blocks = lt8619c->edid_blocks_written;
1337*4882a593Smuzhiyun 		return 0;
1338*4882a593Smuzhiyun 	}
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	if (lt8619c->edid_blocks_written == 0)
1341*4882a593Smuzhiyun 		return -ENODATA;
1342*4882a593Smuzhiyun 
1343*4882a593Smuzhiyun 	if (edid->start_block >= lt8619c->edid_blocks_written ||
1344*4882a593Smuzhiyun 			edid->blocks == 0)
1345*4882a593Smuzhiyun 		return -EINVAL;
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (edid->start_block + edid->blocks > lt8619c->edid_blocks_written)
1348*4882a593Smuzhiyun 		edid->blocks = lt8619c->edid_blocks_written - edid->start_block;
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 	lt8619c_read_edid(sd, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 	return 0;
1353*4882a593Smuzhiyun }
1354*4882a593Smuzhiyun 
lt8619c_s_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1355*4882a593Smuzhiyun static int lt8619c_s_edid(struct v4l2_subdev *sd,
1356*4882a593Smuzhiyun 				struct v4l2_subdev_edid *edid)
1357*4882a593Smuzhiyun {
1358*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1361*4882a593Smuzhiyun 		 __func__, edid->pad, edid->start_block, edid->blocks);
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	memset(edid->reserved, 0, sizeof(edid->reserved));
1364*4882a593Smuzhiyun 
1365*4882a593Smuzhiyun 	if (edid->pad != 0)
1366*4882a593Smuzhiyun 		return -EINVAL;
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	if (edid->start_block != 0)
1369*4882a593Smuzhiyun 		return -EINVAL;
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1372*4882a593Smuzhiyun 		edid->blocks = EDID_NUM_BLOCKS_MAX;
1373*4882a593Smuzhiyun 		return -E2BIG;
1374*4882a593Smuzhiyun 	}
1375*4882a593Smuzhiyun 
1376*4882a593Smuzhiyun 	lt8619c_set_hpd(sd, 0);
1377*4882a593Smuzhiyun 
1378*4882a593Smuzhiyun 	if (edid->blocks == 0) {
1379*4882a593Smuzhiyun 		lt8619c->edid_blocks_written = 0;
1380*4882a593Smuzhiyun 		return 0;
1381*4882a593Smuzhiyun 	}
1382*4882a593Smuzhiyun 
1383*4882a593Smuzhiyun 	lt8619c_write_edid(sd, edid);
1384*4882a593Smuzhiyun 	lt8619c->edid_blocks_written = edid->blocks;
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun 	if (tx_5v_power_present(sd))
1387*4882a593Smuzhiyun 		lt8619c_set_hpd(sd, 1);
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	return 0;
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun 
lt8619c_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1392*4882a593Smuzhiyun static int lt8619c_g_frame_interval(struct v4l2_subdev *sd,
1393*4882a593Smuzhiyun 				    struct v4l2_subdev_frame_interval *fi)
1394*4882a593Smuzhiyun {
1395*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1396*4882a593Smuzhiyun 	const struct lt8619c_mode *mode = lt8619c->cur_mode;
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
1399*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
1400*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
1401*4882a593Smuzhiyun 
1402*4882a593Smuzhiyun 	return 0;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun 
lt8619c_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)1405*4882a593Smuzhiyun static int lt8619c_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1408*4882a593Smuzhiyun 
1409*4882a593Smuzhiyun 	if (lt8619c->yuv_output_mode == BT656_OUTPUT)
1410*4882a593Smuzhiyun 		*std = V4L2_STD_PAL;
1411*4882a593Smuzhiyun 	else
1412*4882a593Smuzhiyun 		*std = V4L2_STD_ATSC;
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	return 0;
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun 
lt8619c_get_module_inf(struct lt8619c * lt8619c,struct rkmodule_inf * inf)1417*4882a593Smuzhiyun static void lt8619c_get_module_inf(struct lt8619c *lt8619c,
1418*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
1421*4882a593Smuzhiyun 	strscpy(inf->base.sensor, LT8619C_NAME, sizeof(inf->base.sensor));
1422*4882a593Smuzhiyun 	strscpy(inf->base.module, lt8619c->module_name,
1423*4882a593Smuzhiyun 		sizeof(inf->base.module));
1424*4882a593Smuzhiyun 	strscpy(inf->base.lens, lt8619c->len_name, sizeof(inf->base.lens));
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun 
1427*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
lt8619c_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1428*4882a593Smuzhiyun static int lt8619c_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1429*4882a593Smuzhiyun {
1430*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1431*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
1432*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1433*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1434*4882a593Smuzhiyun 	const struct lt8619c_mode *def_mode = &supported_modes[0];
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun 	mutex_lock(&lt8619c->confctl_mutex);
1437*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1438*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1439*4882a593Smuzhiyun 	try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
1440*4882a593Smuzhiyun 	if (bt->interlaced == V4L2_DV_INTERLACED)
1441*4882a593Smuzhiyun 		try_fmt->field = V4L2_FIELD_INTERLACED;
1442*4882a593Smuzhiyun 	else
1443*4882a593Smuzhiyun 		try_fmt->field = V4L2_FIELD_NONE;
1444*4882a593Smuzhiyun 	mutex_unlock(&lt8619c->confctl_mutex);
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun 	return 0;
1447*4882a593Smuzhiyun }
1448*4882a593Smuzhiyun #endif
1449*4882a593Smuzhiyun 
lt8619c_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1450*4882a593Smuzhiyun static long lt8619c_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1451*4882a593Smuzhiyun {
1452*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1453*4882a593Smuzhiyun 	long ret = 0;
1454*4882a593Smuzhiyun 
1455*4882a593Smuzhiyun 	switch (cmd) {
1456*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1457*4882a593Smuzhiyun 		lt8619c_get_module_inf(lt8619c, (struct rkmodule_inf *)arg);
1458*4882a593Smuzhiyun 		break;
1459*4882a593Smuzhiyun 	default:
1460*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1461*4882a593Smuzhiyun 		break;
1462*4882a593Smuzhiyun 	}
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	return ret;
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
lt8619c_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1468*4882a593Smuzhiyun static long lt8619c_compat_ioctl32(struct v4l2_subdev *sd,
1469*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
1470*4882a593Smuzhiyun {
1471*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
1472*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
1473*4882a593Smuzhiyun 	long ret;
1474*4882a593Smuzhiyun 
1475*4882a593Smuzhiyun 	switch (cmd) {
1476*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1477*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1478*4882a593Smuzhiyun 		if (!inf) {
1479*4882a593Smuzhiyun 			ret = -ENOMEM;
1480*4882a593Smuzhiyun 			return ret;
1481*4882a593Smuzhiyun 		}
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun 		ret = lt8619c_ioctl(sd, cmd, inf);
1484*4882a593Smuzhiyun 		if (!ret) {
1485*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
1486*4882a593Smuzhiyun 			if (ret)
1487*4882a593Smuzhiyun 				ret = -EFAULT;
1488*4882a593Smuzhiyun 		}
1489*4882a593Smuzhiyun 		kfree(inf);
1490*4882a593Smuzhiyun 		break;
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	default:
1493*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1494*4882a593Smuzhiyun 		break;
1495*4882a593Smuzhiyun 	}
1496*4882a593Smuzhiyun 
1497*4882a593Smuzhiyun 	return ret;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun #endif
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun static const struct v4l2_ctrl_ops lt8619c_ctrl_ops = {
1502*4882a593Smuzhiyun 	.g_volatile_ctrl = lt8619c_get_ctrl,
1503*4882a593Smuzhiyun };
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1506*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops lt8619c_subdev_internal_ops = {
1507*4882a593Smuzhiyun 	.open = lt8619c_open,
1508*4882a593Smuzhiyun };
1509*4882a593Smuzhiyun #endif
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops lt8619c_core_ops = {
1512*4882a593Smuzhiyun 	.subscribe_event = lt8619c_subscribe_event,
1513*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1514*4882a593Smuzhiyun 	.ioctl = lt8619c_ioctl,
1515*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1516*4882a593Smuzhiyun 	.compat_ioctl32 = lt8619c_compat_ioctl32,
1517*4882a593Smuzhiyun #endif
1518*4882a593Smuzhiyun };
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops lt8619c_video_ops = {
1521*4882a593Smuzhiyun 	.g_input_status = lt8619c_g_input_status,
1522*4882a593Smuzhiyun 	.s_dv_timings = lt8619c_s_dv_timings,
1523*4882a593Smuzhiyun 	.g_dv_timings = lt8619c_g_dv_timings,
1524*4882a593Smuzhiyun 	.query_dv_timings = lt8619c_query_dv_timings,
1525*4882a593Smuzhiyun 	.s_stream = lt8619c_s_stream,
1526*4882a593Smuzhiyun 	.g_frame_interval = lt8619c_g_frame_interval,
1527*4882a593Smuzhiyun 	.querystd = lt8619c_querystd,
1528*4882a593Smuzhiyun };
1529*4882a593Smuzhiyun 
1530*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops lt8619c_pad_ops = {
1531*4882a593Smuzhiyun 	.enum_mbus_code = lt8619c_enum_mbus_code,
1532*4882a593Smuzhiyun 	.enum_frame_size = lt8619c_enum_frame_sizes,
1533*4882a593Smuzhiyun 	.enum_frame_interval = lt8619c_enum_frame_interval,
1534*4882a593Smuzhiyun 	.set_fmt = lt8619c_set_fmt,
1535*4882a593Smuzhiyun 	.get_fmt = lt8619c_get_fmt,
1536*4882a593Smuzhiyun 	.get_edid = lt8619c_g_edid,
1537*4882a593Smuzhiyun 	.set_edid = lt8619c_s_edid,
1538*4882a593Smuzhiyun 	.enum_dv_timings = lt8619c_enum_dv_timings,
1539*4882a593Smuzhiyun 	.dv_timings_cap = lt8619c_dv_timings_cap,
1540*4882a593Smuzhiyun 	.get_mbus_config = lt8619c_g_mbus_config,
1541*4882a593Smuzhiyun };
1542*4882a593Smuzhiyun 
1543*4882a593Smuzhiyun static const struct v4l2_subdev_ops lt8619c_ops = {
1544*4882a593Smuzhiyun 	.core = &lt8619c_core_ops,
1545*4882a593Smuzhiyun 	.video = &lt8619c_video_ops,
1546*4882a593Smuzhiyun 	.pad = &lt8619c_pad_ops,
1547*4882a593Smuzhiyun };
1548*4882a593Smuzhiyun 
plugin_detect_irq(int irq,void * dev_id)1549*4882a593Smuzhiyun static irqreturn_t plugin_detect_irq(int irq, void *dev_id)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun 	struct lt8619c *lt8619c = dev_id;
1552*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt8619c->sd;
1553*4882a593Smuzhiyun 
1554*4882a593Smuzhiyun 	/* enable hpd after 100ms */
1555*4882a593Smuzhiyun 	schedule_delayed_work(&lt8619c->delayed_work_enable_hotplug, HZ / 10);
1556*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: plug change!\n", __func__);
1557*4882a593Smuzhiyun 	tx_5v_power_present(sd);
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun 	return IRQ_HANDLED;
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun 
lt8619c_parse_of(struct lt8619c * lt8619c)1562*4882a593Smuzhiyun static int lt8619c_parse_of(struct lt8619c *lt8619c)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun 	struct device *dev = &lt8619c->i2c_client->dev;
1565*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1566*4882a593Smuzhiyun 	int err;
1567*4882a593Smuzhiyun 
1568*4882a593Smuzhiyun 	lt8619c->hpd_output_inverted = of_property_read_bool(node,
1569*4882a593Smuzhiyun 				"hpd-output-inverted");
1570*4882a593Smuzhiyun 	err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1571*4882a593Smuzhiyun 				   &lt8619c->module_index);
1572*4882a593Smuzhiyun 	err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1573*4882a593Smuzhiyun 				       &lt8619c->module_facing);
1574*4882a593Smuzhiyun 	err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1575*4882a593Smuzhiyun 				       &lt8619c->module_name);
1576*4882a593Smuzhiyun 	err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1577*4882a593Smuzhiyun 				       &lt8619c->len_name);
1578*4882a593Smuzhiyun 	if (err) {
1579*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1580*4882a593Smuzhiyun 		return -EINVAL;
1581*4882a593Smuzhiyun 	}
1582*4882a593Smuzhiyun 
1583*4882a593Smuzhiyun 	lt8619c->xvclk = devm_clk_get(dev, "xvclk");
1584*4882a593Smuzhiyun 	if (IS_ERR(lt8619c->xvclk)) {
1585*4882a593Smuzhiyun 		dev_err(dev, "Failed to get xvclk\n");
1586*4882a593Smuzhiyun 		return -EINVAL;
1587*4882a593Smuzhiyun 	}
1588*4882a593Smuzhiyun 
1589*4882a593Smuzhiyun 	err = clk_prepare_enable(lt8619c->xvclk);
1590*4882a593Smuzhiyun 	if (err) {
1591*4882a593Smuzhiyun 		dev_err(dev, "Failed! to enable xvclk\n");
1592*4882a593Smuzhiyun 		return err;
1593*4882a593Smuzhiyun 	}
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 	lt8619c->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
1596*4882a593Smuzhiyun 	if (IS_ERR(lt8619c->power_gpio)) {
1597*4882a593Smuzhiyun 		dev_err(dev, "failed to get power gpio\n");
1598*4882a593Smuzhiyun 		err = PTR_ERR(lt8619c->power_gpio);
1599*4882a593Smuzhiyun 		goto disable_clk;
1600*4882a593Smuzhiyun 	}
1601*4882a593Smuzhiyun 	lt8619c->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1602*4882a593Smuzhiyun 	if (IS_ERR(lt8619c->reset_gpio)) {
1603*4882a593Smuzhiyun 		dev_err(dev, "failed to get reset gpio\n");
1604*4882a593Smuzhiyun 		err = PTR_ERR(lt8619c->reset_gpio);
1605*4882a593Smuzhiyun 		goto disable_clk;
1606*4882a593Smuzhiyun 	}
1607*4882a593Smuzhiyun 
1608*4882a593Smuzhiyun 	lt8619c->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1609*4882a593Smuzhiyun 			GPIOD_IN);
1610*4882a593Smuzhiyun 	if (IS_ERR(lt8619c->plugin_det_gpio)) {
1611*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin_det gpio\n");
1612*4882a593Smuzhiyun 		err = PTR_ERR(lt8619c->plugin_det_gpio);
1613*4882a593Smuzhiyun 		goto disable_clk;
1614*4882a593Smuzhiyun 	}
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun 	if (of_property_read_u32(node, RK_CAMERA_MODULE_DUAL_EDGE,
1617*4882a593Smuzhiyun 					&lt8619c->clk_ddrmode_en)) {
1618*4882a593Smuzhiyun 		lt8619c->clk_ddrmode_en = LT8619C_DEFAULT_DUAL_EDGE;
1619*4882a593Smuzhiyun 		dev_warn(dev, "can not get module %s from dts, use default(%d)!\n",
1620*4882a593Smuzhiyun 			RK_CAMERA_MODULE_DUAL_EDGE, LT8619C_DEFAULT_DUAL_EDGE);
1621*4882a593Smuzhiyun 	} else {
1622*4882a593Smuzhiyun 		dev_info(dev, "get module %s from dts, dual_edge(%d)!\n",
1623*4882a593Smuzhiyun 			RK_CAMERA_MODULE_DUAL_EDGE, lt8619c->clk_ddrmode_en);
1624*4882a593Smuzhiyun 	}
1625*4882a593Smuzhiyun 
1626*4882a593Smuzhiyun 	if (of_property_read_u32(node, RK_CAMERA_MODULE_DVP_MODE,
1627*4882a593Smuzhiyun 					&lt8619c->yuv_output_mode)) {
1628*4882a593Smuzhiyun 		lt8619c->yuv_output_mode = LT8619C_DEFAULT_DVP_MODE;
1629*4882a593Smuzhiyun 		dev_warn(dev, "can not get module %s from dts, use default(BT1120)!\n",
1630*4882a593Smuzhiyun 					RK_CAMERA_MODULE_DVP_MODE);
1631*4882a593Smuzhiyun 	} else {
1632*4882a593Smuzhiyun 		dev_info(dev, "get module %s from dts, dvp mode(%s)!\n",
1633*4882a593Smuzhiyun 			RK_CAMERA_MODULE_DVP_MODE,
1634*4882a593Smuzhiyun 			(lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" : "BT1120");
1635*4882a593Smuzhiyun 	}
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 	return 0;
1638*4882a593Smuzhiyun 
1639*4882a593Smuzhiyun disable_clk:
1640*4882a593Smuzhiyun 	clk_disable_unprepare(lt8619c->xvclk);
1641*4882a593Smuzhiyun 	return err;
1642*4882a593Smuzhiyun }
1643*4882a593Smuzhiyun 
lt8619c_init_v4l2_ctrls(struct lt8619c * lt8619c)1644*4882a593Smuzhiyun static int lt8619c_init_v4l2_ctrls(struct lt8619c *lt8619c)
1645*4882a593Smuzhiyun {
1646*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1647*4882a593Smuzhiyun 	int ret;
1648*4882a593Smuzhiyun 
1649*4882a593Smuzhiyun 	sd = &lt8619c->sd;
1650*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(&lt8619c->hdl, 2);
1651*4882a593Smuzhiyun 	if (ret)
1652*4882a593Smuzhiyun 		return ret;
1653*4882a593Smuzhiyun 
1654*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&lt8619c->hdl, NULL, V4L2_CID_PIXEL_RATE,
1655*4882a593Smuzhiyun 			  0, lt8619c_PIXEL_RATE, 1, lt8619c_PIXEL_RATE);
1656*4882a593Smuzhiyun 	lt8619c->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&lt8619c->hdl,
1657*4882a593Smuzhiyun 			&lt8619c_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
1658*4882a593Smuzhiyun 			0, 1, 0, 0);
1659*4882a593Smuzhiyun 	if (lt8619c->detect_tx_5v_ctrl)
1660*4882a593Smuzhiyun 		lt8619c->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun 	if (lt8619c->hdl.error) {
1663*4882a593Smuzhiyun 		ret = lt8619c->hdl.error;
1664*4882a593Smuzhiyun 		v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
1665*4882a593Smuzhiyun 		return ret;
1666*4882a593Smuzhiyun 	}
1667*4882a593Smuzhiyun 	sd->ctrl_handler = &lt8619c->hdl;
1668*4882a593Smuzhiyun 
1669*4882a593Smuzhiyun 	if (lt8619c_update_controls(sd)) {
1670*4882a593Smuzhiyun 		ret = -ENODEV;
1671*4882a593Smuzhiyun 		v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
1672*4882a593Smuzhiyun 		return ret;
1673*4882a593Smuzhiyun 	}
1674*4882a593Smuzhiyun 
1675*4882a593Smuzhiyun 	return 0;
1676*4882a593Smuzhiyun }
1677*4882a593Smuzhiyun 
lt8619c_check_chip_id(struct lt8619c * lt8619c)1678*4882a593Smuzhiyun static int lt8619c_check_chip_id(struct lt8619c *lt8619c)
1679*4882a593Smuzhiyun {
1680*4882a593Smuzhiyun 	struct device *dev = &lt8619c->i2c_client->dev;
1681*4882a593Smuzhiyun 	u32 id_h, id_m, id_l;
1682*4882a593Smuzhiyun 	int ret;
1683*4882a593Smuzhiyun 	u32 chipid;
1684*4882a593Smuzhiyun 
1685*4882a593Smuzhiyun 	regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
1686*4882a593Smuzhiyun 	ret  = regmap_read(lt8619c->reg_map, CHIPID_REG_H, &id_h);
1687*4882a593Smuzhiyun 	ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_M, &id_m);
1688*4882a593Smuzhiyun 	ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_L, &id_l);
1689*4882a593Smuzhiyun 
1690*4882a593Smuzhiyun 	if (!ret) {
1691*4882a593Smuzhiyun 		chipid = (id_h << 16) | (id_m << 8) | id_l;
1692*4882a593Smuzhiyun 		if (chipid != LT8619C_CHIPID) {
1693*4882a593Smuzhiyun 			dev_err(dev,
1694*4882a593Smuzhiyun 				"check chipid failed, read id:%#x, we expect:%#x\n",
1695*4882a593Smuzhiyun 				chipid, LT8619C_CHIPID);
1696*4882a593Smuzhiyun 			ret = -1;
1697*4882a593Smuzhiyun 		}
1698*4882a593Smuzhiyun 	} else {
1699*4882a593Smuzhiyun 		dev_err(dev, "%s i2c trans failed!\n", __func__);
1700*4882a593Smuzhiyun 		ret = -1;
1701*4882a593Smuzhiyun 	}
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun 	return ret;
1704*4882a593Smuzhiyun }
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun static const struct regmap_range lt8619c_readable_ranges[] = {
1707*4882a593Smuzhiyun 	regmap_reg_range(0x00, 0xff),
1708*4882a593Smuzhiyun };
1709*4882a593Smuzhiyun 
1710*4882a593Smuzhiyun static const struct regmap_access_table lt8619c_readable_table = {
1711*4882a593Smuzhiyun 	.yes_ranges     = lt8619c_readable_ranges,
1712*4882a593Smuzhiyun 	.n_yes_ranges   = ARRAY_SIZE(lt8619c_readable_ranges),
1713*4882a593Smuzhiyun };
1714*4882a593Smuzhiyun 
1715*4882a593Smuzhiyun static const struct regmap_config lt8619c_hdmirx_regmap_cfg = {
1716*4882a593Smuzhiyun 	.name = "lt8619c",
1717*4882a593Smuzhiyun 	.reg_bits = 8,
1718*4882a593Smuzhiyun 	.val_bits = 8,
1719*4882a593Smuzhiyun 	.reg_stride = 1,
1720*4882a593Smuzhiyun 	.max_register = LT8619C_MAX_REGISTER,
1721*4882a593Smuzhiyun 	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
1722*4882a593Smuzhiyun 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
1723*4882a593Smuzhiyun 	.rd_table = &lt8619c_readable_table,
1724*4882a593Smuzhiyun };
1725*4882a593Smuzhiyun 
lt8619c_probe(struct i2c_client * client,const struct i2c_device_id * id)1726*4882a593Smuzhiyun static int lt8619c_probe(struct i2c_client *client,
1727*4882a593Smuzhiyun 			const struct i2c_device_id *id)
1728*4882a593Smuzhiyun {
1729*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1730*4882a593Smuzhiyun 	struct lt8619c *lt8619c;
1731*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1732*4882a593Smuzhiyun 	char facing[2];
1733*4882a593Smuzhiyun 	int err;
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1736*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
1737*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
1738*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun 	lt8619c = devm_kzalloc(dev, sizeof(*lt8619c), GFP_KERNEL);
1741*4882a593Smuzhiyun 	if (!lt8619c)
1742*4882a593Smuzhiyun 		return -ENOMEM;
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun 	sd = &lt8619c->sd;
1745*4882a593Smuzhiyun 	lt8619c->i2c_client = client;
1746*4882a593Smuzhiyun 	lt8619c->cur_mode = &supported_modes[0];
1747*4882a593Smuzhiyun 	lt8619c->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1748*4882a593Smuzhiyun 
1749*4882a593Smuzhiyun 	err = lt8619c_parse_of(lt8619c);
1750*4882a593Smuzhiyun 	if (err)
1751*4882a593Smuzhiyun 		return err;
1752*4882a593Smuzhiyun 
1753*4882a593Smuzhiyun 	mutex_init(&lt8619c->confctl_mutex);
1754*4882a593Smuzhiyun 	err = lt8619c_init_v4l2_ctrls(lt8619c);
1755*4882a593Smuzhiyun 	if (err)
1756*4882a593Smuzhiyun 		goto err_hdl;
1757*4882a593Smuzhiyun 
1758*4882a593Smuzhiyun 	client->flags |= I2C_CLIENT_SCCB;
1759*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1760*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &lt8619c_ops);
1761*4882a593Smuzhiyun 	sd->internal_ops = &lt8619c_subdev_internal_ops;
1762*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1763*4882a593Smuzhiyun #endif
1764*4882a593Smuzhiyun 
1765*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1766*4882a593Smuzhiyun 	lt8619c->pad.flags = MEDIA_PAD_FL_SOURCE;
1767*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1768*4882a593Smuzhiyun 	err = media_entity_pads_init(&sd->entity, 1, &lt8619c->pad);
1769*4882a593Smuzhiyun 	if (err < 0) {
1770*4882a593Smuzhiyun 		v4l2_err(sd, "media entity init failed! err:%d\n", err);
1771*4882a593Smuzhiyun 		goto err_hdl;
1772*4882a593Smuzhiyun 	}
1773*4882a593Smuzhiyun #endif
1774*4882a593Smuzhiyun 
1775*4882a593Smuzhiyun 	lt8619c->reg_map = devm_regmap_init_i2c(client, &lt8619c_hdmirx_regmap_cfg);
1776*4882a593Smuzhiyun 	lt8619c_power_on(lt8619c);
1777*4882a593Smuzhiyun 	err = lt8619c_check_chip_id(lt8619c);
1778*4882a593Smuzhiyun 	if (err < 0)
1779*4882a593Smuzhiyun 		goto err_hdl;
1780*4882a593Smuzhiyun 
1781*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1782*4882a593Smuzhiyun 	if (strcmp(lt8619c->module_facing, "back") == 0)
1783*4882a593Smuzhiyun 		facing[0] = 'b';
1784*4882a593Smuzhiyun 	else
1785*4882a593Smuzhiyun 		facing[0] = 'f';
1786*4882a593Smuzhiyun 
1787*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1788*4882a593Smuzhiyun 		 lt8619c->module_index, facing,
1789*4882a593Smuzhiyun 		 LT8619C_NAME, dev_name(sd->dev));
1790*4882a593Smuzhiyun 	err = v4l2_async_register_subdev_sensor_common(sd);
1791*4882a593Smuzhiyun 	if (err < 0) {
1792*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1793*4882a593Smuzhiyun 		goto err_subdev;
1794*4882a593Smuzhiyun 	}
1795*4882a593Smuzhiyun 
1796*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt8619c->delayed_work_enable_hotplug,
1797*4882a593Smuzhiyun 			lt8619c_delayed_work_enable_hotplug);
1798*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt8619c->delayed_work_monitor_resolution,
1799*4882a593Smuzhiyun 			lt8619c_delayed_work_monitor_resolution);
1800*4882a593Smuzhiyun 	lt8619c_initial_setup(sd);
1801*4882a593Smuzhiyun 
1802*4882a593Smuzhiyun 	lt8619c->plugin_irq = gpiod_to_irq(lt8619c->plugin_det_gpio);
1803*4882a593Smuzhiyun 	if (lt8619c->plugin_irq < 0) {
1804*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin det irq\n");
1805*4882a593Smuzhiyun 		err = lt8619c->plugin_irq;
1806*4882a593Smuzhiyun 		goto err_work_queues;
1807*4882a593Smuzhiyun 	}
1808*4882a593Smuzhiyun 
1809*4882a593Smuzhiyun 	err = devm_request_threaded_irq(dev, lt8619c->plugin_irq, NULL,
1810*4882a593Smuzhiyun 			plugin_detect_irq, IRQF_TRIGGER_FALLING |
1811*4882a593Smuzhiyun 			IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt8619c", lt8619c);
1812*4882a593Smuzhiyun 	if (err) {
1813*4882a593Smuzhiyun 		dev_err(dev, "failed to register plugin det irq (%d)\n", err);
1814*4882a593Smuzhiyun 		goto err_work_queues;
1815*4882a593Smuzhiyun 	}
1816*4882a593Smuzhiyun 
1817*4882a593Smuzhiyun 	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1818*4882a593Smuzhiyun 	if (err) {
1819*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1820*4882a593Smuzhiyun 		goto err_work_queues;
1821*4882a593Smuzhiyun 	}
1822*4882a593Smuzhiyun 
1823*4882a593Smuzhiyun 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1824*4882a593Smuzhiyun 		  client->addr << 1, client->adapter->name);
1825*4882a593Smuzhiyun 
1826*4882a593Smuzhiyun 	return 0;
1827*4882a593Smuzhiyun 
1828*4882a593Smuzhiyun err_work_queues:
1829*4882a593Smuzhiyun 	cancel_delayed_work(&lt8619c->delayed_work_enable_hotplug);
1830*4882a593Smuzhiyun 	cancel_delayed_work(&lt8619c->delayed_work_monitor_resolution);
1831*4882a593Smuzhiyun err_subdev:
1832*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1833*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1834*4882a593Smuzhiyun #endif
1835*4882a593Smuzhiyun err_hdl:
1836*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt8619c->hdl);
1837*4882a593Smuzhiyun 	mutex_destroy(&lt8619c->confctl_mutex);
1838*4882a593Smuzhiyun 	clk_disable_unprepare(lt8619c->xvclk);
1839*4882a593Smuzhiyun 	return err;
1840*4882a593Smuzhiyun }
1841*4882a593Smuzhiyun 
lt8619c_remove(struct i2c_client * client)1842*4882a593Smuzhiyun static int lt8619c_remove(struct i2c_client *client)
1843*4882a593Smuzhiyun {
1844*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1845*4882a593Smuzhiyun 	struct lt8619c *lt8619c = to_lt8619c(sd);
1846*4882a593Smuzhiyun 
1847*4882a593Smuzhiyun 	cancel_delayed_work(&lt8619c->delayed_work_enable_hotplug);
1848*4882a593Smuzhiyun 	cancel_delayed_work(&lt8619c->delayed_work_monitor_resolution);
1849*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1850*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
1851*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1852*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1853*4882a593Smuzhiyun #endif
1854*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt8619c->hdl);
1855*4882a593Smuzhiyun 	mutex_destroy(&lt8619c->confctl_mutex);
1856*4882a593Smuzhiyun 	clk_disable_unprepare(lt8619c->xvclk);
1857*4882a593Smuzhiyun 
1858*4882a593Smuzhiyun 	return 0;
1859*4882a593Smuzhiyun }
1860*4882a593Smuzhiyun 
1861*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1862*4882a593Smuzhiyun static const struct of_device_id lt8619c_of_match[] = {
1863*4882a593Smuzhiyun 	{ .compatible = "lontium,lt8619c" },
1864*4882a593Smuzhiyun 	{},
1865*4882a593Smuzhiyun };
1866*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lt8619c_of_match);
1867*4882a593Smuzhiyun #endif
1868*4882a593Smuzhiyun 
1869*4882a593Smuzhiyun static struct i2c_driver lt8619c_i2c_driver = {
1870*4882a593Smuzhiyun 	.driver = {
1871*4882a593Smuzhiyun 		.name = LT8619C_NAME,
1872*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(lt8619c_of_match),
1873*4882a593Smuzhiyun 	},
1874*4882a593Smuzhiyun 	.probe		= &lt8619c_probe,
1875*4882a593Smuzhiyun 	.remove		= &lt8619c_remove,
1876*4882a593Smuzhiyun };
1877*4882a593Smuzhiyun 
lt8619c_driver_init(void)1878*4882a593Smuzhiyun static int __init lt8619c_driver_init(void)
1879*4882a593Smuzhiyun {
1880*4882a593Smuzhiyun 	return i2c_add_driver(&lt8619c_i2c_driver);
1881*4882a593Smuzhiyun }
1882*4882a593Smuzhiyun 
lt8619c_driver_exit(void)1883*4882a593Smuzhiyun static void __exit lt8619c_driver_exit(void)
1884*4882a593Smuzhiyun {
1885*4882a593Smuzhiyun 	i2c_del_driver(&lt8619c_i2c_driver);
1886*4882a593Smuzhiyun }
1887*4882a593Smuzhiyun 
1888*4882a593Smuzhiyun device_initcall_sync(lt8619c_driver_init);
1889*4882a593Smuzhiyun module_exit(lt8619c_driver_exit);
1890*4882a593Smuzhiyun 
1891*4882a593Smuzhiyun MODULE_DESCRIPTION("Lontium LT8619C HDMI to BT656/BT1120 bridge driver");
1892*4882a593Smuzhiyun MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
1893*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1894